MEMORY CIRCUIT ARCHITECTURE HAVING MULTIPLEXING AMONG MEMORY BANKS - Patent application

Abstract

One implementation includes a random access memory (RAM) with muted multiplexing capabilities. For example, a RAM can be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. The multiplexing circuitry for the outer banks may be located adjacent to the outer banks and away from the controller, while the multiplexing circuitry for the inner banks may be located within or adjacent to the controller.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to and the benefit of U.S. patent application Ser. No. 17 / 654,295, filed Mar. 10, 2022, the entire disclosure of which is incorporated by reference herein as if fully set forth below and for all applicable purposes.

[0002] This application relates generally to memory circuits, and more particularly to memory circuit architectures that place multiplexing circuitry between memory banks. [Background technology]

[0003]

[0003] Computing devices may include random-access memory (RAM) implemented as static RAM (SRAM), dynamic RAM (DRAM), as well as various read-only memories (ROMs). RAM may be implemented within a processor, such as a central processing unit (CPU), a graphics processing unit (GPU), or external to the processor.

[0004]

[0004] For a given memory design, there may be a conflict between density (i.e., area savings) and performance (i.e., speed). For example, a multi-bank memory device may be designed to maximize density at the expense of increased speed. Conversely, a multi-bank memory device may be designed to increase speed at the expense of increased density.

[0005]

[0005] Therefore, there is a need in the art for a memory architecture that achieves a better tradeoff between performance and area. Summary of the Invention

[0006]

[0006] One implementation includes a random access memory (RAM). The random access memory also includes a first memory bank, a second memory bank, a third memory bank, and a fourth memory bank all coupled to the centrally located controller, and write drivers and sense amplifiers in the centrally located controller and coupled to the first memory bank, the second memory bank, the third memory bank, and the fourth memory bank via a plurality of global bit lines, the third memory bank being disposed between the first memory bank and the centrally located controller on one side of the centrally located controller, the fourth memory bank being disposed between the second memory bank and the centrally located controller on the other side of the centrally located controller, the at least one first read multiplexer and the at least one first write multiplexer coupled to the first memory bank being disposed on a remote side of the third memory bank relative to the centrally located controller, and further, the plurality of global bit lines include a first plurality of read data lines and a first plurality of write data lines coupling the centrally located controller to the at least one first read multiplexer and the at least one first write multiplexer.

[0007]

[0007] Another implementation includes a method of operating a random access memory (RAM) having a first inner memory bank, a first outer memory bank, a second inner memory bank, the second outer memory bank, and a controller disposed between the first inner memory bank and the second inner memory bank, the method including transmitting data from a write driver to the first outer memory bank via a first write multiplexer associated with the first outer memory bank, including transmitting data on a first plurality of write data lines coupling the controller of the RAM to the first write multiplexer, and transmitting data from the write driver to the first inner memory bank via a second write multiplexer associated with the first inner memory bank, including transmitting data on a second plurality of write data lines coupling the controller to a second write multiplexer disposed between the controller and the first inner memory bank.

[0008] Another implementation includes a system on chip (SOC). The system includes a random access memory (RAM) having a first inner memory bank, a first outer memory bank, a second inner memory bank, and a second outer memory bank, where the first inner memory bank is disposed between the first outer memory bank and a controller of the RAM and the second inner memory bank is disposed between the second outer memory bank and the controller of the RAM; a distributed multiplexer system in the RAM including a first outer multiplexer disposed on a first side of the first inner memory bank opposite the controller, a first inner multiplexer disposed between the first inner memory bank and a write driver and a sense amplifier of the controller of the RAM, a second inner multiplexer disposed between the second inner memory bank and the write driver and a sense amplifier, and a second outer multiplexer disposed on a second side of the second inner memory bank opposite the controller; a first plurality of data lines coupling the controller to the first outer multiplexer; and a second plurality of data lines coupling the controller to the first inner multiplexer.

[0009]

[0009] Another implementation is a semiconductor device including a first outer memory bank, a second outer memory bank, a first inner memory bank, and a second inner memory bank, all coupled to a controller, where the first inner memory bank is disposed between the first outer memory bank and the controller and the second inner memory bank is disposed between the second outer memory bank and the controller; a data writing means disposed in the controller and coupled to the first outer memory bank, the second outer memory bank, the first inner memory bank, and the second inner memory bank; a data sensing means disposed in the controller and coupled to the first outer memory bank, the second outer memory bank, the first inner memory bank, and the second inner memory bank; the first outer memory bank and disposed on a first side of the first inner memory bank opposite the controller, a second multiplexing means serving the first inner memory bank and disposed within the controller, a third multiplexing means serving the second outer memory bank and disposed on a second side of the second inner memory bank opposite the controller, and a fourth multiplexing means serving the second inner memory bank and disposed within the controller; and a semiconductor device having a controller and means for transporting data between the controller and the first multiplexing means, the second multiplexing means, the third multiplexing means, and the fourth multiplexing means. [Brief description of the drawings]

[0010] [Figure 1]

[0010] FIG. 1 is a simplified diagram illustrating an exemplary memory circuit, according to one implementation. [Diagram 2]

[0011] 2 is a diagram of the example memory circuit of FIG. 1 according to one implementation. [Diagram 3]

[0012] 3 is a diagram of example conductors in metal layers in the example memory circuit of FIGS. 1-2, according to one implementation. [Figure 4]

[0013] 1 is a diagram of a portion of an exemplary memory circuit, according to one implementation. [Diagram 5]

[0014] 1 is a diagram of a portion of an exemplary memory circuit, according to one implementation. [Figure 6]

[0015] 2 is a diagram of example metal layers in a semiconductor device such as the example memory circuit of FIG. 1, according to one implementation. [Figure 7]

[0016] FIG. 7 is a diagram of an exemplary system-on-chip (SOC) in which memory circuits such as those shown in FIGS. 1-6 can be constructed, according to one embodiment. [Figure 8]

[0017] 9 is a diagram of a method of operating the memory circuits of FIGS. 1-8, according to one implementation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0018] Various implementations provided herein include memory architectures that provide a better balance between performance and density than other solutions. One example of a solution is a high density memory architecture that places the write drivers, sense amplifiers, and multiplexing circuits for four memory banks in a central controller. The sense amplifiers and write drivers are located in the center of the architecture, but support four memory banks, thereby avoiding duplication of the sense amplifiers and write drivers. However, a drawback of the high density architecture is that the multiplexing circuits for the four memory banks are located in the center, which may use conductive lines in higher metal layers to service the outer memory banks. Also, the number of conductive lines may be relatively large because the conductive lines are between the multiplexer circuits and the memory banks. Conductive paths that include multiple metal layers may incur larger parasitic resistance and parasitic capacitance than would be expected for conductive paths in a single metal layer. Thus, a higher density architecture may have the drawback of larger parasitic capacitance and parasitic resistance in the communication paths, thereby slowing down the speed of the device.

[0012]

[0019] Another example of an alternative architecture is a high-speed memory architecture. An exemplary high-speed memory architecture may also include a first inner / outer pair of memory banks on a first side of the central controller and a second pair of inner / outer memory banks on a second (opposite) side of the central controller. However, the high-speed memory architecture includes more duplication of parts than the high-density architecture. For example, the high-speed memory architecture may place a sense amplifier and a write driver between the banks of the first inner / outer pair and another sense amplifier and another write driver between the banks of the second inner / outer pair. Multiplexing circuitry may also be placed closer to the sense amplifier and write driver. As a result, sensing, driving, and multiplexing are placed closer to the individual memory banks than in the high-density architecture. The high-speed memory architecture may be more efficient with higher metal layer routing because it routes fewer global bit lines across the inner pair rather than routing a larger number of bit lines. Thus, the high-speed architecture achieves lower parasitic resistance and capacitance in the communication lines and is therefore faster than the high-density architecture. However, the higher speed is obtained at the expense of reduced density due to increased duplication.

[0013]

[0020] Various implementations described herein provide an advantageous balance between speed and density compared to other implementations. One embodiment includes at least four memory banks. A centrally located controller includes write drivers and sense amplifiers that service each of the different memory banks. The central controller may also include read and write multiplexer circuits to service the inner two of the memory banks. Multiplexing circuits for the outer two of the memory banks are not located in the central controller, but rather are located between the banks of each inner / outer pair. In other words, the multiplexing circuits for the outer two of the memory banks are located next to the outer memory banks.

[0014]

[0021] The multiplexing circuitry for the outer two of the memory banks can communicate with the central write driver and sense amplifier circuitry through (upper or lower) metal layers that traverse the physical paths across the inner two memory banks to the outer memory banks above or below the inner two memory banks. Nevertheless, the number of connections traversing (higher / upper or lower) metal layers is less than that of the high density architecture because at least some of the multiplexing is moved outward and those multiplexers communicate with the sense amplifiers and write drivers using fewer lines than would be expected for communication between the multiplexers and the memory banks they serve. As a result, the communication paths have reduced parasitic resistance and parasitic capacitance compared to the high density architecture. Also, such an implementation can avoid duplicating the sense amplifier and write driver circuits, thereby remaining relatively dense compared to the high speed architecture.

[0015]

[0022] Continuing with this example, the lines connecting the central controller to the outer multiplexing circuitry can be made with separate masks to enhance both write and read performance. For example, the lines used for writing can benefit from reduced resistance. Various implementations can use a mask for the write lines in the (top or bottom) metal layer to make them wider and reduce resistance. Similarly, the lines used for reading can benefit from reduced capacitance and those implementations can use a mask for the read lines to make them narrower.

[0016]

[0023] Some implementations may include a method of operating a memory conforming to the above-described architecture. In one embodiment, the method may include performing a read operation on one of the outer memory banks by decoding address information in the outer bank, which causes a read multiplexing circuit located proximate the outer bank to multiplex the bit line voltages. Memory bits are read from bit cells of the memory bank and then transmitted to a centrally located sense amplifier using metal lines that cross the inner memory bank (e.g., located above or below the inner memory bank). In another embodiment, the method may include performing a write operation on one of the outer memory banks. Data to be written to the outer memory bank is transmitted from a centrally located write driver circuit to a write multiplexing circuit located proximate the outer bank. The write operation includes decoding the address information and using the write multiplexing circuit, including multiplexing the bit line voltages according to the decoded address information.

[0017]

[0024] Various implementations may include advantages over other systems. For example, various implementations of the present disclosure may provide higher density by moving some of the components to the center of the memory device while providing higher performance by moving some of the multiplexing away from the center and individually adjusting the write and read lines to provide higher performance for reading and writing, respectively. Such architectural features may result in devices that have faster reads and writes than high density architectures while at the same time being more efficient in terms of silicon area than high speed architectures.

[0018]

[0025] Although the examples provided herein are directed to a memory architecture having four banks, the scope of implementations is not so limited. Rather, other implementations can scale the architecture to 8, 12, 16, or more memory banks by placing the multiplexing circuits away from the center and closer to the memory banks they service.

[0019]

[0026] FIG. 1 is a simplified diagram illustrating an exemplary memory circuit 100 according to one implementation. Memory circuit 100 includes four memory banks, banks 1-4. Each of banks 1-4 may include four different memory cores. For ease of explanation, only the memory core corresponding to bank 1 is given a reference number, but it is understood that the other banks, banks 2-4, may be similarly implemented. For example, bank 1 includes memory cores 101, 102, 103, 104, which in this example are static RAM (SRAM) cores, each including a number of memory cells (memory elements) arranged in rows (words) and columns (bits). At the intersection of each row and column is at least one bit cell. The scope of implementation is not limited to any size of memory cores 101-104, as memory cores of any suitable size may be adapted in accordance with the principles described herein.

[0020]

[0027] The centrally located controller 110 is physically located within the center of the memory circuit 110 and services each of the memory banks, banks 1-4. In other words, the centrally located controller 110 can be arranged such that half of the (even) number of banks, i.e., the two 1 and 2, can be considered outer memory banks, and banks 3 and 4 in the illustrated embodiment can be considered inner memory banks since they are located on either side of the controller 110, relatively closer to the center of the memory circuit than banks 1 and 2. The centrally located controller 110 can include a write driver 115 and a sense amplifier 113. The centrally located controller 110 can further include a write driver assist circuit (also referred to as a boost circuit or a write driver boost circuit) 118, a data out latch 114, a data in latch 116, and / or an input / output (IO exemplified by item 119). The input / output 119 provides a data path into and out of the memory device 100 for both read and write operations. For example, the input / output 119 may include bumps or pins on the outside of the chip or package that provide electrical communication with the latches 114,116.

[0021]

[0028] The sense amplifiers 113 may include multiple individual sense amplifiers, each of which receives a signal from one of the memory banks during a read operation to sense either a digital 1 or a digital 0 being read from a particular memory bit cell in the bank. During a write operation, the write driver 115 and write driver support circuitry 118 receive data from outside the memory circuit 100 and convert the digital 1s and digital 0s to voltages suitable for writing the data to the bit cells of the memory banks. The centrally located controller 110 may further include a header 117. The header 117 may service the memory banks, banks 3-4. The header 117 may include one or more transistors that perform power gating for a given memory bank, thereby allowing the given memory bank to be powered down to conserve power for the device when the bank is not in use.

[0022]

[0029] The centrally located controller 110 may further include a global bank controller (GBC) 125, which may receive control instructions and addresses, pre-decode the addresses, and control the row decoders 150 to access specific word lines in the exemplary memory cores 101-104 for both read and write accesses. In some implementations, the GBC 125 may include timing control logic such as clock triggers, self-timed pulse width control, and latching for clock signal generation. The GBC 125 may also include operation mode decision logic that may determine read or write modes, input signal latches for both data and control signals, sleep and power-up logic, etc.

[0023]

[0030] A particular memory cell can be selected using row decoder 150 and multiplexers 111, 112, 121, 131. Specifically, each of multiplexers 111, 112, 121, 131 can select a particular bit line and bit line bar to address a particular memory cell. In this embodiment, each of multiplexers 111, 112, 121, 131 includes both read multiplexing (rm) and write multiplexing (wm) circuits. Multiplexers 111 and 112 may be included in centrally located controller 110. Precharging (pre) circuits may be included as well. 1, it should be noted that multiplexers 121 and 131 serving the outer banks (banks 1, 2) (relative to the centrally located controller 110) are physically separate from multiplexers 111 and 112 serving the inner banks (banks 3, 4) (relative to the centrally located controller 110). This will be explained in more detail in relation to subsequent figures. Multiplexers 111, 112, 121, 131 communicate with memory cells as well as sense amplifiers 113, write driver 115, and write driver support circuitry 118.

[0024]

[0031] Multiplexers 121, 131 may be physically located in local data paths (LDPs) 120, 130 that service banks 1, 2, respectively. The LDPs, including multiplexers 111, 112, may be included within a centrally located controller 110 and are not shown separately. The LDPs may also include bitline charging and reset circuitry and headers 117, 122, 132, respectively.

[0025]

[0032] Each of the row decoders 150 can be selected by a pre-decoded signal (not shown) output from the GBC 125. In one embodiment, the memory circuit 100 includes a time-sharing memory architecture in which banks 1-4 can be read from or written to during the same cycle of a clock signal. In some implementations, each of the cores in a given bank can be read from or written to during the same cycle of a clock signal.

[0026]

[0033] The memory circuit 100 also includes global bit lines 190 and bit lines 195. The global bit lines 190 extend between the multiplexers 111, 112, 121, 131 and the sense amplifiers 113 and write drivers 115 and write driver support circuits 118. In contrast, the bit lines 195 extend between the multiplexers 111, 112, 121, 131 and the individual bit cells of the core. The present implementation includes global bit lines 190 that serve banks 1 and 2 and are routed in a higher metal layer across banks 3 and 4, respectively. However, the bit lines 195 associated with banks 1 and 2 are not routed across banks 3 and 4, as those bit lines 195 are coupled to multiplexers 121, 131, respectively, and routed to their respective banks 1 and 2. The paths of the global bit lines 190 and bit lines 195 are described in more detail with respect to FIG. 2. Global bit lines 190 servicing banks 3 and 4 extend from sense amplifiers 113 and write drivers 115 to multiplexers 111 , 112 within a centrally located controller 110 .

[0027]

[0034] The implementation of Figure 1 corresponds to a 128x256 memory, where 128 is the number of word lines and 256 is the number of I / Os. Other implementations can scale the number of word lines and input and output pins as needed, and can employ any register transfer level (RTL) or other technology.

[0028]

[0035] FIG. 2 is a diagram of memory circuit 100 according to one implementation, providing a simplified schematic diagram of memory circuit 100. FIG. 2 shows LDPs 220, 230 servicing banks 3, 4, respectively. LDPs 220, 230 are located within or at least adjacent to centrally located controller 110. Looking at bank 1, it includes cores 101-104, each coupled to multiplexing circuitry of LDP 120 by bit lines 195. Looking at core 104, it includes bit lines 195 arranged in columns within core 104. Bit lines 195 are too numerous to give all of them reference numbers in FIG. 2, but it is understood that the other cores in bank 1 and in the other banks 2-4 have similar structures with similar bit lines 195.

[0029]

[0036] The outer banks, banks 1 and 2 (relative to the centrally located controller 110), are arranged to be serviced by read mux (Rm), write mux (wm), and precharge circuits 121 and 131, respectively, of LDPs 120 and 130. The inner banks, banks 3 and 4 (relative to the centrally located controller 110), are arranged to be serviced by read mux, write mux, and precharge circuits 111 and 112, respectively, of LDPs 220 and 230.

[0030]

[0037] Looking at the read multiplexing, write multiplexing, and precharge circuit 121, it is coupled to the sense amplifiers 113 (for reading) by global bit lines 190 and to the write driver 115 (for writing). Similarly, the read multiplexing, write multiplexing, and precharge circuit 131 is coupled to the sense amplifiers 113 and to the write driver 115 by global bit lines 190. The global bit lines 190 coupling the circuits 121, 131 to the sense amplifiers 113 and the write driver 115 are routed in one or more higher metal layers across banks 3 and 4, respectively. For example, the bit lines 195 may be routed in metal layers M0 or M1, while the global bit lines 190 coupling the circuits 121, 131 to the sense amplifiers 113 and the write driver 115 may be routed in metal layers M2 or higher. Stated another way, the global bit lines 190 that couple the circuits 121, 131 to the sense amplifiers 113 and write drivers 115 are routed in metal layers that are higher, i.e., further from the base layer (such as transistor layer 601 in FIG. 6) or substrate. For simplicity, these higher metal layers will be referred to below as being provided above the metal layers used for other lines, such as bit lines 195 (note that the orientation of memory circuit 100 may be flipped such that the higher metal layers are provided below the metal layers used for other lines, such as bit lines 195).

[0031]

[0038] Routing data lines such as global bit line 190 in a higher metal layer can result in some of these data lines also being routed to lower bit lines and coupled to upper layer bit lines by vias, resulting in capacitance due to both metal layers. Higher capacitance can result in lower performance, especially for read operations but also for write operations. Note that global bit line 190, which couples sense amplifier 113 and write driver 115 to LDP 220, 230, does not need to be routed through a higher metal layer because it is routed on a short path that does not cross memory banks.

[0032]

[0039] Various implementations provide advantages by distributing multiplexers throughout the memory circuit 100 so that the multiplexers are closer to the memory banks they service. In an alternative scenario where bank 1 is served by multiplexers that are further away, such as in LDP 220, bitlines would be routed across bank 3 in a higher metal layer rather than global bitlines. Because there are more bitlines than global bitlines and there is a finite width for routing datalines in those higher metal layers, routing the bitlines can cause more technical challenges and result in more compromises. For example, routing a large number of bitlines within a finite routing space can result in narrower wires being used to implement those bitlines, which can incur more resistance and further degrade performance. In contrast, having a smaller number of global bitlines within the same finite routing space can allow at least some of those wires to be wider, thereby allowing some implementations to have more freedom to appropriately reduce capacitance and / or resistance. This is described in more detail with respect to FIG. 3.

[0033]

[0040] Figure 3 is a diagram of wires routed on a higher metal layer, as may be implemented in the implementations of Figures 1 and 2. Figure 3 is provided to illustrate how wires may be placed within a metal layer (e.g., M2 in Figure 6), and Figure 3 is drawn approximately to scale. For example, Figure 3 is used to illustrate how wires may be placed within a metal layer above and across bank 3 or bank 4 in Figure 2 as they traverse the longest dimension of device 100.

[0034]

[0041] First, wire VSSX is coupled to a power supply and is not associated with data. The same is true for wire vddhx_core. The remaining wires labeled wdin, wdin_n, q, and qb are data lines shown as global bit lines 190 in Figures 1-2. These are complementary data lines such that write data is transmitted via wdin and wdin_n and read data is transmitted via q and qb.

[0035]

[0042] Further, in this embodiment, read operations can benefit from wires with less capacitance, and write operations can benefit from wires with less resistance. In the embodiment of FIG. 3, beneficial wire widths are implemented. For example, wire wdin is shown as two separate metal traces, as is wire wdin_n. In this case, by making the wire from two or more metal traces, we reduce resistance at the expense of increased capacitance, but such a tradeoff may be favorable for write operations. Now looking at the read data lines q, qb, they are each routed with a single trace, thereby reducing capacitance but increasing resistance, but such a tradeoff may be favorable for read operations.

[0036]

[0043] Of course, employing different widths is not limited to the embodiment of FIG. 3. Other implementations can be used, such as using one trace per data line and having variations in the width of the traces. Thus, in the embodiment of FIG. 3, wdin and wdin_n can each be formed from one wider width trace instead. In yet another embodiment, a combination of trace numbers and trace widths can be used. For example, the width of the traces can vary and each data line can be implemented with one or more traces, thereby providing two ways to vary the effective width of the data line. In the above embodiment, the total (combined) width of one or more write lines can be greater than the total (combined) width of another read data line.

[0037]

[0044] Using different widths for the read and write data lines can allow for a beneficial tradeoff between resistance and capacitance in these embodiments. The ability to use different widths in this embodiment is due, at least in part, to the use of a reduced number of wires in a higher metal layer. For example, another implementation that routes bit lines (rather than global bit lines) may route 8, 16, or more wires due to the large number of bit lines used in a column. However, in this implementation, the multiplexers 121, 131 perform X:1 multiplexing (X is an integer), thereby reducing the number of wires from the write drivers 115, 118 to the multiplexers 121, 131 and from the sense amplifiers 113 to the multiplexers 121, 131. Reducing the number of wires within a finite width allows some wires to be wider than others.

[0038]

[0045] Various implementations can construct the wires using any suitable technique. For example, during semiconductor processing, the wires used for writing may be fabricated with a different mask than the wires used for reading. The different masks can, for example, allow for different widths for the wires. Of course, the scope of implementations is not limited to using different masks.

[0039]

[0046] The ability to use different widths for different data lines can result in higher performance than would be expected from a higher density device that places all of its multiplexing in the center of the memory circuit. In particular, the ability to lower the capacitance for read operations and lower the resistance for write operations can result in higher throughput than would be expected for a device that routes the bit lines in a higher metal layer. Moreover, such performance can be achieved without substantially increasing the semiconductor area of ​​the memory circuit 100. Even though the multiplexing is distributed around the memory circuit 100, it can be done without duplicating the sense amplifiers 113 and write drivers 115. Thus, the implementations described in Figures 1-7 can provide relatively high performance at a relatively low price in semiconductor area.

[0040]

[0047] Returning now to FIG. 2, global bit lines 190 servicing banks 1 and 3 and bit lines 195 servicing banks 1 and 3 are described. It will be appreciated that multiplexer 112 is configured similarly to multiplexer 111 to service bank 4. Similarly, it will be appreciated that multiplexer 131 is configured similarly to multiplexer 121 to service bank 2. The various bit lines 195 and global bit lines 190 are routed in the same manner as described above. For example, global bit line 190 may be routed in a higher metal layer across bank 4 to couple sense amplifier 113 and write driver 115 to multiplexer 131 at LDP 130 to service bank 2, while bit line 195 coupled to multiplexer 112 may be shorter and not routed in a higher metal layer. Additionally, bit lines 195 associated with banks 3 and 4 are also not routed through a higher metal layer due to the proximity of a given multiplexer to the bank it services.

[0041]

[0048] 4 and 5 are diagrams of a portion of memory circuit 100 according to one implementation and are provided to illustrate the relationships between different components and different signals. FIG. 4 illustrates banks 3 and 4 coupled to global bit lines 190 and sense amplifiers 113 as well as write drivers 115 and write assist circuits 118. Alternatively, FIG. 4 could instead illustrate banks 1 and 2, with the understanding that banks 3 and 4 are omitted for simplicity. In any event, the relationships between signals and cores in FIG. 4-5 are the same for each of banks 1-4 in FIG. 1-2.

[0042]

[0049] The sense amplifier 113 services each of the banks and each of the cores by receiving signals Q_top_b0, QB_top_b0, Q_top_b1, QB_top_b1, Q, QB. The signals Q, QB are received from a lower core in each bank (such as core 103 or 104 in bank 1 of FIG. 1), and the signals Q_top, QB_top are received from an upper core in each bank (such as core 101 or 102 in bank 1 of FIG. 1). A read operation may include providing a digital 0 to two or more of the transistors, e.g., p-type metal oxide semiconductor (PMOS) transistors, to create an open circuit between a particular bit cell and the sense amplifier 113. For example, performing a read operation from a lower core may include providing a digital 0 as a control signal Iso_b0 to turn on transistors P0, P1. Otherwise, P0, P1 may be turned off. Similarly, reading from the top core may include providing a digital 0 as Iso_b1_top or Iso_b0_top to turn on either the P2 / P3 pair or the P4 / P5 pair, otherwise those transistors may be turned off. The Iso control signal may be provided by any suitable component, such as the GBC 125 (FIG. 1). This is true for each of the different control signals in FIGS. 4-5. Although only a single PMOS pair (P2 / P3 and P4 / P5) is shown to read each bank, other implementations may include additional PMOS pairs for the bottom cores of banks 3 and 4 to enable independent read operations of the bottom cores of banks 3 and 4.

[0043]

[0050] Write driver 115 provides signals Wd, Wd_n at voltages associated with writing to different banks. In a scenario where global bit lines 190 are provided to the inner banks (banks 3, 4), the global bit lines 190 may be routed in any suitable metal layer, but perhaps in the lower metal layers M0 or M1. In a scenario where global bit lines 190 are provided to the outer banks (banks 1, 2), the global bit lines 190 may be routed in a higher / upper metal layer, such as M2, in addition to one of the lower metal layers. The implementation of Figures 1-2 includes both scenarios.

[0044]

[0051] 5, an example relationship between the global bit lines and multiplexers for any one of banks 1-4 is shown. For ease of explanation, this example focuses on bank 1, with it being understood that the other banks, banks 2-4, may operate similarly. Additionally, FIG. 5 shows an example for a single column within a bank, with it being understood that other columns within a bank may operate in the same or similar manner.

[0045]

[0052] Figure 5 shows a top core (CORE_TOP), such as core 101 or 102 of Figure 1, and a bottom core (CORE_BOT), such as core 103 or 104 of Figure 1. Note that while the examples of Figures 1-2 show an example having four cores per bank, this is not inconsistent with Figures 4-5. Rather, the examples of Figures 4-5 may be scaled such that a given bank has two top cores and two bottom cores as in Figures 1-2, with the multiplexing and precharge functions scaled accordingly.

[0046]

[0053] In this implementation, the multiplexer 121 is split into two parts, one for each of the cores. This can be scaled to an implementation with four cores in a bank by scaling the multiplexer to four parts. Bit lines 195 are shown as bl_top, blb_top, bl_top, and blb_bot, which are coupled to the multiplexer 121 as well as to the individual bit cells in each core. The bit lines 195 provide complementary values ​​to the individual bit cells in each core.

[0047]

[0054] The precharge circuit is shown as including (e.g., PMOS) transistors P10-P15, and the signal pre_top may take a digital 0 value to turn on transistors P10-P15, thereby applying a voltage from a power supply (e.g., VDD) to bit line 195. Otherwise, transistors P10-P15 may be turned off. Precharge may be used during a read operation, if desired.

[0048]

[0055] The multiplexing function is provided by (e.g., PMOS) transistors P20-P23 and (e.g., NMOS) transistors N20-N23. Looking at the top core, during a read operation, transistors P20 and P21 can be turned on at least long enough to read complementary bits from a particular bit cell selected by a row decoder (as in FIG. 1). Transistors P20 and P21 can be turned on using a control signal rm_top. In this embodiment, a given column can be selected by turning on its read multiplexer transistor using a read multiplex (rm) signal, it being understood that there is a separate rm signal for each column. In such an embodiment, a controller (e.g., GBC125) can select a given column by turning on its transistor while leaving corresponding transistors in other columns (not shown) off.

[0049]

[0056] Similarly, during a write operation in the upper core, transistors N20 and N21 can be turned on using the control signal wm_top while leaving other transistors off, at least long enough to perform a write to a selected bitcell. Again, a particular column can be selected by a controller by turning on transistors N20 and N21 while leaving corresponding transistors in other columns off. The multiplexing signals in both the upper and lower cores can be provided by a controller (e.g., GBC125) or other suitable components.

[0050]

[0057] A similar process may be performed in the lower core. Specifically, a read operation in a column may include using rm_bot to select the column by turning on transistors P22 and P23 long enough to perform the read while leaving corresponding transistors in other columns off. A write operation to a column may include using wm_bot to select the column by turning on transistors N22 and N23 while leaving corresponding transistors in other columns off.

[0051]

[0058] FIG. 5 is provided to illustrate at least one example of a spatial relationship between the multiplexers 121 that service a bank and the bit cells within the bank. As illustrated in FIG. 5, the multiplexers 121 may be split into one portion per core, and the portions may be located adjacent to their corresponding cores. In other words, the LDPs (e.g., LDPs 120) for a given bank may conform to the architecture illustrated in FIG. 5. Of course, the scope of implementations is not limited to the architecture illustrated in FIG. 5, as any suitable architecture may be used. For example, the lower cores or upper cores may share multiplexers and precharge circuits in other implementations.

[0052]

[0059] 6 is a diagram of an exemplary semiconductor device 600, according to one implementation. The memories described above with respect to FIGS. 1-5 can be constructed according to the diagram in FIG.

[0053]

[0060] The embodiment of Figure 6 includes a layer of transistors 601 formed on a semiconductor substrate. For example, transistors 601 may represent transistors forming bit cells in a memory bank, multiplexer transistors, driver transistors, sense amplifiers, etc.

[0054]

[0061] Transistor 601 forms logic, power, memory, etc. circuits that communicate with other circuits within the layer of transistor 601 as well as resources / circuitry outside of semiconductor device 600 (not shown). Electrical communication is facilitated by vias 602-604 and metal layers M0-M2. For example, via 602 may electrically couple a particular terminal of a transistor to metal layer M0, which may be patterned to couple that particular transistor to another transistor by another via (not shown), or may couple that particular transistor to metal layer M1 through via 603. Metal layer M1 may be patterned in any particular manner and may be coupled to layer M0 through any of a number of vias exemplified by via 603. Similarly, metal layer M2 may be patterned in any particular manner and may be coupled to layer M1 through any of a number of vias exemplified by via 604.

[0055]

[0062] The physical conductor routing may be performed in any suitable manner. As noted in the examples above, some of the global bitlines 190 implemented in metal layers that cross (e.g., above or below) bank 3 and bank 4 may use higher metal layers. An example of a higher metal layer is M2. Also, as noted above, the conductive path using M2 may include additional capacitance due to lower metal layers M0, M1 and vias 602-604. In contrast, bitlines 195 may use conductors in the lower metal layers M0, M1 and avoid the use of higher metal layers.

[0056]

[0063] Of course, the specific numbers given in the implementation of FIG. 6 are merely examples. For example, a given semiconductor device 600 may include more or fewer metal layers. Moreover, these metal layers may be patterned in a manner not easily shown in the XY plane of FIG. 6, but it is understood that FIG. 6 provides a simplified illustration of metal layers M0-M2 separated by dielectric materials and a transistor 601 that may be implemented as various devices. It is also understood that FIG. 6 is not drawn to scale. According to one implementation, at least two metal layers may be provided, with a first of the at least two metal layers (e.g., M0) being provided closer to the layer of the transistor 601 than a second of the at least two metal layers (e.g., M2). For simplicity, the first metal layer may be referred to as the lower metal layer and the second metal layer may be referred to as the higher / upper metal layer. The structures of the metal layers may be embedded in respective insulating layers and / or may be separated from each other by at least one insulating layer. As mentioned above, vias 602-604 may be provided to (vertically) connect structures such as electrical leads or conductive paths in metal layers, for example using through holes.

[0057]

[0064] Various implementations described herein may be suitable for use in a system on a chip (SOC). One example of an SOC is a semiconductor chip having multiple processing devices therein, including a graphics processing unit (GPU), a central processing unit (CPU), a modem unit, a camera unit, etc. In some examples, the SOC may be contained in a chip package, mounted on a printed circuit board, and disposed in a portable device such as a smartphone or tablet computer. However, the scope of implementations is not limited to chips implemented in tablet computers or smartphones, as other applications are possible.

[0058]

[0065] 7 is a diagram of an exemplary SOC 700 according to one implementation. In this example, the SOC 700 is implemented on a semiconductor die and includes multiple system components 710-790. Specifically, in this example, the SOC 700 includes a CPU 710, which is a multi-core general-purpose processor having four processor cores, core 0-core 3. Of course, other implementations may include two cores, eight cores, or any other suitable number of cores in the CPU 710, so the scope of the implementation is not limited to any particular number of cores. The SOC 700 further includes other system components, such as a first digital signal processor (DSP) 740, a second DSP 750, a modem 730, a GPU 720, a video subsystem 760, a wireless local area network (WLAN) transceiver 770, and a video-front-end (VFE) subsystem 780.

[0059]

[0066] SOC 700 also includes a RAM memory circuit 790. In this example, RAM memory circuit 790 may include one or more memory circuits corresponding to the architecture described above with respect to FIGS. 1-6. The implementations described herein may be adapted for use with any RAM memory circuit. For example, in this example, SOC 700 may include a stand-alone RAM memory circuit 790, or there may be other RAM components in other processing units, such as GPU 720, modem unit 730, DSP 740, 750, etc. These RAM components may also be adapted according to the architecture described above with respect to FIGS. 1-6.

[0060]

[0067] As discussed above, SOC 700 may include a CPU 710 having multiple cores 0-3, one or more of which may execute computer readable code that provides the functionality of an operating system kernel. Additionally, an exemplary operating system kernel may include memory management logic that may perform read and write operations on various memory circuits, such as the RAM memory circuits described herein. Thus, the principles described with respect to FIGS. 1-6 and 8 may be implemented in SOC 700, and more specifically, the circuits and methods illustrated in FIGS. 1-6 and 8 may be implemented in SOC 700 or other chips to provide memory read and write functionality. For example, an operating system kernel with memory management logic may perform read or write operations to cause RAM memory to be either read or written, as discussed above.

[0061]

[0068] A flow diagram of an exemplary method 800 for performing reads and writes according to one implementation is shown in FIG. 8. In one embodiment, the method 800 is performed by the RAM architecture described above with respect to FIGS. 1-7. In some embodiments, a memory management unit, either internal or external to the CPU or GPU, includes processing circuitry that executes computer-readable instructions to perform read or write operations on the RAM memory circuitry by controlling a centrally located controller (e.g., centrally located controller 110 of FIG. 1). For example, logic in the CPU or GPU may send address and control signals to the centrally located controller to cause the centrally located controller to either read or write data.

[0062]

[0069] Actions 810-840 describe write operations, and actions 850-880 describe read operations. It should be understood that implementations can perform reads before writes, or alternate between reads and writes, as desired.

[0063]

[0070] At action 810, the method includes transmitting data from a write driver to a first outer memory bank via a first write multiplexer associated with the first outer memory bank. An example in which bank 1 is the first outer bank is shown in FIGS. 1-2. The data may be transmitted on a write data line coupling a centrally located controller to the first write multiplexer. The write data line may be disposed in a metal layer that crosses (e.g., above or below) the first inner memory bank (e.g., bank 3) and crosses the first inner memory bank.

[0064]

[0071] Action 820 may include transmitting data from the write driver to the first inner memory bank via a second write multiplexer associated with the first inner memory bank. An example in which bank 3 is the first inner bank is shown in FIGS. 1-2. Also, in this example, the second write multiplexer is located between the centrally located controller and the write driver. In other words, the multiplexing is distributed around the physical architecture of the RAM, such that the multiplexing for the first inner memory bank may be located in or adjacent to the centrally located controller, and the multiplexing for the first outer memory bank may be located adjacent to the first outer memory bank and outside of the centrally located controller, as shown in FIGS. 1-2. The data may be transmitted on global bit lines.

[0065]

[0072] At action 830, the method includes transmitting data from the write driver to the second outer memory bank via a third write multiplexer associated with the second outer memory bank. An example in which the second outer memory bank is bank 2 and is serviced by multiplexer 131 is shown in Figures 1-2.

[0066]

[0073] At action 840, the method includes transmitting data from the write driver to the second interior memory bank via a fourth write multiplexer associated with the second interior memory bank. An example in which the second interior memory bank is bank 4 and is serviced by multiplexer 112 is shown in Figures 1-2.

[0067]

[0074] At action 850, the method includes transmitting data from the first outer memory bank through a first read multiplexer to sense amplifiers located in the centrally located controller. An example in which the first outer memory bank is served by multiplexer 121 is shown in Figures 1-2. Read data lines may couple the centrally located controller to the first read multiplexer, and the read data lines may be located in a metal layer that is routed across the first inner memory bank to the first outer memory bank.

[0068]

[0075] At action 860, the method includes transmitting data from the first interior memory bank through the second read multiplexer to the sense amplifiers. An example in which the first interior memory bank is served by multiplexer 111 is shown in Figures 1-2.

[0069]

[0076] At action 870, the method includes transmitting data from the second outer memory bank through a third read multiplexer to the sense amplifiers. An example in which the second outer memory bank is served by multiplexer 131 is shown in Figures 1-2. The data may be transmitted in read data lines that traverse the second inner memory bank in a metal layer across the second inner memory bank to the second outer memory bank.

[0070]

[0077] At action 880, the method includes transmitting data from the second interior memory bank to the sense amplifiers via the fourth read multiplexer. An example in which the second interior memory bank is served by multiplexer 112 is shown in Figures 1-2.

[0071]

[0078] The scope of implementations is not limited to the specific actions shown in FIG. 8. Rather, other implementations can add, omit, reorder, or modify one or more actions. In one embodiment, memory circuit 100 can perform read and write operations simultaneously in multiple banks. In fact, the architecture of memory circuits 100, 400 can allow up to four read / write operations to be performed simultaneously by utilizing four banks simultaneously. However, there is no requirement that any particular number of banks must be read or written during any particular clock cycle.

[0072]

[0079] Further, an implementation may perform a read or write operation every clock cycle or in subsequent non-consecutive cycles in at least one of the memory banks. The actions of method 800 may be performed as many times as appropriate to read or write the requested data. When a word line is driven, it allows a byte of data to be read from memory, and that byte of data is either written to or read from a physical location in the memory circuit that corresponds to a logical location known to a CPU, GPU, or other processing device. Multiple clock cycles may be used to read or write multiple bytes of data with the number of clock cycles used depending on the size of the read or write request, and this is true for each of the memory banks.

[0073]

[0080] The following numbered clauses describe exemplary implementations.

[0081] 1. a first memory bank, a second memory bank, a third memory bank, and a fourth memory bank, all coupled to a centrally located controller; a write driver and sense amplifier in the centrally located controller coupled to the first memory bank, the second memory bank, the third memory bank, and the fourth memory bank via a plurality of global bit lines; Equipped with a third memory bank is disposed on one side of the centrally located controller between the first memory bank and the centrally located controller, and a fourth memory bank is disposed on the other side of the centrally located controller between the second memory bank and the centrally located controller; at least one first read multiplexer and at least one first write multiplexer coupled to the first memory bank are disposed on a remote side of the third memory bank relative to the centrally located controller; further comprising: a first plurality of read data lines and a first plurality of write data lines coupling the centrally located controller to the at least one first read multiplexer and the at least one first write multiplexer; Random Access Memory (RAM).

[0082] 2. A first plurality of read data lines and a first plurality of write data lines are disposed in a first metal layer across the third memory bank, and the RAM comprises: at least one second read multiplexer and at least one second write multiplexer coupled to the second memory bank, the second memory bank being disposed on a distal side of the centrally located controller relative to the centrally located controller, the plurality of global bit lines further including a second plurality of read data lines and a second plurality of write data lines coupling the centrally located controller to the at least one second read multiplexer and the at least one second write multiplexer, the second plurality of read data lines and the second plurality of write data lines being disposed in a second metal layer across the fourth memory bank. RAM as described in clause 1.

[0083] 3. The RAM of claim 2, wherein the second metal layer is the first metal layer.

[0084] 4. A RAM described in any one of clauses 1 to 3, wherein at least one of the first plurality of read data lines has a different width dimension than at least one of the first plurality of write data lines.

[0085] 5. A RAM described in any one of clauses 1 to 4, wherein a total width dimension of the first plurality of read data lines is smaller than a total width dimension of the first plurality of write data lines.

[0086] 6. The RAM of any one of clauses 1 to 5, further comprising at least one third read multiplexer and at least one third write multiplexer coupled to a third memory bank and disposed at least partially between the third memory bank and the write driver and sense amplifier.

[0087] 7. The RAM of clause 6, wherein the at least one third read multiplexer and the at least one third write multiplexer are located within the centrally located controller.

[0088] 8. The first memory bank comprises an upper core and a lower core, the lower core being disposed between the upper core and the third memory bank; at least one first read multiplexer comprises a first read portion associated with the upper core and a second read portion associated with the lower core; one of the first read portion and the second read portion is disposed between the upper core and the lower core; 6. A RAM according to any one of clauses 1 to 5.

[0089] 9. The RAM of clause 8, wherein the other of the first read portion and the second read portion is disposed between the lower core and the third memory bank.

[0090] 10. A RAM described in any one of clauses 1 to 5, wherein at least one first read multiplexer and at least one first write multiplexer are disposed between the first memory bank and the third memory bank.

[0091] 11. The RAM of any one of clauses 1 to 10, further comprising at least one fourth read multiplexer and at least one fourth write multiplexer coupled to the fourth memory bank and disposed at least partially between the fourth memory bank and the write driver and sense amplifier.

[0092] 12. The RAM of claim 11, wherein the at least one fourth read multiplexer and the at least one fourth write multiplexer are located within the centrally located controller.

[0093] 13. 13. The RAM of any one of clauses 1 to 12, further comprising a first local data path coupled to the first memory bank, the first local data path including a first precharge circuit, at least one first read multiplexer, and at least one first write multiplexer.

[0094] 14. The RAM of clause 13, further comprising a second local data path coupled to the second memory bank, the second local data path including a second precharge circuit, at least one second read multiplexer, and at least one second write multiplexer, the at least one second read multiplexer and the at least one second write multiplexer being coupled to a plurality of global bit lines.

[0095] 15. The RAM of clause 14, further comprising a third local data path associated with the third memory bank, the third local data path including a third precharge circuit, at least one third read multiplexer, and at least one third write multiplexer, the at least one third read multiplexer and the at least one third write multiplexer being coupled to a plurality of global bit lines and disposed between the third memory bank and the write driver and sense amplifier.

[0096] 16. The RAM of clause 15, further comprising a fourth local data path associated with the fourth memory bank, the fourth local data path including a fourth precharge circuit, at least one fourth read multiplexer, and at least one fourth write multiplexer, the at least one fourth read multiplexer and the at least one fourth write multiplexer being coupled to a plurality of global bit lines, and the at least one fourth read multiplexer and the at least one fourth write multiplexer being disposed between the fourth memory bank and the write driver and sense amplifier.

[0097] 17. a data out latch coupled to the sense amplifier and disposed within the centrally located controller; a data-in latch disposed in the centrally located controller, the data-in latch being coupled to the write driver; 17. The RAM of any one of clauses 1 to 16, further comprising:

[0098] 18. a header coupling a power source to the third and fourth memory banks, the header disposed within the centrally located controller; an additional header coupling a power source to the first memory bank, the additional header being disposed between the first memory bank and the third memory bank; 18. The RAM of any one of clauses 1 to 17, further comprising:

[0099] 19. a first plurality of bit lines coupling the first read multiplexer to columns in the first memory bank; a second plurality of bit lines coupling the second read multiplexer to columns in the third memory bank; 19. The RAM of any one of clauses 1 to 18, further comprising:

[0100] 20. A method of operating a random access memory (RAM) having a first inner memory bank, a first outer memory bank, a second inner memory bank, a second outer memory bank, and a controller disposed between the first inner memory bank and the second inner memory bank, comprising: transmitting data from the write driver to the first outer memory bank through a first write multiplexer associated with the first outer memory bank, the first write multiplexer including transmitting data on a first plurality of write data lines coupling a controller of the RAM to the first write multiplexer; transmitting data from the write driver to the first inner memory bank via a second write multiplexer associated with the first inner memory bank, the second write multiplexer including transmitting data on a second plurality of write data lines coupling the controller to a second write multiplexer disposed between the controller and the first inner memory bank; A method comprising:

[0101] 21. The method of claim 20, wherein a first plurality of write data lines are disposed in a metal layer above the first inner memory bank.

[0102] twenty two. transmitting data from the write driver to the second outer memory bank through a third write multiplexer associated with the second outer memory bank, the third write multiplexer including transmitting data on a third plurality of write data lines coupling the controller to the third write multiplexer, the third plurality of write data lines being disposed in a metal layer above the second inner memory bank; transmitting data from the write driver to the second inner memory bank via a fourth write multiplexer associated with the second inner memory bank, the fourth write multiplexer including transmitting data on a fourth plurality of write data lines coupling the controller to a fourth write multiplexer disposed between the controller and the second inner memory bank; 22. The method of claim 21, further comprising:

[0103] twenty three. transmitting data from the first outer memory bank through the first read multiplexer to sense amplifiers in the controller, the first read multiplexer including transmitting data on a first plurality of read data lines coupling the controller to the first read multiplexer, the first plurality of read data lines being disposed in a metal layer above the first inner memory bank; transmitting data from the first interior memory bank through a second read multiplexer to the sense amplifiers, the second read multiplexer including transmitting data on a second plurality of read data lines coupling the controller to a second read multiplexer disposed between the controller and the first interior memory bank; 22. The method of claim 21, further comprising:

[0104] twenty four. transmitting data from the second outer memory bank through the third read multiplexer to the sense amplifiers, the third read multiplexer including transmitting data on a third plurality of read data lines coupling the controller to the third read multiplexer, the third plurality of read data lines being disposed in a metal layer above the second inner memory bank; transmitting data from the second interior memory bank through a fourth read multiplexer to the sense amplifiers, the fourth read multiplexer including transmitting data on a fourth plurality of read data lines coupling the controller to a fourth read multiplexer disposed between the controller and the second interior memory bank; 24. The method of claim 23, further comprising:

[0105] twenty five. a random access memory (RAM) having a first inner memory bank, a first outer memory bank, a second inner memory bank, and a second outer memory bank, the first inner memory bank being disposed between the first outer memory bank and a controller of the RAM, and the second inner memory bank being disposed between the second outer memory bank and the controller of the RAM; a distributed multiplexer system in the RAM including a first outer multiplexer located on a first side of the first inner memory bank opposite the controller, a first inner multiplexer located between the first inner memory bank and a write driver and a sense amplifier of the controller of the RAM, a second inner multiplexer located between the second inner memory bank and the write driver and the sense amplifier, and a second outer multiplexer located on a second side of the second inner memory bank opposite the controller; a first plurality of data lines coupling the controller to the first outer multiplexer; a second plurality of data lines coupling the controller to the first inner multiplexer; A system-on-chip (SOC) comprising:

[0106] 26. The SOC of clause 25, wherein a first plurality of data lines traverse the first interior memory bank, and the second plurality of data lines are physically shorter than the first plurality of data lines.

[0107] 27. 27. The SOC of clause 25 or 26, further comprising a first plurality of bit lines coupling the first outer multiplexer to columns in the first outer memory bank.

[0108] 28. 28. The SOC of any one of clauses 25 to 27, further comprising a third plurality of data lines coupling the controller to the second outer multiplexer, the third plurality of data lines traversing the second inner memory bank.

[0109] 29. 29. The SOC of clause 28, further comprising a fourth plurality of data lines coupling the controller to the second inner multiplexer, the fourth plurality of data lines being physically shorter than the third plurality of data lines.

[0110] 30. The SOC of clause 28, further comprising a second plurality of bit lines coupling the second outer multiplexer to columns in the second outer memory bank.

[0111] 31. The SOC of any one of clauses 25 to 30, wherein the first plurality of data lines includes a first read line and a first write data line, the first read line having a different width than the first write line.

[0112] 32. The SOC of any one of clauses 25 to 31, wherein the first outer multiplexer includes a first read multiplexer and a first write multiplexer, and the first inner multiplexer includes a second read multiplexer and a second write multiplexer.

[0113] 33. The SOC of clause 32, wherein the second outer multiplexer includes a third read multiplexer and a third write multiplexer, and the second inner multiplexer includes a fourth read multiplexer and a fourth write multiplexer.

[0114] 34. The SOC of any one of clauses 25 to 33, wherein the first inner multiplexer and the second inner multiplexer are both located within the controller.

[0115] 35. a first local data path associated with the first outer memory bank, the first local data path including a first precharge circuit and a first outer multiplexer; a second local data path associated with the first inner memory bank, the second local data path including a second precharge circuit and a first inner multiplexer; 35. The SOC of any one of clauses 25 to 34, further comprising:

[0116] 36. A semiconductor device comprising: a first outer memory bank, a second outer memory bank, a first inner memory bank, and a second inner memory bank, all coupled to a controller, the first inner memory bank being disposed between the first outer memory bank and the controller, and the second inner memory bank being disposed between the second outer memory bank and the controller; a means for writing data disposed in the controller and coupled to the first outer memory bank, the second outer memory bank, the first inner memory bank, and the second inner memory bank; a data sensing means disposed within the controller and coupled to the first outer memory bank, the second outer memory bank, the first inner memory bank, and the second inner memory bank; a means for multiplexing data transmitted between the controller and the first outer memory bank, the second outer memory bank, the first inner memory bank, and the second inner memory bank, the means comprising: a first multiplexing means serving the first outer memory bank and disposed on a first side of the first inner memory bank opposite the controller; a second multiplexing means serving the first inner memory bank and disposed within the controller; a third multiplexing means serving the second outer memory bank and disposed on a second side of the second inner memory bank opposite the controller; a fourth multiplexing means serving the second inner memory bank and disposed within the controller; A means for multiplexing data, means for conveying data between the controller and the first multiplexing means, the second multiplexing means, the third multiplexing means, and the fourth multiplexing means; A semiconductor device comprising:

[0117] 37. The semiconductor device of clause 36, wherein the means for carrying data comprises a first plurality of global bit lines between the controller and the first multiplexing means, the means for carrying data being disposed in a metal layer above the first inner memory bank.

[0118] 38. The semiconductor device of clause 37, wherein the means for conveying data further comprises a second plurality of global bit lines between the controller and the second multiplexing means, and the first plurality of global bit lines are physically shorter than the second plurality of global bit lines.

[0119] 39. The semiconductor device of clause 37, wherein the first plurality of global bit lines includes a first read data line and a first write data line, the first read data line having a different length dimension than the first write data line.

[0120] 40. The semiconductor device of clause 37, wherein the first plurality of global bit lines includes a first read data line and a first write data line, the first read data line having a width dimension narrower than a width dimension of the first write data line.

[0074]

[0121] As will be appreciated by those skilled in the art at present, and depending on the specific application at hand, numerous modifications, substitutions, and variations can be made in and to the materials, arrangements, configurations, and methods of use of the disclosed devices without departing from the scope thereof as defined by the appended claims. In light of this, and as the specific embodiments illustrated and described herein are merely by way of example of some of the same, the scope of the disclosure should not be limited to the scope of such specific implementations, but rather should be fully equivalent to the scope of the hereafter appended claims and their functional equivalents.

Claims

1. a first memory bank, a second memory bank, a third memory bank, and a fourth memory bank, all coupled to a centrally located controller; a write driver and sense amplifier within the centrally located controller coupled to the first memory bank, the second memory bank, the third memory bank, and the fourth memory bank via a plurality of global bit lines; Equipped with the third memory bank is disposed on one side of the centrally located controller between the first memory bank and the centrally located controller, and the fourth memory bank is disposed on the other side of the centrally located controller between the second memory bank and the centrally located controller; at least one first read multiplexer and at least one first write multiplexer coupled to the first memory bank are located on a remote side of the third memory bank relative to the centrally located controller; further comprising: a first plurality of read data lines and a first plurality of write data lines coupling the centrally located controller to the at least one first read multiplexer and the at least one first write multiplexer; Random Access Memory (RAM).

2. the first plurality of read data lines and the first plurality of write data lines are disposed in a first metal layer across the third memory bank, and the RAM comprises: and at least one second read multiplexer and at least one second write multiplexer coupled to the second memory bank, the second memory bank being located on a far side of the centrally located controller relative to the centrally located controller, the plurality of global bit lines further including a second plurality of read data lines and a second plurality of write data lines coupling the centrally located controller to the at least one second read multiplexer and the at least one second write multiplexer, the second plurality of read data lines and the second plurality of write data lines being located in a second metal layer that crosses the fourth memory bank; Preferably, the second metal layer is the first metal layer. The RAM of claim 1.

3. 2. The RAM of claim 1, wherein at least one of said first plurality of read data lines has a different width dimension than at least one of said first plurality of write data lines.

4. 2. The RAM of claim 1, wherein a combined width dimension of said first plurality of read data lines is smaller than a combined width dimension of said first plurality of write data lines.

5. at least one third read multiplexer and at least one third write multiplexer coupled to the third memory bank and disposed at least partially between the third memory bank and the write driver and the sense amplifier; 2. The RAM of claim 1, wherein the at least one third read multiplexer and the at least one third write multiplexer are located within the centrally located controller.

6. the first memory bank includes an upper core and a lower core, the lower core being disposed between the upper core and the third memory bank; the at least one first read multiplexer comprises a first read portion associated with the upper core and a second read portion associated with the lower core; one of the first reading portion and the second reading portion is disposed between the upper core and the lower core; The RAM of claim 1.

7. 9. The RAM of claim 8, wherein the other of the first read portion and the second read portion is disposed between the lower core and the third memory bank.

8. 2. The RAM of claim 1, wherein the at least one first read multiplexer and the at least one first write multiplexer are disposed between the first memory bank and the third memory bank.

9. at least one fourth read multiplexer and at least one fourth write multiplexer coupled to the fourth memory bank and disposed at least partially between the fourth memory bank and the write driver and the sense amplifier; 2. The RAM of claim 1, wherein the at least one fourth read multiplexer and the at least one fourth write multiplexer are located within the centrally located controller.

10. a first local data path coupled to the first memory bank, the first local data path including a first precharge circuit, the at least one first read multiplexer, and the at least one first write multiplexer; a second local data path coupled to the second memory bank, the second local data path including a second precharge circuit, at least one second read multiplexer, and at least one second write multiplexer, the at least one second read multiplexer and the at least one second write multiplexer being coupled to the plurality of global bit lines; a third local data path associated with the third memory bank, the third local data path including a third precharge circuit, at least one third read multiplexer, and at least one third write multiplexer, the at least one third read multiplexer and the at least one third write multiplexer coupled to the plurality of global bit lines and disposed between the third memory bank and the write driver and the sense amplifier; 2. The RAM of claim 1, further comprising: a fourth local data path associated with the fourth memory bank, the fourth local data path including a fourth precharge circuit, at least one fourth read multiplexer, and at least one fourth write multiplexer, the at least one fourth read multiplexer and the at least one fourth write multiplexer being coupled to the plurality of global bit lines, and the at least one fourth read multiplexer and the at least one fourth write multiplexer being disposed between the fourth memory bank and the write driver and the sense amplifier.

11. a data-out latch coupled to the sense amplifier and located within the centrally located controller; a data-in latch coupled to the write driver and located within the centrally located controller; The RAM of claim 1 further comprising:

12. a header coupling a power source to the third memory bank and the fourth memory bank, the header located within the centrally located controller; an additional header coupling the power supply to the first memory bank, the additional header being disposed between the first memory bank and the third memory bank; The RAM of claim 1 further comprising:

13. a first plurality of bit lines coupling the first read multiplexer to columns in the first memory bank; a second plurality of bit lines coupling a second read multiplexer to columns in the third memory bank; The RAM of claim 1 further comprising:

14. 1. A method of operating a random access memory (RAM) having a first inner memory bank, a first outer memory bank, a second inner memory bank, a second outer memory bank, and a controller disposed between the first inner memory bank and the second inner memory bank, the method comprising: transmitting the data from a write driver to the first outer memory bank through the first write multiplexer associated with the first outer memory bank, the data including transmitting the data on a first plurality of write data lines coupling the controller to a first write multiplexer; transmitting the data from the write driver to the first interior memory bank via the second write multiplexer associated with the first interior memory bank, including transmitting the data on a second plurality of write data lines coupling the controller to a second write multiplexer disposed between the controller and the first interior memory bank; A method comprising:

15. A system-on-chip (SOC) comprising a RAM described in any one of claims 1 to 13.

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