Etching method for semiconductor manufacturing

Abstract

A method of processing a substrate includes patterning a mask over a dielectric layer and etching an opening in the dielectric layer. The dielectric layer is disposed over a substrate. The etching includes flowing an etchant, a polar gas or H-containing gas, and a phosphorus halide gas. The method may further include forming a contact by filling the opening with a conductive material.

Description

[Technical field]

[0001] Cross-references to related patents and applications This application claims priority to and the benefit of the filing date of U.S. Non-provisional Patent Application No. 17 / 704,372, filed March 25, 2022, which is incorporated herein by reference in its entirety.

[0002] The present invention relates generally to semiconductor manufacturing systems and methods, and in particular embodiments to systems and methods for etching dielectric materials with halogenated phosphorus gases. [Background technology]

[0003] Generally, semiconductor devices, such as integrated circuits (ICs), are fabricated by sequentially depositing and patterning layers of dielectric, conductive, and semiconducting materials over a substrate to form a network of monolithically integrated electronic components and interconnect elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias). Many of the processing steps used to form the constituent structures of semiconductor devices are performed using etching processes. Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor industry has repeatedly reduced the minimum feature size of semiconductor devices to a few nanometers to increase the integration density of components. In response, the semiconductor industry is increasingly demanding of etch technologies to provide processes for patterning features with accuracy, precision, and profile control, often at atomic-scale dimensions. Meeting this challenge with the uniformity and repeatability required for high-volume IC production will require further innovation in etch technology. [Means for solving the problem]

[0005] According to one embodiment of the present invention, a method of processing a substrate includes patterning a mask on a dielectric layer disposed over the substrate, etching openings in the dielectric layer, the etching including flowing an etchant, a polar gas or H-containing gas and a phosphorus halide gas, and forming contacts by filling the openings with a conductive material.

[0006] According to another embodiment, a method for processing a substrate includes performing a cyclical etch process, where each cycle of the cyclical etch process includes flowing an etchant over a dielectric layer on a substrate in a process chamber, forming a catalyst in the process chamber by flowing a polar gas or a H-containing gas and a phosphorus halide gas over the dielectric layer in the process chamber, and purging the catalyst from the process chamber.

[0007] According to yet another embodiment, a method of processing a substrate in a process chamber includes flowing an etchant and a polar gas or a H-containing gas over a dielectric layer including an exposed surface of the substrate and performing a periodic tuning process, each cycle of the periodic tuning process including adjusting a temperature of the process chamber and flowing a phosphorus halide gas over the dielectric layer.

[0008] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure, as claimed.

[0009] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0010] [Figure 1]

[0023] Figures 1A-1C show cross-sections of a substrate during an exemplary process of semiconductor manufacturing including an etching process to form high aspect ratio (HAR) features on the substrate, according to various embodiments. Figure 1 shows an incoming substrate including a dielectric layer and a patterned hardmask layer, Figures 2-3 show the substrate during the formation of the high aspect ratio features by the etching process, Figure 4 shows the substrate after completing the etching process, and Figure 5 shows the substrate after the high aspect ratio features have been formed. [Diagram 2]

[0023] Figures 1A-1C show cross-sections of a substrate during an exemplary process of semiconductor manufacturing including an etching process to form high aspect ratio (HAR) features on the substrate, according to various embodiments. Figure 1 shows an incoming substrate including a dielectric layer and a patterned hardmask layer, Figures 2-3 show the substrate during the formation of the high aspect ratio features by the etching process, Figure 4 shows the substrate after completing the etching process, and Figure 5 shows the substrate after the high aspect ratio features have been formed. [Diagram 3]

[0023] Figures 1A-1C show cross-sections of a substrate during an exemplary process of semiconductor manufacturing including an etching process to form high aspect ratio (HAR) features on the substrate, according to various embodiments. Figure 1 shows an incoming substrate including a dielectric layer and a patterned hardmask layer, Figures 2-3 show the substrate during the formation of the high aspect ratio features by the etching process, Figure 4 shows the substrate after completing the etching process, and Figure 5 shows the substrate after the high aspect ratio features have been formed. [Figure 4]

[0023] Figures 1A-1C show cross-sections of a substrate during an exemplary process of semiconductor manufacturing including an etching process to form high aspect ratio (HAR) features on the substrate, according to various embodiments. Figure 1 shows an incoming substrate including a dielectric layer and a patterned hardmask layer, Figures 2-3 show the substrate during the formation of the high aspect ratio features by the etching process, Figure 4 shows the substrate after completing the etching process, and Figure 5 shows the substrate after the high aspect ratio features have been formed. [Diagram 5]

[0023] Figures 1A-1C show cross-sections of a substrate during an exemplary process of semiconductor manufacturing including an etching process to form high aspect ratio (HAR) features on the substrate, according to various embodiments. Figure 1 shows an incoming substrate including a dielectric layer and a patterned hardmask layer, Figures 2-3 show the substrate during the formation of the high aspect ratio features by the etching process, Figure 4 shows the substrate after completing the etching process, and Figure 5 shows the substrate after the high aspect ratio features have been formed. [Figure 6A] 1 illustrates the catalysis of oxide etching by the presence of water, according to various embodiments. [Figure 6B] 1 illustrates the combination of a phosphorus halide with a hydroxyl group to form an acid, according to various embodiments. [Figure 6C] 1 illustrates increased surface moisture retention due to the presence of acidic molecules, according to various embodiments. [Figure 6D] 4 illustrates the etch rate versus flow rate achieved for different fluorine-containing gases according to various embodiments. [Figure 6E] 1 shows quadrupole mass spectrometer (QMS) intensity versus temperature for H2O, HF, and PF2OH according to various embodiments. [Figure 7] 1 shows a process flow chart diagram of a method of etching processing, according to various embodiments. [Figure 8] 1 shows a process flow chart diagram of a method of etching processing, according to various embodiments. [Figure 9] 1 shows a process flow chart diagram of a method of etching processing, according to various embodiments. [Figure 10] 1 illustrates a plasma system for performing semiconductor manufacturing processes, in accordance with various embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Corresponding numerals and symbols in different drawings generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly show relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the drawings do not necessarily indicate the ends of the extents of the features.

[0012] Detailed descriptions of making and using various embodiments are provided below. It should be understood, however, that the various embodiments described herein may be applied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the various embodiments and should not be construed as limiting in scope.

[0013] References to "one embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Thus, phrases such as "in one embodiment" or "in one embodiment" that may appear in one or more places in this specification do not necessarily refer to one and the same embodiment. Furthermore, particular features, structures, or features may be combined in any suitable manner in one or more embodiments.

[0014] References used herein are provided merely for convenience and thus do not define the scope of protection or the region of the embodiments. According to one or more embodiments of the present disclosure, the present application relates to the fabrication of semiconductor devices, such as integrated circuits including semiconductor devices, more specifically large capacity three-dimensional (3D) memory devices, such as 3D-NAND (or vertical NAND), 3D-NOR or dynamic random access memory (DRAM) devices. The fabrication of such devices may generally require forming conformal high aspect ratio features (e.g., contact holes) of circuit elements. Features having an aspect ratio (ratio of feature height to feature width) higher than 50:1 are generally considered to be high aspect ratio features, and in some cases, fabricating higher aspect ratios such as 100:1 may be desired for advanced 3D semiconductor devices. However, conventional high aspect ratio etching methods may typically include tens, sometimes hundreds of processing steps, which complicates process optimization and etching throughput. Thus, a simple yet effective high aspect ratio process may be desired. The embodiments of the present application disclose a method for producing high aspect ratio features by an etching process based on a combination of etchants, polar gases or H-containing gases and phosphorus halide gases. To produce other semiconductor features that are not high aspect ratio features, the etching process can be further applied using, for example, an isotropic etching process. The increased etch rate of the disclosed etching process can enable faster production times and cost reduction.

[0015] The etching methods described in this disclosure may overcome various challenges posed for etching processes for high aspect ratio features. In various embodiments, an etching process using a combination of an etchant, a polar gas or H-containing gas and a phosphorus halide gas, provides an increased etch rate that may be useful for anisotropic etching of high aspect ratio features. The disclosed etching process may also be useful for achieving improved etch rates for isotropic etching processes on dielectric materials.

[0016] In the following, Figures 1-5 first illustrate an exemplary etch process for forming desired high aspect ratio features according to various embodiments. The effect of etch chemistry on etch rate is explained. Next, the principles behind etch chemistry are explained in Figures 6A-6E. Then, exemplary process flow diagrams are shown in Figures 7, 8 and 9. Figure 10 provides an exemplary plasma system for carrying out the process of semiconductor manufacturing according to various embodiments. All figures are drawn for illustrative purposes only and are not to scale.

[0017] 1-5 show cross-sectional views of a substrate 100 during an exemplary process of semiconductor manufacturing including an etching process for forming high aspect ratio features on the substrate, according to various embodiments.

[0018] 1 shows an incoming substrate 100 including a dielectric layer 110 and a patterned hard mask layer 120 (also referred to as a mask). In one or more embodiments, the substrate 100 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In particular embodiments, the substrate may include silicon germanium wafers, silicon carbide wafers, gallium arsenide wafers, gallium nitride wafers, and other compound semiconductors. In other embodiments, the substrate includes heterogeneous layers such as silicon germanium-on-silicon, gallium nitride-on-silicon, silicon carbon-on-silicon, and silicon-on-silicon layers or SOI substrates.

[0019] In various embodiments, the substrate 100 is part of a semiconductor device and may have undergone several steps of processing, such as following conventional processing. For example, a semiconductor structure may include the substrate 100 in which various device regions have been formed. At this stage, the substrate 100 may include isolation regions, such as shallow trench isolation (STI) regions, and other regions formed therein.

[0020] A dielectric layer 110 may be formed over the substrate 100. In various embodiments, the dielectric layer 110 is a target layer that is to be patterned into one or more high aspect ratio features. In certain embodiments, the high aspect ratio features being etched into the dielectric layer 110 may be contact holes, slits, or other suitable structures including recesses. In some embodiments, the dielectric layer 110 comprises an oxide (e.g., silicon oxide), silicon nitride, silicon oxynitride, an O / N / O / N stack (stacked layers of oxide and nitride), and the like. The dielectric layer 110 may be deposited using any suitable technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), vapor deposition including atomic layer deposition (ALD), and other plasma processes such as plasma enhanced CVD (PECVD) and other processes. In one embodiment, the dielectric layer 110 is an O / N / O / N stack and has a total thickness of 1 μm to 10 μm, with each layer of the stack having a thickness in the range of 50 nm to 2.5 μm.

[0021] Still referring to FIG. 1 , a patterned hardmask layer 120 is formed on the dielectric layer 110. In various embodiments, the patterned hardmask layer 120 may include an amorphous carbon layer (ACL). The patterned hardmask layer 120 may be formed by first depositing a hardmask layer using, for example, a suitable spin-coating technique or a vapor deposition technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other plasma processes such as plasma enhanced CVD (PECVD) and other processes. The deposited hardmask layer may then be patterned using lithography and anisotropic etching processes. The relative thicknesses of the patterned hardmask layer 120 and the dielectric layer 110 may have any suitable relationship. For example, the patterned hardmask layer 120 may be thicker than the dielectric layer 110, thinner than the dielectric layer 110, or the same thickness as the dielectric layer 110. In a particular embodiment, the patterned hardmask layer 120 has a thickness in the range of 1 μm to 4 μm.

[0022] The patterned hardmask layer 120 and / or the dielectric layer 110 can collectively be considered part of the substrate 100. Additionally, the substrate 100 can include other layers. For example, to pattern the hardmask layer, there can be a three-layer structure including a photoresist layer, a SiON layer, and an optical planarization layer (OPL).

[0023] 2 shows substrate 100 at the start of an etching process for the formation of one or more high aspect ratio features (e.g., contact plugs formed through a dielectric layer or stack for a memory array). The etching process may be carried out in a process chamber, such as plasma processing chamber 510 (see, e.g., FIG. 10 below). However, any suitable process chamber may be used.

[0024] The creation of high aspect ratio features in the dielectric layer 110 is performed by an etching process using a combination of gases according to various embodiments. Specifically, an etchant 130, a polar gas or H-containing gas 140, and a phosphorus halide gas 150 are used. To achieve the required high aspect ratio, it is advantageous for the etching process to have an increased etch rate. However, the shape of the high aspect ratio openings to be formed may inhibit the supply of etchant radicals at the etch interface on the bottom surface of the high aspect ratio opening. In this way, the disclosed etching process can increase the concentration of the etchant at the etch interface, resulting in a faster etch rate.

[0025] The etchant 130 is a chemical suitable for etching a dielectric material (e.g., the dielectric layer 110) that may be catalyzed by polar molecules held on the exposed surface of the dielectric layer 110. In various embodiments, the etchant 130 is hydrogen fluoride (HF), hydrogen chloride (HCl), or the like, or a combination thereof. The polar gas or H-containing gas 140 is a gas that includes polar molecules or forms polar molecules on the exposed surface of the dielectric layer 110. In various embodiments, the polar gas or H-containing gas 140 includes water vapor (H2O), hydrogen peroxide (H2O2), hydrogen (H2), a mixture of hydrogen (H2) and oxygen (O2), hydrogen bromide (HBr), or the like, or a combination thereof. However, any suitable polar gas or H-containing gas may be used. The phosphorus halide gas 150 interacts with the polar molecules on the exposed surface of the dielectric layer 110 to form a catalyst for the etchant 130. In various embodiments, the halogenated phosphorus gas 150 may be phosphorus trifluoride (PF), phosphorus trichloride (PCl), phosphoryl fluoride (POF), phosphoryl chloride (POCl), or a compound represented by the formula PX n where X represents H, F, Cl, Br, or a combination thereof, or a combination thereof.

[0026] During the etching process, the polar gas or H-containing gas 140 interacts with the phosphorus halide gas 150 to replace the halogen atoms of the phosphorus halide gas 150 with -OH groups to form a phosphorus-containing acid 160. This phosphorus-containing acid 160 acts as a co-adsorbent for polar molecules (e.g., water) and helps retain the etchant 130 on the etch interface of the dielectric layer 110. The resulting higher density of the etchant 130 on the etch interface can advantageously increase the etch rate.

[0027] Hydrogen-containing polar molecules such as water may also be retained on the etch interface of the dielectric layer 110, thereby further catalyzing the reaction of the etchant 130 with the dielectric layer 110. For example, if the etchant 130 is HF, water retained on the etch interface of the dielectric layer 110 may react with the HF to produce hydrofluoric acid, thereby increasing the etch rate. Phosphorus-containing acids 160 may further catalyze the reaction of the etchant 130 with the dielectric layer 110.

[0028] 3 shows substrate 100 at a later stage of an etching process for the formation of one or more high aspect ratio features. An opening 170 having a high aspect ratio extends into dielectric layer 110. The etching process shown in FIG. 3 is anisotropic, and thus opening 170 is produced with a high aspect ratio.

[0029] In some embodiments, anisotropic etching is possible by providing the etchant 130, the polar gas or H-containing gas 140, and the halogenated phosphorus gas 150 using a plasma process carried out in a suitable plasma processing system as described below with respect to FIG. 10. Due to the induced plasma bombardment, the phosphorus-containing acid 160 and polar molecules (e.g., water, hydroxyl, etc.) are formed to a greater extent on the bottom surface of the opening 170 than on the sidewalls of the opening 170. The high power of the plasma process can induce a reaction between the polar gas or H-containing gas 140 and the oxygen or nitrogen atoms of the dielectric layer 110 to selectively form the polar molecules on the bottom surface of the opening 170. The polar molecules on the bottom surface of the opening 170 then interact with the halogenated phosphorus gas 150 to form the phosphorus-containing acid 160 as a co-adsorbed material on the bottom surface of the opening 170. The plasma process also provides the etchant 130 to a greater extent on the bottom surface of the opening 170 than on the sidewalls of the opening 170. In addition, the greater amount of polar molecules on the bottom surface of the opening 170 helps to further retain the etchant 130. This may direct the catalytic reaction of the etchant 130 with the material of the dielectric layer 110 primarily toward the substrate 100, allowing for anisotropic etching.

[0030] In some embodiments, isotropic etching is possible without plasma treatment by tuning the flow rates of the hydrocarbon gas and the phosphorus-containing gas to promote adsorption of HO and the etchant 130 on the exposed surfaces of the opening 170. This can catalyze the isotropic etching process by the etchant 130 on the exposed surfaces of the opening 170.

[0031] 2-3, sufficient etch rates also enable openings 170 to have high aspect ratios in a short process time compared to conventional high aspect ratio etch methods, while only a small percentage of patterned hardmask layer 120 may be consumed due to good selectivity to patterned hardmask layer 120 during the etching process.

[0032] 4, the patterned hardmask layer 120 is removed from over the dielectric layer 110 and the residue from the etch process is removed. The patterned hardmask layer 120 may be removed using a suitable process, such as a planarization process (e.g., CMP), etc. In some embodiments, the residue from the etch process is removed with a suitable cleaning process, such as rinsing with deionized water, hydrogen peroxide, SC-1, the like, or a combination thereof.

[0033] In FIG. 5, a conductive feature 180 is formed in the opening 170 (see FIG. 4 above). In various embodiments, the conductive feature 180 is a high aspect ratio feature. The conductive feature 180 may be formed to physically and electrically couple to a conductive portion of the substrate 100. As an example of forming the conductive feature 180, a conformal barrier metal (e.g., TiN or TaN) liner is formed on the exposed surface of the dielectric layer 110 and the substrate 100. The opening 170 is then filled with a conductive material, such as a metal. For example, the conductive material may be copper, formed using electroplating. However, any suitable conductive material and deposition method may be used. A planarization process (e.g., CMP) is then used to remove excess conductive material from the top surface of the dielectric layer 110, thereby forming the conductive feature 180 inlaid in the dielectric layer 110.

[0034] FIG. 6A illustrates modeling of the catalysis of oxide etching by the presence of water, according to various embodiments. Various surface energies and reaction barriers can be calculated using suitable methods, such as density functional theory. On the left side, the molecular or atomic structure of the oxide is shown. The oxide may contain silicon atoms (e.g., the oxide may be silicon oxide), and the oxide may have hydroxyl (OH) groups on its surface. The etchant HF may displace the hydroxyl groups, and fluorine atoms F may bond with the silicon atoms to form SiF groups. This process may decompose and etch away the oxide. However, the predicted reaction barrier for the chemical reaction of HF with the oxide is 0.76 eV. As shown in the bottom center, when a polar molecule (e.g., HO) is added and attached to the surface of the oxide, the polar molecule may act as a catalyst for the reaction, since the attachment of HO to the oxide surface is favored (e.g., with an energy state 0.24 eV lower than the initial state). Thereafter, the oxide is further favored (e.g., with an energy state 0.33 eV lower than the initial state) to react with the deposited HO to form an etched oxide (e.g., with SiF groups) and HO. Although FIG. 6A shows oxide as the dielectric material, HF as the etchant, and HO as the polar molecule, catalysis may be possible with other dielectric materials (e.g., nitrides), etchants (e.g., HCl), or polar molecules or H-containing gases (e.g., HBr). Thus, FIG. 6A shows that polar molecules may allow for an increase in the etch rate of the dielectric material by reducing the reaction barrier energy.

[0035] 6B illustrates the formation of an acid by combination of a phosphorus halide with a hydroxyl group, according to various embodiments. For example, a phosphorus halide can react with HO such that a hydroxyl (-OH) group replaces a halogen atom of the phosphorus halide to form a phosphorus-containing acid. The reaction can be described by equation (1): PX n +Y-OH→PX n-1 OH+YX (1)

[0036] In the above formula (1), X represents a halogen atom (e.g., fluorine, chlorine, etc.) and Y represents an atom or group of atoms bonded to a hydroxyl (-OH) group. n and the Y-OH system is the product PX n-1 In the example illustrating the hydrolysis reaction to form OH and YX, Y is a hydrogen atom, Y-OH is a water (HO) molecule, and PX n-1 OH represents a phosphorus-containing acid, and YX represents a hydrogen atom attached to one of the halogen atoms X. PX n If PX is PF3, the hydrolysis reaction may have a change in the internal energy of the system, ΔE, of -0.1 eV. n If PX is PCl3, the hydrolysis reaction may have a change in the internal energy of the system, ΔE, of -0.2 eV. n If PX is POF3, the hydrolysis reaction may have a change in the internal energy of the system, ΔE, of -0.3 eV. n If PX is POCl3, the hydrolysis reaction may have a change in the internal energy of the system, ΔE, of -0.33 eV. However, any suitable PX n The gas may also react with polar or H-containing gases to form phosphorus-containing acids.

[0037] FIG. 6C shows modeling data of increased surface moisture retention due to the presence of acidic molecules, according to various embodiments. The atomic structure of an oxide (e.g., silicon oxide) with bonded fluorine atoms, such as may be produced during an oxide etching process using HF, is shown in the top left. The oxide surface may be relatively hydrophobic due to the presence of fluorine atoms. In the top right, the adsorption response of the oxide to water is shown. The adsorption energy E of water on the oxide surface is ads (H2O) can be -0.24 eV.

[0038] As further shown in FIG. 6C, the adsorption of water on oxide surfaces can be catalyzed by the co-adsorption of phosphorus-containing acids. At the bottom left, the adsorption reaction of phosphorus-containing acid molecules (α-OH, where α contains phosphorus) on an oxide is shown. The adsorption energy of water on an oxide surface, E ads(HO) can be -0.50 eV. The further adsorption reaction of the phosphorus-containing acid oxide with water is shown at the bottom right, with the adsorption energy E ads (HO) is -0.54 eV. The adsorption energy E without coadsorbed phosphorus-containing acid ads (HO), the total adsorption energy is more than twice as large. This increased adsorption energy in the presence of co-adsorbed phosphorus-containing acid can increase the concentration of water (or other polar molecules) adsorbed on the oxide surface, thereby increasing the catalysis of the etching reaction and broadening the operating conditions of the etching process. Increased water adsorption by the co-adsorption reaction with phosphorus-containing acid can also reduce the water vapor pressure, which can increase the operating temperature window of the catalyzed etching process.

[0039] FIG. 6D shows experimental results of etch rate versus flow rate achieved for different fluorine-containing gases according to various embodiments. The x-axis shows the relative flow rates of different fluorine-containing gases PF3, NF3, and SF6 flowed during the respective etching process on oxide (e.g., silicon oxide etching process using HF), and the y-axis shows the relative etch rate (oxide etch rate) of the respective etching process on oxide. As shown in FIG. 6D, the relative etch rate increases most proportionally with the increase in flow rate for PF3, which contains phosphorus, compared to NF3 and SF6, which do not contain phosphorus. This large increase in etch rate with PF3 occurs even when NF3 and SF6 provide the same or more fluorine as PF3. This suggests that the larger increase in etch rate observed by flowing PF3 may be due to the presence of phosphorus, which may catalyze the etching process by the mechanism described above with respect to FIG. 2 and FIG. 6C.

[0040] FIG. 6E shows experimentally measured normalized quadrupole mass spectrometer (QMS) intensity versus temperature for HF, HO, and PFOH during an etching process performed by flowing HF, HO, and PF3 over an oxide (e.g., silicon oxide) according to various embodiments. As the temperature decreases, the normalized QMS intensity of HF and HO decreases, indicating an increase in the adsorption of HF and HO on the oxide surface. In addition, the normalized QMS intensity of PFOH increases with decreasing temperature, meaning that a greater amount of PFOH is due to a greater amount of hydrolysis reaction near the oxide surface due to an increase in the amount of adsorbed HO. This further suggests that the increase in the etch rate in FIG. 6D observed by including PF3 may be due to the formation of a co-adsorbed species of PFOH catalyzing the adsorption of water and the etch reaction of HF being further catalyzed by the adsorbed water.

[0041] 7 shows a process flow diagram of a method 200 of continuous catalytic etch processing, according to some embodiments. In step 202, a mask (e.g., patterned hard mask layer 120) is patterned over dielectric layer 110, as described above with respect to FIG.

[0042] In step 204, an opening 170 is etched in the dielectric layer 110 by flowing the etchant 130, the polar gas or H-containing gas 140, and the halogenated phosphorus gas 150, as described above with respect to Figures 2-3. The etching process is a sequential catalytic etch in which the etchant 130, the polar gas or H-containing gas 140, and the halogenated phosphorus gas 150 are sequentially flowed into a process chamber containing the dielectric layer 110. The polar gas or H-containing gas 140 interacts with the halogenated phosphorus gas 150 to replace the halogen atoms of the halogenated phosphorus gas 150 with -OH groups to form a phosphorus-containing acid 160. This phosphorus-containing acid 160 acts as a co-adsorbent, helping to retain polar molecules (e.g., water, hydroxyl, etc.) with the etchant 130 on the etching interface of the dielectric layer 110. The resulting higher density of the etchant 130 and polar molecules (e.g., water, hydroxyl, etc.) on the etching interface can catalyze the etching process and increase the etch rate.

[0043] In some embodiments, the successive catalytic etches are anisotropic plasma etches performed using a plasma processing system (see FIG. 10 below). In some embodiments, the successive catalytic etches are isotropic etches. The isotropic etches may be performed by tuning the flow rates of the hydrocarbon gas and the phosphorus-containing gas to promote adsorption of HO and the etchant 130 on the exposed surfaces of the opening 170, thereby catalyzing the isotropic etching process.

[0044] In one embodiment of the continuous catalytic plasma etch, the flow rate of the etchant 130 (e.g., HF, HCl, etc.) ranges from 1 sccm to 1000 sccm, the flow rate of the polar or H-containing gas 140 (e.g., HO, HBr, etc.) ranges from 1 sccm to 1000 sccm, and the flow rate of the phosphorus halide gas 150 ranges from 1 sccm to 1000 sccm. The continuous catalytic plasma etch is performed at a temperature ranging from -200°C to 250°C and a pressure ranging from 0.1 mTorr to 1000 mTorr. The continuous catalytic plasma etch is performed with a plasma power ranging from 50W to 15000W.

[0045] In step 206, conductive features 180 (e.g., contact plugs for a memory array) are formed by filling openings 170 with a conductive material, as described above with respect to Figure 5. Conductive features 180 may be high aspect ratio features, for example, having an aspect ratio of greater than 50:1.

[0046] 8 shows a process flow diagram of a method 300 of a quasi-atomic layer catalytic etching process according to some embodiments. The quasi-atomic layer catalytic etching process may improve the controllability of the etching process, such as increasing the anisotropy of the opening 170 formed (see FIG. 3) or controlling the etching depth.

[0047] In step 302, an etchant 130 (e.g., HF, HCl, etc.) is flowed over the dielectric layer 110 in a process chamber. In one embodiment, the flow rate of the etchant 130 is in the range of 1 sccm to 1000 sccm. The etchant 130 is flowed for a period in the range of 1 second to 300 seconds, at a temperature in the range of -200°C to 50°C, and at a pressure in the range of 0.1 mTorr to 1000 mTorr. A small amount of the etchant 130 (e.g., a monolayer or bilayer) is formed on the exposed surface of the dielectric layer 110.

[0048] In step 304, a catalyst for the etching process is formed by flowing a polar or H-containing gas 140 (e.g., HO, HBr, etc.) and a phosphorus halide gas 150 into the process chamber containing the dielectric layer 110. The phosphorus halide gas 150 interacts with the polar or H-containing gas 140 to form catalysts such as phosphorus-containing acids 160 (see FIGS. 2-3 above) and polar molecules on the etching interface of the dielectric layer 110. This catalyzes the etching process and increases the etch rate, as described above with respect to FIGS. 2-3. The etching process consumes a small amount of the etchant on the exposed surface of the dielectric layer 110, leaving catalysts such as phosphorus-containing acids 160 and polar molecules.

[0049] In some embodiments, forming the catalyst includes a flow rate of the polar gas or H-containing gas 140 in the range of 1 sccm to 1000 sccm and a flow rate of the phosphorus halide gas 150 in the range of 0.1 sccm to 1000 sccm. The polar gas or H-containing gas 140 and the phosphorus halide gas 150 are flowed for a period in the range of 1 second to 300 seconds, at a temperature in the range of -200°C to 250°C, and at a pressure in the range of 0.1 mTorr to 1000 mTorr.

[0050] In step 306, the process chamber is purged to remove any remaining catalyst, such as the phosphorus-containing acid 160 and polar molecules. Any remaining etchant 130 may be purged. Purging may be performed by flowing an inert gas (e.g., argon, etc.) into the process chamber, evacuating the process chamber with a vacuum pump, or a combination thereof. Using purging to remove the catalyst may improve the controllability of subsequent steps of the sub-atomic layer catalytic etch process, such as to etch a desired amount of the dielectric layer 110 at each etching step to achieve a desired shape of the opening 170 formed (see FIG. 3 above).

[0051] Steps 302-306 may be repeated for any suitable number of cycles to etch the dielectric layer 110 to a desired depth. In some embodiments, the sub-atomic layer catalytic etch process includes between 1 and 1000 cycles of steps 302-306.

[0052] 9 shows a process flow diagram of a method 400 for an etching process with temperature tuning, according to some embodiments. By tuning the temperature, the temperature and the etch rate can be decoupled, thereby achieving a desired etch rate.

[0053] In step 402, an etchant 130 (e.g., HF or HCl) and a polar or H-containing gas 140 (e.g., H2O, H2O2, H2, HBr, etc., or combinations thereof) are flowed over the dielectric layer 110 in a process chamber. In one embodiment, the flow rate of the etchant 130 ranges from 1 sccm to 1000 sccm, and the flow rate of the polar or H-containing gas 140 ranges from 1 sccm to 1000 sccm. The etchant 130 and the polar or H-containing gas 140 are flowed at a pressure ranging from 1 mTorr to 1000 mTorr for a period ranging from 1 second to 300 seconds. The temperature in the process chamber in step 402 ranges from -200°C to 250°C, which is useful for controlling the amount of polar or H-containing gas 140 that is retained on the surface of the dielectric layer 110. For example, a lower temperature can increase the amount of polar or H-containing gas 140 that is retained on the surface of the dielectric layer 110, which is advantageous for increasing the etch rate.

[0054] In step 404, the temperature of the process chamber is adjusted to provide the desired etch rate. In some embodiments, the initial process temperature in the first cycle of method 400 ranges from −200° C. to 250° C. In subsequent cycles, the temperature can be tuned upward or downward as appropriate to change the etch rate.

[0055] In step 406, a phosphorus halide gas 150 is flowed into the process chamber. The phosphorus halide gas 150 interacts with the polar or H-containing gas to form catalysts such as phosphorus-containing acids 160 (see FIGS. 2-3 above) and polar molecules on the etch interface of the dielectric layer 110. This catalyzes the etching process and increases the etch rate, as described above with respect to FIGS. 2-3. The interaction of the phosphorus halide gas 150 with the polar or H-containing gas and the subsequent catalysis of the reaction of the etchant 130 on the dielectric layer 110 can be controlled by the temperature of the process temperature set in step 404.

[0056] In one embodiment, the phosphorus halide gas 150 is flowed into the process chamber at a pressure ranging from 0.1 mTorr to 1000 mTorr for a period ranging from 1 second to 300 seconds at a flow rate ranging from 1 sccm to 1000 sccm. The flow rate of the phosphorus halide gas 150 can be increased or decreased with each iteration step 406 to achieve the desired etch rate.

[0057] Steps 404-406 may be repeated for any suitable number of cycles to etch the dielectric layer 110 to a desired depth. In some embodiments, the process includes 1 to 1000 cycles of steps 404-406. The temperature of the process chamber may be tuned at each step 404 to achieve a desired etch rate at step 406.

[0058] FIG. 10 illustrates a plasma processing system 500 for performing a semiconductor manufacturing process, according to various embodiments. For illustration purposes, FIG. 10 illustrates a substrate 100 disposed on a substrate holder 554 (e.g., a circular electrostatic chuck (ESC)) inside a plasma processing chamber 510 near the bottom. The substrate 100 may optionally be maintained at a desired temperature using a heater / cooler 556 surrounding the substrate holder 554. The temperature of the substrate 100 may be maintained by a temperature controller 540 connected to the substrate holder 554 and the heater / cooler 556. The ESC may be coated with a conductive material (e.g., a carbon-based or metal nitride-based coating) so that an electrical connection may be made to the substrate holder 554.

[0059] As shown in Figure 10, the substrate holder 554 can be the bottom electrode of the plasma processing chamber 510. In the illustrative example of Figure 5, the substrate holder 554 is connected to two RF bias power supplies 570 and 580 through blocking capacitors 590 and 591. In some embodiments, a conductive circular plate near the top inside the plasma processing chamber 510 is the top electrode 552. In Figure 5, the top electrode 552 is connected to a DC power supply 550 of the plasma processing system 500.

[0060] Gases may be introduced into the plasma processing chamber 510 by a gas delivery system 520. The gas delivery system 520 includes multiple gas flow controllers for controlling the flow of multiple gases into the chamber. Each gas flow controller of the gas delivery system 520 may be assigned to each of the etchant 130, the polar or H-containing gas 140, and / or the phosphorus halide gas 150 (see Figures 2-3 above). In some embodiments, an optional center / edge splitter may be used to independently adjust the gas flow rates at the center and edges of the substrate 100.

[0061] RF bias power supplies 570 and 580 may be used to supply continuous wave (CW) power or pulsed RF power to maintain a plasma such as plasma 560. The plasma 560 shown between the top electrode 552 and the bottom electrode (which is also the substrate holder 554) illustrates a direct plasma generated near the substrate 100 in the plasma processing chamber 510 of the plasma processing system 500. The plasma 560 may contain ions from the etchant 130, the polar or H-containing gas 140, and / or the phosphorus halide gas 150. Etching may be performed by exposing the substrate 100 to the plasma 560 while powering the substrate holder 554 with the RF bias power supplies 570, 580 and powering the top electrode 552 with the DC power supply 550. The etching process performed may be etching of high aspect ratio features as described above in Figures 2-3 using method 200 (see Figure 7 above), method 300 (see Figure 8 above), method 400 (see Figure 9 above), etc., or combinations thereof.

[0062] The configuration of the plasma processing system 500 described above is merely exemplary. In alternative embodiments, various alternative configurations of the plasma processing system 500 can be used. For example, an inductively coupled plasma (ICP) can be used with RF source power coupled to a planar coil above a top dielectric cover, gas inlets and / or gas outlets can be coupled to a top wall, etc. In various embodiments, RF power, chamber pressure, substrate temperature, gas flow rates, and other plasma processing parameters can be selected according to a respective process recipe. In some embodiments, the plasma processing system 500 can be a resonator, such as a helical resonator.

[0063] Although not described herein, embodiments of the present invention may also be applied to remote plasma systems and batch systems, For example, a substrate holder may be capable of supporting multiple wafers that are spun about a central axis as they pass through different plasma zones.

[0064]

[0023] Exemplary embodiments of the present disclosure are summarized herein. Other embodiments can be seen throughout this specification and the claims of this application.

[0065] Example 1. A method of processing a substrate comprising: patterning a mask over a dielectric layer disposed over the substrate; etching openings in the dielectric layer, the etching comprising flowing an etchant, a polar gas or H-containing gas and a phosphorus halide gas; and forming contacts by filling the openings with a conductive material.

[0066] Example 2. The method of example 1, wherein the etching agent is HF or HCl.

[0067] Example 3. The method of example 1, wherein the polar gas or H-containing gas comprises water vapor (H2O), hydrogen peroxide (H2O2), hydrogen (H2), a mixture of hydrogen (H2) and oxygen (O2), or hydrogen bromide (HBr).

[0068] Example 4. The method of Example 1, wherein the halogenated phosphorus gas comprises phosphorus trifluoride (PF3), phosphorus trichloride (PCl3), phosphoryl fluoride (POF3) or phosphoryl chloride (POCl3).

[0069] Example 5. The method of example 1, wherein the dielectric layer comprises silicon oxide or silicon nitride.

[0070] Example 6. The method of example 5, wherein the dielectric layer comprises an O / N / O / N stack.

[0071] Example 7. The method of example 1, wherein the etching is anisotropically etching the opening with an anisotropic etching process.

[0072] Example 8. The method of example 7, wherein the anisotropic etching process is performed as a plasma process in a plasma processing system.

[0073] Example 9. The method of example 1, wherein the contacts have respective aspect ratios of greater than 50:1.

[0074] Example 10. A method for processing a substrate, comprising performing a cyclic etching process, each cycle of the cyclic etching process comprising flowing an etchant over a dielectric layer on the substrate in a process chamber, forming a catalyst in the process chamber by flowing a polar gas or a H-containing gas and a phosphorus halide gas over the dielectric layer in the process chamber, and purging the catalyst from the process chamber.

[0075] Example 11. The method of example 10, wherein the etching agent is HF.

[0076] Example 12. The method of example 10, wherein the halogenated phosphorus gas is phosphorus trifluoride (PF3).

[0077] Example 13. The method of example 10, wherein the catalyst comprises PF2OH.

[0078] Example 14. The method of example 10, wherein the etching process is a plasma process.

[0079] Example 15. The method of example 10, wherein the etching process is anisotropic.

[0080] Example 16. A method of processing a substrate in a process chamber, the method comprising: flowing an etchant and a polar gas or a H-containing gas over a dielectric layer including an exposed surface of the substrate; and performing a periodic tuning process, each cycle of the periodic tuning process comprising adjusting a temperature of the process chamber and flowing a phosphorus halide gas over the dielectric layer.

[0081] Example 17. The method of example 16, wherein the polar gas or H-containing gas comprises HO.

[0082] Example 18. The method of example 16, wherein the halogenated phosphorus gas contains phosphorus and fluorine.

[0083] Example 19. The method of example 16, wherein the dielectric layer comprises silicon oxide.

[0084] Example 20. The method of example 16, further comprising forming an opening in the dielectric layer, the opening having an aspect ratio of greater than 50:1.

[0085] Although the present invention has been described with reference to exemplary embodiments, this specification is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present disclosure, will be apparent to those skilled in the art upon reference to this specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. 1. A method of processing a substrate, comprising: patterning a mask onto a dielectric layer disposed over the substrate; Etching an opening in the dielectric layer, the etching comprising flowing an etchant, a polar gas or a H-containing gas, and a phosphorus halide gas; forming a catalyst comprising a phosphorus-containing acid; filling the opening with a conductive material to form a contact; A method comprising:

2. The method of claim 1 , wherein the etchant is HF or HCl.

3. The polar gas or H-containing gas is water vapor (H ２ O), hydrogen peroxide (H ２ O ２ ), hydrogen (H ２ ), hydrogen (H ２ ) and oxygen (O ２ 2. The method of claim 1 , wherein the amine is a hydroxybenzoate (H2SO4), ... or a mixture of hydroxybenzoates with hydrogen bromide (HBr).

4. The halogenated phosphorus gas is phosphorus trifluoride (PF ３ ), phosphorus trichloride (PCl ３ ), phosphoryl fluoride (POF ３ ), or phosphoryl chloride (POCl ３ 10. The method of claim 1, comprising:

5. The method of claim 1 , wherein the dielectric layer comprises silicon oxide or silicon nitride.

6. The method of claim 5 , wherein the dielectric layer comprises an O / N / O / N stack.

7. The method of claim 1 , wherein said etching step anisotropically etches said openings in an anisotropic etching process.

8. The method of claim 7 , wherein the anisotropic etching process is performed as a plasma process in a plasma processing system.

9. The method of claim 1 , wherein the contacts have a respective aspect ratio greater than 50:

1.

10. 1. A method of processing a substrate, comprising: performing a cyclic etching process; Each cycle of the cyclic etching process comprises: flowing an etchant over a dielectric layer on the substrate in a process chamber; forming a catalyst in the process chamber by simultaneously flowing a polar gas or an H-containing gas and a phosphorus halide gas over the dielectric layer in the process chamber; purging the catalyst from the process chamber; A method comprising:

11. The method of claim 10, wherein the etchant is HF.

12. The halogenated phosphorus gas is phosphorus trifluoride (PF ３ 11. The method of claim 10, wherein

13. The catalyst is PF ２ 11. The method of claim 10, comprising OH.

14. The method of claim 10 , wherein the cyclical etching process is a plasma process.

15. The method of claim 10 , wherein the cyclic etching process is anisotropic.

16. 1. A method for processing a substrate in a process chamber, comprising: co-flowing an etchant and a polar or H-containing gas over the dielectric layer having the exposed surface of the substrate; performing a periodic tuning process; and Each cycle of the periodic tuning process comprises: adjusting the temperature of the process chamber; flowing a phosphorus halide gas over the dielectric layer; A method comprising:

17. The polar gas or H-containing gas is H ２ 17. The method of claim 16, comprising:

18. 17. The method of claim 16, wherein the halogenated phosphorus gas comprises phosphorus and fluorine.

19. The method of claim 16 , wherein the dielectric layer comprises silicon oxide.

20. further comprising forming an opening in the dielectric layer; The method of claim 16 , wherein the opening has an aspect ratio greater than 50:1.

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