Semiconductor optoelectronic integrated circuit using gate-all-around epitaxial structure and method for manufacturing same

Abstract

The integrated circuit is fabricated from a semiconductor layer formed on a substrate, the semiconductor layer having a p-type gate all around (GAA) layer structure having a plurality of quantum well structures formed between a pair of vertically spaced p-type thin doped layers. A p-type layer is formed on the p-type gate all around layer structure. P-type ions are implanted into exposed portions of the p-type layer to extend through the p-type GAA layer structure and contact the thin p-type doped layer of the p-type gate all around layer structure. A gate electrode of the n-channel HFET device is formed in contact with the ion implanted p-type region(s). Source and drain electrodes of the n-channel HFET device are formed in contact with the ion implanted n-type region that contacts the plurality of quantum well structures of the p-type GAA layer structure. P-channel GAA HFET devices, complementary BICFET devices, stacked complementary HFET devices and other circuits and optoelectronic and optical devices may also be formed as part of the integrated circuit.

Description

[Technical field]

[0001] This application relates to semiconductor optoelectronic integrated circuits implementing electronic functions (such as heterojunction field effect transistors), optoelectronic functions (such as light emitters, photodetectors and optical switches, active waveguides) and optical functions (such as passive waveguides and couplers) and methods for manufacturing such integrated circuits. [Background technology]

[0002] This application is a continuation of U.S. Patent No. 6,031,243, U.S. Patent Application No. 09 / 556,285, filed April 24, 2000, U.S. Patent Application No. 09 / 798,316, filed March 2, 2001, International Application No. PCT / US02 / 06802, filed March 4, 2002, U.S. Patent Application No. 08 / 949,504, filed October 14, 1997, U.S. Patent Application No. 10 / 2002, filed July 23, 2002, and U.S. Patent Application No. 11 / 2002, filed May 29, 2002. No. 200,967, U.S. Patent Application No. 09 / 710,217 filed November 10, 2000, U.S. Patent Application No. 60 / 376,238 filed April 26, 2002, U.S. Patent Application No. 10 / 323,390 filed December 19, 2002, U.S. Patent Application No. 10 / 280,892 filed October 25, 2002, U.S. Patent Application No. 10 / 323,390 filed December 19, 2002, U.S. Patent Application No. 10 / 323,513 filed December 19, 2002, U.S. Patent Application No. 10 / 323,389 filed December 19, 2002, U.S. Patent Application No. 10 / 323,388 filed December 19, 2002, U.S. Patent Application No. 10 / 340,942 filed January 13, 2003, U.S. Patent Application No. 13 / 921,311 filed June 19, 2013, U.S. Patent Application No. 13 / 102,311 filed March 24, 2014, No. 14 / 222,841, filed on Mar. 6, 2017, and U.S. patent application Ser. No. 15 / 450,400, filed on Mar. 6, 2017, all of which are incorporated herein by reference in their entireties.

[0003] These structures can utilize fabrication sequences to create devices on a common substrate. In other words, n-type contacts, p-type contacts, critical etching, etc. can be used to monolithically realize all of these devices on a common substrate. The essential features of this device structure include: 1) a non-inverted n-type modulation doped structure vertically offset from an inverted p-type modulation doped quantum well structure by an undoped spacer region; 2) a self-aligned n-type channel contact formed by implanted n-type ions contacting the non-inverted n-type modulation doped structure; 3) a self-aligned p-type channel contact formed by implanted p-type ions contacting the inverted p-type modulation doped structure; 4) an n-type metal formed on a lower n-type layer disposed on the n-type channel contact and below the inverted p-type modulation doped quantum well structure; and 5) a p-type metal formed on an upper p-type layer disposed on the p-type channel contact and above the non-inverted n-type modulation doped quantum well structure. The active device structure is preferably realized in a compound semiconductor system of III-V materials (such as GaAs / AlGAAs). Summary of the Invention [Problem to be solved by the invention]

[0004] POET can be used to construct a variety of high performance transistor devices, such as complementary NHFET unipolar field effect transistors, complementary PHFET unipolar field effect transistors, and complementary bipolar field effect transistors.

[0005] An NHFET transistor (or n-channel HFET transistor) employs an n-type modulation doped quantum well interface with an n-type charge sheet disposed above one or more quantum wells. The quantum well(s) form an active channel for conducting electronic charge carriers between source and drain electrode terminals. A heavily doped p-type layer spaced above the n-type charge sheet forms a gate region that applies an electric field that controls the flow of electronic charge carriers through the active channel formed by the quantum well(s). In this configuration, the inverted p-type modulation doped quantum well structure functions as the backgate terminal of the n-type HFET transistor device.

[0006] A PHFET transistor (or p-channel HFET transistor) employs an inverted p-type modulation doped quantum well structure that includes a p-type charge sheet disposed beneath one or more quantum wells. The quantum wells of the inverted p-type modulation doped quantum well structure form an active channel for conduction of hole charge carriers between the source and drain electrode terminals. A heavily doped n-type layer spaced beneath the p-type charge sheet forms a gate region that applies an electric field that controls the flow of hole charge carriers through the active channel formed by the quantum wells. In this configuration, the non-inverted n-type modulation doped quantum well structure functions as the backgate terminal of the p-type HFET transistor device.

[0007] In both NFET and PHFET transistor devices, the channel charge is modulated by the gate from only one side, and the backgate is DC biased to control the onset of inversion and channel conductivity. Such structures are suitable for long channel lengths in the range of more than 100 μm. In aggressively scaled structures with gate lengths less than 100 μm, the presence of the backgate region leads to degradation of the output resistance and subthreshold turn-off slope as a result of drain-induced barrier lowering (dibl). [Means for solving the problem]

[0008] In accordance with the present disclosure, semiconductor devices are formed from a novel epitaxial layer structure adapted to provide a gate all around (GAA) layer structure for both NHFET and PHFET transistor devices that eliminates contributions from the back gate region of these transistor devices.

[0009] In an embodiment, the GAA layer structure for a PHFET transistor device, referred to herein as the "first GAA layer structure", has a pair of quantum well structures (e.g., an inverted p-type modulation doped quantum well structure disposed below a non-inverted p-type modulation doped quantum well structure) disposed between thin n-type doped layers (e.g., nanosheets) that are vertically spaced apart from one another. One or more additional pair of quantum well structures (e.g., an inverted p-type modulation doped quantum well structure disposed below a non-inverted p-type modulation doped quantum well structure) disposed between thin n-type doped layers (e.g., nanosheets) that are vertically spaced apart from one another may also be used. In this configuration, the thin n-type doped layers are disposed adjacent (preferably in contact with) the upper and lower boundaries of the p-type modulation doped quantum well structure. The thin n-type doped layers form gate regions adjacent to the upper and lower boundaries of the p-type modulation doped quantum well structure. These gate regions may be configured to apply an electric field that controls the flow of hole charge carriers through an active channel formed by the quantum wells of the p-type modulation doped quantum well structure for the NHFET transistor device. A gate contact for the PHFET transistor device is provided by n-type ions implanted to a depth sufficient to contact the n-type thin doped layers disposed above and below the quantum well structure of the first GAA layer structure, and a source contact and a drain contact for the PHFET transistor device are provided by p-type ions implanted to a depth sufficient to contact the quantum well structure of the first GAA layer structure.

[0010] In an embodiment, the GAA layer structure for the NHFET transistor device, referred to herein as the "second GAA layer structure", has a pair of quantum well structures (e.g., an inverted n-type modulation doped quantum well structure disposed below a non-inverted n-type modulation doped quantum well structure) disposed between thin p-type doped layers (e.g., nanosheets) that are vertically spaced apart from one another. One or more additional pair of quantum well structures (e.g., an inverted n-type modulation doped quantum well structure disposed below a non-inverted n-type modulation doped quantum well structure) disposed between thin p-type doped layers (e.g., nanosheets) that are vertically spaced apart from one another may also be used. In this configuration, the thin p-type doped layers are disposed adjacent (preferably in contact with) the upper and lower boundaries of the n-type modulation doped quantum well structure. The thin p-type doped layers form gate regions adjacent to the upper and lower boundaries of the n-type modulation doped quantum well structure. These gate regions may be configured to apply an electric field that controls the flow of electronic charge carriers through the active channel formed by the quantum wells of the n-type modulation doped quantum well structure for the NHFET transistor device. A gate contact for the NHFET transistor device is provided by p-type ions implanted to a depth sufficient to contact thin p-type doped layers disposed above and below the quantum well structure of the second GAA layer structure, and source and drain contacts for the NHFET transistor device are provided by n-type ions implanted to a depth sufficient to contact the quantum well structure of the second GAA layer structure.

[0011] In an embodiment, the intermediate layer structure is disposed between the first GAA layer structure and the second GAA layer structure. In one embodiment, the intermediate layer structure can have an inverted p-type modulation doped quantum well structure vertically spaced apart by an undoped spacer layer below a non-inverted n-type modulation doped quantum well structure. This one embodiment can be used to implement a non-digital optical device (e.g., a laser in which a decrease in voltage can cause an increase in current, a photodetector in which an increase in current can cause a decrease in voltage, or an optical modulator that can operate in either mode). In another embodiment, the intermediate layer structure can have one or more undoped spacer layers, thus omitting the inverted p-type modulation doped quantum well structure vertically spaced apart below the non-inverted n-type modulation doped quantum well structure. This other embodiment can be used to implement an analog optical device (e.g., a laser in which an increase in voltage can cause an increase in current, a photodetector in which a decrease in current can cause a decrease in voltage, or an optical modulator that can operate in either mode).

[0012] Semiconductor devices formed from the novel epitaxial layer structures offer many advantages, including: negligible dibl, Maximizing gm, Smaller HFET capacitance for faster operation Reduced footprint, and This includes decoupling of a given layer structure implementing HFET transistors from a particular layer structure implementing complementary bipolar field effect transistors and digital optical devices (e.g. lasers where a decrease in voltage can cause an increase in current, photodetectors where an increase in current can cause a decrease in voltage, or optical modulators that can operate in either mode) to allow optimization of different device design parameters and scaling in the sub-100 μm region.

[0013] In an embodiment, an HFET transistor device implemented using the first and second GAA layer structures described herein can be characterized by a lower threshold voltage than the corresponding quantum well channels of the non-inverted n-type modulation doped quantum well structure and the inverted p-type modulation doped quantum well structure of the interlayer structure. In this configuration, the quantum well channels of the non-inverted n-type modulation doped quantum well structure and the inverted p-type modulation doped quantum well structure of the interlayer structure are not turned on during operation of the HFET transistor device, but are instead used to control and operate digital optical devices (e.g., lasers in which a decrease in voltage can cause an increase in current, photodetectors in which an increase in current can cause a decrease in voltage, or optical modulators that can operate in either mode) and complementary bipolar field effect transistors. In effect, the novel epitaxial layer structure provides an HFET transistor device with multiple quantum well structures used for electrical and optical operation of the HFET transistor device, as well as independent modulation doped quantum well structures used for control and operation of the digital optical devices and complementary bipolar field effect transistors.

[0014] The method for forming an integrated circuit and the resulting integrated circuit use a plurality of semiconductor layers formed on a substrate, the plurality of semiconductor layers having i) at least one n-type layer, ii) a first GAA layer structure (for a PHFET transistor device) disposed on the at least one n-type layer, iii) an intermediate layer structure for optical devices and complementary bipolar field effect transistors disposed on the first GAA layer structure, iv) a second GAA layer structure (for a NHFET transistor device) disposed on the intermediate layer structure, and v) at least one p-type layer disposed on the second GAA layer structure. The at least one p-type layer in v) has a first p-type layer with a relatively low p-type doping formed under a second p-type layer with a relatively high p-type doping. An etching step (E1) of the plurality of semiconductor layers exposes a portion of the first p-type layer. P-type ions are implanted into the exposed first p-type layer to a depth sufficient to penetrate the second GAA layer structure and contact all of the p-type nanosheets of the second GAA layer structure to form an ion-implanted p-type gate contact region contacting all of the p-type nanosheets of the second GAA layer structure. N-type ions are implanted into the exposed second p-type layer to a depth sufficient to penetrate the second GAA layer structure and contact the quantum well structure of the second GAA layer structure to form an ion-implanted p-type source and drain contact region contacting the quantum well structure of the second GAA layer structure. A gate electrode of the NHFET transistor device is formed in contact with the ion-implanted p-type gate contact region. A source electrode and a drain electrode of the NHFET transistor device are formed in contact with the ion-implanted n-type source contact region and the ion-implanted n-type drain contact region, respectively. PHFET transistor devices, complementary BICFET devices, stacked complementary HFET devices and circuits and / or logic gates based thereon, as well as various optoelectronic and optical devices, may also be formed as part of an integrated circuit. [Brief description of the drawings]

[0015] [Figure 1]FIG. 1 is a schematic diagram illustrating an exemplary epitaxial semiconductor layer structure for the integrated circuit device structures described herein.

[0016] [Figure 2A] FIG. 2A illustrates an exemplary epitaxial semiconductor layer structure for implementing the integrated circuit device structures described herein. [Figure 2B] FIG. 2B illustrates an exemplary epitaxial semiconductor layer structure for implementing the integrated circuit device structures described herein.

[0017] [Figure 3A] FIG. 3A is a schematic top view of an exemplary PHFET (or p-channel HFET) device according to the present disclosure.

[0018] [Figure 3B] FIG. 3B is a schematic cross-sectional view of the exemplary PHFET (or p-channel HFET) device of FIG. 3A taken along the portion marked XX' in FIG. 3A.

[0019] [Figure 3C] FIG. 3C is a schematic cross-sectional view of the exemplary PHFET (or p-channel HFET) device of FIG. 3A taken along the portion marked YY' in FIG. 3A.

[0020] [Figure 3D] FIG. 3D is a schematic top view of an exemplary NHFET (or n-channel HFET) device according to the present disclosure.

[0021] [Figure 3E] FIG. 3E is a schematic cross-sectional view of the exemplary NHFET (or n-channel HFET) device of FIG. 3D taken along the portion marked XX' in FIG. 3D.

[0022] [Figure 3F]FIG. 3F is a schematic cross-sectional view of the exemplary NHFET (or n-channel HFET) device of FIG. 3D taken along the portion marked YY' in FIG. 3D.

[0023] [Figure 4A] FIG. 4A is a schematic diagram of an exemplary stacked complementary HFET inverter according to the present disclosure.

[0024] [Figure 4B] FIG. 4B is a schematic top view of an exemplary stacked complementary HFET inverter according to the present disclosure.

[0025] [Figure 4C] FIG. 4C is a schematic cross-sectional view of the example stacked complementary HFET inverter of FIG. 4B taken along the portion marked XX' in FIG. 4B.

[0026] [Figure 4D] FIG. 4D is a schematic cross-sectional view of the example stacked complementary HFETs of FIG. 4B taken along the portion marked YY' in FIG. 4B.

[0027] [Figure 5A] FIG. 5A is a schematic top view of another exemplary stacked complementary HFET inverter according to the present disclosure. [Figure 5B] FIG. 5B is a schematic top view of another exemplary stacked complementary HFET inverter according to the present disclosure.

[0028] [Figure 6A] FIG. 6A is a schematic diagram of an exemplary two-input NAND gate having stacked complementary HFET devices in accordance with the present disclosure.

[0029] [Figure 6B] FIG. 6B is a schematic top view of an exemplary two-input NAND gate having stacked complementary HFET devices according to the present disclosure.

[0030] [Figure 7A]FIG. 7A is a schematic diagram of an exemplary two-input NOR gate having stacked complementary HFET devices in accordance with the present disclosure.

[0031] [Figure 7B] FIG. 7B is a schematic top view of an exemplary two-input NOR gate having stacked complementary HFET devices in accordance with the present disclosure.

[0032] [Figure 8A] FIG. 8A is a schematic top view of an exemplary PP BICFET device according to the present disclosure.

[0033] [Figure 8B] FIG. 8B is a schematic cross-sectional view of the exemplary PP BICFET device of FIG. 8A taken along the portion marked XX' in FIG. 8A.

[0034] [Figure 8C] FIG. 8C is a schematic cross-sectional view of the exemplary PP BICFET device of FIG. 8A taken along the portion marked YY' in FIG. 8A.

[0035] [Figure 8D] FIG. 8D is a schematic cross-sectional view of the exemplary PP BICFET device of FIG. 8A taken along the portion marked ZZ' in FIG. 8A.

[0036] [Figure 9A] FIG. 9A is a schematic top view of an exemplary NN BICFET device according to the present disclosure.

[0037] [Figure 9B] FIG. 9B is a schematic cross-sectional view of the exemplary NN BICFET device of FIG. 9A taken along the portion marked XX' in FIG. 9A.

[0038] [Figure 9C] FIG. 9C is a schematic cross-sectional view of the exemplary NN BICFET device of FIG. 9A taken along the section marked YY' in FIG. 9A.

[0039] [Figure 9D] FIG. 9D is a schematic cross-sectional view of the exemplary NN BICFET device of FIG. 9A taken along the portion marked ZZ' in FIG. 9A.

[0040] [Figure 10A] FIG. 10A illustrates an HFET VCSEL thyristor laser realized from the epitaxial layer structure and fabrication methods described herein. [Figure 10B] FIG. 10B illustrates an HFET VCSEL thyristor laser realized from the epitaxial layer structure and fabrication methods described herein.

[0041] [Figure 11A] FIG. 11A shows a thyristor VCSEL realized from the epitaxial layer structure and fabrication methods described herein. [Figure 11B] FIG. 11B illustrates a thyristor VCSEL realized from the epitaxial layer structure and fabrication methods described herein.

[0042] [Figure 12] FIG. 12 shows a LIDAR pixel realized from the epitaxial layer structure and fabrication methods described herein.

[0043] [Figure 13] FIG. 13 shows a single frequency thyristor in-plane laser realized from the epitaxial layer structure and fabrication methods described herein.

[0044] [Figure 14A] FIG. 14A shows a tunable frequency thyristor in-plane laser realized from the epitaxial layer structure and fabrication methods described herein. [Figure 14B] FIG. 14B illustrates a tunable frequency thyristor in-plane laser realized from the epitaxial layer structure and fabrication methods described herein. [Figure 14C]FIG. 14C illustrates a tunable frequency thyristor in-plane laser realized from the epitaxial layer structure and fabrication methods described herein. [Figure 14D] FIG. 14D illustrates a tunable frequency thyristor in-plane laser realized from the epitaxial layer structure and fabrication methods described herein.

[0045] [Figure 15] FIG. 15 shows a dual-input directional coupler realized from the epitaxial layer structure and fabrication methods described herein.

[0046] [Figure 16] FIG. 16 illustrates a thyristor optoelectronic oscillator realized from the epitaxial layer structure and fabrication methods described herein.

[0047] [Figure 17A] FIG. 17A illustrates waveguide photodetectors, optical modulators and optical amplifiers realized from the epitaxial layer structures and fabrication methods described herein. [Figure 17B] FIG. 17B illustrates waveguide photodetectors, optical modulators and optical amplifiers realized from the epitaxial layer structures and fabrication methods described herein.

[0048] [Figure 18] FIG. 18 shows active waveguides (suitable for use in HFET lasers, photodetectors, optical modulators and optical amplifiers) realized from the epitaxial layer structures and fabrication methods described herein.

[0049] [Figure 19] FIG. 19 illustrates passive waveguides (suitable for use in photodetectors, optical modulators and optical amplifiers) realized from the epitaxial layer structures and fabrication methods described herein.

[0050] [Figure 20] FIG. 20 illustrates a waveguide splitter or combiner realized from the epitaxial layer structures and fabrication methods described herein.

[0051] [Figure 21] FIG. 21 shows an optical switching structure (having 2×2 optical switching elements) realized from the epitaxial layer structure and fabrication methods described herein.

[0052] [Figure 22] FIG. 22 illustrates a thyristor optical switching node (or generic thyristor whispering gallery mode laser) realized from the epitaxial layer structure and fabrication methods described herein.

[0053] [Diagram 23] FIG. 23 shows an array of in-plane wavelength demultiplexers (or an array of in-plane wavelength multiplexers) realized from the epitaxial layer structures and fabrication methods described herein. [Figure 24] FIG. 24 shows an array of in-plane wavelength demultiplexers (or an array of in-plane wavelength multiplexers) realized from the epitaxial layer structures and fabrication methods described herein.

[0054] [Diagram 25] FIG. 25 illustrates a universal optical data bus with components realized from the epitaxial layer structures and fabrication methods described herein.

[0055] [Figure 26] FIG. 26 illustrates an optical device that converts in-plane light to vertical light (or vice versa) realized from the epitaxial layer structures and fabrication methods described herein.

[0056] [Figure 27] FIG. 27 is a schematic diagram of interconnected bipolar transistors that correspond to the thyristor devices implemented by the device structures of FIGS. 1 and 2A-2B.

[0057] [Figure 28]FIG. 28 is an exemplary energy band diagram of a thyristor device realized by the device structure of FIGS. 1 and 2A-2B.

[0058] [Figure 29] FIG. 29 is a plot of current-voltage characteristics of an exemplary thyristor layer device and an exemplary diode-type laser device realized from the epitaxial layer structures and fabrication methods described herein.

[0059] [Diagram 30] FIG. 30 shows a diode-type laser device (VCSEL) realized from the epitaxial layer structure and fabrication methods described herein. [Diagram 31] FIG. 31 shows a diode-type laser device (VCSEL) realized from the epitaxial layer structure and fabrication methods described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060] Turning now to FIG. 1, the epitaxial semiconductor layer structure of the present application has a bottom mirror layer 103 formed on a substrate 101, such as a substrate realized from a compound semiconductor such as gallium arsenide (GaAs) or other suitable substrate. The bottom mirror layer 103 may form a distributed Bragg reflector (DBR) mirror, typically constructed by epitaxial growth of a pair of semiconductor or dielectric materials having different refractive indices. When two materials with different refractive indices are placed together to form a junction, light is reflected at the junction. The amount of light reflected at such an interface is small. However, when multiple junction / layer pairs are stacked in a periodic fashion, with each layer having an optical thickness of one-quarter wavelength (λ / 4), the light reflected at a particular central wavelength λ is reduced. c The reflected light from each boundary adds topologically to produce a large amount of reflected light (i.e., a large reflection coefficient) at the interface. The mirror layers are usually undoped. However, to reduce the parasitic cathode resistance of the optical device, the top 1-3 layers are doped with n-type doping of 3e18 cm. -3The lower mirror layer 99 may be doped with a typical concentration of 0.15 to 1.0 μm. Active device structures suitable for realizing complementary heterostructure field effect transistor (HFET) devices, and possibly other electronic, optoelectronic and optical devices, are deposited on the lower mirror layer 99.

[0061] First, one or more highly doped n-type layers 105 are formed on the lower mirror layer 103. The highly doped n-type layer(s) 105 have a thickness of at least 3.5e18 cm -3 0.5e16 cm 2 , which enhances electrical conductivity such that the layer(s) 105 have metal-like properties. The heavily doped n-type layer(s) 105 can provide a lower n-type ohmic contact region for a terminal (e.g., a cathode terminal) of an optoelectronic device. One or more lightly doped n-type layers 103 are formed on the heavily doped n-type layer(s) 105. The lightly doped n-type layer(s) 103 can have a doping density of 0.5e16 cm 2 , which enhances electrical conductivity such that the layer(s) 105 have metal-like properties. The heavily doped n-type layer(s) 105 can provide a lower n-type ohmic contact region for a terminal (e.g., a cathode terminal) of an optoelectronic device. The lightly doped n-type layer(s) 103 can be formed on the heavily doped n-type layer(s) 105. -3 ~5e17cm -3 The lightly doped n-type layer(s) 103 provide insulation between the lower n-type ohmic contact region and the layers above it, and provide low capacitance to the P-channel HFET source and drain regions.

[0062] The layers for the first GAA layer structure are formed on the lightly doped n-type layer(s) 103. The first GAA layer structure has a pair of quantum well structures, an inverted p-type modulation doped quantum well structure 107 having a lower p-type modulation doped layer (108a) disposed below a non-inverted p-type modulation doped quantum well structure 109 having an upper p-type modulation doped layer (108b) disposed between vertically spaced apart heavily doped n-type layers 105, 111 (e.g., nanosheets). The inverted p-type modulation doped quantum well structure 107 has a heavily doped p-type modulation doped layer (p-type charge sheet 108a) spaced below the one or more quantum wells by an undoped spacer layer. The quantum well(s) may be surrounded by barrier layers as is well known. The non-inverted p-type modulation doped quantum well structure 109 has a heavily doped p-type modulation doping layer (p-type charge sheet 108b) spaced above one or more quantum wells by an undoped spacer layer. The quantum well(s) may be surrounded by barrier layers as is well known. In this configuration, the thin n-type doped layers 105, 111 are disposed adjacent (in contact with) the upper and lower boundaries of the p-type modulation doped quantum well structure 107, 109. The thin n-type doped layers 105, 111 form gate regions adjacent the upper and lower boundaries of the p-type modulation doped quantum well structure 107, 109. These gate regions may be configured to apply an electric field that controls the flow of hole charge carriers through the active channel formed by the quantum wells of the p-type modulation doped quantum well structure 107, 109 for a PHFET transistor device. The heavily doped p-type modulation doping layers (108a, 108b) have a conductivity of at least 7e18 cm -3 The n-type doped layers 105, 111 may have a p-type doping concentration of at least 3.5e18 cm -3 The first GAA layer structure can have an n-type doping of a concentration of 100 p-type doping. The first GAA layer structure can have an undoped capacitor spacer layer (106) disposed between the n-type nanosheet 105 and the p-type modulation doping layer (108a), and an undoped capacitor spacer layer (110) disposed between the p-type modulation doping layer (108b) and the n-type charge sheet 111.

[0063] Next, a layer 113 for an inverted p-type modulation doped QW structure is optionally deposited and spaced above the first GaAs layer structure by an undoped spacer layer (112). The inverted p-type modulation doped quantum well layer structure 113 has a heavily doped p-type modulation doping layer (p-type charge sheet) spaced below one or more quantum wells by an undoped spacer layer. The heavily doped p-type modulation doping layer has a thickness of at least 7e18 cm. -3 The quantum well(s) may have a p-type doping of a concentration of 100 .mu.m. The quantum well(s) may be surrounded by a barrier layer as is well known. The layer structure 113 may be used when digital optical devices and bipolar transistors are desired. In this embodiment, a thyristor-like current-voltage characteristic suitable for digital optical devices (e.g., lasers in which a decrease in voltage can cause an increase in current, photodetectors in which an increase in current can cause a decrease in voltage, or optical modulators that can operate in either mode) may be obtained vertically through the bulk epitaxial layer structure. On the other hand, when digital optical devices and bipolar transistors are not desired, the layer structure 113 may be omitted. In this alternative embodiment, a PIN diode-like current-voltage characteristic suitable for analog optical devices (e.g., lasers in which an increase in voltage can cause an increase in current, photodetectors in which a decrease in current can cause a decrease in voltage, or optical modulators that can operate in either mode) may be obtained vertically through the bulk epitaxial layer structure.

[0064] One or more undoped spacer layers 115 may be formed on the inverted p-type modulation doped QW structure 113 (if present), or may optionally be formed on or above the first GAA layer structure when the inverted p-type modulation doped QW structure 113 is omitted.

[0065] Next, layers for a non-inverted n-type modulation doped QW structure 117 are formed on the undoped spacer layer(s) 115. The non-inverted n-type modulation doped QW structure 117 has a heavily doped n-type modulation doping layer (n-type charge sheet) spaced below one or more quantum wells by an undoped spacer layer. The heavily doped n-type modulation doping layer has a thickness of at least 3.5e18 cm. -3 The quantum well(s) may be surrounded by a barrier layer as is well known. The layer structure 117 may be used when digital optical devices and bipolar transistors are desired. In this embodiment, a thyristor-like current-voltage characteristic suitable for digital optical devices (e.g., lasers in which a decrease in voltage can cause an increase in current, photodetectors in which an increase in current can cause a decrease in voltage, or optical modulators that can operate in either mode) may be obtained vertically through the bulk epitaxial layer structure. On the other hand, when digital optical devices and bipolar transistors are not desired, the layer structure 117 may be omitted. In this alternative embodiment, a PIN diode-like current-voltage characteristic suitable for analog optical devices (e.g., lasers in which an increase in voltage can cause an increase in current, photodetectors in which a decrease in current can cause a decrease in voltage, or optical modulators that can operate in either mode) may be obtained vertically through the bulk epitaxial layer structure.

[0066] The layers for the second GAA layer structure are spaced apart by an undoped spacer layer (118) above the non-inverted n-type modulation doped QW structure 117 (if present) or optionally above an undoped spacer layer(s) 115 when the non-inverted n-type modulation doped QW structure 117 is omitted. The second GAA layer structure has a pair of quantum well structures, which have an inverted n-type modulation doped quantum well structure 121 having a lower n-type modulation doped layer (122a) disposed below a non-inverted n-type modulation doped quantum well structure 123 having an upper n-type modulation doped layer (122b) disposed between heavily doped p-type doped layers 119, 125 (e.g., nanosheets) vertically spaced apart from each other. The inverted n-type modulation doped quantum well structure 121 has a heavily doped n-type modulation doping layer (n-type charge sheet 122a) spaced below the one or more quantum wells by an undoped spacer layer. The quantum well(s) may be surrounded by barrier layers, as is well known. The non-inverted n-type modulation doped quantum well structure 122 has a heavily doped n-type modulation doping layer (n-type charge sheet 122b) spaced above the one or more quantum wells by an undoped spacer layer. The quantum well(s) may be surrounded by barrier layers, as is well known. In this configuration, the thin p-type doped layers 119, 125 are located adjacent (in contact with) the upper and lower boundaries of the n-type modulation doped quantum well structures 121, 123. The thin p-type doped layers 119, 125 form gate regions adjacent the upper and lower boundaries of the n-type modulation doped quantum well structures 121, 123. These gate regions can be configured to apply an electric field that controls the flow of electronic charge carriers through the active channel formed by the quantum wells of the n-type modulation doped quantum well structures 121, 123 for NHFET transistor devices. The heavily doped n-type modulation doping layers (122a, 122b) have a thickness of at least 3.5e18 cm -3 The p-type doping layers 105, 111 may have an n-type doping concentration of at least 7e18 cm -3The second GAA layer structure can have a p-type doping of a concentration of 100 p-type doping. The second GAA layer structure can have an undoped capacitor spacer layer (118) disposed between the p-type doped layer 119 and the n-type modulation doped layer (122a), and an undoped capacitor spacer layer (124) disposed between the n-type modulation doped layer (1228b) and the p-type doped layer 125.

[0067] One or more moderately doped p-type layers 127 are formed on the second GaAs layer structure. The moderately doped p-type layer 126 has a thickness of 5e16 cm -3 and 5e17cm -3 The concentration of p-type doping ranges between 0.1 and 0.5.

[0068] One or more heavily doped p-type layers 129 are formed on the moderately doped p-type layer(s) 127. The heavily doped p-type layer(s) 129 may provide an upper p-type ohmic contact region for a terminal (e.g., an anode terminal) of an optoelectronic device. The moderately doped p-type layer 127 provides isolation of the optical device between the upper p-type ohmic contact region and the layers below it due to the fact that it may be converted to n-type doping by ion implantation.

[0069] One or more undoped spacer layers 131 may be formed on the heavily doped p-type layer(s) 129 as shown. A top mirror layer 133 may be formed on the active device structures described above to form a resonant cavity device for optical signal emission and / or detection. The top mirror layer 133 may be formed by depositing pairs of semiconductor or dielectric materials having different refractive indices. The one or more undoped spacer layers 131 may provide tuning of the vertical cavity dimensions for the resonant cavity device, may form apertures for the optical devices (such as VCSELs) described herein, and may form active and passive in-plane optical waveguide structures for the optical devices.

[0070] In this configuration, a second GAA layer structure (for a NHFET transistor device) is stacked on top of a first GAA layer structure (for a PHFET transistor device) as part of the active device structure.

[0071] To fabricate an n-channel HFET device, electrical contact is made to the second GAA layer structure (layers 119 and 125) by etching down to expose portions of layers (such as p-type layer 127) overlying the second GAA layer structure and implanting p-type ions into the exposed layers such that the p-type ions penetrate the second GAA layer structure to contact the p-type doped layers (layers 119 and 125) of the second GAA layer structure to form one or more ion-implanted p-type gate contact regions that contact the p-type doped layers of the second GAA layer structure. In an embodiment, the ion-implanted p-type gate contact regions may penetrate both the second GAA layer structure and the n-type modulation doped QW structure 117 (if present) into layer 115. A p-type metal may be deposited and patterned over the p-type ion-implanted region(s). The patterned p-type metal then forms the backgate electrode of the n-channel HFET device.

[0072] The source and drain terminal electrodes of the n-channel HFET device are electrically coupled to opposite ends of the QW channel(s) realized in the n-type modulation doped QW structures 121, 123 of the second GAA layer structure via n-type ion implanted source and drain contact regions. The etching process can etch down and expose a portion of the layer 125. N-type ions are implanted into the exposed second p-type layer 125 to a depth sufficient to penetrate the second GAA layer structure and contact the n-type modulation doped QW structures 121, 123 of the second GAA layer structure to form ion implanted n-type source and drain contact regions that contact the quantum well structures of the second GAA layer structure at opposite ends of the QW channel realized in the GAAn type modulation doped QW structures 121, 123 of the second GAA layer structure. In an embodiment, the ion-implanted n-type source and drain contact regions may penetrate through both the second GAA layer structure and the (if present) n-type modulation doped QW structure 117 into layer 115. An n-type metal may be deposited and patterned over the n-type ion-implanted regions, such that the patterned n-type metal forms the source and drain electrodes of the n-channel HFET device.

[0073] To fabricate a p-channel HFET transistor device, electrical contact is made to the first GAA layer structure (layers 105 and 111) by etching down to expose portions of layers (such as layer 115) overlying the first GAA layer structure region and implanting n-type ions into the exposed layers such that the n-type ions penetrate the first GAA layer structure to contact the n-type doped layers (layers 105 and 111) of the first GAA layer structure to form one or more ion-implanted n-type gate contact regions that contact the n-type doped layers of the first GAA layer structure. In an embodiment, the ion-implanted n-type gate contact regions may penetrate both the p-type modulation doped QW structure 113 (if present) and the first GAA layer structure into layer 103. An n-type metal may be deposited and patterned over the n-type ion-implanted gate contact region(s). The patterned n-type metal then forms the gate electrode of the p-channel HFET transistor device.

[0074] The source and drain terminal electrodes of the p-channel HFET transistor device are electrically coupled to opposite ends of the QW channel realized in the p-type modulation doped QW structure 107, 109 of the first GAA layer structure via p-type ion implanted source contact regions and p-type ion implanted drain contact regions. An etching process can etch down and expose a portion of the layer 115. P-type ions are implanted into the exposed second p-type layer 115 to a depth sufficient to penetrate the first GAA layer structure and contact the p-type modulation doped QW structure 107, 109 of the first GAA layer structure to form ion implanted p-type source contact regions and ion implanted p-type drain contact regions that contact the quantum well structure of the first GAA layer structure at opposite ends of the QW channel realized in the p-type modulation doped QW structure 107, 109 of the first GAA layer structure. In an embodiment, the ion-implanted p-type source and drain contact regions may penetrate through both the p-type modulation doped QW structure 113 (if present) and the first GAA layer structure into layer 103. A p-type metal may be deposited and patterned on the ion-implanted p-type source and drain contact regions, such that the patterned p-type metal forms the source and drain electrodes of the p-channel HFET device.

[0075] Both the GAAn channel and the vp channel HFET transistor devices are field effect transistors in which current flows as a two-dimensional gas through a QW channel contacted at both ends. The basic operation of the transistor is modulation of the conductance of the QW channel by a modulating electric field perpendicular to the QW channel. The modulated electric field modulates the conductance of the QW channel by controlling the inversion layer (i.e., a two-dimensional electron gas for n-channel devices or a two-dimensional hole gas for p-channel HFETs) as a function of gate voltage relative to source voltage.

[0076] For an n-channel HFET transistor device, the conductance of the QW channel is turned on by biasing the gate and source terminal electrodes at a voltage that forward biases the P / N junction of the gate and source regions to minimize gate conduction and creates an inversion layer of electron gas in the QW channel of the n-type modulation doped QW structure 121, 123 in the second GAA layer structure between the source and drain terminal electrodes. In this configuration, the source terminal electrode is the terminal electrode through which electron carriers enter the QW channel of the n-type modulation doped QW structure 121, 123, the drain terminal electrode is the terminal electrode through which electron carriers exit the device, and the gate terminal electrode is the control terminal of the device.

[0077] The p-channel HFET transistor device operates similarly to the n-channel HFET transistor device with the current direction and voltage polarity reversed relative to the n-channel HFET transistor device. For the p-channel HFET transistor device, the conductance of the QW channel is turned on by biasing the gate and source terminal electrodes with a voltage that forward biases the P / N junction of the source and gate regions to minimize gate conduction and creates an inversion layer of hole gas in the QW channel of the p-type modulation doped QW structure 107, 109 of the second GAA layer structure between the source and drain terminal electrodes. In this configuration, the source terminal electrode is the terminal through which hole carriers enter the QW channel of the p-type modulation doped QW structure 107, 109, the drain terminal electrode is the terminal through which hole carriers exit, and the gate terminal electrode is the control terminal of the device.

[0078] 2A and 2B collectively show an exemplary epitaxial semiconductor layer structure for realizing the integrated circuit device structure described herein. In other embodiments, other III-V materials, such as indium phosphide materials, can be used to realize the epitaxial layer structure of FIG. 1. The epitaxial layer structure of FIG. 2A and 2B can be fabricated, for example, using molecular beam epitaxy (MBE), chemical vapor deposition, or other suitable techniques. Starting from FIG. 2B , alternating aluminum arsenide (AlAs) and gallium arsenide (GaAs) semiconductor layers (preferably in at least seven pairs) can be sequentially deposited on a semi-insulating GaAs substrate 97 to form a bottom mirror layer 99. The number of AlAs layers is preferably always one more than the number of GaAs layers, such that the first and last layers of the mirror are AlAs. In an embodiment, the AlAs layers are formed of a compound AlAs such that a mirror is formed at a designed center wavelength. x O y This central wavelength is selected so that all of the desired resonant wavelengths of the device structure are exposed to high reflectivity. In one embodiment, the thicknesses of the AlAs and GaAs layers of the bottom mirror layer 99 are adjusted to 100% by weight for GaAs and 100% by weight for AlAs. x O y The final optical thickness of c Alternatively, the mirrors can be grown as alternating quarter-wave thick layers of GaAs and AlAs at the designed wavelength, avoiding the use of an oxidation step. In this case, many more pairs (such as 27.5 pairs at 980 μm or 29.5 pairs at 850 μm) are required to achieve the reflectivity required for efficient optical lasing and detection.

[0079] The active device structure is deposited on top of the lower mirror layer 99, beginning with a layer 101 of N+ GaAs material to which an ohmic contact can be formed. Layer 101 has a thickness of 4×10 18 cm -3and a typical thickness in the region of 1000 Å. N+ GaAs layer 101 corresponds to the heavily doped n-type layer 101 of FIG.

[0080] A layer 103 of an N-type alloy of AlGaAs is deposited on the layer 101. In an embodiment, the layer 103 is formed by a dummy diffusion method with a parameter x1 preferably between 70 and 100% and a dummy diffusion rate of 1×10 17 cm -3 Al with a typical n-type doping of 1000 Å and a typical thickness of 1000 Å x1 Ga (1-x1) The N-type AlGaAs layer 103 can be an alloy of As. The N-type AlGaAs layer 103 can provide further low waveguide cladding and optical confinement. It also allows for low source-gate and drain-gate capacitances for p-channel HFET devices and low emitter-base capacitance for NN BICFERT devices. The large bandgap (corresponding to the high Al content) makes the layer ideal for blocking minority carrier flow. The N-type AlGaAs layer 103 corresponds to the lightly doped n-type layer 103 of FIG. 1 described above.

[0081] A layer 105 of N+ GaAs material is deposited on layer 103. In an embodiment, the N+ GaAs layer has a thickness of 3.5×10 18 cm -3 1, a typical thickness of 300 Å, and a typical Al concentration of 15%. N+ GaAs layer 105 functions electrically as part of the gate region of the p-channel HFET device and may form the lower plate of a capacitor that defines the input capacitance of the gate region of the p-channel HFET device. Layer 105 may incorporate sufficient n-type doping to limit the penetration of capacitor spacer layer 111 by depletion into layer 105. N+ GaAs layer 105 corresponds to the highly doped n-type layer 105 of FIG. 1 described above.

[0082] An undoped spacer layer 106 formed from an alloy of AlGaAs is then deposited on the N+GaAs layer 105. In an embodiment, the spacer layer 106 is an AlGaAs layer having a parameter x1 of preferably 15%. x 1Ga (1-x1) It is formed from an alloy of As and has a typical thickness of 300 Å. Spacer layer 106 forms a spacer layer between the lower plate (layer 105) and the upper plate (the P+ charge sheet of the inverted p-type modulation doped QW structure 107) of the capacitor that contributes to the input capacitance of the gate region of the p-channel HFET transistor device.

[0083] The next layer is a thin p-type charge sheet made of an alloy of AlGaAs, labeled 108 in FIG. 2B. In an embodiment, the p-type charge sheet is AlGaAs with a parameter x1 of preferably 15%. x1 Ga (1-x1) The p-type charge sheet can be formed from 7x10 As. 18 cm -3 The layer is P+ doped with a typical p-type doping of 100 Å and has a typical thickness of 40 Å. A delta doped layer may also be used. Next is an undoped spacer layer formed from an alloy of AlGaAs. In an embodiment, the undoped spacer layer is AlGaAs with a parameter x1 preferably of 15%. x1 Ga (1-x1) The InGaAs QW layer is formed from InGaAs and has a typical thickness of 30 Å or less. An inverted p-type modulation doped quantum well structure 107 is then formed on top of the 30 Å spacer layer. The inverted p-type modulation doped quantum well structure 107 starts with an InGaAs QW layer and an undoped GaAs barrier layer, which are repeated for the number of quantum wells (typically four or more quantum wells). At least two quantum well structures may be used. In an embodiment, the InGaAs QW layer is formed from InGaAs with a parameter x1 of preferably 20%. x1 Ga (1-x1)In one embodiment, the InGaAs QW layers have a typical thickness of 60 Å. In one embodiment, the undoped GaAs barrier layers have a typical thickness of 100 Å. These layers correspond to the inverted p-type modulation doped quantum well structures 107 and 109 of FIG. 1 described above. In another embodiment, the QW layers of the inverted p-type modulation doped QW structure 107 can be formed from an alloy of InGaAsb or an alloy of InGaAsSb (or InAsSbP) to take advantage of the superior hole mobility of Sb (antimonide). For example, the QW layers can be formed from an alloy of InGaAsSb or InGaAsSb (or InAsSbP) to take advantage of the superior hole mobility of Sb (antimonide). x1 Ga (1-x1) Sb or In x1 Ga (1-x1) As y1 Sb (1-y1) The alloy parameter x1 can be 50% and the thickness can be as low as 20A to improve mobility even at very high compressive stresses. The bottom half of the QW (labeled 107) forms the upper plate of a capacitor that contributes to the input capacitance of the gate region of the bottom channel of the p-channel HFET transistor device. The top half of the quantum well (labeled 109) serves as the quantum well layer of a non-inverted p-type modulation doped quantum well structure 109. The top half of the quantum well also forms the lower plate of a capacitor that contributes to the input capacitance of the gate region of the central non-inverted p-channel HFET. The next layer is a thin p-type charge sheet made of an alloy of AlGaAs, labeled 108b in FIG. 2B. In an embodiment, the p-type charge sheet, with parameter x1 preferably 15%, is made of Al x1 Ga (1-x1) The p-type charge sheet can be formed from 7x10 As. 18 cm -3 It is P+ doped with a typical p-type doping of 100 Å and has a typical thickness of 40 Å.

[0084] An undoped spacer layer 110 formed from an alloy of AlGaAs is then deposited on top of the p-type charge sheet layer. In an embodiment, the spacer layer 110 is AlGaAs with a parameter x1 of preferably 15%. x1 Ga (1-x1)It is formed from an alloy of As and has a typical thickness of 300 Å. The spacer layer 110 forms a spacer layer between the lower plate (QW layers 107 and 109 in FIG. 2B) and the upper plate (N+ gate doped layer of non-inverted p-type modulation doped QW structure 109) of the capacitor that contributes to the input capacitance of the gate region of the p-channel HFET transistor device.

[0085] A layer 111 of N+ AlGaAs material is deposited on layer 110. In an embodiment, the N+ AlGaAs layer has a thickness of 3.5×10 18 cm -3 100 Å, a typical thickness of 300 Å, and a typical Al concentration of 15%. N+ type AlGaAs layer 111 may function electrically as part of the gate region of a p-channel HFET transistor device, forming the upper plate of a capacitor that defines the input capacitance of the gate region of the p-channel HFET transistor device with capacitor spacer layer 110. Layer 111 forms the lower plate of a capacitor that contributes to the input capacitance of the gate region of the p-channel HFET transistor device with capacitor layer 112. Layer 111 may incorporate sufficient n-type doping to limit the penetration of capacitor spacer layer 110 by depletion into layer 111. N+ AlGaAs layer 111 corresponds to the highly doped n-type layer 111 of FIG. 1 described above.

[0086] Layers 105-111 in FIG. 2B correspond to the first GAA layer structure described herein.

[0087] Next, an undoped spacer layer 112 formed from an alloy of AlGaAs is deposited on the N+GaAs layer 111. In an embodiment, the spacer layer 112 is made of an AlGaAs alloy with a parameter x1 of preferably 15%. x1 Ga (1-x1)The spacer layer 112 may be formed from As and has a typical thickness of 300 Å. The spacer layer 112 forms a spacer layer between the lower plate (layer 111) and the upper plate (the P+ charge sheet and the QWs of the inverted p-type modulation doped QW structure 113) of the capacitor that contributes to the input capacitance of the gate region of a p-channel HFET transistor device utilizing the p-type modulation doped QW structure 113.

[0088] Next, a thin p-type charge sheet is deposited, formed from an alloy of AlGaAs. In an embodiment, the thin p-type charge sheet is AlGaAs with a parameter x1 of preferably 15%. x1 Ga (1-x1) The p-type thin charge sheet is formed from 7×10 18 cm -3 The p-type charge sheet and adjacent quantum wells form the upper plate of a capacitor that contributes to the input capacitance of the gate region of a p-channel HFET transistor device utilizing the p-type modulation doped QW structure 113. Next is an undoped spacer layer formed from an alloy of AlGaAs. In an embodiment, the undoped spacer layer is preferably made of AlGaAs with a parameter x1 of 15%. x1 Ga (1-x1) The InGaAs QW layer is formed from InGaAs and has a typical thickness of 30 Å or less. The InGaAs QW layer and undoped GaAs barrier layer are then repeated for the number of quantum wells (such as three or more quantum wells). A single quantum well structure may also be used. In an embodiment, the InGaAs QW layer is formed from InGaAs with a parameter x1 of preferably 20%. x1 Ga (1-x1)In one embodiment, the InGaAs QW layers have a typical thickness of 60 Å. In an embodiment, the undoped GaAs barrier layers have a typical thickness of 100 Å. These layers correspond to the inverted p-type modulation doped quantum well structure 113 of FIG. 1 described above. In another embodiment, the QW layers of the inverted p-type modulation doped QW structure 113 can be formed from an alloy of InGaSb or an alloy of InGaAsSb (or InAsSbP) to take advantage of the superior hole mobility of Sb (antimonide). For example, the QW layers can be formed from an alloy of InGaSb or InGaAsSb (or InAsSbP) to take advantage of the superior hole mobility of Sb (antimonide). x1 Ga (1-x1) Sb or In x1 Ga (1-x1) As y1 Sb (1-y1) The alloy parameter x1 can be 50% and the thickness can be as small as 20 Å to improve the mobility even at very high compressive stress.

[0089] The layer structure 113 can be used when digital optical devices and bipolar transistors are desired. In this embodiment, a thyristor-like current-voltage characteristic suitable for digital optical devices (e.g., a laser in which a decrease in voltage can cause an increase in current, a photodetector in which an increase in current can cause a decrease in voltage, or an optical modulator that can operate in either mode) can be obtained vertically through the bulk epitaxial layer structure. On the other hand, when digital optical devices and polar transistors are not desired, the layer structure 113 can be omitted. In this alternative embodiment, a PIN diode-like current-voltage characteristic suitable for analog optical devices (e.g., a laser in which an increase in voltage can cause an increase in current, a photodetector in which a decrease in current can cause a decrease in voltage, or an optical modulator that can operate in either mode) can be obtained vertically through the bulk epitaxial layer structure.

[0090] An undoped spacer layer 115 of an alloy of AlGaAs is then formed on top of the last undoped GaAs barrier layer (if present) of the inverted p-type modulation doped quantum well structure 113 or on top of the spacer layer 111 if the layer structure 113 is omitted. In an embodiment, the undoped spacer layer 115 is an AlGaAs alloy having a parameter x1 of preferably 20%. x1 Ga (1-x1) It is formed from an alloy of As and has a typical thickness of 2000 Å. Spacer layer 115 is shown in both Figures 2A and 2B to illustrate the continuity of the epitaxial layer structure. Spacer layer 115 corresponds to undoped spacer layer 115 of Figure 1 described above.

[0091] A non-inverted n-type modulation doped quantum well structure 117 is then formed on the undoped spacer layer 115. The non-inverted n-type modulation doped quantum well structure 117 has an undoped InGaAs QW layer and a GaAs barrier layer repeated for the number of quantum wells (such as three or more quantum wells). A single quantum well structure may also be used. In an embodiment, the undoped InGaAs QW layer is an InGaAs QW layer having a parameter x1 of preferably 20%. x1 Ga (1-x1) In an embodiment, the GaAs barrier layer has a typical thickness of 100 Å. Next is an undoped spacer layer formed from an alloy of AlGaAs. In an embodiment, the undoped spacer layer has a typical thickness of 100 Å. x1 Ga (1-x1) Next is the n-type thin charge sheet. In an embodiment, the n-type charge sheet is made of an alloy of Al and As with a typical thickness of 30 Å (or less for scaled structures). x1 Ga (1-x1) The n-type charge sheet is formed from an alloy of As and 3.5×10 18 cm -31 and has a typical thickness of 80 Å. A delta doped layer may be used. The n-type charge sheet serves as the n-type modulation doped layer of the non-inverted n-type modulation doped quantum well structure 117. These layers correspond to the n-type modulation doped QW structure 117 of FIG. 1 described above. In another embodiment, the QW layer(s) of the non-inverted n-type modulation doped QW structure 117 and all the QW layers of the p-channel HFET transistor device (layers 107, 109 and 113 of FIG. 1) may be formed using metamorphic growth techniques to reduce the QW bandgap and shift the wavelength to the 1500 nm range. Indium concentration of the QW layers may then be 60% or more.

[0092] The layer structure 117 can be used when digital optical devices and bipolar transistors are desired. In this embodiment, a thyristor-like current-voltage characteristic suitable for digital optical devices (e.g., lasers in which a decrease in voltage can cause an increase in current, photodetectors in which an increase in current can cause a decrease in voltage, or optical modulators that can operate in either mode) can be obtained vertically through the bulk epitaxial layer structure. On the other hand, when digital optical devices and bipolar transistors are not desired, the layer structure 117 can be omitted. In this alternative embodiment, a PIN diode-like current-voltage characteristic suitable for analog optical devices (e.g., lasers in which an increase in voltage can cause an increase in current, photodetectors in which a decrease in current can cause a decrease in voltage, or optical modulators that can operate in either mode) can be obtained vertically through the bulk epitaxial layer structure.

[0093] An undoped spacer layer 118 formed from an alloy of AlGaAs is then deposited on the n-type charge sheet of the n-type modulation doped quantum well structure 117 (if present) or on the spacer layer 115 if the n-type modulation doped quantum well structure 117 is omitted. In an embodiment, the undoped spacer layer 118 is an AlGaAs layer with a parameter x1 of preferably 15%. x1 Ga (1-x1)It may be formed from As and has a typical thickness of 300 Å. Spacer layer 118 forms a spacer layer between the lower plate (n-type charge sheet of 117) and the upper plate (layer 119) of the capacitor that contributes to the input capacitance of the gate region of the non-inverted n-channel HFET.

[0094] A layer 119 made of an alloy of AlGaAs with p-type doping is then deposited on the undoped AlGaAs layer 118. In an embodiment, the layer 119 is made of an AlGaAs alloy with a parameter x1 preferably of 15%. x1 Ga (1-x1) Layer 119 is made of 7×10 18 cm -3 1 and has a typical thickness of 300 Å. Layer 119 may function electrically as part of the gate region of an n-channel HFET transistor device, forming the upper plate of a capacitor that contributes to the input capacitance of the gate region of the n-channel HFET transistor device. Layer 119 may incorporate sufficient p-type doping to limit penetration of capacitor spacer layer 119 by depletion into layer 119. Layer 119 corresponds to the heavily doped p-type layer(s) 119 of FIG. 1 and is as described above.

[0095] An undoped spacer layer 120 formed from an alloy of AlGaAs is then deposited on the P+GaAs layer 119. In an embodiment, the spacer layer 120 is an AlGaAs layer having a parameter x1 of preferably 15%. x1 Ga (1-x1) It is formed from an alloy of As and has a typical thickness of 300 Å. Spacer layer 120 forms a spacer layer between the lower plate (layer 119) and the upper plate (the N+ charge sheet of inverted n-type modulation doped QW structure 121) of the capacitor that contributes to the input capacitance of the gate region of the central channel of the n-channel HFET transistor device.

[0096] The next layer is a thin n-type charge sheet made from an alloy of AlGaAs. In an embodiment, the n-type charge sheet is made of AlGaAs with a parameter x1 of preferably 15%.x1 Ga (1-x1) The n-type charge sheet can be formed from As. The typical n-type doping is 3.5x10 18 cm -3 The n-type charge sheet is doped N+ with a typical thickness of 80 Å. The n-type charge sheet forms the upper plate of a capacitor that contributes to the input capacitance of the gate region of the central channel of the n-channel HFET transistor device. Next is an undoped spacer layer formed from an alloy of AlGaAs. In an embodiment, the undoped spacer layer is AlGaAs with a parameter x1 preferably of 15%. x1 Ga (1-x1) The spacer layer is formed from InGaAs and has a typical thickness of 30 Å or less. A quantum well structure 121 is then formed on top of the spacer layer. The quantum well structure starts with an InGaAs QW layer and an undoped GaAs barrier layer, and is repeated for the number of quantum wells (such as three or more quantum wells). At least two quantum well structures may be used. In an embodiment, the InGaAs QW layer is formed from InGaAs with a parameter x1 of preferably 20%. x1 Ga (1-x1) The InGaAsQW layer has a typical thickness of 60 Å. In an embodiment, the undoped GaAs barrier layer has a typical thickness of 100 Å. These layers correspond to the quantum well structures 121 and 123 of FIG. 1 described above. These quantum wells function as the conducting channels of the n-channel HFET transistor device. Next is an undoped spacer layer formed from an alloy of AlGaAs. In an embodiment, the undoped spacer layer is formed from an alloy of AlGaAs with parameter x1 preferably being 15%. x1 Ga (1-x1) The next layer is a thin n-type charge sheet made of an alloy of AlGaAs with a parameter x1 preferably of 15%. x1 Ga (1-x1) The n-type charge sheet can be formed from 3.5×10 18 cm -3It is doped N+ with a typical n-type doping of 100 Å and has a typical thickness of 80 Å. A delta doped layer may also be used. The n-type charge sheet forms the lower plate of the capacitor that contributes to the input capacitance of the gate region of the n-channel HFET transistor device.

[0097] Next, an undoped spacer layer 124 is deposited, formed from an alloy of AlGaAs. In an embodiment, the spacer layer 124 is AlGaAs with a parameter x1 of preferably 15%. x1 Ga (1-x1) It is formed from an alloy of As and has a typical thickness of 300 Å. Spacer layer 124 forms a spacer layer between the lower plate (layer 122) and the upper plate (P+ gate doping layer 125 of a non-inverted n-type modulation doped QW structure) of the capacitor that contributes to the input capacitance of the gate region of the n-channel HFET transistor device.

[0098] A layer 125 of P+ AlGaAs material is then deposited on top of the p-type AlGaAs layer 121. In an embodiment, the P+ AlGaAs layer has a thickness of 7×10 18 cm -3 1, a typical thickness of 300 Å, and an Al concentration of 15%. P+ AlGaAs layer 125 may function electrically as part of the gate region of an n-channel HFET device, forming the upper plate of a capacitor that contributes to the input capacitance of the gate region of an n-channel HFET transistor device with capacitor spacer layer 124. Layer 125 may incorporate sufficient p-type doping to limit the penetration of capacitor spacer layer 124 by depletion into layer 125. P+ GaAs layer 125 corresponds to the heavily doped p-type layer 125 of FIG. 1 described above.

[0099] Layer 119 in FIG. 2A corresponds to the second GAA layer structure described herein.

[0100] A layer 127 made of an alloy of AlGaAs with p-type doping is then deposited on the p-type AlGaAs layer 125. In an embodiment, the layer 127 is made of an AlGaAs alloy with a parameter x1 preferably between 70 and 100%. x1 Ga (1-x1) Layer 127 is made of an alloy of 7×10 17 cm -3 1 and a typical thickness of 1000 Å. The p-type AlGaAs material of layer 127 provides the upper waveguide cladding and optical confinement, allowing current controlled injection for VCSEL and other optical waveguide devices. Also, the large bandgap (corresponding to a high Al content) makes this layer ideal for blocking the flow of minority carriers. Layer 127 corresponds to the undoped layer(s) 127 of FIG. 1 described above.

[0101] A layer 129 of P+ GaAs material is then deposited on top of the p-type AlGaAs layer 127. The P+ doped GaAs layer 125 allows for an ohmic contact to be formed thereon. The layer 129 has a thickness of 7×10 18 cm -3 ~10 20 cm -3 1 and has a typical p-type doping in the range of 0.1 μm and a typical thickness of 500 Å. P+ doped GaAs layer 129 corresponds to the heavily doped p-type layer(s) of FIG.

[0102] Next, an undoped GaAs layer 131 is deposited on top of the P+ doped GaAs layer 129. Layer 131 may have a typical thickness of 250 Å or more. Layer 127 may be used to tune the resonant cavity, form the apertures of the optical devices (such as VCSELs) described herein, and form the active and passive in-plane optical waveguide structures of the optical devices. Layer 131 corresponds to the undoped layer(s) 131 of FIG. 1 described above.

[0103] To form a resonant cavity device for optical signal emission and / or detection, a top mirror layer 133 can be formed over the active device structure described above. The top mirror layer 133 can be formed by depositing a pair of semiconductor or dielectric materials having different refractive indices.

[0104] 3A-3C show an exemplary p-channel HFET device (or PHFET device) realized from the epitaxial layer structure of FIG. 1 and / or FIG. 2A-2B. As best shown in FIG. 3A and 3B, source terminal electrode 306A and drain terminal electrode 306B are electrically coupled to p-type modulation doped QW structure 107, 109 through corresponding source p-type ion implantation region 304a and drain p-type ion implantation region 304b such that p-type modulation doped QW structure 107, 109 forms a channel region between source p-type ion implantation region 304a and drain p-type ion implantation region 304b (and between source terminal electrode 306a and drain terminal electrode 306b electrically connected thereto). Feature 301, which may be formed from a refractory metal (such as tungsten) or other suitable material, is patterned on top of the mesa formed by etching layer 115 (FIG. 3B, FIG. 3C). The etch should end at a level about 600 Å above the upper quantum well of 113 (or layer 111 if layer structure 113 is omitted) for a PHFET gate length of 200 Å, determining the level to be about three times less than the gate length. Feature 301 covers the channel region of the PHFET. Etching of layer 115 is performed to about 200 Å above the upper quantum well of PHFETQW structure 113 (or layer 111 if layer structure 113 is omitted). The etch exposes portions of layer 115 (referred to as source and drain contact regions) that extend along both sides of feature 301 and that are subjected to implantation of p-type ions (e.g., Be / F ions) into the exposed portions of layer 115 to form source and drain p-type ion implant regions 304a and 304b that extend along opposite sides of feature 301, as best shown in FIG. 3B. The length (L) dimension of feature 301 contributes to the effective length of the channel region between source p-type ion implant region 304a and drain p-type ion implant region 304b.As best shown in FIG. 3C, an implantation of n-type ions (e.g., Si / F ions) is performed into the exposed layer 115 from the same level of layer 115 to form n-type ion implanted gate regions 302a and 302b that extend vertically down from the exposed layer 115 into the first GAA layer structure (layers 111 and 105) at either end of the feature 301 and into the QW channel of the PHFET structure 107, 109. The feature 301 can be used to define the channel length and to provide a self-aligned implantation mask along opposite sides of the feature for source and drain ion implantation and at one end of the feature for gate ion implantation. Another etch is performed into layer 119 (starting at the tungsten level of layer 123) about 300 Å above the n-type modulation doped QW structure 117. This etch exposes a portion of layer 119 (referred to as the backgate contact region) at the other end of feature 301 opposite the gate contact region and the region of gate n-type ion implantation region 302a. As best shown in FIG. 3C, the exposed portion of layer 119 is implanted with n-type ions (e.g., Si / F ions) to form a backgate n-type ion implantation region 302b that extends vertically down from the exposed layer 119 into the backgate region (including the non-inverted n-type modulation doped QW structure 117) of the n-channel HFET device at the other end of feature 301. Feature 301 can be used to define the channel length and width and to provide a self-aligned implantation mask along the sides of the feature for source and drain ion implantation and at both ends of the feature for gate ion implantation. The ion-implanted n-type gate contact regions 302a, 302b are located at either end of the width (W) dimension of feature 301 and the corresponding effective width of the channel region of the p-channel HFET device. As best seen in Figures 3A and 3C, an etch 309 down to the lower mirror layer 103 can form mesas 303a, 303b incorporating source p-type ion implantation region 304a and drain p-type ion implantation region 304b.The source p-type ion implantation region 304a, the drain p-type ion implantation region 304b, the gate n-type ion implantation region 302a, and the back gate n-type ion implantation region 302b are made amorphous by ion irradiation. Before metallization, a high temperature short time annealing (RTA) step can be performed to anneal the source p-type ion implantation region 304a, the drain p-type ion implantation region 304b, the gate n-type ion implantation region 302a, and the back gate n-type ion implantation region 302b. The thermal energy of the RTA step can return the amorphous structure to a single crystalline structure, and the dopant atoms can form bonds on the semiconductor layer as donors (in the case of n-type) or acceptors (in the case of p-type). A p-type metal (such as p-type gold) can be deposited and patterned on the mesas 303a, 303b that contact the corresponding source p-type ion implanted regions 304a and drain p-type ion implanted regions 304b, respectively, to form the source terminal electrode 306a and drain terminal electrode 306b as shown in Figures 3A and 3B. A p-type metal (such as p-type gold) can be deposited and patterned on the mesas 307a, 307b that contact the corresponding gate n-type ion implanted regions 302a and back gate n-type ion implanted regions 302b, respectively, to form the gate terminal electrode 305a and back gate terminal electrode 305b as shown in Figures 3A and 3C.

[0105] The p-channel HFET device operates at a negative voltage level, V GS Under normal operation, the source terminal electrode 306a is connected to a positive voltage level V SD The drain terminal electrode 306b is forward biased by the negative voltage level V GS A reverse bias is applied to the source terminal electrode 306a by V SD For small values ​​of , the device has a drain current of I D V SD It can operate in the triode region where the voltage varies quasi-linearly with V. SD For large values ​​of , the device will have a drain current of I D V SDIn this GAPHFET structure, all the gate electrode nanosheets 111 and 105 in FIG. 3B and FIG. 3C are connected together by implantation of N+ ions, so that the gate electrode voltage V GS is applied to both the top and bottom of the channel, thereby modulating the inversion charge of the channel from both directions, eliminating the traditional role in planar PHFET structures of adjusting the threshold voltage value by the application of a backgate electrode and positive voltage. The GAA approach is superior to traditional backgate structures in that it reduces the level of drain-induced barrier lowering (dibl), which degrades the output resistance of HFETs, and also degrades (i.e., lowers) the subthreshold slope, which is a measure of how quickly the channel turns off with decreasing gate voltage. By increasing the subthreshold slope, lower threshold voltages and lower supply voltages can be achieved, which are key requirements for scaling HFET channel lengths into the sub-10 nm range and achieving higher speeds and reduced power consumption. Since the backgate and the backgate-associated substrate or body layer are eliminated in the GAA structure, the parasitic capacitances (source-body capacitance CSB and drain-body capacitance CDB) are also eliminated, enabling higher speed operation.

[0106] 3D-3F show an exemplary n-channel HFET device (or NHFET device) realized from the epitaxial layer structure of FIG. 1 and / or FIG. 2A-2B. As shown, source terminal electrode 312a and drain terminal electrode 312b are electrically coupled to n-type modulation doped QW structure 123, 121, 117 through corresponding source n-type ion implantation region 313a and drain n-type ion implantation region 313b. The n-type modulation doped QW structure 123, 121 forms an effective channel region between source n-type ion implantation region 313a and drain n-type ion implantation region b (and between source terminal electrode 312a and drain terminal electrode 312b electrically connected thereto). A feature 301, which may be formed from a refractory metal (such as tungsten) or other suitable material, is patterned on the mesa formed by etching layer 127 (FIGS. 3D, 3E, 3F). The feature 301 covers the channel region of the n-channel HFET. The layer 127 is etched about 300 Å above the P+ charge sheet layer 125 of the GAA layer structure. Note that this etch is performed after the formation of the tungsten feature 301. After patterning with a photoresist mask the S and D contact regions of the NHFET at the tungsten level, i.e., the etched surface at 127, this pattern is used as an etch mask. Alternatively, this etch can be performed by first protecting the gate implant region (which will receive a p-type implant) with a photoresist mask. As best shown in Figures 3D and 3E, this etch exposes portions of the layer 127 that extend along opposite sides of the feature 301 and are exposed to implantation of n-type ions (e.g., Si / F ions) into the exposed layer 127 to form source n-type ion implant regions 313a and drain n-type ion implant regions 313b that extend along opposite sides of the feature 301. Feature 301 can be used to define the channel length and provide a self-aligned implant mask along the edges of the feature for source and drain ion implants.The length (L) dimension of the feature 301 contributes to the effective length of the channel region between the source n-type ion implant region 313a and the drain n-type ion implant region 313b. The same etch (or a separate etch to layer 127) can expose portions of layer 127 at either end of the feature 301 where p-type ions (e.g., Be / F ions) are implanted into the exposed layer regions to form ion-implanted p-type gate contact regions 314a, 314b that extend vertically down from the exposed layer 127 to the gate regions (layers 125, 119) of the second GAA layer structure gate and through the n-type modulation doped QW structure 117 (if present) at either end of the feature 301, as best shown in Figures 3D and 3F. The width (W) dimension of the feature 301 contributes to the effective width of the channel region between the ion-implanted p-type gate contact regions 314a, 314b. In this configuration, the width (W) dimension and corresponding effective width of the n-channel HFET transistor device channel region are significantly longer than the length (L) dimension and corresponding effective length of the n-channel HFET transistor device channel region, and the implanted p-type gate contact regions 314a, 314b are located at opposite ends of the feature 301 from the width (W) dimension and corresponding effective width of the n-channel HFET device channel region. Etching 309 down to the lower mirror layer 103 can form mesas 312a, 312b for the implanted n-type source and drain contact regions 313a, 313b, as best shown in Figures 3D and 3E. Etching 309 down to the lower mirror layer 103 can form mesas 317a, 317b for the implanted p-type gate contact regions 314a, 314b, as best shown in Figures 3D and 3F. The source n-type ion implantation region 313a, the drain n-type ion implantation region 313b, the gate p-type ion implantation region 314a, and the back gate p-type ion implantation region 314b are made amorphous by ion irradiation. Prior to metallization, a high temperature short time anneal (RTA) step can be performed to anneal the source n-type ion implantation region 313a, the drain n-type ion implantation region 313b, the gate p-type ion implantation region 314a, and the back gate p-type ion implantation region 314b.The thermal energy of the RTA process can convert the amorphous structure back to a single crystalline structure, and the dopant atoms can form bonds on the semiconductor layer as donors (for n-type) or acceptors (for p-type). A p-type metal (such as p-type gold) can be deposited and patterned on the mesas 312a, 312b (contacting the corresponding source p-type ion implantation regions 313a and drain p-type ion implantation regions 313b, respectively) to form the source terminal electrode 316a and drain terminal electrode 316b as shown in Figures 3D and 3E. A p-type metal (such as p-type gold) can be deposited and patterned on the mesas 317a, 317b (contacting the corresponding gate n-type ion implantation regions 314a and back gate n-type ion implantation regions 314b, respectively) to form the gate terminal electrode 315a and back gate terminal electrode 315b as shown in Figures 3D and 3F.

[0107] The n-channel HFET device operates at a positive voltage level, V GS Under normal operation, the drain terminal electrode 316b is connected to a positive voltage level V DS The source terminal electrode 316a is forward biased by a positive voltage level V GS The source terminal electrode 316a is forward biased by V DS For small values ​​of , the device has a drain current of I D V DS The system operates in a triode region that varies quasi-linearly with V DS For large values ​​of , the device will have a drain current of I D V DS In this GAANHFET structure, all the gate electrode nanosheets 119 and 125 in FIG. 3E and FIG. 3F are connected together by implantation of P+ ions, so that the gate electrode voltage V GSis applied to both the top and bottom of the channel, thereby modulating the inversion charge of the channel from both directions. This eliminates the traditional role of the backgate electrode and the application of a negative voltage to adjust the threshold voltage value in the planar PHFET structure. The GAA approach is superior to the traditional backgate structure in that it reduces the level of drain-induced barrier lowering (dibl), which degrades the output resistance of the HFET, and also degrades (i.e., lowers) the subthreshold slope, which is a measure of how quickly the channel turns off with decreasing gate voltage. By increasing the subthreshold slope, lower threshold voltages and lower supply voltages can be achieved, which are key requirements for scaling HFET channel lengths into the sub-10 nm range and achieving higher speeds and reduced power consumption. Furthermore, since the backgate and the backgate-associated substrate or body layer are eliminated in the GAA structure, the parasitic capacitances (source-body capacitance CSB and drain-body capacitance CDB) are also eliminated, enabling higher speed operation.

[0108] In the above embodiment, p-type ion implantation is used to contact the second GAA layer structure of the N-channel HFET transistor device, and n-type ion implantation is used to contact the first GAA layer structure of the P-channel HFET transistor device. These implantation processes can be effectively controlled, helping to minimize the gate resistance for high performance operation of the complementary HFET devices. Furthermore, the combination of the lightly doped n-type layer 103 with the p-type source and drain ion implantations ensures low source-gate and drain-gate capacitances of the P-channel HFET transistor device. Such low capacitance is due to the p-type ion implanted source and drain contact regions penetrating the first GAA layer structure to form a PN junction with its bottom at layer 103. This junction has low capacitance (hence, minimal current leakage and capacitance) for high performance operation of the p-channel HFET transistor device.

[0109] The device structures herein can also be configured to implement other transistor devices (such as complementary bipolar inversion channel field effect transistors), optoelectronic devices (such as HFET phototransistors, VCSELs, in-plane lasers, electrically or optically pumped lasers, photothyristors, laser arrays, detectors, modulators and optical switches), and purely optical devices (such as passive waveguides and off-chip couplers).

[0110] In embodiments, the fabrication steps can be used to form electrical devices (such as complementary n-channel HFET devices and / or complementary PP bipolar inversion channel field effect transistors and complementary NN bipolar inversion channel field effect transistors or BICFET devices), along with optoelectronic devices (such as HFET phototransistors, VCSELs, in-plane lasers, electrically or optically pumped lasers, photodetectors and optical switches) and possibly purely optical devices (such as passive waveguides and off-chip couplers) into integrated circuits (ICs) employing epitaxial layers as described herein and shown in Figures 1 and / or 2A and 2B (prior to depositing the top mirror layer).

[0111] The manufacturing steps begin at block 401 where alignment marks are defined on layer 127 of the semiconductor layer structure.

[0112] In block 402, a nitride layer (approximately 500 Å thick) is deposited over layer 127 of the semiconductor layer structure.

[0113] A photoresist mask is deposited and patterned over the nitride layer in block 403. The patterned photoresist mask acts as an etch mask that defines the vertical laser opening and the in-plane waveguide opening. The openings are protected by the patterned photoresist mask.

[0114] In block 404, an etching step is performed in the semiconductor layer structure through the nitride layer deposited in 402 down to the heavily doped p-type layer 125 using the photoresist mask of 403 to define an opening, formed by a mesa in layer 127, which may optically function as a waveguiding region and / or resonant cavity for a particular optoelectronic or optical device in the IC.

[0115] In block 405, oxygen ions and then n-type dopant ions (e.g., Si / F ions) are implanted into the semiconductor layer structure on opposite sides of an opening for a particular optical device of the IC using the photoresist mask of 403. The oxygen ions are implanted to a depth centered at or near the center of the intermediate spacer layer 115.

[0116] N-type dopant ions are implanted to a depth centered at or near the center of layer 123 .

[0117] In block 407, a photoresist mask is deposited and patterned to expose all areas where a particular electronic device (i.e., NHFET transistor device, PHFET transistor device, PP BICFET transistor device, NN BICFET transistor device) will be formed. The openings for the optoelectronic devices, PP BICFET transistor devices and optical devices and the anode or top emitter contact areas are protected by the photoresist mask.

[0118] In block 408a, the semiconductor layer structure is etched using the photoresist mask of 407 to expose all areas where electronic devices (i.e., NHFET transistor devices, PHFET transistor devices, PP BICFET transistor devices, NN BICFET transistor devices) will be formed. The etch is controlled to terminate approximately 300-400 Å above layer 125. This etch depth may be designated as "d1" and is designed for proximity to layer 125. In an embodiment, the etch may employ a dry etch technique using a gas suitable for III-V compounds (e.g., BCl3).

[0119] In block 408b, the semiconductor layer structure is etched using the photoresist mask of 407 to expose all areas where electronic devices having a p-type inversion channel will be formed (including PHFET, PP BICFET, and NN BICFET transistor devices). The etch is controlled to terminate at layer 115, approximately 300-400 Å above layer 113 or layer 111. This etch depth may be designated as "d2", which is designed for proximity to layers 113 and 111. In an embodiment, the etch may employ a dry etch technique using a gas suitable for III-V compounds (e.g., BCl3).

[0120] In block 409, the photoresist mask of 407 is removed.

[0121] In optional block 410, a photoresist mask can be applied to expose certain n-channel devices (such as n-channel HFET devices), followed by an ion implant that is confined to the region above the n-type modulation doped QW structure 117 to maintain high channel mobility. The ion implant species is selected from n-type (e.g., 1e17 cm -3 ~1e18cm -3 Si / F ions in the range of 1e17cm -3 ~1e18cm-3 The doping type and concentration of the ion implantation can be in the range of (Be / F ions) 1e17 cm 2 , 1e20 cm 3 , 1e12 cm 4 , 1e24 cm 5 , 1e30 cm 6 , 1e40 cm 7 , 1e50 cm 8 , 1e60 cm 9 , 1e70 cm 10 , 1e80 cm 11 , 1e90 cm 12 , 1e10 cm 13 , 1e11 cm 14 , 1e12 cm 15 , 1e13 cm 16 , 1e14 cm 17 , 1e15 cm 18 , 1e16 cm 19 , 1e17 cm 20 , 1e17 cm 21 , 1e17 cm 22 , 1e17 cm 23 , 1e17 cm 24 , 1e17 cm 25 , 1e17 cm 26 , 1e17 cm 27 , 1e17 cm 28 , 1e17 cm 29 , 2e17 cm 30 , 1e17 cm 31 , 1e17 cm 32 , 1e17 cm 33 , 1e17 cm 34 , 1e17 cm 35 , 1e17 cm 36 , 1e17 cm 37 , 1e17 cm 38 , 1e17 cm 39 ... -3 ~1e18cm -3 p-type or p-type (such as Be / F ions in the range of 1e17cm -3 ~1e18cm -3 The doping type and concentration of the ion implantation can be configured to shift or adjust the p-channel threshold as deemed appropriate, such as to correct errors in the original epitaxy, to allow matching of optimal laser performance (threshold current) with optimal threshold voltage of n-channel HFET devices, and to allow implementation of multi-level logic designs. In this configuration, the implantation of p-type ions (such as Be / F ions) can shift the p-channel threshold down (i.e., make it more positive or more depletion type), while the implantation of n-type ions (such as Si / F ions) can shift the p-channel threshold up (i.e., make it more negative or more enhancement type). The photoresist mask can then be removed.

[0122] In block 411, a refractory metal (e.g., tungsten) is deposited for the upper features of the electronic devices, including n-channel devices at depth d1 in layer 123 and p-channel devices at depth d1+d2 in layer 115. A refractory metal (e.g., tungsten) is also deposited over layer 129 (exposed by the etch of 404) for anode or upper emitter electrodes for certain optoelectronic devices (e.g., VCSELs, in-plane lasers, electrically or optically pumped lasers, optical thyristors, laser arrays, photodetectors, optical modulators, and optical switches) and PP BICFET transistor devices.

[0123] In block 412, a photoresist mask is deposited and patterned to define the top features of the electronic device. The refractory metal (e.g., tungsten) of 411 is etched using the photoresist mask to define the features of the electronic device. The same or a different photoresist mask is used to etch the refractory metal (e.g., tungsten) to define the anode or top emitter electrodes of the optoelectronic device and the PP BICFET transistor device. The refractory metal (e.g., tungsten) of 411 can be patterned by dry etching using sulfur hexafluoride (SF6).

[0124] In block 413, the photoresist mask of 412 is removed.

[0125] In block 414, a photoresist mask is deposited and patterned to protect all electronic devices except the PP BICFET transistor devices, which is equivalent to exposing all optoelectronic devices, optical devices and the PP BICFET transistor devices.

[0126] In block 415, a photoresist mask is used at 414 to etch the semiconductor layers using, for example, BCl3 to a depth d1 similar to 408 for all n-channel optoelectronic devices. After this etch, the n-channel devices (both electrical and optical) are expected to have a common depth level at or near depth d1 of layer 127.

[0127] In block 416, the photoresist mask of 414 is removed.

[0128] In block 417, a photoresist mask is deposited and patterned on layer 123 at a d1 level to expose the source and drain contact regions of the NHFET transistor device, the base contact region of the PP BICFET transistor device, the collector contact region of the NN BICFET transistor device, and (when used) the n-channel contact region (also referred to as the n-source contact region or source contact region) of the optoelectronic device.

[0129] In block 418, the semiconductor layer structure is etched using, for example, BCl3 and a patterned photoresist mask at 417 to approximately the middle of layer 119 to expose source and drain contact regions of the NHFET transistor device, the base contact region of the PP BICFET transistor device, the collector contact region of the NN BICFET transistor device, and the n-channel contact region (also referred to as the n-source contact region or source contact region) of the optoelectronic device (when used).

[0130] In block 419, the photoresist mask of 417 is removed.

[0131] At block 420, a nitride layer of about 500 Å is deposited, for example by plasma enhanced chemical vapor deposition (PECVD) for conformal deposition. The nitride is then anisotropically etched to form dielectric sidewalls on all of the tungsten-covered mesas. The purpose of these sidewalls is to prevent implant penetration into the semiconductor sidewalls and to maintain the effective length of the submicron n-channel devices.

[0132] N-type dopant ions (eg, Si / F ions) are implanted in block 421. First, a source-drain photoresist mask (similar to the mask in 417) is deposited and patterned.

[0133] Next, n-type dopant ions (e.g., Si / F ions) are implanted into the source and drain contact regions of the NHFET transistor device, the base contact region of the PP BICFET transistor device, the collector contact region of the NN BICFET transistor device, and the n-channel contact region (also referred to as n-source contact region or source contact region) of the optoelectronic device (when used). In an embodiment, the n-type dopant concentration of the ion implantation is 5e 18 ~1e 19 cm -3 The range may be:

[0134] In block 422, the photoresist mask of 421 is removed.

[0135] In block 423, a photoresist mask is deposited and patterned over layer 127 at d1 level to expose the gate contact areas of the NHFET devices.

[0136] In block 424, p-type dopant ions (e.g., BE / F ions) are implanted into the gate contact region of the NHFET device using the photoresist mask of 423. In an embodiment, the p-type dopant concentration of the ion implant is about 1e 19 ~1.5e19 cm -3 The range may be:

[0137] In block 425, the photoresist mask of 423 is removed.

[0138] In block 426, a photoresist mask is deposited and patterned on layer 115 at level d1+d2 to expose the source and drain contact regions of the PHFET transistor device, the p-channel contact region of the optoelectronic device (when used), the base contact region of the NN BICFET transistor device, and the collector contact region of the PP BICFET transistor device.

[0139] In block 427, the semiconductor layer structure is etched using, for example, BCl3 and the patterned photoresist mask of 426 on layer 115 to a level of about 300 Å above layer 113.

[0140] At block 428, the photoresist mask of 426 is removed.

[0141] In block 429, approximately 500 Å of nitride is deposited by PECVD (for conformality) followed by an anisotropic nitride etch to form a dielectric sidewall on all of the tungsten-covered mesas, the purpose of which is to prevent implant penetration into the semiconductor sidewalls and QW channel, which would shorten the effective length of the p-channel HFET device.

[0142] In block 430, a photoresist mask is deposited and patterned on layer 115 (exposed by the etch of 427) to expose the source and drain contact regions of the PHFET transistor device, the p-channel contact region of the optoelectronic device (when used), the base contact region of the NN BICFET transistor device, and the collector contact region of the PP BICFET transistor device.

[0143] In block 431, p-type dopant ions (e.g., BE / F ions) are implanted into the source and drain contact regions of the PHFET transistor device, the p-channel contact region of the optoelectronic device (when in use), the base contact region of the NN BICFET transistor device, and the collector contact region of the PP BICFET device using the photoresist mask of 430. In an embodiment, the p-type dopant concentration of the ion implantation is about 1e 19 ~1.5e 19 cm -3 The range may be:

[0144] In block 432, the photoresist mask of 430 is removed.

[0145] In block 433, a photoresist mask is deposited and patterned on layer 115 (exposed by the etch of 427) to expose the gate contact area(s) of the PHFET device.

[0146] In block 435, n-type dopant ions (e.g., Si / F ions) are implanted into the gate contact region of the PHFET device using the photoresist mask of 434. In an embodiment, the n-type dopant concentration of the ion implantation is 5e 18 ~1e 19 cm -3 The range may be:

[0147] In block 436, the photoresist mask of 433 is removed.

[0148] In block 437, a photoresist mask is deposited and patterned on layer 115 (exposed by the etch of 427) to expose the cathode contact area of ​​the optoelectronic device (in use).

[0149] In block 438, the semiconductor layer structure is etched using, for example, BCl3 and the patterned photoresist mask of 437 down to layer 105 to expose the cathode contact areas and of the optoelectronic device (when in use).

[0150] In block 439, the photoresist mask of 437 is removed.

[0151] In block 440, silicon nitride is deposited to a typical thickness of 500 Å in preparation for rapid thermal annealing of all implanted regions.

[0152] In block 441, a high temperature short time anneal (RTA) step is performed. For example, the RTA step may employ a typical cycle of 850° C., 15 seconds in an inert background. The ion-implanted regions become amorphous due to the ion bombardment. An RTA step may be performed to anneal all the ion-implanted regions prior to metallization. The thermal energy of the RTA step transforms the amorphous structure back to a single crystalline structure, allowing the dopant atoms to form bonds on the semiconductor layer as donors (in the case of n-type) or acceptors (in the case of p-type).

[0153] At block 442, a photoresist mask is deposited and patterned to form n-type Au electrodes via lift-off. The n-type Au electrodes can include a gate electrode of a PHFET transistor device (formed at the n-type ion implanted gate contact region of the PHFET transistor device), a source electrode and a drain electrode of a NHFET transistor device (formed at the n-type ion implanted source contact region and the n-type ion implanted drain contact region of the NHFET transistor device), a base electrode of a PP BICFET transistor device (formed at the n-type ion implanted base contact region of a PP BICFET transistor device), a collector electrode and an emitter electrode of a NN BICFET transistor device (formed at the n-type ion implanted collector contact region and the n-type ion implanted emitter contact region (layer 101) of the NN BICFET transistor device), an n-channel electrode (or n-source electrode) of an optoelectronic device (formed at the n-type ion implanted n-channel contact region(s) of an optoelectronic device), and a cathode electrode of an optoelectronic device (formed at the n-type cathode contact region(s) (layer 101) of the optoelectronic device, when in use).

[0154] In block 443, n-type Au metal (eg, an alloy of AuGe-Ni-Au) for the n-type Au electrode is deposited.

[0155] In block 444, an n-type Au electrode is patterned via lift-off.

[0156] At block 445, a photoresist mask is deposited and patterned to form p-type Au electrodes via lift-off. The p-type Au electrodes can include a gate electrode of an NHFET transistor device (formed at the p-type ion implanted gate contact region of an NHFET transistor device), a source electrode and a drain electrode of a PHFET transistor device (formed at the p-type ion implanted source contact region and the p-type ion implanted drain contact region of a PHFET transistor device), a base electrode of an NN BICFET transistor device (formed at the p-type ion implanted base contact region of an NN BICFET transistor device), a base electrode of an NN BICFET transistor device (formed at the p-type ion implanted base contact region of an NN BICFET transistor device), a collector electrode and an emitter electrode of a PP BICFET device (formed at the p-type ion implanted collector contact region and the p-type ion implanted emitter contact region and the p-type ion implanted refractory metal emitter contact region of a PP BICFET transistor device), and a p-channel electrode (or p-source electrode) of an optoelectronic device (formed at the p-type ion implanted p-channel contact region(s) of an optoelectronic device, when in use).

[0157] At block 446, p-type Au metal (eg, an alloy of AuBe-Cr-Au) for the p-type Au electrode is deposited.

[0158] In block 447, a p-type Au electrode is patterned via lift-off.

[0159] The n-type Au electrode and the p-type Au electrode are sintered or annealed at block 448. For example, the sintering process may employ a typical cycle of 420° C. for 15 seconds.

[0160] In block 449, a photoresist mask is deposited and patterned for all devices to etch trenches (approximately 1000 Å) into the lower mirror layer 103 to isolate all devices.

[0161] In block 450, the photoresist mask 449 is used to etch the semiconductor layer structure down to the bottom mirror layer 103 using, for example, a dry etching technique (eg, BCl3).

[0162] In block 451, the photoresist mask of 449 is removed.

[0163] In block 452, an interlevel dielectric material, such as silicon nitride (SiN) or silicon oxide (SiO2), is deposited to allow for metal interconnect crossovers, if desired.

[0164] In block 453, a photoresist mask is deposited and patterned for etching contact holes for all metal interconnects.

[0165] The photoresist mask of 453 is used to etch contact openings through the interlevel dielectric material in block 454. For example, CF4 and SF6 etchants can be used to etch SiN or SiO2 dielectric materials.

[0166] In block 455, the photoresist mask of 453 is removed.

[0167] In block 456, a photoresist mask is deposited and patterned for Au metal interconnects to the various N-type and P-type Au electrodes required for any circuitry, and for connecting electronic and optoelectronic devices as required.

[0168] At block 457, Au metal is deposited for the Au metal interconnects.

[0169] In block 458, Au metal interconnects are patterned via lift-off.

[0170] Note that blocks 456-458 can be repeated multiple times if multiple metal interconnect levels are used.

[0171] In block 459, a photoresist mask is deposited and patterned to open openings for the optoelectronic and optical devices.

[0172] A photoresist mask 459 is used to etch openings for the optoelectronic and optical devices in block 460. For example, the etch can be a nitride-tungsten nitride etch using SF6 to expose layer 127 in the openings.

[0173] In block 461, the photoresist mask of 459 is removed.

[0174] In block 462, the upper mirror layer 129 is deposited to cover the exposed opening. For example, seven pairs of silicon dioxide (SiO2) and titanium dioxide (TiO2) can be deposited using ion beam assisted deposition (IBAD). The central wavelength of the upper mirror layer 129 is typically 980 nm, 850 nm, or 1310 nm.

[0175] In block 463, a photoresist mask is deposited and patterned to open bond pads for all devices, which may include dry etching of the upper mirror layer 133 using inductively coupled plasma etching (ICP).

[0176] In an optional step, the lower mirror layer exposed by the isolation etch at 450 can be oxidized. This step is useful when the lower mirror layer formed as part of the layer structure does not function as an adequate DBR mirror. In one embodiment, the lower mirror layer of aluminum arsenide (AlAs) exposed by the isolation etch is oxidized by oxidizing the AlAs that forms the lower DBR mirror. x O y ) is exposed to a steam atmosphere which converts to

[0177] It should be noted that the upper opening as described above may be configured to allow light to exit or enter the active region of the semiconductor layer structure.

[0178] Alternatively, the openings can be used to form passive and / or active in-plane waveguide structures as part of an optoelectronic or optical device realized in an IC described herein. Such in-plane waveguides guide the propagation of light in the plane of the IC, and the openings formed on the upper side provide for vertical confinement and guiding of light for the upper part of the IC wafer. In passive in-plane waveguide structures, the patterned anode metal can be omitted, and ion implanted regions can be formed below opposite sides of the upper opening to provide lateral confinement of light within the active region of the semiconductor layer structure located below the upper opening.

[0179] In embodiments, the epitaxial layer structures and fabrication methods described herein can be used to construct an IC having a stacked complementary HFET inverter including an NHFET device stacked with a PHFET device, which helps minimize the area of ​​the complementary HFET inverter as part of the IC.

[0180] 4A-4D illustrate one embodiment of a stacked complementary HFET inverter having an NHFET device stacked on a PHFET device. As best shown in FIG. 4B, the inverter has a generally rectangular layout. As best shown in FIGS. 4B and 4D, in the upper central portion of the rectangular layout, the gate contact electrode 305a for the gate of the PHFET device and the n-type implant region 302a thereunder extend along a straight line path along with the gate contact electrode 315a for the gate of the NHFET device and the p-type implant region 314a thereunder. The gate contact electrode 305a for the gate of the PHFET device and the n-type implant region 302a thereunder are laterally offset toward the periphery of the layout relative to the gate contact electrode 315a for the gate of the NHFET device and the p-type implant region 314a thereunder. The two gate contact electrodes 305a, 305b are connected together by metal to form the IN terminal of the inverter. In other parts of the rectangular layout, as best shown in Figures 4B and 4C, the upper feature 301 covering the channel of the PHFET device with source and drain contact electrodes 306a and 306b for the source and drain terminals of the PHFET device and the underlying p-type implant regions 304a, 304b extends in a segmented U-shape about the periphery of the layout with two segments extending towards the linear path of the gate of the PHFET device. Additionally, the upper feature 301 covering the channel of the NHFET device with drain contact electrode 316b for the node drain terminal of the NHFET device and the underlying n-type implant region 313b extends in a similar segmented U-shape offset laterally towards the central region of the layout. The source contact electrode 316a for the source terminal of the NHFET device and the underlying n-type implant region 313a are located in the central region of the layout. The drain contact electrode 306b of the PHFET device is interconnected by metal to the drain contact electrode 316b of the NHFET device to form the OUT terminal of the inverter. The source contact electrode 306a of the PHFET device forms the VDD terminal of the inverter.And, the source contact electrode 316a of the NHFET forms the GND terminal of the inverter.

[0181] Figures 5A and 5B show other exemplary embodiments of stacked complementary HFET inverters having NHFET devices stacked on PHFET devices. These embodiments are similar to the embodiments of Figures 4A-4D, except that the drain terminals of the NHFET and PHFET devices are maintained electrically and physically isolated from one another. The embodiment of Figure 5B can provide higher drive current, i.e., fan-out, for the inverter.

[0182] The embodiments of Figures 5A and 5B can be used as building blocks for other complementary HFET circuits as part of an IC, such as NOR and NAND gates, flip-flops, counters, etc. For example, Figures 6A and 6B show a two-input NAND gate constructed from stacked complementary HFET devices. In another example, Figures 7A and 7B show a two-input NOR gate constructed from stacked complementary HFET devices.

[0183] The epitaxial layer structures and fabrication methods described herein can also be configured to realize bipolar inversion channel field effect transistors (BICFETs) having an n-type modulation doped quantum well inverted channel base region (PP BICFET) or a p-type modulation doped quantum well inverted channel base region (NN BICFET).

[0184] As shown in Figures 8A-8D, the PP BICFET transistor device employs an interdigital feature 801 overlying an n-type modulation doped quantum well inversion channel base region having a QW channel(s) realized in n-type modulation doped QW structures 117, 121 and 123. The interdigital feature 801 may be formed from a refractory metal such as tungsten. The corresponding interdigital base region (underlying the feature 801) is operatively coupled to an interdigital base contact electrode 806 via an n-type ion implanted region 804. The interdigital collector regions of the p-type modulation doped QW structures 107, 109 and 113 are operatively coupled to an interdigital collector contact electrode 807 via a p-type ion implanted region 805. An emitter electrode 809 is electrically coupled to the p+ doped gate layers 125 and 119 of the interdigital base regions via a p-type ion implanted region 808. The emitter electrode 809 also contacts the tungsten electrode 801 such that the upper P+ layer 129 and the nanosheet 125 are connected. The PP BICFET transistor device is a bipolar junction transistor that can operate in an active mode where holes are injected from the emitter terminal electrode to the collector terminal electrode by reverse biasing the PN junction between the base and collector regions while forward biasing the PN junction between the emitter and base regions. Since holes are positive carriers, the injection of holes causes a current to flow out of the collector terminal electrode and into the emitter terminal electrode. The bias condition causes electrons to be injected from the base to the emitter, thereby contributing to the current flowing out of the base terminal electrode as well as the current flowing into the emitter terminal electrode. The large band gap blocking layer 127 ensures that this flow of electrons from the channel to the emitter is small to allow for large current gain.

[0185] As shown in Figures 9A-9D, the NN BICFET transistor device employs an interdigital feature 901 overlying a p-type modulation doped quantum well inversion channel base region having a QW channel(s) realized in p-type modulation doped QW structures 113, 107, and 109. The interdigital feature 901 may be formed from a refractory metal such as tungsten. The corresponding interdigital base region (underlying the feature 901) is operatively coupled to an interdigital base contact electrode portion 907 via a p-type ion implanted region 905. The interdigital feature 901 overlies the interdigital collector regions of the n-type modulation doped QW structures 117, 121, and 123, which are operatively coupled to an interdigital collector contact electrode portion 906 via an n-type ion implanted region 904. An emitter electrode 908 is electrically coupled to the N+ type modulation doped QW structures 111 and 105 of the interdigital base region via an n-type ion implanted region 910. The emitter electrode 908 also contacts the lower n+ layer 101 such that the layer 101 and the nanosheet 111 are connected. The NN BICFET device is a bipolar junction transistor that can operate in an active mode by injecting electrons from the emitter terminal electrode to the collector terminal electrode by forward biasing the PN junction between the emitter and base regions while reverse biasing the PN junction between the base and collector regions. Since electrons are negative carriers, the injection of electrons causes a current to flow into the collector terminal electrode and out of the emitter terminal electrode. The bias conditions cause holes to be injected from the base to the emitter, which contribute to the current flowing into the base terminal electrode and out of the emitter terminal electrode.

[0186] The epitaxial layer structures and fabrication methods described herein can be used to realize a variety of optoelectronic and optical devices, for example, the epitaxial layer structures and fabrication methods described herein can be used to realize HFET phototransistors.

[0187] For example, an NHFET device similar to that of Figures 3D-3F can be configured to operate as a phototransistor with current flowing as a two-dimensional gas through the QW channel region of the n-type modulation doped QW structures 121, 123 of the second GAA layer structure and the n-type modulation doped QW structure 117 with source and drain terminal electrodes on either side of the absorbing QW channel region, in which case the NHFET becomes a waveguide for in-plane implementation. In this configuration, ion-implanted n-type source contact region 313a and ion-implanted n-type drain contact region 313b can penetrate layer 115 through both the second GAA layer structure and the n-type modulation doped QW structure 117. The QW channel region operates as the active waveguide region and the basic transistor operation is modulation of the QW channel conductance by an inversion layer (i.e., a two-dimensional electron gas) created by absorption of optical modes propagating in the active waveguide region of the phototransistor. In this case, the gate terminal electrode can be omitted. Specifically, the conductance of the QW channel is controlled by the absorption of optical modes propagating in the active waveguide region of the phototransistor, which creates an inversion layer of electron gas in the QW channel of the n-type modulation doped quantum well structure 117, 121, 123 between the source and drain terminal electrodes. This inversion layer provides a source-drain current path that conducts current between the source and drain terminal electrodes. In other words, the source-drain current path of the phototransistor device is in a conducting, on-state. In the absence of inversion, there is no source-drain current path that conducts current between the source and drain terminal electrodes. In other words, the source-drain current path of the phototransistor is in a non-conducting, off-state. In this configuration, the source terminal electrode is the terminal electrode through which electron carriers enter the QW channel of the n-type modulation doped QW structure 117, 121, 123, and the drain terminal electrode is the terminal electrode through which electron carriers exit the device.

[0188] In another embodiment, a PHFET device similar to those of Figures 3A-3C can be configured to operate as a phototransistor with current flowing as a two-dimensional gas through the QW channel region of the p-type modulation doped QW structures 107, 109 of the first GAA layer structure and the p-type modulation doped QW structure 113 with source and drain terminal electrodes on either side of the absorbing QW channel region, in which case the NHFET becomes a waveguide for in-plane implementation. In this configuration, ion-implanted p-type source contact region 304a and ion-implanted p-type drain contact region 304b can penetrate layer 105 through both the p-type modulation doped QW structure 113 and the first GAA layer structure. The QW channel region operates as the active waveguide region and the basic transistor operation is modulation of the QW channel conductance by an inversion layer (i.e., a two-dimensional hole gas) created by absorption of optical modes propagating in the active waveguide region of the phototransistor. In this case, the gate terminal electrode can be omitted. Specifically, the conductance of the QW channel is controlled by the absorption of optical modes propagating within the active waveguide region of the phototransistor, which creates an inversion layer of hole gas in the QW channel of the p-type modulation doped quantum well structure 107, 109, 113 between the source and drain terminal electrodes. This inversion layer provides a source-drain current path that allows current to be conducted between the source and drain terminal electrodes. In other words, the source-drain current path of the phototransistor device is in a conducting ON state. In the absence of inversion, there is no source-drain current path that allows current to be conducted between the source and drain terminal electrodes. In other words, the source-drain current path of the phototransistor is in a non-conducting OFF state. In this configuration, the source terminal electrode is the terminal electrode through which hole carriers enter the QW channel of the p-type modulation doped QW structure 107, 109, 113, and the drain terminal electrode is the terminal electrode through which hole carriers exit the device.

[0189] Examples of such optoelectronic and optical devices are shown in Figures 10A to 23. Such devices may employ resonant cavities for emission and / or detection of optical signals.

[0190] In one configuration, the resonant cavity of the device can be configured as a vertical cavity, and light can enter and exit the vertical cavity through an optical opening (not shown) in the top surface of the device. In this configuration, the distance between the top mirror layer 133 and the bottom mirror layer 99 represents the length of the optical cavity, and this distance can be set to correspond to a specified wavelength (e.g., 1-4 times the specified wavelength in the material). This distance can take into account the penetration depth of the light into the bottom mirror layer and the top mirror layer. This distance is controlled by adjusting the thickness of one or more layers in between to enable this condition.

[0191] In other configurations, the resonant cavity of the device can be configured as a whispering gallery microresonator or a closed loop microresonator to support the propagation of an optical mode signal within a waveguide region formed from the device structure. In the case of a whispering gallery microresonator, the waveguide region can be a disk-like structure that supports the propagation of a whispering gallery mode. The shape of the disk-like structure is tuned to a specific wavelength of the whispering gallery mode. For example, the periphery of the disk-like structure can be configured to correspond to an integer multiple of the wavelength of the standing wave circulating within the disk-like structure. For a relatively small disk-like structure (e.g., diameter 10 μm or less), the free spectral range FSR is large enough that the diameter of the disk-like structure can determine the specific wavelength of the whispering gallery mode. In the case of a closed loop microresonator, the waveguide can support the circulating propagation of the optical mode following a circular, rectangular, elliptical path or other suitable shape. The optical path length of the closed loop waveguide is tuned to a specific wavelength of the optical mode signal propagating within the closed loop waveguide. At least one coupling waveguide is integrally formed adjacent to the whispering gallery microresonator or the closed-loop microresonator. The coupling waveguide provides evanescent coupling of light to and / or from the whispering gallery microresonator or the closed-loop microresonator. Specifically, in the case of a laser, the coupling waveguide couples the whispering gallery modes generated by the whispering gallery microresonator or the optical mode signals circulating in the closed-loop waveguide of the closed-loop microresonator to generate an output optical signal that propagates through the coupling waveguide for output. In the case of a detector, input light is provided to the coupling waveguide, which couples the input optical signal as a whispering gallery mode in the whispering gallery microresonator for detection or as an optical mode signal circulating in the closed-loop waveguide of the closed-loop microresonator for detection.

[0192] 10A and 10B show an HFET VCSEL thyristor laser realized from the epitaxial layer structure and fabrication methods described herein. In another embodiment, an array of HFET VCSEL devices can be integrally formed with a common top emitter electrode and a common source electrode.

[0193] 11A and 11B show a thyristor VCSEL realized from the epitaxial layer structure and fabrication methods described herein.

[0194] FIG. 12 shows a LIDAR pixel realized from the epitaxial layer structure and fabrication methods described herein.

[0195] FIG. 13 shows a single frequency thyristor in-plane laser realized from the epitaxial layer structure and fabrication methods described herein.

[0196] 14A-14D show a frequency tunable thyristor in-plane laser realized from the epitaxial layer structure and fabrication methods described herein.

[0197] FIG. 15 shows a dual-input directional coupler realized from the epitaxial layer structure and fabrication methods described herein.

[0198] FIG. 16 illustrates a thyristor optoelectronic oscillator realized from the epitaxial layer structure and fabrication methods described herein.

[0199] 17A and 18B show waveguide photodetectors, optical modulators and optical amplifiers realized from the epitaxial layer structures and fabrication methods described herein.

[0200] FIG. 18 shows active waveguides (suitable for use in HFET lasers, photodetectors, optical modulators and optical amplifiers) realized from the epitaxial layer structures and fabrication methods described herein.

[0201] FIG. 19 illustrates passive waveguides (suitable for use in photodetectors, optical modulators and optical amplifiers) realized from the epitaxial layer structures and fabrication methods described herein.

[0202] FIG. 20 illustrates a waveguide splitter or combiner realized from the epitaxial layer structures and fabrication methods described herein.

[0203] FIG. 21 shows an optical switching structure (having 2×2 optical switching elements) realized from the epitaxial layer structure and fabrication methods described herein.

[0204] FIG. 22 illustrates a thyristor optical switching node (or generic thyristor whispering gallery mode laser) realized from the epitaxial layer structure and fabrication methods described herein.

[0205] 23 and 24 show an array of in-plane wavelength demultiplexers (or an array of in-plane wavelength multiplexers) realized from the epitaxial layer structures and fabrication methods described herein.

[0206] FIG. 25 illustrates a universal optical data bus with components realized from the epitaxial layer structures and fabrication methods described herein.

[0207] FIG. 26 illustrates an optical device that converts in-plane light to vertical light (or vice versa) realized from the epitaxial layer structures and fabrication methods described herein.

[0208] FIG. 27 is a schematic diagram of interconnected bipolar transistors that correspond to the thyristor devices implemented by the device structures of FIGS. 1 and 2A-2B.

[0209] FIG. 28 is an exemplary energy band diagram of a thyristor device realized by the device structure of FIGS. 1 and 2A-2B. For the thyristor labeled GAA Thyristor with Double Emitter BICFET, the diagram shows two energy barriers for hole flow associated with the anode and two energy barriers for electron flow associated with the cathode. This is in comparison to a thyristor structure using a single emitter BICFET (labeled "Original Thyristor") that uses one energy barrier for the anode and one for the cathode. Both structures meet the requirements for thyristor operation: i) a pair of complementary bipolar transistors, ii) a common collector region, and ii) the base of each component of the pair connected to the collector of the other component. Assuming that the inversion layer charge (upper well electrons and lower well holes) is shared equally between the two quantum well sets (by conduction of electrons over the barrier between 117 and 121 / 123 in FIG. 2A and conduction of holes over the barrier between 113 and 109 / 107 in FIG. 2B, or by a common injected N+ source for electrons and a common injected P+ source for holes as shown in FIG. 11B), the emitter current injected into the common collector region is the same for the two structures, provided that the charge sheet is appropriately reduced (by about a factor of two) to compensate for the reduced barrier voltage drop due to the reduced inversion charge. This situation results in approximately the same switching voltage (V sw ) and holding voltage (V h ) for the HFET. Thus, similar performance is expected for the two structures. Alternatively, the HFET quantum wells (121 / 123 for electrons and 109 / 107 for holes) can be adjusted to different V by choosing different values ​​for the doping of the modulator sheets, the thickness of the spacer layers, the number of quantum wells, etc. sw and V h The voltage drop can be designed to be small to achieve even smaller values ​​of V. A good example of this design flexibility is the selection of d (collector region spacing) in Figure 27. Since the backgate electrode does not affect the performance of the HFET, it is possible to select a desired value of V without compromising the HFET. swTo achieve this, d can be reduced to a significantly smaller value.

[0210] In the case of a thyristor laser device, i) the anode terminal electrode is forward biased with respect to the cathode terminal electrode, and ii) a critical switching charge Q is a charge that reduces the forward breakdown voltage in the n-type modulation doped QW structures 117, 121, and 123 such that there is no off-state bias point. CR When the voltage between the n-channel source and anode electrodes is biased to generate a charge greater than the critical switching charge Q CR Alternatively, the critical switching charge can be generated by integrating the charge in some or all of the sets of quantum wells over time with light incident on the device, via absorption. The critical switching charge Q CR is specific to the device geometry and doping level. The charge on the n-type modulation doped QW structures 117, 121 and 123 (or the charge on the p-type modulation doped QW structures 113, 109 and 107) reaches a critical value of channel charge that maintains retention operation, the retained charge Q H When the current I through the device falls below the holding current of the device for a sufficient time such that I decreases below the holding current of the device, the device switches from a conducting / on state (where I is significantly greater than zero) to a non-conducting / off state (where I is approximately zero through the device). Thus, when the anode terminal electrode is forward biased with respect to the cathode terminal electrode, and a critical switching charge Q CRWhen the n-channel source electrode (and / or p-channel source electrode) is biased to generate a current I, the device switches to the conductive / on state. In this state, the electrons and holes required for light emission are concentrated in both quantum wells. The current I in the conductive / on state is equal to or greater than the threshold current I for lasing. TH If the photon emission is above 100 nm, photon emission occurs within the device structure. An example plot of the current-voltage IV characteristics of a thyristor laser is shown in FIG. 29. In the case of a vertical cavity surface emitting laser, photon emission within the device structure produces an optical mode that emits vertically from the top surface of the device structure. In the case of a whispering gallery microresonator, photon emission within the device structure produces a whispering gallery mode signal that circulates within the waveguide region of the whispering gallery microresonator. In the case of a closed loop microresonator, photon emission within the device structure produces an optical mode signal that circulates within the closed loop waveguide of the closed loop microresonator.

[0211] It is important to note in the overall growth structure that quantum wells are used to support laser action. There are two groups of quantum wells that are relevant for NHFET devices. The lower quantum wells are used to turn the thyristor on and off, are not involved in NHFET conduction, and are used for photon generation for thyristor and HFET lasers. The upper quantum wells are used for NHFET operation and also generate photons for thyristor and HFET lasers. Thus, these quantum well groups are known as λ lase A design constraint is a spacing of 0.1 / 2 between the quantum wells. There are also two quantum well groups associated with the PHFET device. The upper quantum well is used to switch the thyristor on and off, does not participate in the PHFET conduction, and can be chosen to be the same bandgap as the quantum wells in the NHFET or a larger bandgap to prevent interference with the laser function. The lower quantum well forms the PHFET conduction channel, optimizing hole mobility and chosen so as not to interfere with the laser function.

[0212] In the case of a thyristor detector, the device structure switches from a non-conducting / off state (where the current I through the device is approximately zero) to a conducting / on state (where the current I is significantly greater than zero) in response to an input optical signal that induces charge in the n-type modulation doped QW structures 117, 121 and 123 and / or the p-type modulation doped QW structures 113, 109 and 107 due to photon absorption of the input optical signal. Specifically, the anode terminal electrode is forward biased with respect to the cathode terminal electrode, and the voltage between the n-channel source electrode and the anode electrode (and / or the voltage between the p-channel source electrode and the cathode terminal electrode) is biased such that the charge induced in the n-type modulation doped QW structures 117, 121 and 123 (and / or the p-type modulation doped QW structures 113, 109 and 107) as a result of photon absorption of the input optical pulse is greater than the critical switching charge QCR. In this situation, the thyristor switches to the on state, as it was in the presence of optical input. When the input optical signal is removed, the device converts the charge in the n-type modulation doped QW structures 117, 121 and 123 (and / or the p-type modulation doped QW structures 113, 109 and 107) to a retained charge Q H The device switches from a conducting / on state (current I is significantly greater than zero) to a non-conducting / off state (current I through the device is approximately zero) when the I decreases below 100 . In the case of a vertical cavity surface detector, the device structure absorbs optical modes that receive light vertically through the top surface of the device structure. In the case of a whispering gallery microresonator, the device structure absorbs whispering gallery modes that circulate within the waveguide region of the whispering gallery microresonator. In the case of a closed loop microresonator, the device structure absorbs optical mode signals that circulate within the closed loop waveguide of the closed loop microresonator.

[0213] FIG. 30 illustrates a diode-like laser (analog VCSEL) realized from the epitaxial layer structure and fabrication methods described herein. In this embodiment, the epitaxial layer structure omits the inverted p-type modulation doped quantum well structure 113 spaced vertically below the non-inverted n-type modulation doped quantum well structure 117, resulting in a PIN diode type current-voltage characteristic suitable for analog optical devices obtained vertically through a bulk epitaxial layer structure. An example plot of the current-voltage IV characteristic of a diode type laser (e.g., FIG. 30) is shown in FIG. 29. In this embodiment, when the anode terminal electrode is forward biased with respect to the cathode terminal electrode and the current I flowing vertically through the device structure is greater than the laser threshold I TH photon emission occurs in the device structure when the photon emission exceeds 100 nm. In an embodiment, photon emission can occur in the quantum well layers of both the p-type all-around gate layer structure (layers 119-125) and the n-type all-around gate layer structure (layers 105-111). Light is emitted through an aperture located between the anode terminals and the top mirror 133.

[0214] In another embodiment, a device similar to FIG. 30 can be configured to implement a photodetector that converts an optical signal into an electrical signal (an analog photodetector). In this embodiment, when the anode terminal electrodes are reverse biased with respect to the cathode terminal electrodes, an optical signal received at the photodetector produces an electrical signal (e.g., a current signal at the cathode terminal) whose magnitude corresponds to the intensity of the received optical signal. The received optical signal is directed to the active device structure through an opening disposed between the anode terminals. In an embodiment, photon absorption can occur in the quantum well layers of both the p-type all-around gate layer structure (layers 119-125) and the n-type all-around gate layer structure (layers 105-111).

[0215] FIG. 31 illustrates another diode type laser (analog VCSEL) realized from the epitaxial layer structure and fabrication methods described herein. In this embodiment, the epitaxial layer structure omits the inverted p-type modulation doped quantum well structure 113 spaced vertically below the non-inverted n-type modulation doped quantum well structure 117 and the n-type all-around gate layer structure (layers 105-111), resulting in a PIN diode type current-voltage characteristic suitable for analog optical devices obtained vertically through the bulk epitaxial layer structure. An example plot of the current-voltage IV characteristic of a diode type laser (e.g., FIG. 31) is shown in FIG. 29. In this embodiment, when the anode terminal electrode is forward biased with respect to the cathode terminal electrode and the current I flowing vertically through the device structure is greater than the laser threshold I TH photon emission occurs in the device structure when the photon emission exceeds 100 nm. In an embodiment, photon emission may occur in a quantum well layer of a p-type all-around gate layer structure (layers 119-125). Light is emitted through an aperture located between the anode terminals and the top mirror 133.

[0216] In another embodiment, a device similar to FIG. 31 can be configured to implement a photodetector that converts an optical signal to an electrical signal (analog photodetector). In this embodiment, when the anode terminal electrodes are reverse biased with respect to the cathode terminal electrodes, the optical signal received at the photodetector produces an electrical signal (e.g., a current signal at the cathode terminal) whose magnitude corresponds to the intensity of the received optical signal. The received optical signal is directed to the active device structure through an opening disposed between the anode terminals. In an embodiment, absorption of photons can occur in the quantum well layer (layers 119-125) of a p-type all-around gate layer structure.

[0217] In some embodiments, a diffraction grating can be formed in the device structure described above to provide total internal reflection in the in-plane waveguide. In effect, the diffraction grating provides a mirror across the waveguide.

[0218] It is also contemplated that the layer structures described herein may include a metamorphic buffer structure formed on the substrate between the lower mirror layer(s) and the lower n-type layer of the active device structure. The metamorphic buffer structure may employ multiple layers configured to accommodate lattice distortions resulting from mismatch between the active device structure and the substrate. An example of such a metamorphic buffer structure is described in U.S. Patent Application Serial No. 14 / 222,841, filed March 24, 2014, which is incorporated herein by reference in its entirety.

[0219] Herein, several embodiments of methods for forming integrated circuits employing complementary modulation doped quantum well structures for both complementary transistor devices and optoelectronic devices integrally formed as part of the integrated circuit have been described and illustrated. Although specific embodiments of the invention have been described, it is not intended that the invention be so limited, and it is intended that the invention be as broad as the art will permit, and that the specification be read in the same manner. Thus, while specific III-V material systems and heterostructures have been disclosed, it is understood that other III-V material systems and heterostructures can be used to realize the optoelectronic integrated circuits described herein. Thus, it will be understood by those skilled in the art that the invention provided may be further modified without departing from the spirit and scope as claimed.

Claims

1. 1. A method of forming an integrated circuit, comprising: depositing or providing a plurality of semiconductor layers supported on a substrate, the plurality of semiconductor layers having a p-type gate-all-around layer structure having a plurality of quantum well structures formed between a pair of vertically spaced p-type thinly doped layers; implanting p-type ions into the plurality of semiconductor layers to form at least one ion-implanted p-type gate contact region extending through the p-type gate layer all around structure and contacting the lightly p-type doped layer of the p-type gate layer all around structure; implanting n-type ions into the plurality of semiconductor layers to form ion-implanted n-type source contact regions and ion-implanted n-type drain contact regions contacting the p-type gate-all-around layer structure; forming a gate electrode of an n-channel HFET transistor device contacting the at least one ion-implanted p-type gate contact region; forming source and drain electrodes of the n-channel HFET transistor device contacting the ion-implanted n-type source contact region and the ion-implanted n-type drain contact region, respectively; A method for providing the above.

2. the plurality of semiconductor layers further comprises a non-inverted n-type modulation doped quantum well structure formed under the p-type gate-all-around layer structure, the non-inverted n-type modulation doped quantum well structure having an n-type charge sheet disposed on at least one pair of quantum well layer and barrier layer; and / or the ion-implanted n-type source contact region and the ion-implanted n-type drain contact region both contact the non-inverted n-type modulation doped quantum well structure; and / or the multiple quantum well structures of the p-type gate layer all around structure comprise a non-inverted n-type modulation doped quantum well structure disposed on an inverted n-type modulation doped quantum well structure, the non-inverted n-type modulation doped quantum well structure having an n-type charge sheet disposed on at least one pair of quantum well layers and barrier layers, the inverted n-type modulation doped quantum well structure having at least one pair of quantum well layers and barrier layers disposed on an n-type charge sheet; and / or performing a thermal annealing step to anneal the at least one ion-implanted p-type gate contact region, the ion-implanted n-type source contact region, and the ion-implanted n-type drain contact region before forming the gate electrode, source electrode, and drain electrode of the n-channel HFET device; and / or 10. The method of claim 1, wherein a feature is formed from a refractory metal, the feature covering a quantum well channel region provided by the p-type gate layer all around structure, the ion-implanted n-type source contact region and the ion-implanted n-type drain contact region being disposed opposite each other along opposite sides of the feature, and the at least one ion-implanted p-type gate contact region being disposed adjacent at least one end of the feature.

3. the plurality of semiconductor layers further comprises at least one additional layer formed on the p-type gate-all-around layer structure; performing an etching step (El) on the plurality of semiconductor layers, the etching step (El) exposing a portion of at least one additional layer; 2. The method of claim 1, wherein p-type ions are implanted into the plurality of semiconductor layers through a portion of the at least one additional layer exposed by the etching step (El) to form the at least one ion-implanted p-type gate contact region.

4. the plurality of semiconductor layers further comprises an n-type gate layer structure all around having at least one quantum well structure formed between a pair of n-type lightly doped layers spaced apart in a vertical direction from each other, and at least one spacer layer is disposed between the p-type gate layer structure all around and the n-type gate layer structure; implanting n-type ions into the plurality of semiconductor layers to form at least one ion-implanted n-type gate contact region extending through the n-type gate layer all around structure and contacting the lightly n-type doped layer of the n-type gate layer all around structure; implanting p-type ions into the plurality of semiconductor layers to form ion-implanted p-type source contact regions and ion-implanted p-type drain contact regions contacting the n-type gate-all-around layer structure; forming a gate electrode of a p-channel HFET device in contact with the at least one ion-implanted n-type gate contact region; 2. The method of claim 1, wherein source and drain electrodes of the p-channel HFET device are formed in contact with the ion-implanted n-type source contact region and the ion-implanted n-type drain contact region, respectively.

5. the plurality of semiconductor layers further comprises an inverted p-type modulation doped quantum well structure formed on the n-type gate-all-around layer structure, the inverted p-type modulation doped quantum well structure having at least one pair of quantum well and barrier layers spaced apart above the p-type charge sheet by at least one spacer layer; and / or both the ion-implanted p-type source contact region and the ion-implanted n-type drain contact region contact the inverted p-type modulation doped quantum well structure; and / or the at least one quantum well structure of the n-type gate layer all around structure comprises a non-inverted p-type modulation doped quantum well structure disposed on the inverted p-type modulation doped quantum well structure, the non-inverted p-type modulation doped quantum well structure having a p-type charge sheet disposed on at least one pair of quantum well and barrier layers, the inverted p-type modulation doped quantum well structure having at least one pair of quantum well and barrier layers disposed on the p-type charge sheet; and / or performing a thermal annealing step to anneal the at least one ion-implanted n-type gate contact region, the ion-implanted p-type source contact region, and the ion-implanted p-type drain contact region before forming the gate electrode, source electrode, and drain electrode of the p-channel HFET device; and / or 5. The method of claim 4, further comprising forming an additional feature from a refractory metal, the additional feature covering a quantum well channel region provided by the n-type gate-all-around layer structure, the ion-implanted p-type source contact region and the ion-implanted p-type drain contact region being disposed opposite each other along opposite sides of the additional feature, and the at least one ion-implanted n-type gate contact region being disposed adjacent at least one end of the additional feature.

6. performing an etching step (E2) on the plurality of semiconductor layers, the etching step (E2) exposing a portion of the at least one spacer layer; 5. The method of claim 4, further comprising implanting n-type ions into the plurality of semiconductor layers through a portion of the at least one spacer layer exposed by the etching step (E2) to form the at least one ion-implanted n-type gate contact region.

7. the plurality of semiconductor layers further comprises a non-inverted n-type modulation doped quantum well structure formed under the p-type gate-all-around layer structure, the non-inverted n-type modulation doped quantum well structure having an n-type charge sheet disposed on at least one pair of quantum well layer and barrier layer; implanting p-type ions into the plurality of semiconductor layers to form an ion-implanted p-type emitter contact region contacting the p-type all-around gate layer structure; implanting n-type ions into the plurality of semiconductor layers to form an ion-implanted n-type base contact region contacting the p-type gate-all-around layer structure and the non-inverted n-type modulation doped quantum well structure; implanting p-type ions into the plurality of semiconductor layers to form an ion-implanted p-type collector contact region contacting the inverted p-type modulation doped quantum well structure and the n-type gate layer all around structure; forming an emitter electrode of the P-P BICFET device in contact with the ion-implanted p-type emitter contact region; forming a base electrode of the P-P BICFET device in contact with the ion-implanted n-type base contact region; forming a collector electrode of the P-P BICFET device in contact with the ion-implanted p-type collector contact region; the base and collector electrodes of the P-P BICFET device have interdigitated segments; 6. The method of claim 5, wherein the emitter electrode of the PP BICFET device contacts a refractory metal covering an emitter region of the PP BICFET device.

8. implanting n-type ions into the plurality of semiconductor layers to form an ion-implanted n-type collector contact region contacting the p-type gate-all-around layer structure and the non-inverted n-type modulation doped quantum well structure; implanting p-type ions into the plurality of semiconductor layers to form an ion-implanted p-type base contact region contacting the inverted p-type modulation doped quantum well structure and the n-type gate layer all around structure; implanting n-type ions into the plurality of semiconductor layers to form an ion-implanted n-type emitter contact region contacting the inverted p-type modulation doped quantum well structure and the n-type gate-all-around layer structure; forming a collector electrode of the N-N BICFET device in contact with the ion-implanted n-type collector contact region; forming an emitter electrode of the N-N BICFET device in contact with the ion-implanted n-type emitter contact region; forming a base electrode of the N-N BICFET device in contact with the ion-implanted p-type base contact region; The method of claim 7, wherein the base and collector electrodes of the N-N BICFET device have segments that are interdigitated with one another.

9. forming at least one optoelectronic or optical device as part of the integrated circuit while forming the n-channel HFET device; and / or the at least one optoelectronic or optical device has a PIN diode type current-voltage characteristic; and / or the at least one optoelectronic or optical device has a thyristor-type current-voltage characteristic; and / or The method of claim 1 , wherein the plurality of semiconductor layers comprises a III-V compound semiconductor material.

10. a plurality of semiconductor layers supported on a substrate, the plurality of semiconductor layers having a p-type gate-all-around structure having a plurality of quantum well structures formed between a pair of vertically spaced p-type thinly doped layers; at least one ion-implanted p-type gate contact region extending through the p-type gate layer all around structure and contacting the lightly p-type doped layer of the p-type gate layer all around structure; an ion-implanted n-type source contact region and an ion-implanted n-type drain contact region contacting the p-type all-around gate layer structure; a gate electrode of an n-channel HFET transistor device contacting the at least one ion-implanted p-type gate contact region; source and drain electrodes of the n-channel HFET transistor device contacting the ion-implanted n-type source contact region and the ion-implanted n-type drain contact region, respectively; 1. An integrated circuit comprising:

11. the plurality of semiconductor layers further comprises a non-inverted n-type modulation doped quantum well structure formed under the p-type gate-all-around layer structure, the non-inverted n-type modulation doped quantum well structure having an n-type charge sheet disposed on at least one pair of quantum well layer and barrier layer; and / or the ion-implanted n-type source contact region and the ion-implanted n-type drain contact region both contact the non-inverted n-type modulation doped quantum well structure; and / or and / or, before forming the gate electrode, the source electrode, and the drain electrode of the n-channel HFET device, the at least one ion-implanted p-type gate contact region, the ion-implanted n-type source contact region, and the ion-implanted n-type drain contact region are annealed by a thermal annealing process. the multiple quantum well structures of the p-type gate layer all around structure comprise a non-inverted n-type modulation doped quantum well structure disposed on an inverted n-type modulation doped quantum well structure, the non-inverted n-type modulation doped quantum well structure having an n-type charge sheet disposed on at least one pair of quantum well layers and barrier layers, the inverted n-type modulation doped quantum well structure having at least one pair of quantum well layers and barrier layers disposed on an n-type charge sheet; and / or 11. The integrated circuit of claim 10, wherein a feature is formed from a refractory metal, the feature overlies a quantum well channel region provided by the p-type gate layer all around structure, the ion-implanted n-type source contact region and the ion-implanted n-type drain contact region are disposed opposite each other along opposite sides of the feature, and the at least one ion-implanted p-type gate contact region is disposed adjacent at least one end of the feature.

12. the plurality of semiconductor layers further comprises an n-type gate layer structure all around having at least one quantum well structure formed between a pair of n-type lightly doped layers spaced apart in a vertical direction from each other, and at least one spacer layer is disposed between the p-type gate layer structure all around and the n-type gate layer structure; at least one ion-implanted n-type gate contact region extends through the n-type gate-all-around layer structure and contacts the n-type lightly doped layer of the n-type gate-all-around layer structure; both an ion-implanted p-type source contact region and an ion-implanted p-type drain contact region contact the n-type gate-all-around layer structure; a gate electrode of the p-channel HFET device contacting the at least one ion-implanted n-type gate contact region; 11. The integrated circuit of claim 10, wherein the source and drain electrodes of the p-channel HFET device are contacted to the ion-implanted n-type source and drain contact regions, respectively.

13. the plurality of semiconductor layers further comprises an inverted p-type modulation doped quantum well structure formed on the n-type gate-all-around layer structure, the inverted p-type modulation doped quantum well structure having at least one pair of quantum well and barrier layers spaced apart above the p-type charge sheet by at least one spacer layer; and / or both the ion-implanted p-type source contact region and the ion-implanted n-type drain contact region contact the inverted p-type modulation doped quantum well structure; and / or the at least one ion-implanted n-type gate contact region, the ion-implanted p-type source contact region, and the ion-implanted p-type drain contact region are annealed by a thermal annealing process; and / or 13. The integrated circuit of claim 12, wherein an additional feature is formed from a refractory metal, said additional feature covers a quantum well channel region provided by said n-type gate-all-around layer structure, said ion-implanted p-type source contact region and said ion-implanted p-type drain contact region are disposed opposite each other along opposite sides of said additional feature, and said at least one ion-implanted n-type gate contact region is disposed adjacent at least one end of said additional feature.

14. the plurality of semiconductor layers further comprises a non-inverted n-type modulation doped quantum well structure formed under the p-type gate-all-around layer structure, the non-inverted n-type modulation doped quantum well structure having an n-type charge sheet disposed on at least one pair of quantum well layer and barrier layer; an ion-implanted p-type emitter contact region contacting the p-type gate-all-around layer structure; an ion-implanted n-type base contact region contacts the p-type gate-all-around layer structure and the non-inverted n-type modulation doped quantum well structure; an ion-implanted p-type collector contact region contacts the inverted p-type modulation doped quantum well structure and the n-type gate layer all around structure; an emitter electrode of the P-P BICFET device contacting the ion-implanted p-type emitter contact region; a base electrode of the P-P BICFET device contacting the ion-implanted n-type base contact region; a collector electrode of the PP BICFET device contacting the ion-implanted p-type collector contact region; the base and collector electrodes of the P-P BICFET device have interdigitated segments; 14. The integrated circuit of claim 13, wherein the emitter electrode of the PP BICFET device contacted a refractory metal covering an emitter region of the PP BICFET device.

15. an ion-implanted n-type collector contact region contacts the p-type gate-all-around layer structure and the non-inverted n-type modulation doped quantum well structure; an ion-implanted p-type base contact region contacts the inverted p-type modulation doped quantum well structure and the n-type gate layer all around structure; an ion-implanted n-type emitter contact region contacting the inverted p-type modulation doped quantum well structure and the n-type gate layer all around structure; a collector electrode of the N-N BICFET device contacting the ion-implanted n-type collector contact region; an emitter electrode of the N-N BICFET device contacting the ion-implanted n-type emitter contact region; a base electrode of the N-N BICFET device contacting the ion-implanted p-type base contact region; The integrated circuit of claim 14 wherein the base and collector electrodes of the N-N BICFET device have segments that are interdigitated with one another.

16. 13. The integrated circuit of claim 12, wherein the n-channel HFET device is stacked above the p-channel HFET device as part of an inverter circuit or a logic gate.

17. at least one optoelectronic or optical device formed as part of the integrated circuit; and / or the at least one optoelectronic or optical device has a PIN diode type current-voltage characteristic; and / or the at least one optoelectronic or optical device has a thyristor-type current-voltage characteristic; and / or 11. The integrated circuit of claim 10, wherein the plurality of semiconductor layers comprises a III-V compound semiconductor material.

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