Inter-chiplet performance data streaming

Abstract

A method and system for inter-chiplet performance data streaming is disclosed. The disclosed technique includes the steps of: a subordinate chiplet accumulating event data associated with an event indicative of a performance aspect of the subordinate chiplet, the subordinate chiplet transmitting the event data to a master chiplet over a chiplet bus, and the master chiplet adding the received event data to an event record, the event record including the event data associated with the event previously received from the subordinate chiplet over the chiplet bus.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Patent Application No. 17 / 710,413, filed March 31, 2022, the entirety of which is incorporated by reference as if fully set forth herein. [Background technology]

[0002] The performance of a chiplet is typically measured by a diagnostic program that collects and analyzes performance data generated while the chiplet is being used in a target workload. Dedicated circuitry within the chiplet is designed to detect performance-related events and monitor the rate of occurrence of these events. Thus, during a monitoring phase, the chiplet's circuitry may be configured to execute a particular workload. During such execution, the occurrence of performance-related events is recorded and stored in memory. These stored records may then be post-processed to provide insights into the behavior of the chiplet under the workload. Because collecting diagnostic data is performed concurrently with other operations executed on the chiplet, the resources consumed thereby should be limited. Furthermore, recording of the collected data requires access to memory. In a package layout that includes multiple chiplets, not all chiplets have access to memory, and therefore recording of diagnostic data may be limited to only some of the chiplets.

[0003] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0004] [Figure 1] 1 is a block diagram of an example system in which one or more features of the present disclosure may be implemented. [Diagram 2]Based on this figure, a diagram of an example device composed of multiple chiplets in a packaging layout that may implement one or more features of the present disclosure. [Diagram 3] 1 is a block diagram of an example master chiplet and an example subordinate chiplet illustrating inter-chiplet performance data streaming, according to which one or more features of the present disclosure may be implemented. [Figure 4] 1 is a flow diagram of an example method for performance data streaming from a subordinate chiplet, according to which one or more features of the present disclosure may be implemented. [Diagram 5] 1 is a flow diagram of an example method for inter-chiplet performance data streaming, according to which one or more features of the present disclosure may be implemented. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] Systems and methods are provided for collecting and recording diagnostic data (including performance profiling) across a system of chiplets. As disclosed herein, chiplets that do not have access to dynamic random access memory (DRAM) (i.e., subordinate chiplets) are configured to stream the diagnostic data they collect to a chiplet that has access to DRAM (i.e., a master chiplet) over a chiplet bus, through which the former's diagnostic data is stored in the DRAM. Thus, the event data of the subordinate chiplets (including counts of occurrences of events in the subordinate chiplets during multiple time periods) are packed into respective event data packets and transmitted over the chiplet bus to the master chiplet. The master chiplet is configured to aggregate the received event data packets into event records and store the event records in DRAM. Assuming that a large number of events occur in multiple subordinate chiplets, the event data packets transmitted by the subordinate chiplets for each tracked event may consume a large portion of the available bandwidth on the chiplet bus. As disclosed herein, such bandwidth consumption can be limited by dynamically controlling the frequency at which each subordinate chiplet may transmit event data packets over the chiplet bus.

[0006] Aspects of the disclosure describe a method for inter-chiplet performance data streaming. The method includes accumulating, by a subordinate chiplet, event data associated with events indicative of performance aspects of the subordinate chiplet. The method further includes transmitting, by the subordinate chiplet, the event data to a master chiplet over a chiplet bus, receiving, by the master chiplet, the event data from the subordinate chiplet, and adding, by the master chiplet, the received event data to an event record. The event record includes event data associated with events previously received from the subordinate chiplet over the chiplet bus.

[0007] Aspects of the disclosure also describe a system for inter-chiplet performance data streaming. The system includes at least one processor and a memory that stores instructions that, when executed by the at least one processor, cause the system to accumulate, by a subordinate chiplet, event data, the event data being associated with an event indicative of a performance aspect of the subordinate chiplet. The instructions further cause the system to transmit, by the subordinate chiplet, the event data to a master chiplet over a chiplet bus, receive, by the master chiplet, the event data from the subordinate chiplet, and add, by the master chiplet, the received event data to an event record. The event record includes the event data associated with an event previously received from the subordinate chiplet over the chiplet bus.

[0008] Further aspects of the disclosure describe a non-transitory computer-readable storage medium including instructions executable by at least one processor to perform a method for inter-chiplet performance data streaming. The method includes accumulating, by a subordinate chiplet, event data associated with an event indicative of a performance aspect of the subordinate chiplet. The method further includes transmitting, by the subordinate chiplet, the event data to a master chiplet via a chiplet bus, receiving, by the master chiplet, the event data from the subordinate chiplet, and adding, by the master chiplet, the received event data to an event record. The event record includes the event data associated with the event previously received from the subordinate chiplet via the chiplet bus.

[0009] FIG. 1 is a block diagram of an example system 100 in which one or more features of the present disclosure may be implemented based on this block diagram. The system 100 may relate to, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. The device 100 may include a processor 110, an accelerated processing unit (APU) 120, a storage 130, an input device 140, a memory 150, and an output device 160. The system 100 may also include an input driver 145 and an output driver 165. Each of the processor 110 and the APU 120 may represent one or more cores of a central processing unit (CPU) and one or more cores of an APU. The memory 150 may represent a volatile or non-volatile memory, including a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a cache, or a combination thereof. The processor 110, the APU 120, the memory 150, or a subset thereof, may be located on the same die or on separate dies. In one aspect, the system 100 may include additional components not shown in FIG.

[0010] APU 120 may represent a graphics processing unit (GPU), i.e., a shader system with one or more arithmetic units configured to perform computations in parallel, for example according to a single instruction multiple data (SIMD) paradigm. APU 120 may be configured to accept computational and graphics rendering instructions from processor 110, process the computational and graphics rendering instructions, and / or provide output to a display (output device 160). In alternative aspects, APU 120 may be employed to perform signal processing operations (e.g., when embodied in a digital signal processor (DSP)), to perform accelerated operations through the use of a bitstream-configured field programmable gate array (FPGA), to perform neural processing operations through the use of a neural processing unit (NPU), or to perform other operations that may be more efficiently performed through the use of an accelerated processing unit rather than by processor 110.

[0011] Storage 130 may include fixed or removable storage (e.g., hard disk drive, solid state drive, optical disk, flash drive). Input device 140 may represent, for example, a keyboard, a keypad, a touch screen, a touch pad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless local area network card for receiving wireless IEEE 802 signals). Output device 160 may represent, for example, a display, a speaker, a printer, a haptic feedback device, one or more lights, an antenna, or a network connection (e.g., a wireless local area network card for transmitting wireless IEEE 802 signals). In one aspect, input driver 145 communicates with processor 110 (or APU 120) and input device 140 to facilitate receipt of input from input device 140 to processor 110 (or APU 120). In another aspect, the output driver 165 communicates with the processor 110 (or APU 120 ) and the output device 160 and facilitates transmission of output from the processor 110 (or APU 120 ) to the output device 160 .

[0012] FIG. 2 is a diagram of an example device configured with multiple chiplets in a package layout 200 that may implement one or more features of the present disclosure. Package layout 200 may include chiplets that are part of an APU (e.g., APU 120 of FIG. 1). For example, package layout 200 may include processing unit chiplet 230, compute unit (CU) chiplets 240.1-240.8, memory channel interface (MCI) chiplets 220.1-220.6, and microcontroller 250. Processing unit chiplet 230 may be used by a host (e.g., processor 110 of FIG. 1) to perform computational tasks associated with rendering graphics or any other multi-dimensional data processing. Computing unit chiplets 240.1-240.8 may each include a SIMD core that may be scheduled by processing unit 230 to perform computational tasks. MCI chiplets 220.1-220.6 may be used by other chiplets, such as processing unit 230, to access DRAM (eg, memory 150 of FIG. 1) via a communications link, such as interconnect fabric 210.

[0013] By design, some chiplets may access the DRAM through interconnect fabric 210 (to read or write, respectively, data they use or generate), while some chiplets are unable to access the DRAM. For example, MCI chiplets 220.1-220.6 are designed to facilitate read and write access to the DRAM for other chiplets (e.g., processing unit 230), but are unable to store data generated by their own circuitry in the DRAM. The inability to store such data presents a problem when performance related information must be collected from a chiplet and stored for later analysis of that chiplet's performance. For example, for an MCI chiplet, e.g., 220.1, it may be desirable to monitor the performance of a cache system that interfaces with the memory channel of the DRAM. In such a case, performance related events, such as hit or miss events, should be tracked and recorded. Thus, the ability of a chiplet to store its own generated data is useful, at least for diagnostic purposes.

[0014] To monitor performance aspects of various chiplets, diagnostic programs (e.g., running on the chiplets, such as host 110 and / or microcontroller 250) may be applied to track the occurrence of performance-related events in the chiplets when the chiplets are used to execute particular workloads. Such diagnostic programs may thus test various performance aspects while stressing the system of chiplet 200 with different workloads. The rate at which performance-related events occur within the chiplets may be recorded and used (possibly along with the recorded rates of other performance-related events) to measure the performance of the chiplets or of system 200 as a whole, for example. Performance monitoring of chiplets with and without access to DRAM is further described with reference to FIG. 3.

[0015] FIG. 3 is a block diagram of an example master chiplet and an example subordinate chiplet illustrating inter-chiplet performance data streaming according to which one or more features of the present disclosure may be implemented. FIG. 3 illustrates a master chiplet 310, which represents a chiplet that has access to DRAM (such as processing unit 230 of FIG. 2), and a subordinate chiplet 350, which represents a chiplet that does not have access to DRAM (such as any of MCI chiplets 220.1-220.6 of FIG. 2). Master chiplet 310 and subordinate chiplet 350, like other chiplets in package layout 200, are communicatively coupled via chiplet bus 390. As disclosed herein, both chiplets 310, 350 are configured to support performance monitoring by generating data associated with performance-related events. However, while master chiplet 310 may have access to DRAM 336 to store performance-related data (to enable performance analysis), subordinate chiplet 350 does not have such access. Thus, as disclosed herein, performance-related data generated by subordinate chiplet 350 is stored in DRAM via master chiplet 310.

[0016] Master chiplet 310 includes circuitry to facilitate performance monitoring performed by a diagnostic program driven by logic circuitry of microcontroller 250, for example. Master chiplet 310 includes multiplexer 320, recorder 325, event recording packet generator 330, memory interface 335, and decoder 340. Various circuits within master chiplet 310 are configured to generate an alert whenever a performance related event occurs. For example, logic associated with a cache system may be configured to generate an event signal whenever a hit event occurs in the cache system. Such an event signal, e.g., 305.1, is sent to multiplexer 320 along with other types of event signals 305.2-305.N that indicate the occurrence of other performance related events in the master chiplet, such as a miss event or a branch misprediction event. Events may be programmably selected (315) to be tracked by the diagnostic program depending on the performance aspect being monitored. For example, an event corresponding to the event signal 305.1 may be selected, such that each occurrence of such a selected event causes the generated event signal 305.1 to be sent via multiplexer 320 to recorder 325, whereby the corresponding event record is updated. Thus, recorder 325 includes event records that include the occurrence of each event and, possibly, other information associated with each event. For example, the recorder may include 16 counters (e.g., each of which may be implemented by a 48-bit register) that are used to record the occurrence of corresponding events.

[0017] Thus, in a monitoring phase in which performance aspects for a workload may be tested, the diagnostic program may programmatically select (315) events associated with the performance aspect being tested. Furthermore, the diagnostic program may programmatically select corresponding counters in which occurrences of the selected events are counted, i.e., the occurrences of the selected events are recorded in respective event records. The event record packet generator 330 is configured to retrieve event records from the recorder 325 and pack these records into corresponding event record packets. The packed event records are then sent to the memory interface 335 where the event record packets are stored in the DRAM 336. The event record packet generator 330 may be triggered to retrieve each event record from the recorder 325 periodically or whenever the corresponding counter of the recorder 325 approaches saturation (e.g., reaches a saturation threshold, such as that associated with a 90% saturation level). When an event record is retrieved by the event record packet generator 330, the corresponding counter in the recorder 325 may be reset.

[0018] Subordinate chiplet 350 also includes circuitry to facilitate performance monitoring performed by the diagnostic program. In this case, however, recording of event occurrences is accomplished via the chiplet with access to the DRAM, i.e., master chiplet 310. Subordinate chiplet 350 includes multiplexer 370, accumulator 375, clock controller 385, and event data packet generator 380. Similar to master chiplet 310, various circuits within subordinate chiplet 350 are configured to generate an alert whenever a performance-related event occurs. When a performance-related event occurs, respective logic within subordinate chiplet 350 generates event signals 355.1-355.N that are sent to multiplexer 370. Depending on the performance aspect being monitored, the event may be programmatically selected (365) by the diagnostic program to be tracked. Thus, whenever such an event occurs, an event signal, e.g., 355.1, is generated and sent via multiplexer 370 to accumulator 375, and the corresponding event data in accumulator 375 is updated. Thus, accumulator 375 contains event data including occurrences of respective events and possibly other information associated with each event. For example, accumulator 375 may contain 16 counters (e.g., each may be implemented by a 12-bit register) that are used to record occurrences of corresponding events. Thus, during the monitoring phase, the diagnostic program may programmatically select 365 an event (associated with the performance aspect being tested) and a corresponding counter (from accumulator 375) in which occurrences of the selected event are counted.

[0019] The event data in the accumulators 375 may be retrieved by the event data packet generator 380 and packed into event data packets. These event data packets are then transmitted to the master chiplet 310 via the chiplet bus 390. The event data packet generator 380 may be triggered to retrieve event data from the accumulators 375 periodically or whenever a respective counter in the accumulators 325 approaches saturation (e.g., reaches a saturation threshold, such as that associated with a 90% saturation level). For example, if one or more counters in the accumulators 325 are approaching saturation, the accumulators may signal to the clock controller 385 that event data corresponding to one or more of the counters is ready to be retrieved. In response, the clock controller may send clock signals to both the accumulators 375 and the event data packet generator 380 to trigger the retrieval of event data corresponding to one or more counters and the packing of the retrieved data into respective event data packets. When event data is acquired by the event data packet generator 380, a corresponding counter in the accumulator 375 may be reset.

[0020] In one aspect, each of two counters A and B of accumulator 375 may be configured to count events signaled by event signals 355.1 and 355.2. When either of these counters reaches a saturation threshold (e.g., the counter reaches 90% of its counting capacity), a respective saturation flag in accumulator 375 may be turned on. In response to the saturation flag being turned on, accumulator 375 may signal clock controller 385 to schedule acquisition of respective event data corresponding to counters A and B. Upon receiving such a signal, clock controller 385 may send a clock signal to initiate the process of acquiring the event data corresponding to these counters and packing the acquired event data into one or more packets. For example, a 32-bit packet format may be used in which bits 0-3 record an identification number associated with a first event, bits 4-15 record event data for the first event (e.g., the cumulative occurrences of the first event counted by counter A), bits 16-19 record an identification number associated with a second event, and bits 20-31 record event data for the second event (e.g., the cumulative occurrences of the second event counted by counter B). When the respective event data corresponding to counters A and B have been obtained and packed, accumulator 375 resets these counters, as described above, and the counts in counters A and B start again at 0.

[0021] Thus, as described above, the cumulative occurrences of events (occurring during operation of the respective circuits in the subordinate chiplets 350) recorded in the respective counters are obtained and packed by the event data packet generator 380 and then transmitted to the decoder 340 of the master chiplet 310 via the chiplet bus 390. The decoder 340 is configured to decode the received event packets. Applying the 32-bit packet format described above, the decoder may map the event data stored in bits 4-15 (e.g., data representing the cumulative number of occurrences of a first event) to a first counter in the recorder 325 identified based on the identification number (associated with the first event) stored in bits 0-3. Similarly, the decoder may map the event data stored in bits 20-31 (e.g., data representing the cumulative number of occurrences of a second event) to a second counter in the recorder 325 identified based on the identification number (associated with the second event) stored in bits 16-19. Thus, event data associated with a first event received in an event data packet over the chiplet bus is added to previously received event data associated with the first event. Similarly, event data associated with a second event received in an event data packet over the chiplet bus is added to previously received event data associated with the second event. Thus, recorder 325 may, for example, record the occurrence of a remote event (an event occurring in subordinate chiplet 350) in its first and second counters and record the occurrence of a local event (an event occurring in master chiplet 310) in another counter.

[0022] To accurately identify defects across the chiplet's circuits, the chiplets 310, 350 are designed to generate hundreds of event signals, the detection of which increases the complexity of the performance monitoring process. Furthermore, the large number of event signals generated by the subordinate chiplets 350 leads to the dispatch of a large number of event data packets to the master chiplet 310, as described above, which may consume a significant portion of the bandwidth available on the chiplet bus 390. Since the chiplet bus is typically designed for other control and data traffic between the chiplets in the package layout 200, the extra bandwidth consumed by these event packets should be balanced against the need to frequently update the event records in the DRAM. That is, there is a trade-off between the need to limit the bandwidth utilization on the chiplet bus 390 and the need to reduce the latency associated with the frequency of updating the event records in the DRAM used for performance analysis.

[0023] One way to limit bandwidth consumption may be by reducing the size of each message. As described above, a 32-bit packet format may be used to encode data associated with an event pair. For one event pair, for example, the event data and an identification number associated with the event may be encoded in 16 bits. The identification number associated with the event may be used to map the event to a counter in the recorder 325. Thus, each of the 16 counters in the recorder 325 may be specified with 4 bits. This leaves 12 bits to represent the event data. Thus, the counters in the accumulator 375 may be used to count up to 4,096 occurrences of each event. If the counter reaches its limit (to prevent saturation), it should be reset after its contents are retrieved, as described with reference to FIG. 4.

[0024] Another way to limit bandwidth consumption is to control the frequency at which event data packets are sent. To do so, a programmable timer 386 may be used to strike a balance between low bandwidth consumption and low latency. The timer 386 may be set to a periodic value that is programmatically and dynamically set, for example, by a diagnostic program. The timer's period value determines the period between successive messages of the event data packet (i.e., how often these messages are sent over the chiplet bus 390). In one aspect, each time the event data packet generator 380 sends an event data packet message 395 over the chiplet bus 390, the event data packet generator 380 may send a signal to the clock controller 385 to trigger a reset of the timer 386 to its period value. The timer 386 may then be decremented by the clock controller 386 using a reference clock. Thus, an event data packet message 395 is sent from a subordinate chiplet 350 over the chiplet bus 390 when 1) any of the accumulator counters are nearing saturation, or 2) the timer 386 expires.

[0025] Bandwidth consumption is also affected by the number of subordinate chiplets 350 simultaneously streaming their respective event data packet messages to the master chiplet 310 via the chiplet bus 390. In one aspect, the period value of the timer 386 in each chiplet 350 may be dynamically set according to the currently available bandwidth on the chiplet bus 390. For example, the available bandwidth may be shared among the streams of subordinate chiplets 350. In another example, some subordinate chiplets may be prioritized over other subordinate chiplets 350, and thus the former timers may be set to have shorter period values ​​than the latter timers. Thus, by measuring the currently available bandwidth on the chiplet bus 390, the diagnostic program may, for example, dynamically set the period value of the timer 386 in each subordinate chiplet to control (or limit) the overall bandwidth used by these chiplets during the monitoring phase.

[0026] FIG. 4 is a flow diagram of an example method 400 for performance data streaming from a subordinate chiplet, according to which one or more features of the present disclosure may be implemented. The method 400 begins with selecting an event to be tracked in a monitoring phase in step 410. In step 420, occurrences of the selected event in the subordinate chiplet 350 are counted. These event occurrences may be counted by a counter in the accumulator 375. The count may proceed until a saturation threshold T is reached. The saturation threshold is set relative to the counting capacity of the counter (e.g., 4,096 times for a 12-bit counter). Thus, in step 430, if the occurrence count reaches the saturation threshold, the method 400 proceeds to step 440. In step 440, if the timer 386 expires, the method 400 proceeds to step 450. As described above, to control bandwidth consumption, the timer 386 is set to a periodic value that determines how often messages in the event data packet are transmitted over the chiplet bus 390. At step 450, event data associated with the selected event is retrieved from the accumulator 375. The event data includes a count value retrieved from the counter that represents the cumulative number of occurrences of the selected event. Once the event data is retrieved (450), the counter is reset (480) and may continue to count (420) further occurrences of the selected event. At step 460, the retrieved event data is packed into an event data packet. In one aspect, the two selected events and their corresponding event data may be packed into a 32-bit packet format as described above. At step 470, the event data packet is then transmitted over the chiplet bus 390 to the master chiplet 310. A timer is then reset (490) to a period value, the expiration of which will trigger the next transmission of the event data packet 470.

[0027] FIG. 5 is a flow diagram of an example method 500 for inter-chiplet performance data streaming, according to which one or more features of the present disclosure may be implemented. The method 500 begins with accumulating event data by the subordinate chiplet 350 at step 510. The event data is associated with an event indicative of a performance aspect of the subordinate chiplet 350. Next, at step 520, the subordinate chiplet 350 transmits the event data to the master chiplet 310 via the chiplet bus 390. As disclosed herein, transmitting the event data via the chiplet bus 390 may be performed periodically according to a period that may be dynamically determined based on available bandwidth on the chiplet bus 390. The master chiplet 310 receives the event data at step 530 and then adds the received event data to an event record at step 540. The event record includes previously received event data (from the subordinate chiplet 350 via the chiplet bus 390) associated with the event. The master chiplet 310 is configured to store the event records in DRAM 336 for further performance processing.

[0028] In one aspect, the steps of method 500 may be applied to additional subordinate chiplets. For example, the steps of method 500 may be applied to the first and second subordinate chiplets 350 each time an event is selected to be tracked. In this case, the event data received from the first subordinate chiplet 350 may be added to a first event record in the master chiplet 310. This first event record includes event data associated with the first event previously received from the first subordinate chiplet via the chiplet bus. Similarly, the event data received from the second subordinate chiplet 350 may be added to a second event record in the master chiplet 310. This second event record includes event data associated with the second event previously received from the second subordinate chiplet via the chiplet bus. The transmitting of respective event data by the multiple subordinate chiplets 350 over the chiplet bus 390 may be performed periodically according to respective time periods that may be dynamically determined based on the available bandwidth on the chiplet bus 390.

[0029] In another aspect, the master chiplet 310 may be configured to record event data associated with a third event into a third event record, the third event being indicative of a performance aspect of the master chiplet. The master chiplet may be further configured to store the third event record in DRAM 336 along with the event record including the event data received from each of the multiple subordinate chiplets 350 over the chiplet bus 390.

[0030] It should be understood that many variations are possible based on the disclosure herein. Although features and elements are described above in specific combinations, each feature or element may be used alone without other features and elements, or in various combinations with or without other features and elements. It should be understood that the use of the "subordinate" and "master" modifiers for chiplets herein is merely a naming scheme meant to indicate that, in the context of this disclosure, a first chiplet (qualified as master) has access to memory, while a second chiplet (qualified as subordinate) does not have access to memory. However, such a naming scheme is not intended to otherwise limit or characterize the relationship between the first and second chiplets.

[0031] The provided methods may be performed in a general purpose computer, processor, or processor core. Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), multiple microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine. Such a processor may be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data including a netlist (such as instructions that may be stored on a computer readable storage medium). The result of such processing may be a mask work, which is then used in a semiconductor manufacturing process to manufacture a processor implementing aspects of the embodiments.

[0032] The methods or flow diagrams provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard drives and disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A method for inter-chiplet performance data streaming, comprising: a subordinate chiplet accumulating event data associated with events indicative of a performance aspect of the subordinate chiplet; the subordinate chiplet transmitting the event data to a master chiplet via a chiplet bus; the master chiplet receiving the event data from the subordinate chiplet; the master chiplet adding received event data to an event record, the event record including event data associated with the event previously received from the subordinate chiplet via the chiplet bus. method.

2. the master chiplet storing the event record in a memory; 2. The method of claim 1.

3. The storing step includes: an accumulator of the slave chiplet counting occurrences of the event, the event data including a number of the counts.

2. The method of claim 1.

4. the transmitting step is performed if the number of the counts is above a saturation threshold. The method of claim 3.

5. the transmitting step is performed periodically according to a period that is dynamically determined based on available bandwidth on the chiplet bus.

2. The method of claim 1.

6. The transmitting step includes: obtaining the event data from an accumulator of the subordinate chiplet; resetting the accumulator; packing the event data and an identification number associated with the event into an event data packet.

2. The method of claim 1.

7. The receiving step includes: receiving the event data packet; a decoder of the master chiplet extracting from a received event data packet the event data and the identification number associated with the event; selecting the event record in a recorder of the master chiplet based on the identification number; The method of claim 6.

8. a second subordinate chiplet accumulating event data associated with a second event indicative of a performance aspect of the second subordinate chiplet; the second subordinate chiplet transmitting the event data to the master chiplet via the chiplet bus; the master chiplet receiving the event data from the second subordinate chiplet; the master chiplet adding the received event data to a second event record, the second event record including event data associated with the second event previously received from the second subordinate chiplet over the chiplet bus.

2. The method of claim 1.

9. the transmission of the respective event data by the subordinate chiplet and the transmission of the respective event data by the second subordinate chiplet over the chiplet bus are performed periodically according to respective periods that are dynamically determined based on available bandwidth on the chiplet bus. The method of claim 8.

10. the master chiplet recording event data associated with a third event indicative of a performance aspect of the master chiplet in a third event record.

2. The method of claim 1.

11. the master chiplet storing the event record and the third event record in a memory. The method of claim 10.

12. 1. A system for inter-chiplet performance data streaming, comprising: At least one processor; A memory for storing instructions, The instructions, when executed by the at least one processor, provide the system with: a subordinate chiplet accumulating event data associated with events indicative of a performance aspect of the subordinate chiplet; the subordinate chiplet transmitting the event data to a master chiplet via a chiplet bus; the master chiplet receiving the event data from the subordinate chiplet; the master chiplet adding received event data to an event record, the event record including event data associated with the event previously received from the subordinate chiplet via the chiplet bus; causing the system to system.

13. The storing step includes: an accumulator of the slave chiplet counting occurrences of the event, the event data including a number of the counts. The system of claim 12.

14. the transmitting step is performed if the number of the counts is above a saturation threshold. The system of claim 13.

15. the transmitting step is performed periodically according to a period that is dynamically determined based on available bandwidth on the chiplet bus. The system of claim 12.

16. The instruction: a second subordinate chiplet accumulating event data associated with a second event indicative of a performance aspect of the second subordinate chiplet; the second subordinate chiplet transmitting the event data to the master chiplet via the chiplet bus; the master chiplet receiving the event data from the second subordinate chiplet; the master chiplet adding received event data to a second event record, the second event record including event data associated with the second event previously received from the second subordinate chiplet over the chiplet bus; causing the system to The system of claim 12.

17. the transmission of the respective event data by the subordinate chiplet and the transmission of the respective event data by the second subordinate chiplet over the chiplet bus are performed periodically according to respective periods that are dynamically determined based on available bandwidth on the chiplet bus.

17. The system of claim 16.

18. The instruction: causing the master chiplet to record event data associated with a third event indicative of a performance aspect of the master chiplet in a third event record; The system of claim 12.

19. The instruction: causing the system to store the event record and the third event record in a memory by the master chiplet; 20. The system of claim 18.

20. 1. A computer-readable storage medium comprising instructions executable by at least one processor to perform a method for inter-chiplet performance data streaming, the method comprising: The method comprises: a subordinate chiplet accumulating event data associated with events indicative of a performance aspect of the subordinate chiplet; the subordinate chiplet transmitting the event data to a master chiplet via a chiplet bus; the master chiplet receiving the event data from the subordinate chiplet; the master chiplet adding received event data to an event record, the event record including event data associated with the event previously received from the subordinate chiplet via the chiplet bus. A computer-readable storage medium.

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