Nanosheet pull-up transistors in SRAM

Abstract

An embodiment of the invention provides a static random access memory (SRAM) device comprising a first set of nanosheets used in n-type transistors and a second set of nanosheets including one or more nanosheets used in p-type transistors, the second set of nanosheets having a width greater than the width of the first set of nanosheets. In one embodiment, the p-type transistors are used as pull-up transistors and the n-type transistors are used as pull-down or pass-gate transistors. A method of manufacturing the SRAM device is also provided.

Description

[Technical field]

[0001] This application relates to the fabrication of semiconductor integrated circuits. More particularly, this application relates to nanosheet pull-up transistors for use in SRAM memory devices and methods of fabricating nanosheet pull-up transistors. [Background technology]

[0002] Static random-access-memory (SRAM) has been widely used in semiconductor devices and circuit equipment. When designing and manufacturing SRAM memory, factors important to the performance of SRAM memory include, for example, write-read-margin (WRM) and bias temperature instability (BTI) or normalized BTI (NBTI). Generally, in order to increase the write-read margin, in the overall design of the SRAM configuration, and / or the pull-up (PU) transistor is made to have a relatively small or weak current compared to the pull-down (PD) transistor and the pass-gate (PG) transistor. For example, in an SRAM memory using fin field effect transistors (finFETs), making the current small and weak for the PU transistor leads to using a smaller number of fins for the PU transistor. Similarly, when applying nanosheet transistor technology in designing SRAM memory, making small and weak current for PU transistor means using nanosheet with narrow sheet width for PU transistor. Although the write-read margin (WRM) can be improved by using nanosheet with narrow sheet width for PU transistor, there is still a concern about how to improve the bias temperature instability of SRAM memory based on nanosheet technology due to the trade-off between sheet width and NBTI. Summary of the Invention

[0003] According to an aspect of the invention, there is provided a transistor circuitry, such as an SRAM memory device, comprising a first set of nanosheets used in n-type transistors and a second set of nanosheets including one or more nanosheets used in p-type transistors, the width of the second set of nanosheets being greater than the width of the first set of nanosheets.

[0004] Preferably, the present invention provides a transistor circuit device, wherein the one or more nanosheets are a first subset of a second set of nanosheets, the second set of nanosheets further comprising a second subset. The p-type transistor has a source / drain region formed at two ends of the first subset of the second set of nanosheets, and the two ends of the second subset of the second set of nanosheets are insulated from the source / drain region of the p-type transistor. In one embodiment, the first subset of the second set of nanosheets is disposed on top of the second subset of the second set of nanosheets.

[0005] Preferably, the present invention provides a transistor circuit device, wherein the first set of nanosheets and the second set of nanosheets have the same number of nanosheets, and the p-type transistor is a pull-up transistor and the n-type transistor is either a pull-down transistor or a pass-gate transistor.

[0006] Preferably, the present invention provides a transistor circuit device, wherein the one or more nanosheets have the same number of nanosheets as the number of the first set of nanosheets. According to another embodiment, the first set of nanosheets and the second set of nanosheets are stacked vertically together.

[0007] According to another aspect of the present invention, there is provided a method of manufacturing the above-mentioned transistor circuit device, such as an SRAM memory device, the method comprising forming a first set of nanosheets and a second set of nanosheets, wherein a width of the second set of nanosheets is wider than a width of the first set of nanosheets, forming source / drain regions of a p-type transistor at two ends of one or more nanosheets of the second set of nanosheets, and forming source / drain regions of an n-type transistor at two ends of the first set of nanosheets.

[0008] According to another aspect of the present invention, a semiconductor structure is provided, the semiconductor structure comprising a first set of nanosheets for use in an n-type transistor and a second set of nanosheets having a first subset and a second subset of the second set of nanosheets, the first subset of the second set of nanosheets for use in a p-type transistor, and a width of the second set of nanosheets being wider than a width of the first set of nanosheets.

[0009] The present invention will be more fully understood and appreciated from the following detailed description of the embodiments thereof, taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] 1A, 1B, 1C, and 1D are illustrations of various cross-sectional views of a semiconductor structure during the process of fabricating an SRAM memory according to an embodiment of a method of the present invention. [Diagram 2] 1(A), (B), (C), and (D) are illustrations of various cross-sectional views of a semiconductor structure following the steps shown in FIG. 1(A), FIG. 1(B), FIG. 1(C), and FIG. 1(D) during the process of fabricating an SRAM memory according to an embodiment of the method of the present invention. [Diagram 3]2(A), (B), (C), and (D) are illustrations of various cross-sectional views of a semiconductor structure following the steps shown in FIG. 2(A), FIG. 2(B), FIG. 2(C), and FIG. 2(D) during the process of fabricating an SRAM memory according to an embodiment of the method of the present invention. [Figure 4] 3A, 3B, 3C, and 3D are illustrations of various cross-sectional views of a semiconductor structure following the steps shown in FIG. 3(A), FIG. 3(B), FIG. 3(C), and FIG. 3(D) during the process of fabricating an SRAM memory according to an embodiment of the method of the present invention. [Diagram 5] 4(A), (B), (C), and (D) are illustrations of various cross-sectional views of a semiconductor structure following the steps shown in FIG. 4(A), FIG. 4(B), FIG. 4(C), and FIG. 4(D) during the process of fabricating an SRAM memory according to an embodiment of the method of the present invention. [Figure 6] 5(A), (B), (C), and (D) are illustrations of various cross-sectional views of a semiconductor structure following the steps shown in FIG. 5(A), FIG. 5(B), FIG. 5(C), and FIG. 5(D) during the process of fabricating an SRAM memory according to an embodiment of the method of the present invention. [Figure 7] 6(A), (B), (C), and (D) are illustrations of various cross-sectional views of a semiconductor structure following the steps shown in FIG. 6(A), FIG. 6(B), FIG. 6(C), and FIG. 6(D) during the process of fabricating an SRAM memory according to an embodiment of the method of the present invention. [Figure 8] 7(A), (B), (C), and (D) are illustrations of various cross-sectional views of a semiconductor structure following the steps shown in FIG. 7(A), FIG. 7(B), FIG. 7(C), and FIG. 7(D) during the process of fabricating an SRAM memory according to an embodiment of the method of the present invention. [Figure 9] 1A, 1B, 1C, and 1D are illustrations of various cross-sectional views of a semiconductor structure during the process of fabricating an SRAM memory according to an additional embodiment of the method of the present invention. [Figure 10]9(A), (B), (C), and (D) are illustrations of various cross-sectional views of a semiconductor structure after steps shown in FIG. 9(A), FIG. 9(B), FIG. 9(C), and FIG. 9(D), as well as other steps similar to those shown in FIG. 2(A)-FIG. 7(D), during a process of fabricating an SRAM memory according to an embodiment of the method of the present invention. [Figure 11] 1 is an illustration of a flow chart of a method for manufacturing a semiconductor structure, in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] It will be understood that for simplicity and clarity, elements shown in the figures have not necessarily been drawn to scale. Additionally, and where applicable, in various functional block diagrams, two connected devices and / or elements may not necessarily be shown as connected. In some other instances, the grouping of certain elements in the functional block diagrams may be for illustrative purposes only and may not necessarily suggest that they are within or embodied within a single physical entity.

[0012] In the detailed description below and in the accompanying drawings, it should be understood that the various layers, structures, and regions shown in the drawings are both demonstrative and schematic views and are not drawn to scale. Additionally, for ease of illustration, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This is not to suggest that any layers, structures, and regions not explicitly shown are omitted from an actual semiconductor structure. Additionally, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it should be emphasized that the descriptions made herein are not intended to be inclusive of all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposely not described herein for economy of explanation.

[0013] Moreover, the same or similar reference numbers are used throughout the drawings to represent the same or similar features, elements, or structures, and therefore, detailed descriptions of the same or similar features, elements, or structures may not be repeated from one drawing to the next. It should be understood that the terms "about" or "substantially" as used herein with respect to thickness, width, percentage, range, etc., are intended to represent close or approximate but not exact. For example, the terms "about" or "substantially" as used herein suggest that there may be a small margin of error, such as 1% or less of a stated amount. In the same manner, the terms "on," "over," or "on top of" as used herein to describe the positional relationship between two layers or structures are intended to be taken in a broad sense and should not be interpreted as excluding the presence of one or more intervening layers or structures.

[0014] To provide spatial context for the various structural orientations of the semiconductor structures shown throughout the figures, XYZ Cartesian coordinates may be shown for each figure. As used herein, the term "vertical" or "vertical direction" or "vertical height" refers to the Z direction of the Cartesian coordinates shown in the figures, and as used herein, the term "horizontal" or "horizontal direction" or "lateral direction" refers to the X and / or Y directions of the Cartesian coordinates shown in the figures.

[0015] 1(A), 1(B), 1(C) and 1(D) are illustrations of various cross-sectional views of a semiconductor structure 11 during the process of fabricating a transistor circuit device such as an SRAM memory according to an embodiment of the present invention. More specifically, referring to the simplified top view of the layout of the semiconductor structure 11 shown at the top right, 1(A) and 1(C) respectively show cross-sectional views of the semiconductor structure 11 along dashed lines AA and CC perpendicularly across the gate, 1(B) shows cross-sectional view of the semiconductor structure 11 along dashed line BB perpendicularly across the nanosheet, and 1(D) shows cross-sectional view of the semiconductor structure 11 along dashed line DD perpendicularly across the source / drain region. The dashed line DD is parallel to the dashed line BB. In the following figures from 2(A)-2(D) to 10(A)-10(D), cross-sectional views of the semiconductor structure at various stages of fabrication are also provided in a similar manner to 1(A)-1(D). The explicit meaning of these figures is similar to that above and will not be repeated.

[0016] For example, FIG. 1(A) shows a cross-sectional view of the semiconductor structure 11 perpendicularly across the gate of an n-type transistor, and FIG. 1(C) shows a cross-sectional view of the semiconductor structure 11 perpendicularly across the gate of a p-type transistor. According to one embodiment of the present invention, and as described below, the n-type transistor is used as a pass-gate (PG) transistor and a pull-down (PD) transistor in a static random access memory (SRAM), and the p-type transistor is used as a pull-up (PU) transistor of the SRAM. FIG. 1(B) shows a cross-sectional view of the semiconductor structure 11 perpendicularly across the gate width of the n-type and p-type transistors.

[0017] More specifically, the n-type transistor 230 includes a first set of nanosheets having a first width W1, and the p-type transistor 240 includes a second set of nanosheets having a second width W2. The first width W1 is the channel width of the n-type transistor 230, and the second width W2 is the channel width of the p-type transistor 240. According to one embodiment of the present invention, the channel width of the p-type transistor 240, i.e., the second width W2, is wider than the channel width of the n-type transistor 230, i.e., the first width W1. According to one embodiment of the present invention, the p-type transistor made from the second set of nanosheets having the wider channel width W2 can have improved bias temperature instability (BTI).

[0018] To balance between BTI and write-read margin (WRM), according to one embodiment of the present invention, the use of a wider channel width W2 for the p-type transistors may be partially compensated for by using a smaller number of nanosheets for the p-type transistors, such that the current of the p-type transistors may be weakened or reduced. Using a smaller number of nanosheets may be achieved, in one embodiment, by removing or etching some nanosheets from the second set of nanosheets of the second width W2 through additional patterning and etching processes. Alternatively, some of the nanosheets in the second set of nanosheets may be blocked by a dielectric material, which may prevent source / drains from being formed at the ends of the second set of nanosheets, resulting in a smaller or fewer number of nanosheets having the second width W2 being used in forming the p-type transistors, as described in more detail below. Additionally, the second set of nanosheets (for the p-type transistors) may be very lightly doped, not doped at all, or possibly doped with an anti-dopant, to reduce or weaken the current of the p-type transistors. Doping the second set of nanosheets may be performed at one or more stages in the fabrication of the SRAM device.

[0019] More specifically, one embodiment of the present invention includes providing a semiconductor substrate 100 and forming a first set of nanosheets 210 and a second set of nanosheets 220 on an upper surface of the semiconductor substrate 100. The semiconductor substrate 100 may be, for example, a bulk silicon (Si) substrate, a bulk germanium (Ge) substrate, a SiGe substrate, or a silicon-on-insulator (SOI) substrate. Nevertheless, the embodiment of the present invention is not limited to this aspect, and other types of substrates may be used as well. Hereinafter, for ease of explanation without loss of generality, the semiconductor substrate 100 may be described as a silicon (Si) substrate. The semiconductor substrate 100 may have one or more shallow trench isolations (STIs) 101 formed in the semiconductor substrate 100.

[0020] The first set of nanosheets 210 and the second set of nanosheets 220 may be formed in the same plane, parallel or side-by-side with each other, and separated by the STI 101 in the semiconductor substrate 100, as will be demonstratively shown below. Nevertheless, the embodiment of the present invention is not limited to this aspect. For example, the first set of nanosheets 210 and the second set of nanosheets 220 may be formed in a stacked manner. In other words, the first set of nanosheets 210 may be formed on the top or bottom surface of the second set of nanosheets 220, and vertically separated by a dielectric layer. Moreover, the first set of nanosheets 210 and the second set of nanosheets 220 may be formed in any other positional relationship. The following description mainly focuses on the first and second sets of nanosheets 210 and 220 formed in the same plane parallel to each other, as shown in most of the drawings. Nevertheless, one skilled in the art will understand that similar descriptions may apply to first and second sets of nanosheets 210 and 220 formed, for example, in a stacked manner or in any other positional relationship. In all embodiments, the first set of nanosheets 210 has a first width W1 and the second set of nanosheets 220 has a width W2, where W2 is wider than W1.

[0021] The first set of nanosheets 210 can include, for example, nanosheets 211, 212, and 213, although a greater or lesser number of nanosheets is possible and fully contemplated herein. The second set of nanosheets 220 can include, for example, nanosheets 221, 222, and 223, although a greater or lesser number of nanosheets is possible and fully contemplated herein. In one embodiment, the first set of nanosheets 210 can have the same number of nanosheets as the number of the second set of nanosheets 220. The first set of nanosheets 210 can be formed on an upper surface of a dielectric layer 201, such as silicon nitride (SiN), on the semiconductor substrate 100, and the second set of nanosheets 220 can be similarly formed on an upper surface of a dielectric layer 202, such as SiN, on the semiconductor substrate 100. The first set of nanosheets 210 and the second set of nanosheets 220 can be covered by a dummy gate 301, such as a polysilicon dummy gate. In one embodiment, the dummy gate 301 can fill the gap between the first set of nanosheets 210 and the second set of nanosheets 220, directly above the STI 101.

[0022] 2(A), 2(B), 2(C), and 2(D) are illustrations of various cross-sectional views of a semiconductor structure 12 after the steps shown in FIG. 1(A), 1(B), 1(C), and 1(D) during a process of fabricating a transistor circuit device, such as an SRAM memory, according to an embodiment of a method of the present invention. More specifically, an embodiment of the present invention uses a first set of nanosheets 210 to form source / drain regions of an n-type transistor 230 and uses a second set of nanosheets 220 to form source / drain regions of a p-type transistor 240. The source / drain regions of the n-type transistor 230 may be formed first, or alternatively, the source / drain regions of the p-type transistor 240 may be formed first. In the following description, for purposes of explanation, the source / drain regions of the p-type transistor 240 are described as being formed first, prior to the formation of the source / drain regions of the n-type transistor 230. Nevertheless, one skilled in the art will appreciate that a similar process may be used to first form the source / drain regions of n-type transistor 230 prior to the formation of the source / drain regions of p-type transistor 240.

[0023] In particular, embodiments of the present invention involve forming a hard mask 302 that covers two ends of the first set of nanosheets 210. In other words, embodiments of the present invention involve forming a hard mask 302 to protect areas of the first set of nanosheets 210 where the source / drain regions of the n-type transistor 230 may be formed, before proceeding to form the source / drain regions of the p-type transistor 240, as described in more detail below.

[0024] 3(A), 3(B), 3(C), and 3(D) are illustrations of various cross-sectional views of the semiconductor structure 13 after the steps shown in FIG. 2(A), 2(B), 2(C), and 2(D) during the process of fabricating a transistor circuit device, such as an SRAM memory, according to an embodiment of the method of the present invention. More specifically, after covering the first set of nanosheets 210, an embodiment of the present invention provides for forming a dielectric layer 410 to cover two ends of one or more nanosheets of the second set of nanosheets 220. For example, the two ends of nanosheets 222 and 223 of the second set of nanosheets 220 may be covered by the dielectric layer 410, leaving only the two ends of nanosheet 221 exposed. In doing so, embodiments of the invention may include forming a dielectric layer, such as silicon oxide (SiO2), and for example, through a deposition process, to cover two end sidewall surfaces of all of the nanosheets of the second set of nanosheets 220, and then recessing the dielectric layer to expose one or more nanosheets of the second set of nanosheets 220. By exposing only one or more nanosheets rather than all of the nanosheets of the second set of nanosheets 220, embodiments of the invention may enable the formation of a p-type transistor 240 with a reduced number of nanosheets compared to forming an n-type transistor 230 with all of the nanosheets in the first set of nanosheets 210, as described in more detail below.

[0025] According to an embodiment of the present invention, using a smaller number of nanosheets in forming the p-type transistor 240 helps at least in part to weaken the current of the p-type transistor 240. By weakening the current of the p-type transistor 240, the write-read margin of the SRAM memory using the p-type transistor as a pull-up transistor can be improved. Meanwhile, the wider channel width of the p-type transistor 240 helps to improve the bias temperature instability (BTI) of the p-type transistor 240 by using the second set of nanosheets 220 having a wider width W2.

[0026] The use of a smaller number of nanosheets partially compensates for the use of wider nanosheets in the p-type transistor 240 by selectively omitting some nanosheets that are otherwise available for forming the p-type transistor, as explained above. Furthermore, a reduction in the number of sheets used for the p-type transistors can also be achieved by initially forming a smaller number of nanosheets for the p-type transistors compared to the nanosheets for the n-type transistors. For example, instead of forming the first set of nanosheets 210 to have the same number of nanosheets as the number of the second set of nanosheets 220, the second set of nanosheets 220 may be formed to have a smaller number of nanosheets. Other ways to achieve having different numbers of nanosheets for the p-type and n-type transistors can include, for example, removing or etching some of the nanosheets for the p-type transistors at different stages of the SRAM fabrication process with additional patterning.

[0027] In reducing the current of p-type transistor 240, embodiments of the present invention are not limited to the above aspects. For example, embodiments of the present invention provide a method for reducing or decreasing the p-type transistor current by using a dopant density in the channel region of the p-type transistor that is significantly smaller than the dopant density typically used in p-type logic transistors. For example, 10 15 From 10 18 atoms / cm 3Dopant densities or concentrations up to 1000 nm may be used. In some other embodiments, the channel region of the p-type transistor may be undoped to include no dopant at all. In yet another embodiment, instead of a p-type dopant, an n-type dopant normally used for an n-type transistor may be used here as an anti-dopant for the p-type transistor, so that the current of the p-type transistor may be further weakened. As known in the art, boron (B), gallium (Ga), and indium (In) are well-known p-type dopants, and arsenic (As) and phosphorus (P) are well-known n-type dopants. Nevertheless, the dopants are not limited to the above, and other types of dopants may be used as well. Additional embodiments of the present invention may include reducing the source / drain contact size, for example, by performing contact size adjustments to the p-type transistor. Reducing the contact size to the source / drain region of the p-type transistor substantially increases the contact resistance to the source / drain region, which affects the current passing through the source / drain region of the p-type transistor.

[0028] 4(A), 4(B), 4(C), and 4(D) are illustrations of various cross-sectional views of the semiconductor structure 14 after the steps shown in FIG. 3(A), 3(B), 3(C), and 3(D) during the process of fabricating a transistor circuit device, such as an SRAM memory, according to an embodiment of the method of the present invention. More specifically, an embodiment of the present invention provides for forming a source / drain region 420 of a p-type transistor 240 through epitaxial growth on the exposed nanosheets 221 of the second set of nanosheets 220, and in particular on the sidewall surfaces of the two ends of the nanosheets 221. The second set of nanosheets 220 can include a first subset of nanosheets, e.g., including nanosheet 221, and a second subset of nanosheets, e.g., including nanosheets 222 and 223. Together with a dummy gate 301 covering the gate region, a hard mask 302 covering the first set of nanosheets 210, and a dielectric layer 410 covering the second subset of the second set of nanosheets 220, source / drain regions 420 may be formed through epitaxial growth on the sidewall surfaces of the two ends of the first subset of the second set of nanosheets 220.

[0029] It should be noted that the first subset of the second set of nanosheets 220 is shown and described as a non-limiting example as including nanosheet 221, and the second subset of the second set of nanosheets 220 is shown and described as a non-limiting example as including nanosheet 222 and nanosheet 223. The first subset of the second set of nanosheets 220 is shown and described as a non-limiting example as being disposed on the second subset of the second set of nanosheets 220. The first subset of the second set of nanosheets 220 forms a p-type transistor 240 without the second subset of the second set of nanosheets 220. In other words, the second subset of the second set of nanosheets 220 is not used in the p-type transistor 240 and is insulated from the source / drain region 420 of the p-type transistor 240. Those of skill in the art will understand that embodiments of the present invention can include a variety of variations on the above, such as the number of nanosheets in the first and second subsets, their positional relationship to one another, and the like, all of which are fully contemplated herein.

[0030] 5(A), 5(B), 5(C), and 5(D) are illustrations of various cross-sectional views of a semiconductor structure 15 after the steps shown in 4(A), 4(B), 4(C), and 4(D) during a process of fabricating a transistor circuit device such as an SRAM memory according to an embodiment of a method of the present invention. More specifically, after forming the source / drain region 420 of the p-type transistor 240, an embodiment of the present invention forms a hard mask 430 to cover the source / drain region 420 and removes the hard mask 302 to expose the sidewall surfaces of the two ends of the first set of nanosheets 210. Thereafter, the source / drain region 520 of the n-type transistor 230 using the first set of nanosheets 210 may be formed. The formation may be through epitaxial growth on the sidewall surfaces of the two ends of the first set of nanosheets 210, including all of the nanosheets 211, 212, and 213. In other words, n-type transistor 230 uses a greater number of nanosheets than p-type transistor 240.

[0031] 6(A), 6(B), 6(C), and 6(D) are illustrations of various cross-sectional views of semiconductor structure 16 after the steps shown in Fig. 5(A), 5(B), 5(C), and 5(D) during the process of fabricating a transistor circuit device, such as an SRAM memory, according to an embodiment of a method of the present invention. Following the formation of source / drain regions 420 of p-type transistor 240 and source / drain regions 520 of n-type transistor 230, an embodiment of the present invention removes hard mask 430 and forms an inter-level-dielectric (ILD) layer 610 overlying source / drain regions 420 and 520 of both p-type transistor 240 and n-type transistor 230 in preparation for the subsequent formation of gate metal for the transistors.

[0032] 7(A), 7(B), 7(C), and 7(D) are illustrations of various cross-sectional views of the semiconductor structure 17 after the steps shown in FIG. 6(A), 6(B), 6(C), and 6(D) during the process of fabricating a transistor circuit device such as an SRAM memory according to an embodiment of the method of the present invention. More specifically, the gate metal 710 for the n-type transistor 230 may be formed through a replacement-metal-gate (RMG) process to surround each individual nanosheet 211, 212, and 213 in the first set of nanosheets 210. For example, the dummy gate 301 may first be selectively removed through a selective etching process. Then, the semiconductor material surrounding the nanosheets 211, 212, and 213 may be similarly removed through a selective etching process. Gate metal 710, including one or more layers of a work function metal for an n-type transistor, may be deposited on the exposed surfaces of nanosheets 211, 212, and 213. Similarly, gate metal 720 may be formed through another RMG process to surround each individual nanosheet 221, 222, and 223 in the second set of nanosheets 220. Note that here, the source / drain region of p-type transistor 240 is only formed at the two ends of nanosheet 221, but gate metal 720 may be similarly formed to surround nanosheets 222 and 223. Nevertheless, nanosheets 222 and 223 are inactive, and the two ends of nanosheets 222 and 223 are insulated from the source / drain region 420 of p-type transistor 240.

[0033] 8(A), 8(B), 8(C), and 8(D) are illustrations of various cross-sectional views of a semiconductor structure after the steps shown in FIG. 7(A), 7(B), 7(C), and 7(D) during a process of fabricating a transistor circuit device, such as an SRAM memory, according to an embodiment of a method of the present invention. More specifically, contacts may be formed to contact the source / drain regions of p-type transistor 240 and n-type transistor 230. For example, contact 810 may be formed to contact source / drain region 520 of n-type transistor 230, and contact 820 may be formed to contact source / drain region 420 of p-type transistor 240. More specifically, contact openings in ILD layer 610 may first be created, for example, through lithographic patterning and etching processes. The contact openings may then be filled with a conductive material, such as, for example, tungsten (W), cobalt (Co), and copper (Cu), to name a few.

[0034] 9(A), 9(B), 9(C), and 9(D) are illustrations of various cross-sectional views of a semiconductor structure 19 during the process of fabricating a transistor circuit device, such as an SRAM memory, according to an additional embodiment of the method of the present invention. More specifically, unlike the first set of nanosheets 210 and the second set of nanosheets 220 shown in FIGS. 1(A)-1(D), in this embodiment, the first set of nanosheets 210 and the second set of nanosheets 220 are directly separated by a dielectric layer 203 therebetween. According to an embodiment of the present invention, fabrication process steps similar to those described above may likewise be applied to form a p-type transistor 240 having a channel width W2 wider and a smaller number of channels than the channel width W1 and number of channels of an n-type transistor 239. Here, the number of channels refers to the corresponding number of nanosheets used in the transistor. The resulting structure is described in more detail below with reference to FIGS. 10(A)-10(D).

[0035] 10(A), 10B, 10C, and 10(D) are illustrations of various cross-sectional views of a semiconductor structure 20 after steps similar to those shown in FIGS. 9(A), 9(B), 9(C), and 9(D) and other steps similar to those shown in FIGS. 2(A)-7(D) during a process of fabricating a transistor circuit device such as an SRAM memory according to an embodiment of the method of the present invention. More specifically, the p-type transistor 240 and the n-type transistor 230 as shown in FIGS. 10(A)-10(D) have a structure and / or configuration similar to those shown in FIGS. 8(A)-8(D). For example, the p-type transistor 240 has a width W2 that is wider than the width of the n-type transistor 230, which helps improve the bias temperature instability (BTI) of the p-type transistor 240. On the other hand, p-type transistor 240 uses a smaller number of nanosheets than n-type transistor 230, which reduces the current of p-type transistor 240, thereby at least partially compensating for the increase in current due to the increase in channel width W2 of p-type transistor 240. The reduction in current helps improve the write-read margin (WRM) of the SRAM device.

[0036] 11 is a flow chart illustration of a method of fabricating a semiconductor structure according to an embodiment of the invention. More specifically, in forming a semiconductor structure, which may be an SRAM memory device, or more generally, a transistor circuit device, an embodiment of the invention involves forming a first set of nanosheets and a second set of (1110) nanosheets, where the width of the second set of nanosheets is greater than the width of the first set of nanosheets. The first set of nanosheets may be used in forming n-type transistors, and at least a first subset of the second set of nanosheets may be used in forming p-type transistors. The embodiment further includes (1120) covering two ends of the first set of nanosheets with a first hard mask in preparation for forming source / drain regions of a p-type transistor, (1130) forming a dielectric layer, such as an interlayer dielectric (ILD) layer, over a second subset of the second set of nanosheets such that only the first subset of the second set of nanosheets is used in forming a p-type transistor, and (1140) forming epitaxial source / drain regions of a p-type transistor at the two ends of the exposed first subset of the second set of nanosheets. After forming the source / drain regions of the p-type transistor, the embodiment further includes (1150) covering the source / drain regions of the p-type transistor with a second hard mask and removing the first hard mask to expose the first set of nanosheets for an n-type transistor, and (1160) forming epitaxial source / drain regions of an n-type transistor at the two ends of the first set of nanosheets. Next, the embodiment (1170) forms a gate metal surrounding the first and second sets of nanosheets in one or more replacement metal gate (RMG) processes, and then (1180) forms contacts to contact the source / drain regions of the p-type and n-type transistors.

[0037] It should be understood that the exemplary methods discussed herein may be readily incorporated with other semiconductor process flows, semiconductor devices, and integrated circuits with various analog and digital or mixed signal circuit devices. In particular, integrated circuit dies with various devices such as field effect transistors, bipolar transistors, metal oxide semiconductor transistors, diodes, capacitors, inductors, and the like may be fabricated. Integrated circuits according to the present invention may be employed in applications, hardware, or electronic systems, or combinations thereof. Hardware and systems suitable for implementing the present invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., mobile phones), solid state media storage devices, functional circuit devices, and the like. Systems and hardware incorporating such integrated circuits are considered to be part of the embodiments described herein. Given the teachings of the present invention provided herein, one skilled in the art will be able to envision other implementations and applications of the techniques of the present invention.

[0038] Although illustrative embodiments have been described herein with reference to the accompanying figures, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications can be made by those skilled in the art without departing from the scope of the appended claims.

[0039] It should be understood that the various layers, structures, or regions described above, or combinations thereof, are not necessarily drawn to scale. Moreover, for ease of illustration, one or more layers, structures, and regions of the type commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure or drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structure.

[0040] Further, it should be understood that the embodiments discussed herein are not limited to the specific processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it should be emphasized that the descriptions provided herein are not intended to be inclusive of all of the processing steps that may be used to form a functional semiconductor integrated circuit device. Rather, certain processing steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, have purposely not been described herein for economy of description.

[0041] Terms such as "about" or "substantially" as used herein with respect to thicknesses, widths, percentages, ranges, etc. are intended to indicate close or approximate but not exact. For example, the terms "about" or "substantially" as used herein suggest that there may be a small margin of error, such as, by way of example only, 1% or less of a stated amount. Also, in the figures, the depicted scale of one layer, structure, or region relative to another layer, structure, or region, or combination thereof, is not necessarily intended to represent actual scale.

[0042] Semiconductor devices and methods for forming semiconductor devices according to the techniques described above may be employed in a variety of applications, hardware, or electronic systems, or combinations thereof, including, but not limited to, personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., cell phones and smart phones), solid state media storage devices, functional circuit equipment, etc. Given the teachings provided herein, those skilled in the art will be able to envision other implementations and applications of embodiments of the present invention.

[0043] In some embodiments, the techniques described above are used in conjunction with the manufacture of semiconductor integrated circuit devices, illustratively including, by way of non-limiting example, CMOS devices, MOSFET devices, or FinFET devices, or combinations thereof, and / or other types of semiconductor integrated circuit devices incorporating or otherwise utilizing CMOS, MOSFET, or FinFET technologies, or combinations thereof.

[0044] Thus, at least a portion of one or more of the semiconductor structures described herein may be implemented in an integrated circuit. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form as bare die (i.e., as a single wafer having multiple unpackaged chips) or in packaged form. In the latter case, the chips may be mounted in a single chip package (such as a plastic carrier with conductors attached to a motherboard or other higher level carrier) or in a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects or both). In either case, the chips may thus be integrated with other chips, discrete circuit elements, or other signal processing devices, or combinations thereof, either as part of an intermediate product, such as a motherboard, or as part of a final product. The final product may be any product that includes the integrated circuit chip, ranging from toys and other low-cost applications to advanced computer products with displays, keyboards or other input devices, and central processors.

[0045] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used in this specification has been selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0046] While certain features of the invention have been illustrated and described herein, many modifications, substitutions, variations, and equivalents will now occur to those skilled in the art. All such modifications, variations, or alternative embodiments, or combinations thereof, are hereby considered to be within the scope of the present invention.

Claims

1. A transistor circuit device, comprising: a first set of nanosheets used in n-type transistors; a second set of nanosheets, including one or more nanosheets used in a p-type transistor; Equipped with The width of the second set of nanosheets is greater than the width of the first set of nanosheets; Transistor circuit equipment.

2. 2. The transistor circuit device of claim 1, wherein the one or more nanosheets are a first subset of the second set of nanosheets, the second set of nanosheets further comprising a second subset, the p-type transistor having source / drain regions formed at two ends of the first subset of the second set of nanosheets, and the two ends of the second subset of the second set of nanosheets are insulated from the source / drain regions of the p-type transistor.

3. The transistor circuit device of claim 2 , wherein the first subset of the second set of nanosheets is disposed on top of the second subset of the second set of nanosheets.

4. 2. The transistor circuit device of claim 1, wherein the first set of nanosheets and the second set of nanosheets have the same number of nanosheets, the p-type transistor is a pull-up transistor, and the n-type transistor is a pull-down transistor or a pass-gate transistor.

5. The transistor circuit device of claim 1 , wherein the one or more nanosheets of the second set of nanosheets have the same number of nanosheets as the number of nanosheets in the first set of nanosheets.

6. 2. The transistor circuit device of claim 1, wherein the width of the first set of nanosheets is a channel width of the n-type transistor and the width of the second set of nanosheets is a channel width of the p-type transistor.

7. 1. A method of making a transistor circuit device, comprising the steps of: forming a first set of nanosheets and a second set of nanosheets, the second set of nanosheets having a width greater than a width of the first set of nanosheets; forming source / drain regions of a p-type transistor at two ends of one or more nanosheets of the second set of nanosheets; forming source / drain regions of an n-type transistor at two ends of the first set of nanosheets; A method comprising:

8. 8. The method of claim 7, further comprising covering the two ends of the first set of nanosheets with a first hard mask before forming the source / drain regions of the p-type transistor.

9. 9. The method of claim 8, wherein the one or more nanosheets are a first subset of the second set of nanosheets, the second set of nanosheets further comprising a second subset, and forming the source / drain regions of the p-type transistor comprises forming a dielectric layer covering the second subset of the second set of nanosheets and forming the source / drain regions of the p-type transistor at the two ends of the first subset of the second set of nanosheets.

10. 10. The method of claim 9, wherein forming the dielectric layer overlying the second subset of the second set of nanosheets comprises depositing the dielectric layer overlying all of the second set of nanosheets and then recessing the dielectric layer to expose the first subset of the second set of nanosheets.

11. 11. The method of claim 10, further comprising covering the source / drain regions of the p-type transistor with a second hard mask before forming the source / drain regions of the n-type transistor.

12. 8. The method of claim 7, further comprising forming a first gate metal surrounding the first set of nanosheets for the n-type transistor, and forming a second gate metal surrounding the one or more nanosheets of at least the second set of nanosheets for the p-type transistor.

13. 13. The method of claim 12, wherein the one or more nanosheets of the second set of nanosheets is a first subset of the second set of nanosheets, the second set of nanosheets further comprising a second subset, and the second gate metal further surrounds the second subset of the second set of nanosheets.

14. The one or more nanosheets of the second set of nanosheets are １５ atoms / cm ３ 8. The method of claim 7, wherein the semiconductor substrate is doped with a p-type dopant at a density of less than 1000 nm, is undoped, or is doped with an n-type dopant.

15. 1. A semiconductor structure comprising: a first set of nanosheets used in n-type transistors; a second set of nanosheets, the second set of nanosheets having a first subset and a second subset of the second set of nanosheets; Equipped with the first subset of the second set of nanosheets is used in a p-type transistor, and the width of the second set of nanosheets is greater than the width of the first set of nanosheets; Semiconductor structure.

16. 16. The semiconductor structure of claim 15, wherein the p-type transistor has source / drain regions formed at two ends of the first subset of the second set of nanosheets.

17. 17. The semiconductor structure of claim 16, wherein two ends of the second subset of the second set of nanosheets are covered by a dielectric layer and insulated from the source / drain regions of the p-type transistor.

18. 16. The semiconductor structure of claim 15, wherein the first set of nanosheets and the second set of nanosheets have the same number of nanosheets, and the first subset of the second set of nanosheets is disposed on top of the second subset of the second set of nanosheets.

19. 16. The semiconductor structure of claim 15, wherein the first set of nanosheets and the second set of nanosheets are arranged in the same plane parallel to each other and separated by a dielectric layer.

20. 16. The semiconductor structure of claim 15, wherein the p-type transistor is a pull-up transistor and the n-type transistor is a pull-down transistor or a pass-gate transistor, the width of the first set of nanosheets is a channel width of the pull-down transistor or the pass-gate transistor, and the width of the second set of nanosheets is a channel width of the pull-up transistor.

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