Pulse Width Modulator for Stacked Half-Bridges

Abstract

An IC is coupled to a power stage having a first half bridge with first and second transistors and a second half bridge with third and fourth transistors. A controller (110) has a first control output for providing first to fourth control signals to the first to fourth transistors. The controller asserts the first to fourth control signals to implement a state sequence. The state sequence includes a first state in which the first and fourth transistors are on, a second state in which the first and third transistors are on, a third state in which the second and fourth transistors are on, and a fourth state in which the second and third transistors are on. During each switching cycle, the controller implements the first and fourth states, and one of the second or third states is implemented between the first and fourth states, alternating between implementing the second or third state every n switching cycles.

Description

[Technical field]

[0001] Many types of systems operate at relatively high voltages. An electric vehicle (EV) includes a battery pack that may provide a voltage of, for example, 400V, 800V, etc. Such systems include a voltage converter that converts the relatively high input voltage to a much lower voltage for use by electronics in the system (e.g., infotainment system, microcontroller, etc.). Summary of the Invention

[0002] In one example, an integrated circuit (IC) is adapted to be coupled to a stacked half-bridge power stage, the stacked half-bridge power stage having a first half-bridge including a first transistor coupled to a second transistor, and a second half-bridge including a third transistor coupled to a fourth transistor. The IC includes a memory and a controller. The controller has a first control output adapted to provide a first control signal to the first transistor, a second control output adapted to provide a second control signal to the second transistor, a third control output adapted to provide a third control signal to the third transistor, and a fourth control output adapted to provide a fourth control signal to the fourth transistor. The controller asserts the first through fourth control signals to implement a state sequence for the stacked half-bridge power stage. The state sequence includes a first state in which the first and fourth transistors are on and the second and third transistors are off, a second state in which the first and third transistors are on and the second and fourth transistors are off, a third state in which the second and fourth transistors are on and the first and third transistors are off, and a fourth state in which the second and third transistors are on and the first and fourth transistors are off. During each switching cycle, the controller implements the first and fourth states, with one of the second or third states being implemented between instances of the first and fourth states, alternating between whether the second or third state is implemented between instances of the first and fourth state every n switching cycles, where n is an integer. [Brief description of the drawings]

[0003] [Figure 1] FIG. 2 is a schematic diagram of a voltage converter according to one embodiment.

[0004] [Diagram 2] 4 is a schematic diagram of a voltage converter illustrating different states of a transistor according to one embodiment. [Diagram 3]4 is a schematic diagram of a voltage converter illustrating different states of a transistor according to one embodiment. [Figure 4] 4 is a schematic diagram of a voltage converter illustrating different states of a transistor according to one embodiment. [Diagram 5] 4 is a schematic diagram of a voltage converter illustrating different states of a transistor according to one embodiment. [Figure 6] 4 is a schematic diagram of a voltage converter illustrating different states of a transistor according to one embodiment. [Figure 7] 4 is a schematic diagram of a voltage converter illustrating different states of a transistor according to one embodiment. [Figure 8] 4 is a schematic diagram of a voltage converter illustrating different states of a transistor according to one embodiment. [Figure 9] 4 is a schematic diagram of a voltage converter illustrating different states of a transistor according to one embodiment.

[0005] [Figure 10] 1 is a state diagram illustrating a set of possible candidate states for operating transistors of a voltage converter.

[0006] [Figure 11] FIG. 11 is a state diagram illustrating another set of possible states for operating the transistors of the voltage converter.

[0007] [Figure 12] 1 is a diagram illustrating an intermediate current waveform of a stacked half bridge according to an example.

[0008] [Figure 13] 11 is a state diagram illustrating yet another set of possible states for operating the transistors of the voltage converter.

[0009] [Figure 14] 4 shows transistor intermediate current and drain current waveforms for different operating conditions of the voltage converter;

[0010] [Figure 15] 14 is an example waveform of an intermediate current of a stacked half bridge according to the state diagram of FIG. 13. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the drawings, the same or different reference numbers are used to denote identical or similar features (in function and / or structure).

[0012] FIG. 1 is a schematic diagram of a voltage converter 100 according to one embodiment. The voltage converter 100 is an electronic device including transistors Q1, Q2, Q3, and Q4 arranged in a stacked half-bridge configuration. A first half-bridge 111 includes transistor Q1 coupled to transistor Q2, and a second half-bridge 112 includes transistor Q3 coupled to transistor Q4. The transistors Q1-Q4 are connected in series between a voltage input (VIN) 101 and ground 102. In this example, the transistors Q1-Q4 are n-channel field effect transistors (NFETs), but in other examples they may be implemented as other types of transistors (e.g., gallium nitride transistors). The drain of transistor Q1 is coupled to the voltage input 101, and the source of transistor Q4 is coupled to ground 102. The source of transistor Q1 is coupled to the drain of transistor Q2 at node 113a, where the voltage is labeled VA. The source of transistor Q2 is coupled to the drain of transistor Q3. The source of transistor Q3 is coupled to the drain of transistor Q4 at node 113c, whose voltage is labeled VC.

[0013] Capacitors C1 and C2 are coupled in series between VIN and ground. The connection between capacitors C1 and C2 is an intermediate node, the voltage of which is labeled VMID. The intermediate node is coupled to the source of transistor Q2 and the drain of transistor Q3. Current IMID is the current through the intermediate node and has a positive polarity in the direction of the arrow.

[0014] Voltage converter 100 also includes capacitors C3 and COUT, a transformer 130, resistors R1 and R2, a pulse width modulation (PWM) controller 110, and gate drivers 121, 122, 123, and 124. Transformer 130 includes a primary coil 131 and a secondary coil 132. Capacitor C3 is coupled between node 113a and primary winding 131. A current through primary winding 131 is identified as current IL, which is positive when flowing in the direction shown by the arrow and negative in the opposite direction. A voltage on the right plate of capacitor C3 is labeled VB and is coupled to primary winding 131 through inductor L1. Secondary winding 132 is coupled to capacitor COUT through inductors L2 and L3, and to transistors Q5 and Q6, which are operated by PWM 110 to rectify the voltage across the secondary winding. The topology of the secondary side of the voltage converter is a current doubler, but can also be implemented as other types of topologies (eg, a center-tapped secondary of the transformer 130).

[0015] The upper plate of capacitor COUT is the voltage output (VOUT) of converter 100. Resistors R1 and R2 are coupled in series between VOUT and ground, thereby forming a voltage divider. The voltage at the connection between resistors R1 and R2 is the feedback voltage (VFB), which is proportional to VOUT. The feedback voltage VFB is provided to the input of PWM controller 110. The voltage VFB may be provided to PWM 110 through an isolation barrier (transformer, optocoupler, etc.).

[0016] 1, PWM controller 110 includes a microcontroller 112 coupled to non-transitory memory 114. Software 115 may be stored in memory 114 and executed by microcontroller 112 to implement some or all of the functionality described herein attributable to PWM controller 110. In other embodiments, PWM controller 110 may be implemented as a finite state machine (e.g., a combination of logic gates, flip-flops, registers, etc.).

[0017] The PWM controller 110 includes outputs 116, 117, 118, and 119. The PWM controller 110 asserts a control signal on each respective output 116-119, one controller signal corresponding to each of the four transistors Q1-Q4. The control signals are CONT Gl, CONT G2, CONT G3 and CONT The input of driver 121 is coupled to PWM controller output 116 and hence the control signal CONT Gl. The output of the gate driver is a gate signal G1 that is coupled to the gate of transistor Q1. The control signal CONT In response to Gl being in a logic state indicating that transistor Q1 should be turned on (e.g., logic high), gate driver 121 responds by asserting an appropriate current and / or voltage on the gate of transistor Q1 to turn it on. In the opposite logic state (e.g., logic low), driver 121 responds by asserting an appropriate current and / or voltage on the gate of transistor Q1 to turn it off. Similarly, gate drivers 121, 123, and 124 drive their respective gate signals G2, G3, and G4 through their input control signals CONT G2, CONT G3 and CONT G4 at the gates of transistors Q2, Q3, and Q4.

[0018] In general, for each half-bridge 111 and 112, either one of the two transistors is on at any given time, or neither transistor is on. Therefore, the PWM controller 110 asserts the control signals CONT_G1 and CONT_G2 such that either only one of the transistors Q1 and Q2 is on at any given time, or both transistors Q1 and Q2 are off. Similarly, the PWM controller 110 asserts the control signals CONT_G3 and CONT_G4 such that either only one of the transistors Q3 and Q4 is on at any given time, or both transistors Q3 and Q4 are off.

[0019] The PWM controller 110 sequences the on / off states of the transistors in a manner that ensures that one or more of the following conditions are true: First, the sequencing implemented by the PWM controller 110 ensures that the average of the current IMID is approximately 0 amps. Because the average of IMID is approximately 0 amps, VMID remains at approximately the level of VIN / 2. If VMID deviates substantially from VIN / 2, one or more of the transistors Q1-Q4 may experience a drain-source voltage (Vds) large enough that it may damage that transistor. The sequencing implemented by the PWM controller 110 also ensures that the root mean square (rms) current for each of the transistors Q1-Q4 is approximately equal. Having the rms currents of the transistors all approximately the same ensures that the thermal load is approximately evenly distributed among the four transistors. Thermal balancing can increase the efficiency of the thermal solution and reduce the size of the thermal solution.

[0020] 2-9 illustrate eight different operating states of the converter, in which the PWM controller 110 operates the converter 100. Each operating state shown in FIG. 2-9 identifies which transistors of the two half-bridges 111 and 112 are on and which are off. In some operating states, a particular transistor is off (its channel is not conducting) but its body diode is on. The components (transistors or body diodes) that are on are circled in each figure. The operating states include operating states 1 (FIG. 2), 2 (FIG. 4), 3 (FIG. 8), and 4 (FIG. 6), as well as operating states 1-2 and 1-3 (FIG. 3), 2-4 and 3-4 (FIG. 5), 4-2 and 4-3 (FIG. 7), and 2-1 and 3-1 (FIG. 9). References to operating states mn refer to transition states between states m and n, where m is an integer between 1 and 4, and n is an integer between 1 and 4. For example, operating state 1-2 is an operating state of the converter that transitions the on / off control of the transistors between operating state 1 and operating state 2. Figures 2 and 6 illustrate one operating state in each figure, and Figures 3-5 and 7-9 illustrate two operating states in each figure. Each of Figures 2-9 also includes an example waveform of the current IL through the primary winding 131 that identifies that portion of the waveform produced by the corresponding operating state.

[0021] In this specification, reference is made to the body diode of a field effect transistor. In other embodiments, gallium nitride transistors may be used instead of field effect transistors. Gallium nitride transistors do not have a body diode, but they exhibit a body diode-like behavior, referred to as "3RD quadrant conduction."

[0022] The following description illustrates the progression from operating state 1 (through operating states 1-2) to operating state 2 (through operating states 2-4) to operating state 4. In the example of FIG. 2, in operating state 1, transistors Q1 and Q4 are on and transistors Q2 and Q3 are off. When transistor Q1 is on, voltage VA is approximately equal to VIN. As a result of the switching pattern described herein, the voltage across capacitor C3 is approximately half the input voltage VIN, and therefore voltage VB is approximately equal to VIN / 2. Also, when transistor Q4 is on, voltage VC is approximately equal to ground (0V). Thus, the voltage across primary winding 131 is VIN / 2 (the terminal of the winding with a dot is VIN / 2 higher than the opposite terminal of the winding). Current flows in the direction of the arrows, for example, from VIN, through transistor Q1, capacitor C3, through winding 131, through transistor Q4 to ground. Current IL increases as identified by reference numeral 210 in the waveforms. When the rate of increase of the current is very steep, the voltage across the transformer is 0V. This means that all the switched voltage appears across the resonant inductor (less the blocking capacitor voltage). After the transformer receives a voltage (either positive or negative depending on the particular half cycle of operation), the applied voltage to the resonant inductor is reduced by that same voltage. The current IMID is approximately equal to 0 amperes in this operating condition.

[0023] FIG. 3 shows an example of an operating state 1-2, in which transistor Q1 is still on (from operating state 200) and transistor Q4 is turned off (and transistors Q2 and Q3 remain off from operating state 1). During this operating state, as described above, both transistors Q3 and Q4 are off to implement the dead time between turning off transistor Q4 and turning on transistor Q3. When transistor Q1 is still on, voltage VA remains approximately equal to VIN, and voltage VB is approximately equal to VIN / 2. Also, when transistor Q4 is off, current flows in the direction of the arrows, for example, from VIN through transistor Q1, capacitor C3, through winding 131, and through the body diode of transistor Q3 and capacitor C3. Current IMID is non-zero in this configuration and is a negative current (with reference to the polarity defined above). When the body diode is on, voltage VC is VMID plus the voltage drop (Vd) across the body diode. Voltage Vd (e.g., 0.7 V) is substantially less than VMID. VMID is approximately equal to the target VIN / 2 (according to the control scheme described herein), which may be 400V for a VIN of 800V. FIG. 3 shows that the voltage VC is approximately VMID (the difference is the small voltage drop across the body diode). In this operating condition, the voltage drop across the primary winding is approximately 0V. The current through the inductor with 0V drop across it remains relatively constant, which means that the current IL remains relatively flat, as identified by reference numeral 310 in FIG. 3 (reference numeral 310 identifies the portion of the switching cycle during which the converter will be configured according to operating time 1-2).

[0024] FIG. 4 shows an example of operating state 2, where transistor Q1 is still on (from operating state 1-2) and transistor Q3 is turned on (and transistors Q2 and Q4 remain off from operating state 1-2). Because of the Vd voltage drop across the body diode of transistor Q3 (which is relatively small), relatively little switching loss occurs when turning on transistor Q3 (referred to as zero voltage switching, ZVS). Operating state 400 is similar to operating state 1-2, except that transistor Q3 is turned on and current flows through the channel of that transistor instead of through its body diode. Current IMID remains negative. The current through winding 131 is also approximately constant, as indicated by reference numeral 410, as a result of the approximately 0V drop across the winding, as described above.

[0025] 5 shows an example of operating states 2-4 in which transistor Q1 is turned off and transistor Q3 remains on (from operating state 2). The body diode of transistor Q2 is on and conducts current. Because transistor Q3 and the body diode of transistor Q2 are on, voltages VA and VC are approximately VMID. Due to the VIN / 2 voltage drop across capacitor C3, voltage VB is approximately 0V and therefore the voltage drop across primary winding 131 is approximately -VMID. The negative voltage drop across the primary winding reduces the current through the primary winding, as identified by reference numeral 510.

[0026] FIG. 6 shows an example of operating state 4 in which transistors Q2 and Q3 are on and transistors Q1 and Q4 are off. In operating states 2-4, the PWM controller 110 can turn on transistor Q2 with ZVS because the body diode of the transistor was on. When transistors Q2 and Q3 are on, voltages VA and VC are approximately equal to VMID. Voltage VB is approximately equal to 0V as a result of the VIN / 2 voltage drop across capacitor C3. The voltage drop across primary winding 131 is negative, which causes a continuous and rapid decrease in current through the winding, as shown at 610. Current IL becomes negative as shown. The two different slopes of the current at this point arise for approximately the same reasons as described above with respect to FIG. 2. The direction of current flow in this operating state is from VMID, through primary winding 131, through capacitor C3 and transistor Q2, and back to VMID. Current IMID is approximately equal to 0A in this operating state.

[0027] 7, 8, and 9 show possible sequences of operating states 4-2, 2, and 2-1 to return to operating state 1. In FIG. 7, the PWM controller 110 turns off transistor Q2 so that transistor Q3 remains on and transistors Q1, Q2, and Q4 are off. In this operating state, voltages VA, VB, and VC are approximately equal to VIN, VIN / 2, and VMID, respectively. Since VMID is equal to VIN / 2, the voltage drop across the primary winding 131 is approximately equal to 0V, and the current through the primary winding remains relatively constant, as shown by reference numeral 710. Since the current IL was negative in the previous operating state 4, the current IL remains negative in operating state 4-2. The direction of current flow is from VIN, through capacitor C1, through transistor Q3, through the primary winding, capacitor C3, and body diode transistor Q1, and back to VIN. The direction of current IL is opposite to that during operating state 1 and is shown as a negative current in the waveforms of Figure 7. Current IMID is positive in this operating state.

[0028] As shown in Figure 8, the PWM controller 110 can then turn on transistor Q1 in ZVS to configure the converter again to operating state 2. The voltages on VA, VB, and VC are approximately the same as those described above for operating state 2 in Figure 2, but the direction of current through the circuit is reversed. As described above, the voltage difference across the primary winding is approximately 0V, and therefore the current IL is negative, as identified by reference numeral 810, but approximately constant. The current IMID remains positive in this state.

[0029] FIG. 9 illustrates operating state 2-1, in which transistor Q3 is turned off by the PWM controller 110, which turns on the body diode of transistor Q4. Voltages VA, VB, and VC are approximately equal to VIN, VIN / 2, and 0V, respectively. Current in operating state 2-1 of FIG. 9 flows through the body diode of transistor Q4, the primary winding 131, capacitor C3, and transistor Q1 through VIN. The current in the primary winding is negative (with respect to the polarity defined above for IL), but increases toward 0 amperes because voltage VB is more positive than voltage VC. Following operating state 2-1 in FIG. 9, the PWM controller 110 can be configured to return the converter to operating state 1, as shown in FIG. 2.

[0030] 2-9 illustrate another possible sequence of operating states. From operating state 1 in FIG. 2, the PWM controller 110 can configure the converter to operating states 1-3, as shown on the right side of FIG. 3. In operating states 1-3, current flows through transistor Q2, capacitor C3, primary winding 131, and the body diode of transistor Q4. The direction of current IMID in states 1-3 is opposite to the direction of current IMID in states 1-2. Voltages VA, VB, and VC are approximately VMID, 0V, and 0V, respectively, and therefore the voltage drop across primary winding 131 is approximately 0V. The current through primary winding 131 remains relatively constant (310) as in operating states 1-2 in FIG. 3.

[0031] From operating states 1-3, the PWM controller 110 may configure the converter to operating state 3 on the right side of FIG. 4. In operating state 3, the PWM controller 110 turns on transistor Q2 and maintains transistor Q4 in an on state. The direction of current flow through the primary winding 131 is the same in operating state 3 as in operating states 1-3 on the right side of FIG. 3, but now the current flows through the channel of transistor Q3 instead of through its body diode. Current IMID continues to flow in the direction shown in FIG. 3. The voltage drop across the primary winding remains at about 0V in this operating state, and therefore the primary winding current is relatively constant, as shown at 410.

[0032] FIG. 5 shows another example of operating states 3-4 in which the PWM controller 110 turns off transistor Q4 and keeps transistor Q2 on. The body diode of transistor Q3 is on and conducts current. Because the body diodes of transistor Q2 and transistor Q3 are on, voltages VA and VC are approximately VMID. Due to the VIN / 2 voltage drop across capacitor C3, voltage VB is approximately 0V, and therefore, as in operating state 4, the voltage drop across primary winding 131 is approximately −VMID. The negative voltage drop across the primary winding reduces the current through the primary winding, as identified by reference numeral 510. Current circulates through the body diode of transistor Q3, capacitor C3, primary winding 131, and transistor Q4 in the same direction as shown for operating states 2-4 in FIG. 5.

[0033] From operating state 3-4, the PWM controller may configure the converter to operating state 4 shown in FIG. 6 and described above. From operating state 3-4, the PWM controller 110 may then configure the converter to operating state 4-3 shown on the right side of FIG. 7. In this state, the PWM controller turns off transistor Q3, which results in the body diode of transistor Q4 and transistor Q2 turning on. In this configuration, the voltage drop across the primary winding 131 is approximately 0V, as in operating state 4-2 shown on the left side of FIG. 7. The current through the primary winding remains relatively constant, as shown at 710. In FIG. 7, the current IMID is negative for operating state 4-3 and therefore in the opposite direction in FIG. 7 as compared to operating state 4-2.

[0034] The PWM controller 110 may then turn on transistor Q4 (as shown for operating state 3 on the right side of FIG. 8) and current will flow in the same direction as for operating state 4-3 on the right side of FIG. 7. The voltage drop across the primary winding 131 is approximately 0V and the current through the primary winding is relatively constant as shown at 810.

[0035] The PWM controller 110 may then configure the converter into operating state 3-1, shown on the right side of Figure 9. In this configuration, transistor Q2 is turned off and transistor Q4 remains on. In this state, the current IMID is approximately 0 amps.

[0036] 2-9 and the above description describe multiple possible operating states of the converter's transistors Q1-Q4, as well as the currents and voltages during progression from one operating state to the next. FIG. 10 illustrates a possible sequencing of the above operating states in a manner that results in a near-zero average IMID current. Intermediate states (e.g., operating states 1-2, 2-4, etc.) are not shown for ease of understanding, but such states may also be included in the progression between operating states shown in FIG. 10. Transistors that are on are circled. In this example, the PWM controller 110 sequences the converter from operating state 1 to operating state 2 (indicated by arrow 1001), to operating state 4 (indicated by arrow 1002), to operating state 2 (indicated by arrow 1003), to operating state 1 (indicated by arrow 1004). In one embodiment, the PWM controller 110 repeatedly sequences the converter between operating states 1, 2, and 4 as shown, without also including operating state 3.

[0037] Looking at the magnitude of the current IMID during operating states 1, 2, and 4, in operating state 1, IMID is 0 amperes as described above for operating state 1 on the left side of FIG. 2. Similarly, IMID is 0 as described above for operating state 4 on the left side of FIG. 6. However, when proceeding from operating state 1 to operating state 2, IMID is negative as described above for operating state 2 on the left side of FIG. 4. When proceeding from operating state 4 back to operating state 2, IMID is positive as described above for operating state 2 shown on the left side of FIG. 8. The direction of the current IMID is reversed each time the converter is configured for operating state 2 in a repeated sequencing of operating states 1, 2, 4, 2, 1, 2, 4, etc. Thus, the average value of the current IMID is approximately 0 amperes, which greatly reduces the deviation of the voltage VMID from VIN / 2.

[0038] 11 illustrates another possible sequencing of the operating states described above, also in a manner that results in a near-zero average IMID current. Transistors that are on are circled. In this example, PWM controller 110 sequences the converter to transition from operating state 1 to operating state 3 (indicated by arrow 1101), to operating state 4 (indicated by arrow 1102), back to operating state 3 (indicated by arrow 1103), and back to operating state 1 (indicated by arrow 1104). In one embodiment, PWM controller 110 repeatedly sequences the converter between operating states 1, 3, and 4 as shown, without also including operating state 2.

[0039] Looking at the magnitude of the current IMID during operating states 1, 3, and 4, in operating state 1, IMID is 0 amps, as described above with respect to operating state 1 on the left side of FIG. 2. Similarly, IMID is 0, as described above with respect to operating state 4 on the left side of FIG. 6. However, when proceeding from operating state 1 to operating state 3, IMID is positive, as described above with respect to operating state 3 on the right side of FIG. 4. When proceeding from operating state 4 back to operating state 3, IMID is negative, as described above with respect to operating state 3 shown on the right side of FIG. 8. The direction of the current IMID is reversed each time the converter is configured for operating state 3 in a repeated sequencing of operating states 1, 3, 4, 3, 1, 3, 4, etc. Thus, the average value of the current IMID is approximately 0 amps, which greatly reduces the deviation of the voltage VMID from VIN / 2.

[0040] Sequencing between operating states 1 and 4 may include an intervening operating state 2 (FIG. 10) or an intervening operating state 3 (FIG. 11). In either case, the average level of current IMID is advantageously about 0 amperes. FIG. 12 shows an example waveform 1200 of current IMID. While in operating states 1 or 4, current IMID is about 0 amperes as shown at 1201. Current IMID is positive (1202) every other cycle and negative (1203) for the other cycles during intermediate operating states 2 or 3. In this example, the average level of current IMID is −390.72 picoamperes (pA), which is about 0 amperes.

[0041] In FIG. 10, transistor Q1 is on for both operating states 1 and 2, while transistor Q2 is on for operating state 3 but not on for operating states 1 or 2. Thus, transistor Q1 is on for a longer time (higher duty cycle) than transistor Q2. Similarly, transistor Q3 is on for a longer time than transistor Q4 in the sequencing of FIG. 10. Thus, transistors Q1 and Q3 are on for a longer time than transistors Q2 and Q4 in the sequencing of FIG. 10. In FIG. 11, transistors Q2 and Q4 are on for a longer time than transistors Q1 and Q3. This imbalance in the on-times of the transistors results in uneven thermal loading of the transistors. Uneven thermal loading can result in higher power losses, lower efficiency, and greater thermal solutions to adequately cool the transistors.

[0042] In accordance with another embodiment, FIG. 13 illustrates another possible sequencing between operating states 1-4 in a manner that reduces thermal imbalance among converter transistors. In the example of FIG. 13, PWM controller 110 sequences between operating states 1 and 4 by alternately transitioning through operating states 2 and 3. In one example, the sequencing includes a repeating pattern that includes operating states 1-2-4-2-1-3-4-3-1, etc. The sequencing of FIG. 13 alternates between the sequencing of FIG. 10 and the sequencing of FIG. 11. As a result, the thermal load is more evenly distributed among converter transistors Q1-Q4 than with either the sequencing of FIG. 11 or FIG. 12 individually.

[0043] Variations on the sequencing of Figure 13 are also possible. For example, PWM controller 110 may transition between operating states 1 and 4 via intervening operating state 2, and then transition between operating states 1 and 4 via intervening operating state 3. In this case, the sequencing would include 1-2-4-2-1-2-4-2-1-1-3-4-3-1-3-4-3-1, etc.

[0044] FIG. 14 includes waveforms including IMID 1401, the drain current of transistor Q1 (1402), the drain current of Q2 (1403), the drain current of transistor Q3 (1404), the drain current of transistor Q4 (1405), and the current through the transformer primary winding 131 (1406). These waveforms are the result of the sequencing illustrated in FIG. 13, which alternates between intermediate states 2 and 3, as described above. Between operating state 1 and operating state 4, the PWM controller 110 implements operating state 2 twice in succession, as indicated by reference numeral 1421, and then implements operating state 3 twice in succession, as indicated by reference numeral 1422. The current IMID is negative for one instance of operating state 2 (or 3) and positive for the other instance of operating state 2 (or 3). Because IMID is negative and positive for approximately the same amount of time, the average level of IMID is advantageously about 0 amperes. The timing diagram shown at 1410 illustrates the on and off states of transistors Q1 and Q2 for the various operating conditions described above.

[0045] Figure 15 shows an example waveform 1500 of the current IMID for the operating state sequencing illustrated in Figure 13. The average of IMID is 3.97 pA (approximately 0 amperes).

[0046] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal that controls device B to perform an action, (a) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not change the functional relationship between device A and device B.

[0047] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be via firmware and / or software programming of the device, via the configuration and / or layout of hardware components, via the device's interconnections, or via a combination thereof.

[0048] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless otherwise noted, these terms are used generally to mean an interconnection between, or the termination of, a device element, a circuit element, an integrated circuit, a device, or other electronic or semiconductor component.

[0049] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacture, e.g., by an end user and / or a third party, to form the described structure.

[0050] Although the use of certain transistors is described herein, other transistors (or equivalent devices) may be substituted with little or no change to the remaining circuit elements. For example, bipolar junction transistors (BJTs, e.g., NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the transistors described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, natural transistors, or other types of device structure transistors. Additionally, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0051] As used herein, a FET is "on" means that the FET has a conducting channel and drain current can flow through the FET. As used herein, a FET is "off" means that there is no conducting channel and therefore no drain current flows through the FET. However, an "off" FET may have current flowing through the body diode of the transistor.

[0052] The circuits described herein are reconfigurable to include additional or different components to provide at least partially similar functionality to that available prior to the component replacement. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise noted. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0053] While certain elements of the described examples are included in an integrated circuit and others are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and / or some features illustrated as being internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are (1) incorporated in / on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated in the same module, and / or (4) incorporated in / on the same printed circuit board.

[0054] Use of the term "ground" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable for the teachings of the present description. Unless otherwise stated herein, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of that parameter.

[0055] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. Integrated circuits (ICs) Memory and A controller coupled to the memory, comprising: a first control output configured to provide a first control signal to a first transistor of a first half-bridge power stage; a second control output configured to provide a second control signal to a second transistor coupled to the first transistor; a third control output configured to provide a third control signal to a third transistor of a second half-bridge power stage; and a fourth control output configured to provide a fourth control signal to a fourth transistor coupled to the third transistor, wherein the controller is configured to assert the first, second, third, and fourth control signals in order to implement a state sequence; Includes, The state sequence includes a first state in which the first and fourth transistors are on and the second and third transistors are off; a second state in which the first and third transistors are on and the second and fourth transistors are off; a third state in which the second and fourth transistors are on and the first and third transistors are off; and a fourth state in which the second and third transistors are on and the first and fourth transistors are off. An integrated circuit wherein, between each switching cycle, the controller is further configured to implement the first and fourth states, with either the second or third state being implemented between instances of the first and fourth states, and every n switching cycles, the implementation of either the second or third state between instances of the first and fourth states alternates, where n is an integer.

2. The integrated circuit according to claim 1, An integrated circuit in which n is 1.

3. The integrated circuit according to claim 1, An integrated circuit where n is 2.

4. The integrated circuit according to claim 1, The aforementioned state sequence is A first-to-second intermediate state in which the first transistor is ON and the second, third, and fourth transistors are OFF, The first to third intermediate state is when the fourth transistor is ON, the first, second and third transistors are OFF, and the body diode of the second transistor is ON, The second-to-fourth intermediate state is when the third transistor is ON, the first, second, and fourth transistors are OFF, and the body diode of the second transistor is ON. A third-to-fourth intermediate state in which the second transistor is ON, the first, third, and fourth transistors are OFF, and the body diode of the third transistor is ON, The fourth-to-second intermediate state is when the third transistor is ON, the first, second, and fourth transistors are OFF, and the body diode of the first transistor is ON. The fourth-to-third intermediate state is when the second transistor is ON, the first, third, and fourth transistors are OFF, and the body diode of the fourth transistor is ON. A second-to-first intermediate state in which the first transistor is ON, the second, third, and fourth transistors are OFF, and the body diode of the fourth transistor is ON, A third-to-first intermediate state in which the fourth transistor is ON, the first, second and third transistors are OFF, and the body diode of the first transistor is ON, An integrated circuit, further including the following.

5. The integrated circuit according to claim 4, In response to the controller implementing the state sequence of the first state, the second state, the fourth state, the second state, and the first state, the controller Following the implementation of the first instance of the first state, the first-second intermediate state is implemented. Following the implementation of the first instance of the second state, the second to fourth intermediate states are implemented. Following the implementation of the fourth state, the fourth-second intermediate state is implemented. The second instance of the second state is implemented, followed by the implementation of the second-first intermediate state. An integrated circuit, further configured in this way.

6. The integrated circuit according to claim 4, In response to the controller implementing a state sequence in the order of the first state, the third state, the fourth state, the third state, and the first state, the controller Following the implementation of the first instance of the first state, the first to third intermediate states are implemented. Following the implementation of the first instance of the third state, the third-fourth intermediate state is implemented. Following the implementation of the fourth state, the fourth-to-third intermediate state is implemented. The third-first intermediate state is implemented following the implementation of the second instance of the third state. An integrated circuit, further configured in this way.

7. The integrated circuit according to claim 1, An integrated circuit further configured so that, during a switching cycle, the controller implements a sequence of states in the order of first state, second state, fourth state, second state, first state, third state, fourth state, third state, and first state.

8. An integrated circuit according to claim 1, An integrated circuit further configured to implement a sequence of states in the order of first state, second state, fourth state, second state, first state, second state, first state, first state, third state, fourth state, third state, first state, third state, fourth state, third state, and first state.

9. It is an electronic device, A first half-bridge comprising a first transistor and a second transistor coupled to the first transistor, wherein each of the first and second transistors has its own control input, A second half-bridge coupled to the first half-bridge, comprising a third transistor and a fourth transistor coupled to the third transistor, wherein each of the third and fourth transistors has its own control input, A controller having first, second, third, and fourth control outputs coupled to the control inputs of the first, second, third, and fourth transistors, respectively, wherein the controller is configured to provide control signals on the first, second, third, and fourth control outputs so that the controller implements state sequences for the transistors of the first and second halfbridges, Includes, The state sequence includes a first state in which the first and fourth transistors are on and the second and third transistors are off; a second state in which the first and third transistors are on and the second and fourth transistors are off; a third state in which the second and fourth transistors are on and the first and third transistors are off; and a fourth state in which the second and third transistors are on and the first and fourth transistors are off. An electronic device wherein, between each switching cycle, the controller is further configured to implement the first and fourth states, with either the second or third state being implemented between instances of the first and fourth states, and alternating every n switching cycles, where n is an integer, in which case either the second or third state is implemented between instances of the first and fourth states.

10. The electronic device according to claim 9, An electronic device in which n is 1.

11. The electronic device according to claim 9, An electronic device where n is 2.

12. An electronic device according to claim 9, The aforementioned state sequence is A first-to-second intermediate state in which the first transistor is ON and the second, third, and fourth transistors are OFF, The first to third intermediate state is when the fourth transistor is ON, the first, second and third transistors are OFF, and the body diode of the second transistor is ON, The second-to-fourth intermediate state is when the third transistor is ON, the first, second, and fourth transistors are OFF, and the body diode of the second transistor is ON. A third-to-fourth intermediate state in which the second transistor is ON, the first, third, and fourth transistors are OFF, and the body diode of the third transistor is ON, The fourth-to-second intermediate state is when the third transistor is ON, the first, second, and fourth transistors are OFF, and the body diode of the first transistor is ON. The fourth-to-third intermediate state is when the second transistor is ON, the first, third, and fourth transistors are OFF, and the body diode of the fourth transistor is ON. A second-to-first intermediate state in which the first transistor is ON, the second, third, and fourth transistors are OFF, and the body diode of the fourth transistor is ON, A third-to-first intermediate state in which the fourth transistor is ON, the first, second and third transistors are OFF, and the body diode of the first transistor is ON, Electronic devices, including further...

13. An electronic device according to claim 12, In response to the controller implementing a state sequence in the order of the first state, the second state, the fourth state, the second state, and the first state, the controller Following the implementation of the first instance of the first state, the first-second intermediate state is implemented. Following the implementation of the first instance of the second state, the second to fourth intermediate states are implemented. Following the implementation of the fourth state, the fourth-second intermediate state is implemented. The second instance of the second state is implemented, followed by the implementation of the second-first intermediate state. An electronic device further configured in this way.

14. An electronic device according to claim 12, In response to the controller implementing a state sequence in the order of the first state, the third state, the fourth state, the third state, and the first state, the controller Following the implementation of the first instance of the first state, the first to third intermediate states are implemented. Following the implementation of the first instance of the third state, the third-fourth intermediate state is implemented. Following the implementation of the fourth state, the fourth-to-third intermediate state is implemented. The third-first intermediate state is implemented following the implementation of the second instance of the third state. An electronic device further configured in this way.

15. An electronic device according to claim 9, An electronic device in which, during a first switching cycle, the controller is further configured to implement a sequence of states in the order of first state, second state, fourth state, second state, first state, third state, fourth state, third state, and first state.

16. An electronic device according to claim 9, An electronic device in which, during a first switching cycle, the controller is further configured to implement a sequence of states in the order of first state, second state, fourth state, second state, first state, second state, first state, first state, third state, fourth state, third state, first state, third state, fourth state, third state, and first state.

17. A system, A first half-bridge comprising a first transistor and a second transistor coupled to the first transistor, wherein each of the first and second transistors has its own control input, A second half-bridge coupled to the first half-bridge, comprising a third transistor and a fourth transistor coupled to the third transistor, wherein each of the third and fourth transistors has its own control input, Each of the aforementioned driver circuits is coupled to each of the control inputs, A transistor coupled to the further first half-bridge, the further second half-bridge, and the output capacitor, A controller coupled to the output capacitor, the controller including a memory and having first, second, third, and fourth control outputs coupled to the respective driver circuits, Includes, The controller is configured to provide control signals on the first, second, third, and fourth control outputs to implement a state sequence for the first and second half-bridge transistors, the state sequence including a first state in which the first and fourth transistors are on and the second and third transistors are off; a second state in which the first and third transistors are on and the second and fourth transistors are off; a third state in which the second and fourth transistors are on and the first and third transistors are off; and a fourth state in which the second and third transistors are on and the first and fourth transistors are off. A system in which, for each switching cycle, the controller is further configured to implement the first and fourth states together with one of the second or third states implemented between instances of the first and fourth states, and every n switching cycles, the system switches to either the second or fourth state implemented between instances of the first and fourth states, where n is an integer.

18. The system according to claim 17, A system in which, during a first switching cycle, the controller is further configured to implement a sequence of states in the order of first state, second state, fourth state, second state, first state, third state, fourth state, third state, and first state.

19. The system according to claim 17, A system in which, during a first switching cycle, the controller is further configured to implement a sequence of states in the order of first state, second state, fourth state, second state, first state, second state, first state, first state, third state, fourth state, third state, first state, third state, fourth state, third state, and first state.

20. The system according to claim 19, The aforementioned state sequence is A first-to-second intermediate state in which the first transistor is ON and the second, third, and fourth transistors are OFF, The first to third intermediate state is when the fourth transistor is ON, the first, second and third transistors are OFF, and the body diode of the second transistor is ON, The second-to-fourth intermediate state is when the third transistor is ON, the first, second, and fourth transistors are OFF, and the body diode of the second transistor is ON. A third-to-fourth intermediate state in which the second transistor is ON, the first, third, and fourth transistors are OFF, and the body diode of the third transistor is ON, The fourth-to-second intermediate state is when the third transistor is ON, the first, second, and fourth transistors are OFF, and the body diode of the first transistor is ON. The fourth-to-third intermediate state is when the second transistor is ON, the first, third, and fourth transistors are OFF, and the body diode of the fourth transistor is ON. A second-to-first intermediate state in which the first transistor is ON, the second, third, and fourth transistors are OFF, and the body diode of the fourth transistor is ON, A third-to-first intermediate state in which the fourth transistor is ON, the first, second and third transistors are OFF, and the body diode of the first transistor is ON, A system that further includes the following.

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