Substrate with vias and related manufacturing method - Patents.com

Abstract

The invention relates to a substrate (3) comprising a first layer (30) based on a semiconductor material and a second layer (31) lying on the first layer. The substrate (3) comprises a plurality of embedded vias (32) extending from the second layer (31) over a portion of the first layer (30), each via (32) being defined by a side wall (320), a bottom wall (321) and a top wall (322) opposite said bottom wall (321), at least one set (32a) of the plurality of vias (32) forming a pattern (32b) repeated along at least one direction of the main extension planes of the first layer (30) and the second layer (31). The substrate (3) thus forms a generic substrate making it possible to facilitate the use of vias for manufacturing microelectronic devices.

Description

[Technical field]

[0001] The present invention relates to the field of substrates intended for the manufacture of electronic devices, and more particularly microelectronic devices. These substrates may ultimately allow the electrical and mechanical connection of component electrical elements. The present invention has advantageous, but not exclusive, applications when manufacturing microelectronic devices. [Background technology]

[0002] There is an interest in producing microelectronic devices using vias that extend perpendicularly to the main extension plane of the substrate. This may be of particular interest for producing MicroElectroMechanical Systems (MEMS). It may also be of particular interest for producing assemblies of components on a substrate with vias for forming through contacts, in order to be able to interconnect these components on the front and rear sides of the substrate to obtain microelectronic devices. The components may then be connected to a printed circuit, such as through a casing. These substrates may in particular be semiconductor substrates, for example of the semiconductor-on-insulator type, in particular of the silicon-on-insulator (SOI) type.

[0003] The etching and filling of these vias (commonly called TSVs, or Through Silicon Vias) with conductive or semiconducting material is a very specific process step that is often fabricated not on the fabrication premises, but on the assembly premises (commonly called OSAT, or Outsourced Semiconductor Assembly and Test).

[0004] The two types of vias are differentiated according to the time of their manufacture in the production line of microelectronic devices. The so-called "TSV-middle" vias are generally manufactured in the middle of the process, after manufacturing the component patterns during the front-end (FEOL) but before depositing the back-end (BEOL) metal layers. This generally requires the transfer of the substrate and components from the fabricator to the assembler to manufacture the vias, then back to the fabricator for the BEOL steps, and finally also to the assembler to finish the process. These manufacturing steps are very limited in terms of planarity and contamination that are very incompatible with movements back and forth between the fabricator and the assembler.

[0005] "TSV last" vias can be fabricated at the end of the process, after FEOL and BEOL steps. This generally requires only one transfer from fabrication to assembly after the BEOL steps. However, it limits the via geometries that can be achieved. In particular, it limits the via density that can be obtained.

[0006] Therefore, there is a need to obtain these structures without relying on other manufacturing steps in the line. Summary of the Invention [Problem to be solved by the invention]

[0007] SUMMARY OF THE PRESENT EMBODIMENT It is therefore an object of the present invention to facilitate the manufacture of vias in microelectronic devices.

[0008] Other objects, features, and advantages of the present invention will become apparent from a review of the following description and accompanying drawings, and it will be understood that other advantages may be incorporated. [Means for solving the problem]

[0009] To this end, according to a first aspect, a substrate, in particular for a microelectronic device, is provided, a first base layer, preferably made of a semiconducting material; - A second layer on top of the first layer A substrate comprising:

[0010] The substrate comprises a plurality of embedded vias extending from the second layer across a portion of the first layer, each via being defined by a sidewall, a bottom wall, and a top wall opposite the bottom wall, and at least one group of the plurality of vias forms a pattern that is repeated along at least one direction of a main extension plane of the first layer and the second layer.

[0011] Thus, the substrate is generic, comprising non-open vias that are previously filled or configured for subsequent filling with conductive or semiconductive conductor material. This allows for the provision of vias independent of other steps in fabricating a microelectronic device. The substrate with the filled vias can be used for layer deposition, e.g., from the FEOL or from the BEOL, whereby the vias can be used to fabricate desired conductive or semiconductive material, such as electrical interconnects. Furthermore, by prefabricating the vias, the shape of the vias is not limited.

[0012] The substrate comprises a via matrix that can be selected in whole or in part to produce the desired conductive or semiconductive components that are best adapted from the desired shape, thus making the generic substrate with these vias easier to manufacture the vias and the conductive or semiconductive components, in particular by being adaptable to different microelectronic devices.

[0013] It will thus be appreciated that fabricating vias is particularly facilitated with respect to other steps of fabricating microelectronic devices by allowing one and the same generic substrate to accommodate different microelectronic devices, and fabricating vias filled with conductive or semiconductive material is even more particularly facilitated.

[0014] A second aspect is a method for manufacturing a substrate, comprising the steps of: - providing a supporting sub-substrate comprising at least one first layer based on a semiconductor material and having an exposed surface; - forming a plurality of vias such that the vias extend from the exposed surface across a portion of the first layer, each via being defined by a sidewall and a bottom wall, at least one set of vias forming a pattern that is repeated along at least one direction of a main extension plane of the first layer and the second layer; - providing a donor sub-substrate comprising a surface layer having an exposed surface; - assembling the support sub-substrate and the donor sub-substrate with their exposed surfaces such that the vias are covered such that each via is defined by a side wall, a bottom wall and a top wall opposite the bottom wall; The present invention relates to a method comprising the steps of:

[0015] This method therefore makes it possible to produce a matrix of buried vias in a substrate, which method has the effects and advantages described with respect to the first aspect.

[0016] A third aspect is a method for manufacturing a microelectronic device, comprising the steps of: - providing a substrate according to the first aspect and / or a substrate manufactured by a method according to the second aspect, the substrate having a front exposed surface and a back exposed surface; - forming at least one layer portion of the device on at least one of the front or rear exposed surfaces of the substrate, e.g. the first exposed surface and the front exposed surface, by deposition of said portion and / or etching at least one of the front or rear exposed surfaces of the substrate, e.g. the first exposed surface and the front exposed surface, configured to form said portion; - etching through one of the front or rear exposed surfaces of the substrate, for example a second exposed surface different from the first exposed surface, and for example the rear exposed surface, in at least one via until the via is reached; continuing the etching until reaching at least one layer portion of the device; or - in at least one via, etching with the other of the front exposed surface or the rear exposed surface of the substrate, e.g., with the first exposed surface and, e.g., with the front exposed surface, until the via is reached; - depositing at least one conductive or semiconductive material, for example further through the front and / or back surface of the substrate, to provide electrical continuity to at least the vias and to portions of the device layer; The present invention relates to a method comprising the steps of:

[0017] The provided substrate thus allows the formation of microelectronic devices, thereby allowing the opening of buried vias to fabricate desired conductive or semiconductive components, which can be fabricated in a facile manner relative to current solutions.

[0018] The objects, aims, as well as features and advantages of the present invention will be best apparent from the following detailed description of embodiments of the invention, as illustrated by the accompanying drawings. [Brief description of the drawings]

[0019] [Figure 1A] 1 is a cross-sectional view of a substrate according to an example embodiment. [Figure 1B] 3 is a cross-sectional view of a substrate according to an example embodiment in the main extension plane of a first layer and a second layer; [Figure 2A] 1A-1C are cross-sectional views of different via configurations. [Figure 2B] 1A-1C are cross-sectional views of different via configurations. [Figure 2C] 1A-1C are cross-sectional views of different via configurations. [Figure 3A] 11 is a cross-sectional view of a substrate according to another example embodiment. FIG. [Figure 3B] 4 is a cross-sectional view in the main extension plane of the first layer and the second layer of a substrate according to another example of an embodiment; [Figure 4A]1A-1D are cross-sectional views of steps of a method for manufacturing a substrate, according to an example embodiment. [Figure 4B] 1A-1D are cross-sectional views of steps of a method for manufacturing a substrate, according to an example embodiment. [Figure 4C] 1A-1D are cross-sectional views of steps of a method for manufacturing a substrate, according to an example embodiment. [Figure 4D] 1A-1D are cross-sectional views of steps of a method for manufacturing a substrate, according to an example embodiment. [Figure 4E] 1A-1D are cross-sectional views of steps of a method for manufacturing a substrate, according to an example embodiment. [Figure 5A] 5A-5C are cross-sectional views of steps of a method for manufacturing a substrate according to another example embodiment. [Figure 5B] 5A-5C are cross-sectional views of steps of a method for manufacturing a substrate according to another example embodiment. [Figure 5C] 5A-5C are cross-sectional views of steps of a method for manufacturing a substrate according to another example embodiment. [Figure 5D] 5A-5C are cross-sectional views of steps of a method for manufacturing a substrate according to another example embodiment. [Figure 6A] 1A-1D are cross-sectional views of steps of a method for manufacturing a microelectronic device, according to an example embodiment. [Figure 6B] 1A-1D are cross-sectional views of steps of a method for manufacturing a microelectronic device, according to an example embodiment. [Figure 6C] 1A-1D are cross-sectional views of steps of a method for manufacturing a microelectronic device, according to an example embodiment. [Figure 6D] 1A-1D are cross-sectional views of steps of a method for manufacturing a microelectronic device, according to an example embodiment. [Figure 7] 10A-10C are cross-sectional views of steps of a method for manufacturing a microelectronic device according to another example embodiment. [Figure 8A] 10A-10C are cross-sectional views of steps of a method for manufacturing a microelectronic device according to another example embodiment. [Figure 8B]10A-10C are cross-sectional views of steps of a method for manufacturing a microelectronic device according to another example embodiment. [Figure 8C] 10A-10C are cross-sectional views of steps of a method for manufacturing a microelectronic device according to another example embodiment. [Figure 8D] 10A-10C are cross-sectional views of steps of a method for manufacturing a microelectronic device according to another example embodiment. [Figure 9A] 1A-1D are cross-sectional views of steps of a method for manufacturing a microelectronic device according to an example in which a via comprises several portions each having a different configuration. [Figure 9B] 1A-1D are cross-sectional views of steps of a method for manufacturing a microelectronic device according to an example in which a via comprises several portions each having a different configuration. [Figure 9C] 1A-1D are cross-sectional views of steps of a method for manufacturing a microelectronic device according to an example in which a via comprises several portions each having a different configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The drawings are provided as examples and not as limitations of the invention. The drawings constitute schematic illustrations of principles intended to facilitate understanding of the invention and are not necessarily to scale for practical application. In particular, the relative dimensions of layers, vias, and walls of sub-substrates and substrates are not representative of reality.

[0021] Before commencing a detailed discussion of embodiments of the present invention, optional features that may optionally be used in conjunction or alternatively are set out below.

[0022] According to an example, for at least some of the vias, eg, for each via, the via is at least partially filled with material.

[0023] According to an example, each via has at least one transverse dimension between 1 μm and 30 μm. According to an example, all transverse dimensions of each via are between 1 μm and 30 μm.

[0024] By way of example, at least some of the vias, and preferably each via, have an aspect ratio of their longer dimension oriented along the thickness dimension of the first and second layers of greater than or equal to 10. This form factor is particularly suited for obtaining large via densities in the substrate, particularly in synergy with the pitch value ranges described below.

[0025] According to an example, within the set of vias, two patterns of continuously repeated vias, for example two vias, are spaced apart at a constant pitch in at least one direction of the main extension plane of the first layer and the second layer:

[0026] According to an example, the pitch is substantially between 50 μm and 300 μm, preferably between 100 μm and 200 μm. This pitch allows a better via density in the substrate. Thus, a greater interconnection density is possible. Furthermore, the compatibility of the substrate with different microelectronic devices is improved.

[0027] According to an example, the substrate comprises several sets of vias each forming a pattern that is repeated along at least one direction of the main extension plane of the first layer and the second layer, so that the generic substrate can comprise different via pattern arrangements to be adapted to different microelectronic devices.

[0028] According to an example, at least one via, preferably at least some of the plurality of vias, preferably each via, has at least one via configuration, in which the sidewalls of the vias are made from a dielectric material and the vias are filled with a conductive or semiconductive material or the vias are hollow; - the sidewalls of the via are made from a dielectric material and the via is filled with a first layer material; - The sidewalls of the via are made from the first layer material and the via is hollow.

[0029] Thus, the vias can be solid or hollow and can optionally already be electrically insulated from the first layer. When the sidewalls of the vias are made from a dielectric material, the vias formed in the substrate have a dielectric layer at least on the sidewalls of the vias before using the substrate in a method for manufacturing a microelectronic device. Walls made from a dielectric material are pre-formed, allowing good isolation of the vias once filled with a conductive or semiconductive material, while being compatible with FEOL steps or with temporary mounting of supports.

[0030] According to an example, at least one via, preferably at least some of the vias, preferably each via of at least one set, has a first via configuration in a first portion and a second via configuration in a second portion, different from the first via configuration, the first and second portions extending continuously along the thickness dimension of the first and second layers. According to an example, some of these vias can be hollow and other parts can be solid. This type of via allows making a smaller via width for the solid part, thus making it possible to make more vias on a given surface. Their accessibility is made easier by the already formed hollow part.

[0031] According to an example, the substrate comprises several sets of vias each forming a pattern repeated along at least one direction of the main extension plane of the first and second layers, at least one set, preferably each set, having at least one via configuration different from the other sets. Thus, the generic substrate can comprise different via structures to be adapted to different microelectronic devices.

[0032] According to an example, the substrate further comprises a system configured to facilitate alignment of the substrate, in particular to create the FEOL and BEOL structures and thus the photolithography steps required for opening the vias, thereby facilitating the manufacturing of the microelectronic device.

[0033] By way of example, the vias are parallel to each other.

[0034] According to an example, the via has a longitudinal dimension oriented along a dimension in thickness of the first and second layers.

[0035] According to an example, the vias extend along a direction parallel to the normal of the main extension planes of the first and second layers.

[0036] According to an example, at least some of the plurality of vias, preferably each via of at least one set, have a square, polygonal or cylindrical cross-section, for example in a plane substantially parallel to the main extension plane of the first layer and the second layer.

[0037] According to an example, the second layer is on the first layer which is in direct contact with the second layer.

[0038] According to an example, at least some of the vias, and preferably each via, have a cross-section, for example in a plane substantially parallel to the main extension plane of the first and second layers, with a ratio of the maximum dimension to the minimum dimension of the cross-section equal to or less than 3, preferably equal to or less than 2. Thus, vias are categorically distinct from other structures such as trenches.

[0039] According to an example, at least some of the vias, and preferably each of the at least one set, have rotational symmetry around an axis substantially parallel to the dimension in the thickness of the first layer and the second layer. Preferably, at least some of the vias, and preferably each of the at least one set, are cylindrical. Thus, the bottom wall of the via is more uniform than a non-cylindrical shape, for example a square, whose corners are shallower than the center after etching of the via. The cylindrical shape minimizes this effect. Furthermore, mechanical stresses are smaller for cylindrical vias that do not have corner singularities. The cylindrical shape is advantageous for heat treatment during the manufacture of the circuit.

[0040] According to an example, at least one via, preferably each via of at least one set, is completely surrounded by a trench extending from the second layer to a portion of the first layer in at least a portion of the longitudinal dimension of said via. The trench allows for improved electrical isolation between the vias. The trench is therefore prefabricated and manufactured independently from other steps of manufacturing the microelectronic device. The trench is therefore compatible with FEOL steps carried out at high temperatures. Furthermore, by having the trench prefabricated, the shape of the trench is not limited by other steps of manufacturing the microelectronic device.

[0041] According to an example, each groove is not filled with a solid material: each groove is filled with an electrically insulating gas atmosphere, such as air.

[0042] According to an example, each groove is defined by a bottom wall, a side wall and a top wall opposite the bottom wall. For at least one groove, and preferably for each groove, at least a part of the side wall and the bottom wall can be made of the same material as the material of the first layer. The insulation of the via is in fact sufficient thanks to the insulating atmosphere contained in the groove. Alternatively, for at least one groove, and preferably for each groove, at least a part of the side wall and the bottom wall can be made of a dielectric material, such as the same dielectric material as the wall of the via. Thus, the electrical insulation of the via is also improved.

[0043] According to an example, the groove is concentric with said via, which in particular makes it possible to reduce the interference potential between the via and the substrate and to increase the breakdown voltage.

[0044] By way of example, the groove extends from the second layer to the first layer over a longitudinal dimension that is smaller than the longitudinal dimension of the via, and preferably the longitudinal dimension of the groove is equal to or smaller than the longitudinal dimension of the via, preferably plus or minus 5 μm. Thus, the groove surrounds the via at least in part, and preferably substantially over its entire longitudinal dimension.

[0045] By way of example, the semiconductor material is selected from the group consisting of silicon Si, germanium Ge, SiGe, III-V materials (e.g., GaN, InN, InGaAs, GaP, InP, InAs, AsGa, etc.), II-VI materials, and wide band gap materials greater than 3 eV.

[0046] By way of example, the semiconductor material comprises silicon, and preferably is silicon.

[0047] By way of example, the piezoelectric material may be lithium tantalate (LiTaO3), lithium niobate (LiNbO3), potassium sodium niobate (K X Na 1-X The material is selected from lead zirconate titanate (PZT), lead magnesium titanate-lead niobate titanate (PMN-PT), zinc oxide (ZnO), aluminum nitride (AlN), or aluminum scandium nitride (AlScN).

[0048] By way of example, the dielectric material is a semiconducting oxide, preferably silica of formula SiO2.

[0049] According to an example method for manufacturing a substrate, forming the plurality of vias includes forming at least some of the plurality of vias in at least one via configuration from the following: - via configurations in which the sidewalls of the via are made from a dielectric material and the via is filled with a conductive or semiconductive material or the via is hollow; - a via configuration in which the sidewalls of the via are made from a dielectric material and the via is filled with a first layer material; - A via configuration in which the sidewalls of the via are made from the first layer material and the via is hollow The device is configured to have at least one of the following:

[0050] According to an example, the via configurations differ in at least one of the following characteristics: the dielectric nature or absence of the via sidewalls, the via shape (specifically, cross-section), the dimensions, the via filling material, and the hollow or solid nature of the via.

[0051] According to an example, forming the plurality of vias includes, for at least one set of vias, etching at least one perimeter of the vias in at least one first portion of said vias.

[0052] According to an example, the etching is configured to etch only the periphery of the via. Equivalently, the etching is configured to etch a groove forming the periphery of the via. Thus, after the formation of the oxide in the groove, the sidewalls of the via are made of the dielectric material and the via is filled with the material of the first layer.

[0053] According to another example, the etching is configured to etch the via throughout substantially all of its volume. Thus, the sidewalls of the via can be made from the material of the first layer and the via can be hollow. Alternatively, after the formation of an oxide around the periphery of the formed cavity, the sidewalls of the via can be made from a dielectric material and the via can be hollow or filled.

[0054] According to an example, forming the multiple vias includes etching at least the periphery of the vias followed by forming a dielectric material at least at the etched periphery of the vias to form sidewalls of the vias made from the dielectric material.

[0055] According to an example, during etching at least the periphery of the via, the via is etched throughout substantially all of its volume, and forming the plurality of vias includes forming a dielectric material at least in the etched periphery of the via, followed by depositing a conductive or semiconductive material to at least partially fill the via, so as to form sidewalls of the via made from the dielectric material, such that the sidewalls of the via are made from the dielectric material and the via is filled with the conductive or semiconductive material.

[0056] It is therefore understood that these different steps may lead to the via configuration previously described.

[0057] According to an example, forming the plurality of vias includes forming several sets of vias each forming a pattern that is repeated along at least one direction of the main extension plane of the first layer and the second layer.

[0058] According to an example, the formation of via sets is configured such that each set has at least one via configuration that is different from the other sets.

[0059] According to an example, the formation of the plurality of vias includes at least one via, preferably at least some of the plurality of vias, having a first via configuration in a first portion and a second via configuration in a second portion that is different from the first via configuration, the first portion and the second portion being configured to extend along a dimension in the thickness of the first layer and the second layer.

[0060] According to an example, forming a dielectric material on at least the bottom and side walls of the plurality of vias includes: - a thermal oxidation so as to oxidize the semiconductor material of the first layer at least on the bottom wall and on the side walls; and / or - Deposition of a dielectric material on at least the bottom and side walls. Includes.

[0061] These techniques, and specifically thermal oxidation, allow to obtain good conformation of the walls of the dielectric material. The conformation of thermal oxidation allows to obtain oxides with a high density and uniform thickness on the bottom and side walls. Therefore, thermal oxidation is particularly advantageous in combination with a high via form factor. As for the deposition, thermal oxidation also allows to smooth the etched via walls, suppressing the presence of defects between the semiconductor material of the first layer and the dielectric.

[0062] By way of example, when the sidewalls are made of a dielectric material, the sidewalls of the vias have a transverse dimension substantially between 50 nm and 600 nm, preferably substantially equal to 400 nm.

[0063] By way of example, when the bottom wall is made of a dielectric material, the wall has a longitudinal dimension substantially between 50 nm and 600 nm, preferably substantially equal to 400 nm.

[0064] According to an example, the surface layer of the donor sub-substrate is a layer with a main component of a material selected from a dielectric material, for example an oxide, a semiconductor material or a piezoelectric material, and is preferably made of such a material.

[0065] According to the example, the supporting sub-substrate further comprises a surface layer with a dielectric material, e.g. an oxide main component, on top of the first layer, preferably made of such a dielectric material, the surface layer having an exposed surface; and / or the surface layer of the donor sub-substrate is a layer with a dielectric material, for example a main component of an oxide, preferably made from such a dielectric material, on top of a layer based on a material chosen from a semiconductor material or a piezoelectric material;

[0066] It is therefore understood that the buried oxide layer of the substrate can come from the donor sub-substrate and / or the support sub-substrate.

[0067] According to an example, the surface layer of the donor substrate has a main component of one of a semiconductor material or a dielectric material, preferably made of one of a semiconductor material or a dielectric material, whereby it is understood that the surface layer is based on a semiconductor material or a dielectric material and the upper walls of the vias and, if necessary, the upper walls of the trenches are based on or made of a semiconductor material or a dielectric material.

[0068] According to an example, the method for manufacturing a substrate further comprises, prior to assembly of the support sub-substrate and the donor sub-substrate, etching a trench completely surrounding at least one via in at least a portion of a longitudinal dimension of said via, the trench extending from the surface layer to the first layer, thereby obtaining the effects and advantages described with respect to the trench.

[0069] According to an example, the method includes forming an embrittled region at a surface depth of a surface layer of a donor substrate, and then separating the donor substrate at the embrittled region.

[0070] According to an example, the method for manufacturing a microelectronic device includes selecting at least one via to be etched from among a plurality of vias, where only some of the plurality of vias are selected as the via to be etched. Thus, it is possible to select the via to be etched from the vias present in the substrate. Thus, the method can be adapted according to the desired microelectronic device configuration for different microelectronic devices. This selection can be performed before etching by one of the front exposed surface or the back exposed surface of the substrate.

[0071] According to an example, selecting at least one via to be etched includes applying a mask with an opening located vertically aligned with at least one via to be etched at said front exposed surface or said back exposed surface of the substrate, and continuing said etching to reach at least one via to be etched. Thus, potential embrittlement of the walls of the etched via is avoided with respect to the stretching and thinning of the surface of the substrate. Thus, this etching etches the layer on the right side of at least one via to be etched until it opens up to at least one via to be etched.

[0072] According to an example, when the method performs etching by the other of the front exposed surface or the back exposed surface of the substrate, selecting at least one via to be etched from among the plurality of vias until reaching the via comprises applying a mask with an opening positioned vertically aligned with the at least one via to be etched at said other exposed surface or the back exposed surface of the substrate, the method further comprises etching to reach the at least one via to be etched. This is particularly advantageous when the via is filled with a conductive or semiconductive material, including the material of the first layer. This allows the via to be reached by the back and front surfaces of the substrate to provide electrical continuity to the via.

[0073] According to an example, the deposition of the conductive or semiconductive material is configured to further cover at least a portion of the front exposed surface and / or the rear exposed surface of the substrate with a conductive or semiconductive layer.

[0074] According to an example, the method includes creating a pattern in a conductive or semiconductive back layer.

[0075] According to an example, the method includes passivating the rear exposed surface of the substrate.

[0076] According to an example, a method for manufacturing a microelectronic device includes: - mounting a support on the front exposed surface of the substrate between forming at least one layer portion of the device and etching through the rear exposed surface of the substrate; depositing a conductive or semiconductive material to fill the electrical cavity and then removing the support. Includes.

[0077] The support therefore allows for easy handling of the substrate.

[0078] By microelectronic devices, this is meant any type of device that is fabricated by microelectronic means. These devices are in particular devices with a purely electronic purpose, micromechanical devices or electromechanical devices, but also optical or optoelectronic devices. Microelectronic devices can be intended to ensure electronic, optical, mechanical functions, etc. Microelectronic devices may also be intermediate products that are only intended for the fabrication of other microelectronic devices. Microelectronic devices may also be passive electrical interconnect structures.

[0079] It is clarified that within the scope of the present invention, the terms "in" or "over" do not necessarily mean "in contact with." Thus, for example, deposition of a layer onto another layer does not necessarily mean that the two layers are in direct contact with each other, but means that one of the layers at least partially covers the other layer, either in direct contact with the other layer or by being separated from the other layer by a membrane, other layer, or other element.

[0080] Furthermore, a layer can consist of several sub-layers of one and the same material or of different materials.

[0081] By an element "based on" material A, or based on A, this means an element that comprises only this material A, or an element that comprises this material A and optionally other materials.

[0082] In the detailed description that follows, terms such as "longitudinal", "transverse" and the like may be used. These terms must be interpreted relative to a dimension in the thickness of a substrate or device. Thus, the longitudinal dimension, height, depth, or thickness of an element or layer refers to the dimension along the thickness of the substrate carrying or containing the element or layer. The width, cross-sectional dimension, or transverse dimension refers to the dimension perpendicular to the thickness of the substrate.

[0083] Certain components of the substrate or device of the present invention may have an electrical function. Some are used for electrical conductivity, and by conductive or equivalent, this means an element formed from at least one material that has sufficient conductivity to perform the desired function in the application. Other components, on the contrary, are used for electrical insulation, and all materials that have sufficient resistance to achieve this insulation are considered, specifically called dielectric or electrically insulating.

[0084] The term "dielectric" more specifically qualifies a material whose electrical conductivity is low enough to serve as an insulator in a given application. In the present invention, a dielectric material preferably has a dielectric constant of less than 4.

[0085] By "direct bonding" this means, for example, bonding with a distance of 10 nm (typically less than 5 Å). -10 "bonding" refers to bonding that consists of contacting relatively smooth surfaces (root mean square (RMS) of m) achieved in an ambient atmosphere at ambient temperature to produce a bond between those surfaces, without the addition of adhesive materials (specifically of the adhesive or polymer type).

[0086] According to an embodiment, direct bonding of two substrates means that the bond is obtained by chemical bonds established between the two contacting surfaces. These chemical bonds can be, for example, van der Waals bonds and / or strong covalent chemical bonds, in particular when the bond is enhanced by plasma activation or followed by an enhanced heat treatment (typically 200-1200° C. for 1 h).

[0087] A direct bond can be obtained without the need for application of significant pressure to the assembled structures. Only slight pressure may be applied to initiate bonding. Thermal annealing may be further performed to strengthen the bond.

[0088] By a parameter "substantially equal to / greater than / less than" a given value, this means that the parameter is substantially equal to / greater than / less than the given value by plus or minus 10%, or even plus or minus 5% of the given value.

[0089] The substrate 3 will now be described according to some example embodiments with reference to Figures 1A to 2C.

[0090] For example, as shown by FIG. 1A, the substrate 3 comprises a first layer 30 with a main component of or made of a semiconductor material. By way of example, the semiconductor material comprises silicon, preferably silicon. It is noted that other semiconductor materials may be considered, as will be described later. The first layer 30 has a thickness L , for example substantially between 100 μm and 800 μm. 30 has.

[0091] The substrate 3 further comprises a second layer 31. As shown by Figs. 1A and 2A, the second layer 31 may have a main component of a dielectric material or may be made of a dielectric material. According to an example, the dielectric material comprises a semiconducting oxide, for example silica of formula SiO2, preferably such a semiconducting oxide. The second layer 31 is preferably in direct contact with the first layer 30 and is on top of the first layer 30. As shown by Fig. 2B, the second layer 31 may alternatively have a main component of a semiconductor material or a piezoelectric material, preferably monocrystalline, or may be made of a semiconductor material or a piezoelectric material. The second layer 31 has a thickness L of, for example, 10 nm or more, preferably 100 nm. 31 The thickness L 31 can be less than or equal to 3000 nm. The second layer 31 of the substrate 3 is preferably free of metallic parts. The second layer 31 is preferably continuous in the main extension plane of the substrate 3.

[0092] According to an example that can be illustrated by Figures 1A and 2A, the second layer 31 is surmounted by a third layer 33 with or made of a semiconductor or piezoelectric material, preferably monocrystalline. According to an example, the semiconductor material comprises silicon, preferably silicon. It is noted in this case that other semiconductor materials may also be considered, as will be described later. The third layer 33 has a thickness L , for example substantially between 100 nm and 20000 nm. 33 The substrate 3 may therefore comprise a structure of the semiconductor-on-insulator type, in particular of the silicon-on-insulator (SOI) type. It should be noted that it is possible to provide that the second layer 31 is not overlain by a third semiconducting layer. The third layer 33 of the substrate 3 preferably does not have any metallic parts. The third layer 33 is preferably continuous in the main extension plane of the substrate 3.

[0093] By way of example, the material on the basis of which the layers 30, 31, 33 are formed is preferably continuous in the extension plane of the layers. At least one, and preferably each layer 30, 31, 33 is preferably continuous over at least 80%, preferably over at least 90%, and even more preferably over the entirety, of the main extension plane of the substrate 3.

[0094] The first layer 30 and / or the second layer 31 are preferably monolithic. The first layer 30 is preferably monolithic at least over the portion through which the vias 32 extend.

[0095] In the following, unless explicitly stated otherwise, it is considered in a non-limiting manner that the substrate 3 is an SOI substrate, the first layer 30 is made from monocrystalline silicon, the second layer is made from SiO2 and the third layer is made from monocrystalline silicon.

[0096] The substrate 3 comprises a via 32 extending in the first layer 30 from the second layer 31. The via 32 preferably has a longitudinal dimension L oriented in the direction of the thickness of the first layer 30 and the second layer 31. 32 . The vias 32 can be parallel to one another. The vias 32 are embedded in the substrate 3, i.e. they are not open on one or the other of the exposed faces 3a, 3b of the substrate 3. The vias 32 therefore define a closed volume.

[0097] Thus, the substrate 3 comprises vias 32 for later use in the method for manufacturing a microelectronic device. This makes it possible to provide the vias independently from other steps of fabricating the microelectronic device 4, as described later with reference to the method for manufacturing a microelectronic device.

[0098] Longitudinal dimension L 32can be chosen so that the via 32 is flush with the surface of the first layer 30 at the interface with the second layer 31, for example as in Figures 1A to 2A and 2C. In a variant, not shown in this case, the via 32 may be placed at a thickness L of the second layer 31. 31 For example, when the donor sub-substrate 2 and the support sub-substrate 1 each have a surface layer based on a dielectric material, these surface layers may together form the second layer 31 after assembly.

[0099] Since the via 32 is not open, it is defined by a side wall 320, a bottom wall 321 and a top wall 322 opposite the bottom wall 321. It should be noted that the front face 3a and the rear face 3b of the substrate 3 can be interchangeably defined relative to the bottom wall 321 and the top wall 322 of the via. Later, including the method for manufacturing a microelectronic device described later, it is considered in a non-limiting manner that the bottom wall 321 is arranged toward the rear face 3b of the substrate 3 and the top wall 322 is arranged toward the front face 3a of the substrate 3. However, the method described later can be adapted to the case where the bottom wall 321 is arranged toward the front face 3a of the substrate 3 and the top wall 322 is arranged toward the rear face 3b of the substrate 3.

[0100] One and / or the other of the exposed surfaces of the substrate 3 may be based on a semiconductor material, preferably monocrystalline. The via 32 may have a layer or a stack of layers above it, with at least one layer preferably based on a semiconductor material, preferably monocrystalline. It is therefore understood that the second layer 31 and / or the second layer 33 may be based on a semiconductor material, preferably monocrystalline, as described above. The generic substrate 3 with vias is therefore compatible with FEOL and BEOL steps.

[0101] For example, the selection of the vias 32' to be etched can be done by the front side, such as after etching of the substrate 3 of the vias 32 on the back side. The selection of the vias 32' to be etched can be done by the back side, such as before or after etching of the substrate 3 of the vias 32 on the front side.

[0102] According to the example that can be illustrated by Figures 1A and 1B, the vias 32 form at least one set 32a comprising a pattern 32b that is repeated at least once along at least one direction, preferably along two directions, of the main extension planes of the first layer 30 and the second layer 31. These directions are preferably orthogonal. It is also possible to provide that these directions are not orthogonal to each other. There is thus at least one pattern 32b of vias 32 and one or more sets 32a of vias 32 that repeat the pattern 32b. Each set comprises a repeated pattern 32b of vias 32. The pattern 32b can differ between several sets 32a.

[0103] The pattern 32b may comprise only one via 32, as shown in Fig. 1B, or several vias 32. The via pattern 32b may be of any shape. By way of example, several vias 32 may form a polygonal pattern taken in a plane parallel to the main extension plane of the first layer 30 and the second layer 31. The pattern 32b of vias 32 may be arranged at regular intervals in the main extension plane of the first layer 30 and the second layer 31.

[0104] Thus, substrate 3 can be a generic substrate including a via matrix, with the etched vias 32' being selected depending on the conductive or semiconductive material being formed, as described in more detail below.

[0105] For this purpose, the patterns 32b of the vias 32 may be successively spaced apart with a first pitch A along a first direction comprised in the main extension plane of the first layer 30 and the second layer 31. The patterns 32b of the vias 32 may be successively spaced apart with a second pitch B along a second direction different from the first direction comprised in the main extension plane of the first layer 30 and the second layer 31. Preferably, these first and second directions are orthogonal. These pitches are taken from center to center between the vias of a pattern 32b and the corresponding vias of the following pattern 32b, as FIG. 1B shows. The pitches A and / or B are preferably constant, i.e. substantially identical for each pattern repetition.

[0106] One and / or the other of these pitches A and / or B can be substantially between 50 μm and 300 μm, preferably between 100 μm and 200 μm. These pitches can be different from each other or equal to each other, depending on the desired matrix shape.

[0107] According to a preferred example, the substrate 3 comprises only one pattern 32b of vias 32, preferably comprising only one via 32. According to this example, each via 32 is separated from adjacent vias 32 by pitches A and B that are substantially identical for each pattern repetition. The pitches A and B are preferably equal to each other.

[0108] According to the example shown by Figures 3A and 3B, the vias 32 form several sets 32a, 32a', 32a", i.e. at least two or more sets. Each set 32a, 32a', 32a" may include a repeated via pattern 32b as previously described. The patterns 32b, 32b', 32b" of the different sets may be different, for example as shown in Figure 3B.

[0109] The pattern 32b may be repeated along the direction of the main extension plane of the first layer 30 and the second layer 31, preferably along the two different directions mentioned above, over at least 80% of the dimension of the substrate 3 along this / these directions. The pattern 32b of the vias 32 is preferably repeated in the main extension plane of the first layer 30 over at least 80%, preferably at least 90%, even more preferably at least 95% of the main extension plane of the first layer 30. The pattern 32b of the vias 32 is further preferably repeated in the main extension plane of the substrate 3 over at least 80%, preferably at least 90%, even more preferably at least 95% of the main extension plane of the substrate 3. The generic substrate 3 thus comprises one or more generic matrices of vias 32 over most of its surface to facilitate the manufacture of microelectronic devices as described in detail later. These vias 32 can be selected depending on the desired architecture, in particular by the generic substrate 3 being adaptable to manufacture different microelectronic devices.

[0110] According to an example, at least some of the vias 32, and preferably each via, extend over a height of 50% or more of the thickness of the substrate 3, preferably 70% or more of the thickness of the substrate 3.

[0111] The vias 32 may further have one of several configurations, or equivalently one of several structures. For example, the vias 32 may be at least partially hollow and / or at least partially filled with a solid material. These configurations will now be described with reference to Figures 2A-C, which show different possible via configurations. The repeating via pattern 32b is not depicted.

[0112] By way of example, the sidewalls 320 of the via 32 may be made from a dielectric material, and the via 32 may be filled with a conductive or semiconductive material 323. This configuration is compatible with FEOL steps.

[0113] The sidewalls 320 of the vias 32 may be made of a dielectric material and the vias 32 may be hollow. Preferably, according to these examples, at least the sidewalls 320 and the bottom wall 321 are made of a dielectric material. The top wall 322 may be made of a dielectric material, a semiconductor material, or a piezoelectric material, as will become more apparent during the description of the method for manufacturing the substrate 3.

[0114] According to another example, the sidewall 320 of the via 32 can be made of a dielectric material and the via 32 is filled with the material of the first layer 30. According to this example, the bottom wall 321 of the via can be located at the perpendicular of the sidewall 320 at the end of the sidewall 320. This bottom wall cannot be physically materialized by a change in material, as shown by the dotted line in FIG. 2A.

[0115] According to another example, the via 32 can be hollow and not defined by sidewalls of dielectric material. The sidewalls 320 of the via 32 can be made from the material of the first layer 30.

[0116] When via 32 is hollow, it is not filled with a solid material. Via 32 is preferably filled with a gas atmosphere, such as air, nitrogen, or argon, optionally at subambient pressure.

[0117] When at least the bottom wall 321 and the side walls 320 are made of a dielectric material, the via 32, when filled with a conductive or semiconductive material, will be electrically isolated from the first layer 30 and from the other vias 32. In a variant, the walls of the via 32, in particular the side walls 320, can be made of a semiconducting material, more specifically from the same material as that of the first layer 30. Electrical isolation of the via 32 can then be achieved during a method for manufacturing a microelectronic device from the substrate 3, which will be described later.

[0118] The vias have a transverse dimension D substantially equal to or less than 30 μm, preferably substantially between 1 μm and 30 μm, preferably substantially between 5 μm and 15 μm, and even more preferably between 8 μm and 12 μm. 32, for example, a diameter. Thus, the transverse dimension D 32 is smaller than the typical dimension of a TSV-last, which makes it possible to have a larger number of vias 32, i.e. a higher density of vias 32, for one and the same surface of the substrate 3 in the main extension plane of the first layer 30 and the second layer 31. 32 is approximately 30 layers thick L 30 and the via 32 is not open. 32 can be substantially equal to or less than 200 μm, preferably between substantially 50 μm and 150 μm, for example substantially equal to 100 μm. These length ranges make it possible to facilitate the formation of interconnections through conductive or semiconductive through members, such as vias 32, of the substrate 3 during the manufacture of the microelectronic device 4.

[0119] The via 32 may further have several portions each having a configuration, and the configuration may vary between the portions. For example, the via may have a first portion 32c having one configuration and a second portion 32d having a different configuration, as shown, for example, in Figures 2A and 2B. 32 can differ between the portions, such as between the first portion 32c and the second portion 32d. In particular, the first portion can be filled and the second portion can be hollow. This allows to obtain smaller sized vias while facilitating access through the hollow portion.

[0120] The via 32 may have a form factor that is substantially greater than or equal to 5, and preferably greater than or equal to 10. By form factor, this means the ratio between the longest dimension to the shorter dimension. In this case, the form factor F is given by F=L 32 / D 32 This form factor allows for easier formation of through interconnects with conductive or semiconductive feedthrough members, such as vias 32, during device fabrication, and for increased density of vias 32 in the substrate.

[0121] 2C, the vias can have, for example, a square, polygonal or cylindrical cross section in a plane substantially parallel to the main extension plane of the first layer 30 and the second layer 31. Preferably, the vias 32 are cylindrical.

[0122] According to the example shown in Figures 2A and 2B, the via 32 can be provided with a groove 35 configured to improve the electrical insulation of the via 32. The substrate 3 is therefore particularly adapted for high frequency applications and / or instead of substrates with high resistance as the application demands. To that end, the via 32 has a cross section taken in the main extension plane of the first layer 30 and the second layer 31, which is completely surrounded by the groove 35. The groove 35 has a longitudinal dimension L 32 The grooves 35 may surround the vias 32 over at least a portion of the first layer 30. The grooves 35 are preferably arranged to insulate the vias 32 from each other, and preferably surround only one via 32. The grooves 35 preferably do not contact each other. The grooves 35 may extend more specifically from the second layer 31 over a portion of the first layer 30. It is noted that the grooves 35 may be arranged around the vias 32 in any of the configurations of vias 32 described above. The grooves provide better dielectric insulation to the via configurations they surround.

[0123] Each groove 35 is preferably recessed, i.e. not open on one or the other of the exposed faces 3a, 3b of the substrate 3. Each groove 35 therefore defines a closed volume. Each groove 35 can be hollow and not filled with a solid material. Each groove 35 is therefore preferably filled with a gaseous atmosphere such as air, nitrogen or argon, optionally at a pressure below ambient pressure. Each groove 35 can be filled, preferably completely, with a solid material such as a dielectric material.

[0124] Each groove 35 may be defined by a side wall 350, a bottom wall 351 and a top wall 352 opposite the bottom wall 351. The bottom wall 351 is arranged towards the rear face 3b of the substrate, and the top wall 352 is arranged towards the front face 3a of the substrate 3. Of these walls, at least the bottom wall 351 and the side wall 350 may be made of a dielectric material, such as SiO2. As FIG. 2A shows, all walls may be made of a dielectric material. It may be provided that the grooves 35 are flush with the surface of the first layer 30, as the vias 32 shown in FIGS. 2A and 2B. The top wall 352 may be of the same material as the second layer 31. All walls may be made of the same material as the layer in which they extend or in contact with, and may be made of a dielectric, semiconducting or piezoelectric material, along with the layer under consideration.

[0125] As shown, for example, in accordance with FIGS. 2A and 2B, each groove 35 has a depth substantially equal to the via depth L 32 The longitudinal dimension L is equal to or less than, and according to the example, plus or minus 5 μm 35 , or equivalently, depth L 35 may have the following structure:

[0126] As shown, for example, by FIGS. 2A and 2B, each groove 35 has a transverse dimension D taken on both sides of the via 32 that is substantially equal to or less than 50 μm, and preferably substantially between 20 μm and 30 μm. 35 , for example. Each groove 35 may have a width that is substantially equal to or less than 5 μm and is substantially between 2 μm and 4 μm. It is thus possible to obtain a high density of vias 32, as well as the dimensions of the vias 32, while obtaining an improvement in electrical insulation. It is particularly advantageous to use these grooves 35 when the vias 32 are close to each other, as is the case for a high density of vias 32 in the substrate 3, in order to synergistically improve the electrical insulation. A high density results, for example, in a pitch A and / or B of 100 μm or less. It can be provided that the grooves 35 have equal or different dimensions between the different grooves 35.

[0127] Along the dimension of the grooves 35 in the main extension plane of the first layer 30 and the second layer 31, the pitch can be adapted such that the grooves 35 are different from each other. Each groove 35 can be cylindrical and preferably concentric with the via 32 that it surrounds.

[0128] When the substrate 3 comprises several sets 32a, each set can have a via configuration or, if necessary, several configuration areas. The via configurations 32 of the different sets 32a can differ from each other. Preferably, each via 32 of one and the same set 32a has the same via configuration or, if necessary, several configuration areas. The dimensions of the vias 32 can furthermore vary between the different sets 32a. Preferably, each via 32 of one and the same set 32a has the same dimensions. The cross-section of the vias 32 can furthermore vary between the different sets 32a. Preferably, each via 32 of one and the same set 32a has the same cross-section.

[0129] For example, as shown in Figures 1A, 1B, 3A and 3B, the substrate 3 can be provided with at least one landmark, or equivalently a marker 34, allowing alignment of the substrate 3 with other elements. Thus, the placement of the vias 32 during the method for manufacturing the microelectronic device is made more reliable. This marker 34 can be formed by one or more dielectric material layer parts of the first layer 30 and / or the second layer 31. The skilled person can naturally think of other variations of the marker, such as, for example, a marking placed on the front surface 3a or the rear surface 3b of the substrate 3.

[0130] A method for manufacturing the substrate 3 will now be described with reference to Figures 4A to 5D.

[0131] The method comprises providing a sub-substrate 1. The sub-substrate 1 comprises at least one first layer 10 intended to form a first layer 30 of a substrate 3 to be obtained, as for example shown in Figures 4A and 5A. According to a non-illustrated example, the sub-substrate 1 may further comprise a surface layer intended to at least partially form a second layer 31 of the substrate 3. The surface layer preferably has a main component of or is made of a dielectric material. The sub-substrate 1 further comprises an exposed surface 1a of the first layer 10 or of the surface layer 11.

[0132] For example, as shown by Figures 4A and 5A, the vias 32 can be formed by etching, preferably by deep reactive ion etching (DRIE). For this, the etching step can include applying a mask 12 with an opening 120 in which the vias 32 are to be etched, as shown for example in Figure 5A. The mask 12 is preferably a resin mask. The mask being hard can for example be provided by applying the resin mask 12 and then etching a surface layer 11 of dielectric material, removing this mask and etching the first layer 10 thanks to the so-called "hard" oxide mask thus formed. It is noted that the surface layer 11 can be removed after etching the vias 32, the latter being electrically isolated by subsequent deposition of a dielectric layer.

[0133] The etch is preferably configured to obtain the characteristics of the vias 32 described above, in particular the dimensions of the vias 32 and the pitch separating the vias 32. For example, the dimensions of the mask 12 and / or the etch time and etch rate are adjusted for this purpose.

[0134] The etching is configured to etch only the periphery of the via 32. For example, as shown in Fig. 4A, a groove 320' can be etched, which groove 320' is intended to form the sidewall 320 of the via 32. In a variant, as shown in Fig. 5A, for example, the via 32 can be etched over substantially its entire volume.

[0135] To form a sidewall 320 of a dielectric material, the method may then include forming a dielectric material to form the sidewall 320. For example, as FIG. 4B shows, the groove 320' may be filled, preferably completely, with a dielectric material. For this purpose, a dielectric material such as silica SiO2 may be deposited. This deposition may be, for example, chemical vapor deposition (CVD) from a gaseous precursor containing oxide and silicon, for example tetraethylorthosilicate (TEOS) or silane of formula SiH4, optionally combined with dioxygen. The deposition may be, for example, subatmospheric pressure CVD (SACVD) or plasma enhanced chemical vapor deposition (PECVD).

[0136] When the via 32 is etched substantially throughout its volume, the formation of a dielectric material can take place on the side walls 320 and on the bottom wall 321, as shown for example in FIG. 5B. This can take place by deposition of a dielectric material as previously described. In a variant, this can take place by thermal oxidation, for example at a temperature of substantially 1050° C. in an oxygen-containing atmosphere.

[0137] Preferably, the formation of the walls 320, 321 is configured such that the walls 320, 321 of the dielectric material have a dimension substantially between 50 nm and 600 nm, preferably substantially equal to 400 nm. For the side walls 320, this dimension is the transverse dimension. For the bottom wall 321, this dimension is the longitudinal dimension. For example, the thermal oxidation time or the deposition time and / or deposition rate can be adjusted for this purpose.

[0138] When the via 32 has been etched throughout its volume, following the formation of walls 320, 321, preferably of dielectric material, the via 32 can be filled with a conductive or semiconducting material 323, for example as shown in FIG. 5C. The conductive material can be a metal, such as copper or tungsten. The semiconducting material can be polycrystalline silicon (generally called poly-Si). This filling is preferably performed by deposition of the material 323 in the via 32. For example, the deposition of poly-Si is generally performed by LPCVD (Low Pressure Chemical Vapor Deposition).

[0139] According to the previously described steps of forming the vias, the different configurations of the vias 32 described above can be obtained. For example, Fig. 5A can be transferred to the assembly with a donor sub-substrate 2 to obtain a hollow via 32 without a sidewall 320 of dielectric material. For example, Fig. 5B can be transferred to the assembly with a donor sub-substrate 2 to obtain a hollow via 32 with a sidewall 320 and a bottom wall 321 of dielectric material.

[0140] It is possible to carry out a combination of etching and deposition, and even a transfer of the substrate layer 1, to fill the vias at the rear of the substrate, in order to obtain vias with several portions each having a structure.

[0141] Mask 12 can be removed following the formation of the dielectric material and further following the filling of vias 32 with material 323. In a variant, mask 12 can be removed prior to the formation of these walls of dielectric material. If layer 11 served as a hard mask, it is preferable to also remove layer 11.

[0142] The method may include a step of forming the marker 34 together with or following the formation of the vias. For this, the mask may further comprise an opening, not depicted in this case, for example to etch the opening in the second layer 31 down to the first layer 30. The opening may be filled with a dielectric material during the formation of the walls. The formation of the marker 34 may be separate from these steps of etching and filling the opening, for example by application of a mask specific to this marker 34. If the formation of the marker 34 is separate from these steps, it is advantageously performed beforehand to serve as a marker for the positioning of the vias 32.

[0143] The formation of the grooves 35 may include the same steps as for the etching of the vias 32 and, if necessary, the same steps as for the formation of walls of dielectric material. The grooves 35 may be formed simultaneously with the vias 32, so that the mask 12 comprises an opening corresponding to the grooves 35 to be etched. The grooves 35 may alternatively be etched before or after the etching of the vias 32, such as by application of a mask and an etching specific to the grooves 35. According to an example, once the grooves 35 and the vias 32 are etched, a dielectric material may be formed in the walls 350, 351, 320, 321, as previously described. Alternatively, the grooves 35 may be formed after the formation of the dielectric material in the walls 320 and 321. According to the method previously described, it may be provided that another formation of a dielectric material is performed in the walls 350, 351. The etching of the grooves 35 may also not be followed by the formation of a dielectric material in the walls 350 and 351. The grooves 35 and the vias 32 may, according to a variant, not have walls of dielectric material.

[0144] Following the formation of the vias 32 and, if necessary, the grooves 35, these structures can be covered so as to be embedded during assembly of the sub-substrate 1 with the donor sub-substrate 2. To that end, the method can include providing a donor sub-substrate 2 having an exposed surface 2a'. The assembly method described later can be applied to all the examples described above.

[0145] For example, as shown by Fig. 4D, the support sub-substrate 1 and the donor sub-substrate 2 can be assembled by direct bonding contact of their respective surfaces 1a, 2a, so that the donor substrate 2 can be thinned, for example by cutting by a method known as Smart-Cut®.

[0146] The assembly may for this purpose comprise, prior to contacting the surfaces 1a, 2a, forming an embrittled region 22 at a non-zero depth from the surface 2a of the donor sub-substrate 2. This embrittled region 22 is formed, for example, by ion implantation, such as hydrogen and / or helium ions. It is noted that any other technique for forming an embrittled region may be considered, in particular any other technique used in SOI type stack development methods.

[0147] Following the assembly of the support sub-substrate 1 and the donor sub-substrate 2, the method may include separating the surface layer from the donor sub-substrate 2 at the embrittled region 22, as shown in the transition from Figure 4D to Figure 4E . This separation can be performed thermally or mechanically, by steps known to those skilled in the art.

[0148] After separation, the resulting surface 3a may be irregular. Surface 3a may be polished, chemically smoothed, chemically, mechanically, and / or thermally hardened, or ion beam hardened based on atomic groups or monomers, so that it has a crystalline quality and roughness that is compatible with other subsequent methods. Any chemical mechanical polishing (CMP) or thermal polishing method intended to smooth semiconductor-based surfaces, in particular silicon-based surfaces, may be considered.

[0149] According to an example, the donor sub-substrate 2 comprises a layer 20 with a main content of or made of a semiconductor material, for example made of silicon, more specifically monocrystalline silicon or a piezoelectric material. The donor sub-substrate 2 may further comprise a layer 21 with a main content of or made of a dielectric material, for example made of silica SiO2.

[0150] By way of example, a layer 21 based on a dielectric material can form the surface layer of the donor sub-substrate 2. A direct bond of a dielectric material, for example silicon oxide, can in particular be made to a dielectric material, for example silicon oxide. Following their assembly, the layer 21 and the layer 11 form the second layer 31 of the substrate 3. The thickness of each of these layers is then determined according to the desired thickness L 31 According to this example, it will be appreciated that the top wall 322 of the via 32 and, if desired, the top wall 352 of the trench 35 may be formed from a dielectric material.

[0151] In a variant, a direct bond of a dielectric material, in particular silicon oxide, can be made to the semiconductor of layer 10 of the supporting sub-substrate 1. Following their assembly, layer 21 will form the second layer 31 of the substrate 3. It is understood that, according to this example, the upper wall 322 of the via 32 and, if necessary, the upper wall 352 of the groove 35 can be made of a dielectric material.

[0152] According to an example, layer 20 may form a surface layer of donor sub-substrate 2. Direct bonding of a dielectric material, for example silicon oxide, may be performed to a semiconductor or piezoelectric material. Following their assembly, layer 20 will form second layer 31 of substrate 3, an intermediate dielectric layer being arranged between first layer 30 and second layer 31. It is understood that according to this example, upper wall 322 of via 32 and, if necessary, upper wall 352 of trench 35 may be formed from a semiconductor or piezoelectric material.

[0153] By way of example, layer 20 may form a surface layer of donor sub-substrate 2. Direct bonding of semiconductor to semiconductor, in particular silicon, or piezoelectric, may be performed when layer 20 is based on a semiconductor or piezoelectric material. Following their assembly, layer 20 will form second layer 31 of substrate 3.

[0154] It is noted that for assembly, it is preferable to have a thickness of dielectric material, in particular an oxide thickness, at the bonding interface of at least 10 nm to avoid the appearance of defects.

[0155] A method for manufacturing the microelectronic device 4 will now be described with reference to Figures 6A to 8D.

[0156] In this manner, the vias 32 may serve to establish an interconnection. The vias 32 may alternatively or complementary serve to form part of a microelectronic device without necessarily having a metallic interconnection, such as in a MEMS device.

[0157] The method may include providing a substrate 3. The method may include depositing layers of components, for example transistors, diodes, memory points. This deposition may include for example FEOL steps.

[0158] 6D, the method may include depositing at least one layer portion 40, also called device portion 40, on the front surface 3a of the substrate 3. In the following, it is considered in a non-limiting manner that several portions 40 are deposited. Alternatively or complementary, the device portion may be etched on the front exposed surface 3a of the substrate 3.

[0159] These portions can be metal 40, specifically forming metal interconnect lines. Typically, these metal portions 40 serve to redistribute electrical signals. These metal portions can also be called metallization levels. There can be several metal portions 40 with interconnections between these portions. This deposition can include, for example, BEOL steps.

[0160] In the following, it is considered in a non-limiting manner that these parts 40 are metallic and serve to establish interconnections with etched vias 32. The following steps naturally apply if parts 40 of a non-metallic device 4 are deposited and / or etched.

[0161] Deposition of at least one layer portion 40 may occur after formation of vias 32 as shown, and may occur after or before formation of conductive or semiconductive features 45, if desired.

[0162] To facilitate handling of the substrate 3, the method may comprise mounting a support 41 on the side of the front face 3a and / or the exposed rear face 3b of the substrate 3, depending on the manufacturing step. This mounting may for example be performed through a bond 410, as illustrated by Fig. 6B. This further makes it possible to protect the deposition carried out on the surface of the substrate 3. The method may further comprise removing this support 41, for example when it is necessary to access the surface covered by the support 41 or at the end of the method.

[0163] The method comprises etching at least one via 32 to achieve at least one provision of electrical continuity between the portion 40, the via 32 and the rear face 3b of the substrate. To this end, several examples are possible and are now described. To simplify the figures, the portion 40 is not depicted in all figures. In the following, it is considered in a non-limiting manner that several vias 32 are etched.

[0164] Preferably, the method includes selecting only some of the vias 32 to define a group of vias 32' to be etched. Thus, from the generic substrate 3, only the vias of interest can be used to manufacture the microelectronic device 4. In the following, it is considered in a non-limiting manner that the method includes this selection and that only some of the vias 32 are used, rather than all of the vias 32.

[0165] According to a first example, as illustrated by Figures 6A to 6D, from the front side 3a a cavity 43 can be created reaching the via 32'. For this, a mask 42 can be applied to the front side of the substrate 3. The mask can be provided with or etched to have openings 420. The mask can be, for example, a hard mask with a main component of SiO2 or a hard mask made from SiO2. The mask is, for example, deposited by PECVD.

[0166] The cavity 43 can be etched, for example as shown by FIG. 6B, to reach the via 32', more precisely to reach and preferably beyond the upper wall 322. For this, for example an SF6 silicon etch is performed. Preferably, the etch does not renew the conductive material of the via 32' at this time, to avoid contamination of the substrate, which can actually be disruptive if active devices are fabricated. To renew the conductive material 323 of the via, the method can include a RIE (reactive ion etching), also called "etch back", to open the bottom of the cavity. It is preferable that the conductive material of the via is only found after the formation of the dielectric wall 450, which is described later.

[0167] Once the cavities 43 are formed, the method may include depositing a conductive or semiconductive member 45. This member 45 may have or be made of a metallic material 45, for example, based on electrolytic copper or CVD tungsten. Alternatively, this member 45 may have or be made of a semiconductive material, for example, based on poly-Si. The deposition may be configured to fill these cavities 43 with a metallic material to form electrical interconnects or device portions 40, for example, as shown by FIG. 6D.

[0168] From the rear face 3b of the substrate 3, the first layer 30 can be etched until it is flush with or beyond the bottom walls 321 of the vias 32. For this, the first layer 30 can be thinned and etched by etching the material of the first layer 30. The whole of the rear face 3b of the substrate 3 can be etched, so that all the vias 32 are reached.

[0169] This etching may be, by way of example, a selective etching of the material of the layer 30 with respect to the dielectric material of the walls of the vias 32. The etching may be, for example, a selective etching of silicon with respect to silica SiO2 in a reactive ion etch, using a precursor such as SF6. By "selective etching of material A with respect to material B", this means that the etching rate of material A is 10 times greater, preferably 100 times greater, than the etching rate of material B. It may be considered to carry out a partial mechanical thinning of the substrate 3, which ends with a plasma or selective chemical etch. The walls of the dielectric material may then be etched selectively with respect to the material of the first layer 30, in order to open up to the vias 32. Some vias 32' may only undergo this selective etching. For example, the etching of the dielectric material may be a reactive ion etch. The etching of the semiconductor material may be similar to that carried out to etch the layer 30.

[0170] Alternatively or complementary, one could also consider local etching from the rear face 3b through a mask having openings vertically aligned with the vias 32' to be etched, the etched cavities being filled with a conductive or semiconductive material.

[0171] Preferably, before the deposition of the conductive or semiconductive material on the front face 3a and / or the rear face 3b of the substrate 3, the method comprises forming a wall 450 of a dielectric material so as to insulate this material from the layers it passes through, as for example shown in Fig. 6C. The wall 450 may be formed by PECVD, such as SiO2. This deposition is preferably sufficiently conformal to cover the sides of the cavity 43. This makes it possible to avoid short circuits with the substrate 3.

[0172] The method may then include deposition configured to cover at least a portion of the rear exposed surface 3b of the substrate 3 with a metallic or semiconducting layer 46 to provide continuity to the device portion 40, the via 32, and the rear surface 3b of the substrate 3, as shown, for example, by FIG. 6D.

[0173] The method may further include, preferably between the formation of cavity 43 and the deposition of layer 46, at least one of the following: - Removal of Mask 42. passivation of the rear exposed face 3b of the substrate 3, for example by the formation of a layer of dielectric material 44, also called passivation layer 44. This formation can be carried out, for example, by deposition of a dielectric material as described above. an etching of layer 44 so as to remove the optional oxide layer formed in via 32', which may in fact limit electrical recontact in portion 40;

[0174] According to the example illustrated by Figure 7, the method can also be applied to vias having sidewalls of dielectric material and filled with the same material as the first layer 30. The same steps described previously can be applied.

[0175] 8A-8D illustrate another example in which the via 32 is hollow. As previously described, a cavity 43 can be formed vertically aligned with the via 32' that is etched to open into the via 32.

[0176] When the walls of the etched via 32' are not made of a dielectric material, the method may include forming a dielectric layer at least on the sidewalls 320, according to the method previously described with reference to the method for manufacturing the substrate 3. An example of this can be shown by Fig. 8B. Walls 450 of dielectric material are further advantageously formed in the etched cavity 43.

[0177] The vias 32' can then be filled with a conductive or semiconductive material 45. The steps described with reference to the previous example are applicable.

[0178] In a variant, the etching can be carried out from the face of the substrate 3 until it opens up to the via 32' and can be continued to form at least one cavity 43, for example an electrical connection cavity 43, and to reach the other face of the substrate 3, whether from the front or rear face. The method can further comprise other steps as previously described, to obtain the device shown in FIG. 8D.

[0179] 9A-9C, the described example can also be applied to an example where the via 32 has several configuration areas along one and the same via 32. For example, the parts filled with conductive or semiconductive material can be connected by the member 45. The hollow part of the via 32 can be at least partially filled with a layer 46 and / or other members 45 after the formation of the dielectric material to insulate the via 32.

[0180] The described example can also be applied to the example in which the via 32 comprises a groove 35. In order not to fill the groove with a conductive or semiconductive material, the opening 420 of the mask 42 can be arranged so as not to allow etching of the groove 35. During the steps following the formation of the cavity 43, the groove 35 preferably remains closed and is therefore not filled with the material 45.

[0181] In view of the above, it becomes clearly evident that the present invention proposes a substrate, a method for its manufacture and a method for manufacturing a microelectronic device, which makes it possible to simulate the manufacture of vias in a microelectronic device.

[0182] The present invention is not limited to the embodiments described above, but extends to all embodiments covered by the present invention. The present invention is not limited to the examples described above. Many other variations of the embodiments are possible, for example by combining the above features, without departing from the scope of the present invention. Moreover, features described with respect to an aspect of the present invention can be combined with other aspects of the present invention.

[0183] In particular, the substrate may have any characteristic resulting from its manufacturing method, and vice versa, and the method may include any step configured to obtain the characteristic of the substrate. A method for manufacturing a microelectronic device may implement any characteristic of the substrate.

[0184] In the described example, the semiconductor material is silicon. The invention is of course applicable to other monocrystalline or polycrystalline semiconductors, optionally doped, in particular to Si, Ge, SiGe, SiC, III-V materials (e.g. AlN, GaN, InN, InGaAs, GaP, InP, InAs, AsGa, etc.), and II-VI materials. The dielectric material can be an oxide or semiconducting nitride, such as SiO2, SiN, Al2O3, etc. The piezoelectric material can be, by way of example, lithium tantalate (LiTaO3), lithium niobate (LiNbO3), potassium sodium niobate (KNaO3), etc. X Na 1-X The material may be selected from lead zirconate titanate (NbO3 or KNN), barium titanate (BaTiO3), quartz, lead zirconate titanate (PZT), lead magnesium titanate niobate (PMN-PT), zinc oxide (ZnO), aluminum nitride (AlN) or aluminum scandium nitride (AlScN), and of course other materials are conceivable. [Explanation of symbols]

[0185] 1 Support sub-board 1a Exposed surface, surface 2 Donor Substrate 2a surface 2a' Exposed surface 3. Substrate 3a Front exposed surface 3b Rear exposed surface 4. Microelectronic devices, non-metallic devices 10 First Layer 11 Surface layer 12. Mask 20 Layers with a semiconductor material as the main component, layers made of semiconductor materials 21 Layers with a main component of dielectric material, layers made of dielectric material 22 Embrittlement area 30 First Layer 31 Second Layer 32 Vias, Via Configurations 32' Etched Via 32a, 32a', 32a” set 32b, 32b', 32b" patterns 33 The Third Layer 34 Marker 35 Groove 40 Device part, layer part, metal part 41 Support 42 Mask 43 Cavity 44 Dielectric material layer, passivation layer 45 Conductive or semiconductive materials, metallic materials 46 Metallic or semiconducting layer 120 aperture 320 side wall 320' groove 321 Bottom wall 322 Upper Wall 323 Conductive or semiconductive materials 350 side wall 351 Bottom wall 352 Upper Wall 410 Junction 450 Dielectric material wall A 1st pitch B 2nd pitch D 32 Transverse dimension, horizontal dimension L 30 Thickness of the first layer 30 L 31 Thickness of the second layer 31 L 32 Longitudinal dimension and depth of via 32 L 33 Thickness of the third layer 33 L 35 Longitudinal dimension and depth of groove 35 D 35 Transverse dimension of groove 35, diameter

Claims

1. a first layer (30) based on a semiconductor material; a second layer (31) on the first layer (30); A substrate (3) comprising: The substrate (3) comprises a plurality of embedded vias (32) extending from the second layer (31) across a portion of the first layer (30), each via (32) being defined by a side wall (320), a bottom wall (321) and a top wall (322) opposite the bottom wall (321), and at least one group (32a) of the plurality of vias (32) forming a pattern (32b) that is repeated along at least one direction of a main extension plane of the first layer (30) and the second layer (31).

2. The substrate (3) of claim 1, wherein each via (32) has at least one transverse dimension between 1 μm and 30 μm.

3. 3. The substrate (3) of claim 1 or 2, wherein at least some of the vias (32) have an aspect ratio of 10 or greater of their longest dimension oriented along a dimension in thickness of the first layer (30) and the second layer (31).

4. 4. The substrate (3) according to claim 1, wherein within a set (32a) of vias (32), two patterns (32b) of continuously repeated vias (32) are spaced apart at a constant pitch along at least one direction of the main extension planes of the first layer (30) and the second layer (31), the pitch being between 50 μm and 300 μm.

5. 5. The substrate (3) according to claim 1, wherein the substrate (3) comprises a single via set (32a) forming a pattern (32b) comprising a single via (32), each via (32) being spaced apart from its nearest neighboring via (32) at a constant pitch along two directions different from the main extension planes of the first layer (30) and the second layer (31).

6. 5. The substrate (3) according to claim 1, comprising several sets (32a, 32a', 32a") of vias (32) each forming a pattern (32b, 32b', 32b") that is repeated along at least one direction of the main extension plane of the first layer (30) and the second layer (31).

7. At least one via (32) has at least one of the following via configurations: a via configuration in which the sidewalls (320) of the vias (32) are made of a dielectric material and the vias (32) are filled with a conductive or semiconductive material or the vias (32) are hollow; a via configuration in which the sidewalls (320) of the vias (32) are made of a dielectric material and the vias (32) are filled with the material of the first layer (30); A via configuration in which the sidewalls (320) of the via (32) are made from the material of the first layer (30) and the via is hollow. The substrate (3) according to any one of claims 1 to 6, comprising at least one of:

8. 8. The substrate (3) of claim 7, wherein at least one via (32) has a first via configuration in a first portion (32c) and a second via configuration in a second portion (32d) that is different from the first via configuration, and the first portion (32c) and the second portion (32d) extend continuously along a thickness dimension of the first layer (30) and the second layer (31).

9. The substrate (3) according to claim 7 or 8 in combination with claim 6, wherein at least one set (32a, 32a', 32a'') has at least one via configuration different from the other sets (32a, 32a', 32a'').

10. 10. The substrate according to claim 1, wherein the pattern (32b) of at least one set (32a) repeated along at least one direction of the main extension plane of the first layer (30) and the second layer (31) spans at least 80% of a dimension of the substrate (3) along this direction.

11. A method for manufacturing a substrate (3) according to any one of claims 1 to 10, comprising the steps of: Providing a supporting sub-substrate (1) comprising at least one first layer (10) based on a semiconductor material and having an exposed surface (1a); forming a plurality of vias (32) such that the vias (32) extend from the exposed surface (1 a) across a portion of the first layer (10), each via being defined by a sidewall (320) and a bottom wall (321), and at least one set (32a) of vias (32) forming a pattern (32b) that is repeated along at least one direction of the main planes of extension of the first layer (30) and the second layer (31); Providing a donor sub-substrate (2) comprising a surface layer (20, 21) having an exposed surface (2a); assembling said support sub-substrate (1) and said donor sub-substrate (2) with their exposed surfaces (1a, 2a) such that said vias (32) are covered, such that each via is defined by said side wall (320), said bottom wall (321) and a top wall (322) opposite said bottom wall (321); A method comprising:

12. 12. The method of claim 11, wherein the step of forming the plurality of vias (32) includes, for at least one set of vias (32a), etching at least one periphery of the vias (32) in at least one first portion (32c) of the vias (32).

13. 13. The method of claim 12, wherein the step of forming the plurality of vias (32) includes, following the step of etching at least the perimeters of the vias (32), forming a dielectric material at least over the etched perimeters of the vias (32) to form the sidewalls (320) of the vias (32) of dielectric material.

14. 14. The method of claim 13, wherein during the etching of the periphery of the via (32), the via (32) is etched over substantially its entire volume, and wherein the step of forming the plurality of vias (32) comprises, following the step of forming a dielectric material over at least the etched periphery of the via (32), depositing a conductive or semiconductive material (323) to at least partially fill the vias (32) so as to form the sidewalls (320) of the vias (32) of the dielectric material.

15. 15. The method according to any one of claims 11 to 14, wherein the step of forming the plurality of vias (32) comprises the step of forming several sets (32a, 32a', 32a") of vias (32) each forming a pattern (32b, 32b', 32b") that is repeated along at least one direction of the main extension plane of the first layer (30) and the second layer (31).

16. A method for manufacturing a microelectronic device (4), comprising the steps of: Providing a substrate (3) according to any one of claims 1 to 10 and / or a substrate (3) manufactured by the method according to any one of claims 11 to 15, said substrate (3) having a front exposed surface (3a) and a rear exposed surface (3b); forming at least one layer portion (40) of said device (4) on at least one of said front exposed surface (3a) or said rear exposed surface (3b) of said substrate (3) by deposition of said portion and / or etching of at least one of said front exposed surface (3a) or said rear exposed surface (3b) of said substrate (3) configured to form said portion (40); Etching in at least one via by one of the front exposed surface (3a) or the rear exposed surface (3b) of the substrate (3) until the via is reached; continuing said etching until reaching said at least one layer portion (40) of said device (4); or - etching in said at least one via by the other of said front exposed surface (3a) or said rear exposed surface (3b) of said substrate (3) until said via is reached; depositing at least one conductive or semiconductive member (45) to provide electrical continuity to at least said via (32) and said device layer portion (40); A method comprising:

17. 17. The method of claim 16, comprising the step of selecting at least one via (32') to be etched from among the plurality of vias (32), wherein only some of the plurality of vias (32) are selected as the via (32') to be etched.

18. 18. The method of claim 17, wherein the step of selecting the at least one via (32') to be etched comprises a step of applying a mask (42) at the front exposed face (3a) or the rear exposed face (3b) of the substrate (3) with an opening (420) positioned vertically aligned with the at least one via (32') to be etched, and continuing the etching to reach the at least one via (32') to be etched.

19. 19. The method according to claim 17 or 18, wherein when the method performs the etching through the other of the front exposed surface (3a) or the rear exposed surface (3b) of the substrate (3), the step of selecting the at least one via (32') to be etched from among the plurality of vias (32) until the via is reached comprises a step of applying a mask (42) comprising an opening (420) positioned vertically aligned with the at least one via (32') to be etched in the other of the front exposed surface (3a) or the rear exposed surface (3b) of the substrate (3), the method further comprising a step of etching to reach the at least one via (32') to be etched.

20. 20. The method according to any one of claims 16 to 19, wherein the step of depositing the conductive or semiconductive member (45) is configured to further cover at least a portion of the front exposed surface (3a) and / or the rear exposed surface (3b) of the substrate (3) with a conductive or semiconductive layer (46).

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