Diamond-metal composite high-power device package

Abstract

An object of the present invention is to provide a semiconductor device package having improved thermal conductivity and a method for manufacturing the same. The semiconductor device package includes a flange, a frame secured to a major surface of the flange, the frame forming an air cavity partially surrounded by a surface of the flange, and at least one conductive lead extending from an exterior of the frame through a portion of the frame and exposed within the air cavity for wire bonding. The flange may incorporate a composite core material including diamond particles dispersed in a metal. The flange improves thermal conductivity, increasing heat dissipation from the semiconductor device within the package, further improving performance. The flange exhibits a higher thermal conductivity than copper and other materials. Additionally, the flange exhibits a suitable coefficient of thermal expansion for bonding semiconductor dies, including GaN and SiC materials, to the flange.

Description

[Technical field]

[0001] (Related Applications) This application claims the benefit of and priority to U.S. Non-Provisional Patent Application No. 17 / 661,418, entitled "DIAMOND-METAL COMPOSITE HIGH POWER DEVICE PACKAGES," filed April 29, 2022, the entire disclosure of which is incorporated herein by reference. [Background technology]

[0002] Various types of packages are available for electrical components such as active and passive semiconductor devices, resistors, capacitors, and inductors. The packages can protect and secure the components and provide conductive leads for making one or more electrical contacts with the components. Such packages can be surface mounted, through-hole mounted, inserted into a printed circuit board, or other such technologies. The type, size, lead style, construction, materials, and other characteristics of the package can be selected based on the type of component housed therein and the application of the component. For example, a particular package may be more or less suitable for components used in high power and high frequency applications. Summary of the Invention [Means for solving the problem]

[0003] Aspects of the present disclosure can be better understood with reference to the following drawings. It should be noted that the elements in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the embodiments. In the drawings, like reference numerals indicate similar or corresponding, but not necessarily identical, elements throughout the several views. [Brief description of the drawings]

[0004] [Figure 1A] 1 illustrates a perspective view of a semiconductor device package according to various embodiments described herein. [Figure 1B] 1B illustrates an exploded view of the semiconductor device package shown in FIG. 1A according to various embodiments described herein. [Figure 1C] 1B illustrates a top view of the semiconductor device package shown in FIG. 1A according to various embodiments described herein. [Diagram 2] 2 illustrates a top view of another exemplary semiconductor device package in accordance with various embodiments described herein. [Diagram 3] 1B illustrates the semiconductor device package shown in FIG. 1A having components attached to a flange within the package according to various embodiments described herein. [Figure 4] 1B illustrates a cross-sectional view of the package indicated at AA in FIG. 1A positioned through and attached to a printed circuit board according to various embodiments described herein. [Diagram 5] 1 illustrates a representative example of a core material within a flange according to various embodiments described herein. [Figure 6] 1B illustrates an example process flow for assembly of the semiconductor device package shown in FIG. 1A according to example embodiments described herein. [Figure 7] 2 illustrates a perspective view of another exemplary semiconductor device package according to various embodiments described herein. [Figure 8] 8 illustrates a cross-sectional view of a semiconductor device package, as indicated at BB in FIG. 7, according to various embodiments described herein. [Figure 9] 1 illustrates an example of a lead frame and a semiconductor device package according to various embodiments described herein. [Figure 10] 1 illustrates a portion of an exemplary leadframe with flanges or slugs positioned to form a package according to various embodiments described herein. [Figure 11] 11 illustrates a cross-sectional view of a lead frame with a flange positioned as indicated by CC in FIG. 10 according to various embodiments described herein. [Figure 12]1 illustrates an exemplary process for manufacturing and assembling a leadframe semiconductor device package according to embodiments described herein. [Figure 13] 4 illustrates another exemplary process for leadframe semiconductor device package manufacturing and assembly according to embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] Many different packages are available for electrical components, including devices formed on semiconductor dies. The packages can protect and secure the components and provide conductive leads to make one or more electrical contacts to the components. As an example, flat no-lead packages, such as the quad flat no-lead (QFN) package, can be used to physically protect and electrically connect semiconductor devices and integrated circuits to a printed circuit board (PCB). Flat no-lead packages are one of several types of packages that can be used to connect devices to a PCB without using through holes. Air-cavity packages are also used for semiconductor devices in high-power and high-frequency applications because of advantages such as minimizing dielectric capacitance. Air-cavity packages include leads and can be mounted on the PCB, in through holes in the PCB, or in other configurations. Some packages are better suited for components used in high-power and high-frequency applications, and the type, size, lead style, construction, materials, and other characteristics of the package can be selected and designed based on the type of component housed therein, as well as the application of the component.

[0006] Adequate heat dissipation is a key characteristic of high power radio frequency (RF) packages, especially for packaged devices formed on gallium nitride (GaN), silicon carbide (SiC), and other high power density semiconductor materials. High power semiconductor dies have been directly attached to metallic package flanges or slugs. One fundamental problem with metallic flanges is the trade-off between the thermal conductivity (TC) and coefficient of thermal expansion (CTE) of the flange. In general, the higher the thermal conductivity of the flange material, the higher the CTE, making the flange less compatible with the CTE of GaN, SiC, and similar semiconductor materials.

[0007] Diamond is a unique material with high TC and low CTE. According to aspects of the embodiment, diamond or diamond particles are incorporated into the flanges and slugs of high power RF packages. Composite materials for flanges according to embodiments include diamond or diamond particles and other metals, particularly silver (Ag). These core materials can be tailored to meet the needs of a particular application by varying the diamond-to-metal ratio, diamond particle size, metal type, total thickness, and plated metal layers above and / or below the diamond-metal core composite. Materials can be tailored for targeted TC, CTE, flatness, or roughness to produce surfaces compatible with specific die attach materials or bonding processes.

[0008] The diamond composite flange is only one component of a functional RF package. The frame and conductive leads are assembled with the diamond composite flange according to the embodiment to form an internal air cavity within the package. Both preformed and molded frames can be used. As an example, a preformed window frame with conductive leads can be attached to the flange with a plastic adhesive. The preformed frame can be supplied with different lead configurations to allow flexibility. Also, the fixing of the preformed frame to the flange using a plastic adhesive is a low temperature process and can protect the diamond composite of the flange.

[0009] In the context outlined above, the embodiments described herein relate to a semiconductor device package and a method for manufacturing such a package. In one example, the semiconductor device package includes a flange, a frame secured to the top surface of the flange, the frame forming an air cavity partially surrounded by the top surface of the flange, and at least one conductive lead extending from the outside of the frame through a portion of the frame and exposed within the air cavity for wire bonding. The flange incorporates a composite core material including diamond particles dispersed in a metal. The flange exhibits a higher thermal conductivity than copper (Cu), aluminum nitride (AlN), copper molybdenum (CuMo), copper tungsten (CuW), stacks of CuMo and / or CuW, and other materials. The flange also exhibits a thermal expansion coefficient suitable for bonding a semiconductor die to the flange, including gallium nitride (GaN) and silicon carbide (SiC) materials.

[0010] In another example, a lead frame and a package formed using the lead frame are described. By using the lead frame, multiple packages can be formed at once. Furthermore, electrical components can be placed in the package by rearranging multiple devices at once using the lead frame. After assembly, the package can be separated from the lead frame. The package can include a flange or slug incorporating the diamond composite material described herein, a plastic frame surrounding the flange to form an air cavity, and a cover surrounding the air cavity. The package further includes one or more conductive leads of the lead frame extending through the plastic frame and exposed in the air cavity. The conductive leads can be relied upon to bond the components secured in the air cavity. Finally, a cover can be secured to surround the air cavity.

[0011] Referring to the drawings, FIG. 1A is a perspective view of an exemplary semiconductor device package 10, FIG. 1B is an exploded perspective view of the package 10 shown in FIG. 1A, and FIG. 1C is a top view of the package 10 shown in FIG. 1A. The package 10 is shown as a representative example to convey the concepts of the embodiments described herein. The package 10 is not drawn to scale, and other packages consistent with the concepts described herein may vary in shape and / or size as compared to the illustrated one. For example, the length "L", width "W", and height "H" of the package 10 may vary between embodiments. Similarly, the size, number, and location of the conductive leads of the package 10 may vary, as described below. Additionally, aspects of the embodiments are not limited to a particular package type, size, lead style, or configuration.

[0012] 1A-1C, package 10 includes a flange 20, a frame 30 secured to a major surface of flange 20, and a cover 40 secured over frame 30. An air cavity is formed within package 10, bounded by the top surface of flange 20, an opening in frame 30, and cover 40. As will be described below with reference to FIG. 3, multiple semiconductor devices formed on a semiconductor die may be secured within package 10. Because components within the air cavity are not surrounded by (i.e., not in contact with) the package molding material, they are not subject to electrical influences (e.g., parasitic capacitance, etc.) from the material.

[0013] The package 10 also includes a number of conductive leads 31-34, each of which extends from outside the frame 30 through at least a portion of the frame 30 and is partially exposed within the air cavity within the package 10. The semiconductor device within the package 10 may be electrically coupled to exposed portions of the conductive leads 31-34 within the package 10 using wire bonding or other means, as described in more detail below. The conductive leads 31-34 may be formed from Cu, Al, tin (Sn), Ag, Au, zinc (Zn), other metals, or any composition thereof, and may be plated with Ag, Au, Ni, Pd, or other metals using full plating, spot plating, or other techniques.

[0014] Flange 20 may also be electrically conductive in some embodiments and therefore may function as an electrically conductive lead for package 10. Thus, a semiconductor device die including a transistor source metal layer on the bottom surface of the die may be electrically coupled to flange 20. In that case, flange 20 may function as a source contact or lead for package 10. In other cases, as described below, flange 20 functions as a heat sink but not as an electrical contact.

[0015] The package 10 is designed with the goal of increasing thermal conductivity and heat dissipation from a semiconductor device packaged within the package 10. In one aspect, the flange 20 includes a material that exhibits a high TC to dissipate heat more effectively than other types of materials. The flange 20 material also exhibits a CTE value that is compatible with securely attaching the semiconductor die to the flange 20, and there is not a large enough mismatch between the CTE of the flange 20 and the die to result in mechanical separation under heating cycles. In one case, the flange 20 material can be selected in part so that the CTE of the flange 20 matches the CTE of the SiC substrate to the extent necessary for reliable attachment. In other cases, the flange 20 material can be tailored to have a CTE that is compatible with other substrate materials.

[0016] As described in more detail below, the flange 20 is embodied using a composite core material that has a higher thermal conductivity than materials commonly used for semiconductor package flanges and heat slugs. The flange 20 can include a composite core material of diamond particles dispersed in a metal or metal alloy. The diamond particles provide a high TC, since natural diamond has a TC of about 2200 W / m·K, while Cu has a TC of about 398 W / m·K. Concentrated single crystal synthetic diamond has been shown to have an even higher TC than natural diamond, and the flange 20 can incorporate synthetic diamond particles. Diamond particles of various sizes and shapes can be used in the composite material of the flange 20 to tailor the TC of the flange 20, the CTE of the flange 20, or other properties.

[0017] The diamond particles are mixed or dispersed in a metal, such as silver (Ag), copper (Cu), molybdenum (Mo), or other suitable metal. The metal may also be selected to tailor the TC of the flange 20, the CTE of the flange 20, or other properties. In some cases, the diamond particles are mixed and dispersed relatively evenly throughout the composite core material, while in other cases, larger diamond particles may be used and placed at specific locations within the metal of the composite core material. The metal provides electrical conductivity to the flange 20, which may be relied upon as a conductive terminal for the package 10.

[0018] 1B, flange 20, frame 30, and cover 40 are shown separate from one another to illustrate the individual features of each. Flange 20 includes a top surface 21, a bottom surface 22, and a peripheral surface 23. Top surface 21 and bottom surface 22 are the two largest (e.g., major) surfaces of flange 20. Additional details relating to flange 20, flange 20 materials, and other flanges and slugs that exhibit high thermal conductivity are described below with reference to FIG.

[0019] The frame 30 is formed to have a ring or frame shape with a central opening, as shown in FIG. 1A. In one example, the frame 30 can be formed by molding a plastic or polymer, such as a liquid crystal polymer (LCP) or polymer blend, with or without glass, carbon, or other reinforcements, among other materials. The frame 30 can be formed using a material selected to provide protection for the components within the package 10 (e.g., protection against temperature, vibration, moisture, and other conditions), mechanical strength, thermal expansion matching compared to other materials within the package 10, and other related factors. In another example, the frame 30 can be formed using a ceramic material. In that case, the frame 30 can be formed of a ceramic material and the cover 40 can be formed as a ceramic, metal, or glass lid. The cover 40 can be secured onto the frame 30 using any suitable method to create a hermetic (or semi-hermetic) seal for the package 10.

[0020] The frame 30 includes a central opening or aperture that surrounds an air cavity formed between the top surface 21 of the flange 20, the inner periphery of the frame 30, and the bottom surface of the cover 40 of the package 10. The flange 20 and the frame 30 are secured together to form a seal therebetween. The bottom surface of the frame 30 may be secured to the top surface 21 of the flange 20 using an adhesive, such as an epoxy or other plastic adhesive, using a mechanical interconnect or interference fit, using fasteners, or a combination thereof. In other cases, the bottom surface of the frame 30 may be secured to the top surface 21 of the flange 20 by brazing or soldering.

[0021] The bottom surface of the frame 30 can cover the peripheral edge 21A of the top surface 21 of the flange 20. A portion of the peripheral edge 21A is identified in FIG. 2. In some cases, the peripheral edge 21A of the top surface 21 of the flange 20 can be prepared for bonding with the bottom surface of the frame 30. For example, the top surface 21 of the flange 20 can be smooth and uniform in some cases as manufactured. Thus, the peripheral edge 21a can be roughened in some cases using laser etching, mechanical abrasion (e.g., sand blasting or abrasion with or without a mask), chemical etching, or other techniques. In other cases, the peripheral edge 21A can be treated by selective plating to add roughness. Treating the peripheral edge 21A in this manner can help to enhance the adhesion or bond between the bottom surface of the frame 30 and the peripheral edge 21A of the flange 20.

[0022] The frame 30 includes a central opening and a raised platform 35 that extends around the periphery of the frame 30. As mentioned above, the frame 30 also includes conductive leads 31-34, which are fixed in place by the molding material of the frame 30. The conductive leads 31-34 may include openings or apertures (not shown) in the portions of the conductive leads 31-34 that are surrounded by the molding material of the frame 30. The molding material of the frame 30 is allowed to flow through the openings during manufacture of the frame 30, helping to hold the conductive leads 31-34 in place.

[0023] Conductive leads 31-34 extend from the exterior of frame 30, through at least a portion of frame 30, and into a central opening in frame 30. Portions of conductive leads 31-34 are exposed at the level of raised platform 35. Exposed portions 33A and 34A of conductive leads 33 and 34 are shown in FIG. 1A, with similar portions of conductive leads 31 and 32 exposed at the level of raised platform 35 on the opposite side of frame 30 (see FIG. 3). Frame 30 can include other numbers of conductive leads. For example, frame 30 can include two conductive leads, one on each side, or three or more conductive leads on each side, as described below.

[0024] A number of semiconductor dies, including transistors, capacitor banks, and other circuit elements, may be attached and secured to the top surface 21 of the flange 20. Certain semiconductor dies may be electrically coupled to the flange 20 itself. For example, a semiconductor device die including a transistor source metal layer at the bottom of the die may be electrically coupled to the flange 20. The flange 20 may then function as a source contact or lead for the package 10. The semiconductor dies may also be electrically coupled to the conductive leads 31-34 of the frame 30, such as the conductive portions 33A and 34A of the conductive leads 33 and 34, using wire bonding or other means. Examples of semiconductor dies within the package 10 are described below with reference to FIG. 3.

[0025] The cover 40 may be made of plastic or other materials similar to the frame 30. In other cases, the cover 40 may be made using ceramic, glass, metal, or other materials. After the frame 30 is secured to the flange 20, the cover 40 may be secured to the frame 30. The underside of the cover 40 may be secured to the top side of the frame 30 using adhesives such as epoxy or other plastic adhesives, plastic welding, heating, or melting processes, using mechanical interconnects or interference fits, using fasteners, or a combination thereof. The material used for the cover 40 may also be selected to provide protection against vibration, moisture, and other conditions for the components in the package 10, mechanical strength, a suitable thermal expansion match compared to other materials in the package 10, and other related factors. In some cases, the cover 40 may be hermetically sealed to the frame 30, and the package 10 may be a hermetically sealed package.

[0026] FIG. 2 illustrates a top view of another exemplary package 10A according to various embodiments described herein. Package 10A is similar to package 10, but flange 20A is relatively longer than flange 20 and includes mounting ears or eyelets 24A and 24B at the ends of flange 20A. Package 10A can be secured to a heat sink, for example, at mounting eyelets 24A and 24B using mechanical fasteners such as screws, bolts, etc. Package 10A also includes two conductive leads 36 and 37 rather than the four conductive leads 31-34 of package 10. Like flange 20, flange 20A incorporates a composite core material including diamond particles dispersed in a metal, an example of which is described below with reference to FIG. 5. Other packages incorporating flanges similar to flanges 20 and 20A are within the scope of the embodiments, and a plastic molded package including such a flange or slug is described below with reference to FIG. 7.

[0027] FIG. 3 illustrates the semiconductor device package 10 shown in FIG. 2 with components attached to the top surface 21 of the flange 20 within the package 10. In FIG. 3, the cover 40 is not shown. Various types of active and passive components, such as integrated circuits formed on a semiconductor substrate (formed with any semiconductor processing technology), particularly components including configurations of transistors, resistors, capacitors, and inductors, discrete electronic components, electro-optical components, electro-mechanical components, and other components and combinations thereof, can be placed, arranged, and secured within the package 10. Thus, FIG. 3 illustrates an exemplary arrangement of semiconductor devices formed on a semiconductor die, and other arrangements of the die can depend on the package 10. The arrangement of semiconductor devices shown in FIG. 3 can also be extended to any of the other packages described herein.

[0028] In FIG. 3, rows 50 and 51 of semiconductor dies are secured to the top surface 21 of flange 20 in frame 30 to form die group 52. As shown in FIG. 3, row 50 includes semiconductor dies 60-62. Row 51 includes a row of similar semiconductor dies, not individually referenced in FIG. 3. Additional rows of dies may be relied upon. Rows 50 and 51 are coupled to each other in parallel between conductive lead 34 and conductive lead 32 using wire bonding, as described below. Die group 53 is coupled in parallel between conductive lead 33 and conductive lead 31. Each of the other semiconductor dies 60-62 in package 10 may be secured to the top surface 21 of flange 20 using thermal epoxy, solder, solder preform, sintered silver die attach, or other suitable means. For example, gold-tin solder or solder preforms can be used to help mitigate the effects of thermal expansion mismatch between the flange 20 and the semiconductor dies 60-62, although the material of the flange 20 reduces this mismatch to some extent compared to other materials, as described below.

[0029] In the illustrated example, the semiconductor die 60 includes a high power transistor amplifier, such as, by way of example, a transistor formed of GaN material on a SiC substrate. In accordance with the concepts described herein, the composite core material of the flange 20 has a relatively high CT while at the same time having a CTE that more closely matches the CTE of the SiC substrate than a material such as Cu. Thus, the flange 20 is particularly well suited to reliably dissipate heat from the transistor amplifier on the semiconductor die 60.

[0030] Semiconductor dies 61 and 62 include one or more capacitors for input impedance matching. In some cases, semiconductor dies 61 and 62 may also include resistors to form a resistor-capacitor network for input impedance matching, among other circuit components. Together, semiconductor dies 61 and 62 may be relied upon for first and second harmonic termination, control, and input impedance matching of the transistor amplifier on semiconductor die 60. Depending on the need for input impedance matching, semiconductor die 61 may be omitted, semiconductor die 62 may be omitted, or both semiconductor dies 61 and 62 may be omitted.

[0031] After the dies 52 and 53 are secured to the top surface 21 of the flange 20 of the semiconductor device package 10, the dies are electrically coupled to the conductive leads 31-34 of the frame 30 and to each other. In particular, a bond wire 65 is coupled between the conductive leads 34 and a bond pad on the semiconductor die 62. A bond wire 66 is coupled between a bond pad on the semiconductor die 62 and a bond pad on the semiconductor die 61. A bond wire 67 is coupled between a bond pad on the semiconductor die 61 and a bond pad on the semiconductor die 60. Additionally, a bond wire 68 is coupled between a bond pad on the semiconductor die 60 and the conductive leads 32. Any suitable type and number of bond wires may be used, such as gold bond wires of a suitable diameter or thickness. Additional bond wires may also be used to electrically couple the semiconductor dies 60-62 in the row 50 to the corresponding semiconductor dies in the row 51 between stitch pads on the dies. In this way, the respective potentials at particular circuit nodes between the dies can be referenced in agreement with one another and help maintain stability.

[0032] Dies 52 in semiconductor device package 10 can collectively operate as a single three terminal active device. In particular, dies 52 can operate as a single common source transistor amplifier with conductive lead 34 acting as a gate input, conductive lead 32 acting as a drain output, and flange 20 acting as a common source. Dies 53 can also collectively operate as another single three terminal active device in semiconductor device package 10. Dies 52 and 53 can potentially be used together to form a D-mode amplifier, although other amplifier configurations can be used.

[0033] In other cases, the semiconductor device package 10 may omit the semiconductor die group 53 and the conductive leads 31 and 33. In that case, the semiconductor device package 10 may appear as a single three terminal active device having or consisting of only three terminals or package leads. In still other cases, the semiconductor device package 10 may include additional rows of semiconductor die bonded together in groups. Additionally, the semiconductor device package 10 may include additional leads and additional die groups, and other variations are within the scope of the embodiments.

[0034] 4 illustrates a cross-sectional view of the package 10 shown in FIG. 1 positioned with a printed circuit board (PCB) 70. In particular, the PCB 70 includes a through hole or opening large enough for clearance of the flange 20 of the package 10, which is disposed within the opening of the PCB 70. The conductive leads 32 and 34 of the package 10 are electrically coupled to traces on the PCB 70 for electrical coupling with other components on the PCB 70. As an example, the PCB 70 may be embodied as an RF pallet for high power amplification of RF signals, and the package 10 may provide an amplifier on the RF pallet.

[0035] Also, the heat sink 72 is disposed below the PCB 70, and the bottom surface 22 of the flange 20 is disposed on and in contact with the top surface of the heat sink 72. The heat sink 72 may be embodied as a plate of Cu, Al, or other metal suitable for conducting heat out of the package 10. The flange 20 of the package 10 may be secured to the heat sink 72 in a variety of ways. By way of example, the flange 20 may be secured to the heat sink 72 using thermal paste, thermal epoxy, solder, or other suitable techniques. The package 10 may also be held in place relative to the heat sink 72 using mechanical fasteners, clips, clasps, or other means using the flange 20. Other packages incorporating flanges similar to the flange 20 may be secured to the heat sink 72 in other ways. For example, the flange 20A shown in FIG. 2 may be secured to the heat sink 72 using mechanical fasteners such as screws, bolts, or other fastening means at the mounting eyelets 24A and 24B, with or without the use of thermal paste between the flange 20A and the heat sink 72. Flange 20 transfers heat “H” from within package 10, specifically semiconductor dies 60-62, to heat sink 72.

[0036] FIG. 5 shows an exemplary cross-sectional view of the flange 20 to illustrate the core material used therein. The flange 20 includes a core of diamond particles 81 dispersed in metal 82, plating layers 83 and 84 forming the upper surface 21 of the flange 20, and plating layers 85 and 86 forming the lower surface 22 of the flange 20. The diamond particles 81 can be synthetically manufactured in one example, but any diamond can be used. Diamonds and diamond particles with consistent and strong carbon bonds are preferred, and such diamonds exhibit higher thermal conductivity. The size and shape of the diamond particles 81 can vary between embodiments. For example, relatively small diamond particles 81 are shown in FIG. 5, but larger particles can be relied upon.

[0037] The thickness "T" of the flange 20 can vary between embodiments. Exemplary thicknesses of the flange 20 and other flanges described herein can range from 20-80 mils (i.e., several thousand inches) by way of example, although other thicknesses can be relied upon. Larger thicknesses can also be used, including thicknesses greater than 80 mils, greater than 90 mils, or greater. The thicknesses of the plated layers 83-86 can each range from 0.05-2 mils, although other thicknesses can be relied upon. In other aspects, the ratio of diamond particles to metal in the core of the flange 20 can range, such as from a ratio of 30% diamond to 70% metal to a ratio of 70% diamond to 30% metal. These aspects of the flange 20 can be tailored to meet the needs of a particular application by varying the diamond to metal ratio, the size of the diamond particles 81, the type of metal 82, the thickness "T", and the type and thickness of the plated metal layers 83-85. The materials can be tailored to a target TC, CTE, flatness, or roughness to produce a surface compatible with a particular die attach material or bonding process.

[0038] The metal 82 can be embodied as Ag, Cu, or Mo, among other metals, with Ag being preferred due to its high electrical and thermal conductivity. The diamond particles 81 can be mixed and uniformly dispersed in the metal 82 while the metal 82 is heated to a liquid state, and the shape of the flange 20 core can be established by pressing the mixture between hot plates, although other manufacturing techniques can be used.

[0039] The plating layers 83-86 may be deposited or formed on the major surfaces of the core to help planarize the top surface 21 and the bottom surface 22. As an example, the plating layer 83 may include a layer of nickel (Ni) deposited on the top of the core, and the plating layer 84 may include a layer of gold (Au) deposited on the plating layer 83. Similarly, the plating layer 85 may include a layer of Ni deposited on the bottom of the core, and the plating layer 86 may include a layer of Au deposited on the plating layer 84. However, other metals may be used for the plating layers 83-86, including plating techniques using one or more layers of Ni, Au, palladium (Pd), Cu, and other metals. The plating layers 83-86 may be formed by vapor deposition of metals or other suitable techniques. The plating layers 83-86 may help smooth or planarize roughness caused in part by the corners and edges of the diamonds 81 in the metal 82. A relatively large sheet of diamond grains 81 in metal 82 including plating layers 83-86 can be formed and individual flanges can be cut from the sheet. Alternatively, diamond grains 81 and metal 82 can be individually formed into the final shape using appropriate tooling and then plating layers 83-86 can be added to all sides of flange 20.

[0040] Due to the materials used, the flange 20 exhibits a higher TC than conventional types of materials such as Cu, CuMo, CuMo laminates, and other materials commonly used for semiconductor package flanges and heat slugs. Natural diamond has a thermal conductivity of about 2200 W / m·K, while Cu has a thermal conductivity of about 398 W / m·K and CuMo has a thermal conductivity of about 220 W / m·K. Concentrated single crystal synthetic diamond has been shown to have an even higher thermal conductivity than natural diamond, and the flange 20 can incorporate synthetic diamond particles. The metal 82 provides electrical conductivity to the flange 20, which can be relied upon as a terminal for the package 10 as described herein.

[0041] The flange 20 also exhibits a CTE that is more suitable for packaging certain devices than other materials. For example, Cu has a CTE of about 17.6 ppm / °C, which is a mismatch compared to many semiconductor substrates and materials, such as GaN or SiC, that can be used to manufacture high-power semiconductor devices. SiC has a CTE closer to 3, 4 ppm / °C, and it can be difficult to securely fasten a SiC die to a Cu flange, especially during temperature changes. Flanges made of CuMo, CuW, and other metals have a CTE closer to the SiC substrate, but have a lower thermal conductivity, typically less than 250 W / m·K. The CTE of the flange 20 according to embodiments can be in the range of 6-9 ppm / °C, which matches the SiC substrate more closely while at the same time having a higher TC than Cu. The flange 20 can exhibit a TC of 400, 500, 600, 700, 800, 900, 1000 W / m·K or more, providing a thermal advantage depending on the amount of diamond in the flange 20, the metal in the flange 20, and other factors described below.

[0042] FIG. 6 illustrates an exemplary process flow for the assembly of the semiconductor device package 10 shown in FIG. 1A according to exemplary embodiments described herein. The steps and arrangement of steps illustrated in FIG. 6 are provided as an example. In other embodiments, the order of steps may differ from that shown. For example, the order of performance of two or more steps may be scrambled or changed relative to the order shown. Also, in some cases, two or more steps may be performed simultaneously or partially simultaneously. Furthermore, in some cases, one or more of the steps illustrated in FIG. 6 may be skipped or omitted. Additionally, the process is not limited to the production of packages of any particular size, shape, or style.

[0043] At reference numeral 90, the process includes forming or preparing, and in some cases preparing, a flange incorporating a core material as described herein. For example, the flange 20 or 20A can be sourced from a manufacturer or manufactured separately. Also, the flange 20 or 20A can in some cases be modified or prepared even when provided by a supplier. For example, the peripheral edge 21A (see FIG. 1B) of the flange 20 can in some cases be roughened using laser etching, mechanical abrasion (e.g., sandblasting or abrasion with or without a mask), chemical etching, or other techniques. In other cases, the peripheral edge 21A can be prepared by selective plating to add roughness. Preparing the peripheral edge 21A in this manner can help strengthen the bond between the bottom surface of the frame 30 and the peripheral edge 21A of the flange 20 in a later process step.

[0044] At reference numeral 92, the process includes attaching one or more semiconductor dies to the flange. For example, the one or more semiconductor dies may be secured to the top surface 21 of the flange 20 using thermal epoxy, solder, solder preform, sintered silver die attach, or other suitable means, as described above with reference to FIG.

[0045] At reference numeral 94, the process includes attaching or adhering the frame to the flange. For example, the bottom surface of the frame 30 may be secured to the top surface 21 of the flange 20 using an adhesive, such as an epoxy or other plastic adhesive, using solder, using a mechanical interconnect or interference fit, using fasteners, or using a combination thereof. The bottom surface of the frame 30 may cover the peripheral edge 21 a of the top surface 21 of the flange 20.

[0046] At 96, the process includes bonding the device mounted to the flange at 92 to the conductive leads of the flange mounted at 94. By way of example, and referring again to Figure 3, the semiconductor die may be electrically coupled to the conductive leads 31-34 of the frame 30, such as conductive portions 33A and 34A of the conductive leads 33 and 34, using wire bonding or other means.

[0047] At reference numeral 98, the process includes adhering the cover to the frame. For example, the bottom surface of the cover 40 can be secured to the top surface of the frame 30 using an adhesive, such as an epoxy or other plastic adhesive, a plastic welding, heating, or melting process, using solder, using a mechanical interconnect or interference fit, using fasteners, or using a combination thereof.

[0048] Referring to another example, FIG. 7 illustrates a perspective view of another semiconductor device package 100 according to embodiments described herein. Package 100 is shown as a representative example. Package 100 is not drawn to scale, and other packages consistent with the concepts described herein may vary in shape and / or size as compared to the illustrated one. Package 100 includes a flange or slug 120, a frame 130 molded around a periphery of flange 120 and forming an air cavity within package 100, and a cover 140. Package 100 also includes conductive leads 131 and 132, each of which extends from outside frame 130 through at least a portion of frame 130 and is partially exposed within the air cavity within package 100. Packages similar to package 100, but without an air cavity, are also within the scope of the embodiments described below.

[0049] The frame 130 may be formed by molding a plastic or similar material, such as a polymer or polymer blend, with or without glass, carbon, or other reinforcements, among other materials. In the example shown in FIG. 7, the frame 130 is molded to provide an air cavity within the package 100, but the frame 130 may also be molded without an air cavity. In that case, the cover 140 is not necessary and may be omitted. In another example, the frame 130 may be formed of a ceramic material. In that case, the frame 130 may be formed of a ceramic material and the cover 140 may be formed as a ceramic, metal, or glass lid. The cover 140 may be secured over the air cavity within the frame 130 using any suitable method to create an airtight (or quasi-airtight) seal.

[0050] Conductive leads 131 and 132 may be cut from a larger leadframe assembly after construction of package 100. Construction of package 100 using a leadframe assembly is described in more detail below. Conductive leads 131 and 132 may be formed from Cu, Al, Sn, Ag, Au, Zn, other metals, or any composition thereof, and may be plated with Ag, Au, Ni, Pd, or other metals using full plating, spot plating, or other techniques.

[0051] Similar to package 10, multiple semiconductor devices formed on a semiconductor die can be secured within package 100. The semiconductor die can be secured within package 100 either before or after frame 130 is formed around flange or slug 120. The semiconductor die can be secured to top surface 121 of flange 120 using thermal epoxy, solder, solder preform, sintered silver die attach, or other suitable means. The semiconductor die within package 100 can be electrically coupled to exposed portions 131A and 132A of conductive leads 131 and 132 within package 100 using wire bonding or other means. Cover 140 can then be placed and secured within package 100 on raised platform 133 so as to enclose the air cavity.

[0052] Similar to flange 20, flange 120 includes a core of diamond particles dispersed in a metal, a plating layer forming a top surface of the flange, and a plating layer forming a bottom surface of flange 120. Flange 120 may be formed as described above with reference to Figure 5 to provide a high TC and low CTE.

[0053] FIG. 8 illustrates a cross-sectional view of the package 100 designated BB in FIG. 7. As illustrated, the flange 120 includes a top surface 121, a bottom surface 122, and an interconnecting end surface 123. The interconnecting end surface 123 includes a lip, teeth, or other mechanical interference fit feature that extends around the outer periphery of the flange 120 relative to its bottom periphery. Because the frame 130 surrounds the lip or teeth of the interconnecting end surface 123, the flange 120 cannot be easily pulled out from the frame 130 or the bottom of the package 100. The interconnecting end surface 123 may be added to the flange 120 after the flange 120 is provided by a manufacturer or supplier, as the case may be. The interconnecting end surface 123 may be formed using any suitable material removal technique.

[0054] FIG. 9 illustrates an exemplary leadframe 210 and air cavity packages 220-225 according to embodiments described herein. Each of the air cavity packages 220-225 is similar to the package 100 described above. The leadframe 210 may be formed (e.g., cut, sheared, extruded, etched, etc.) from a larger strip or sheet of conductive metal(s), such as Cu, Al, Sn, Ag, Au, Zn, other metals, compositions thereof, and plated with Ag, Au, Ni, Pd, or other metals. As shown in FIG. 9, the leadframe 210 includes conductive leads 212A and 212B for the package 220 and similar conductive leads (not individually referenced) for the other packages 221-225. The leadframe 210 illustrated in FIG. 9 is provided by way of example, and different types of larger or smaller leadframes may be relied upon.

[0055] Using the leadframe 210 as a starting point for the manufacture of the packages 220-225 provides advantages including higher assembly throughput, lower cost, greater precision, and the ability to use a manufacturer's and supplier's existing toolsets and equipment. For example, the leadframe 210 can be used to grip, hold, and move a relatively large number of packages without having to individually reposition them. Furthermore, once the leadframe 210 is formed with an appropriate level of precision, the relative spacing of each package 220-225 once formed is known. Thus, electrical components can be easily placed and interconnected within each package 220-225 by automated machinery without the need to individually move and reposition the air cavity packages 220-225.

[0056] During manufacture, the lead frame 210 can be placed in the correct relative position with the flanges 230-235. Each of the flanges 230-235 can include a composite core material and a plating layer as described above with reference to FIG. 5. The lead frame 210 can be positioned relative to the flanges 230-235 and, in some cases, secured to the flanges 230-235. A mold can be placed around the lead frame 210 and the flanges 230-235 and plastic can be injected into the mold to form the frame 240-245. In other cases, the lead frame 210 can be placed in a mold with the flanges 230-235 and plastic can be injected into the mold to form the frame 240-245. A plurality of semiconductor devices formed on a semiconductor die can be secured to the flanges 230-235 with a mold either before or after the frame 240-245 is formed around the flanges 230-235.

[0057] The packages 220-225 may remain attached to the leadframe 210 during subsequent assembly steps. After assembly is complete, the individual packages 220-225 may be separated from the leadframe 210 by cutting or shearing the leadframe 210 at locations that separate the conductive leads 212A and 212B (and other conductive leads) of each package 220-225.

[0058] FIG. 10 illustrates a portion of an exemplary leadframe 310 with flange 320 disposed thereon to form a package. Also illustrated in FIG. 10 is a bounding box 330. Bounding box 330 is representative of the size of the plastic frame or body of the package that will be formed around leadframe 310 and flange 320 illustrated in FIG. 10. Consistent with the above discussion, leadframe 310 may be formed (e.g., cut, sheared, extruded, etched, etc.) from a larger strip or sheet of conductive metal(s). Among other features, leadframe 310 includes conductive leads 312A and 312B, downset facets 321A and 321B, and leadframe structural supports 331 and 332 (notably not referenced individually in FIG. 10). Portions of conductive leads 312A and 312B that are exposed within the air cavity of the air cavity package are shown hatched in FIG. 10. Leadframe 310 is presented as an example in FIG. 10, and other leadframes may be relied upon. For example, other lead frames with three or more conductive leads per individual package can be used, including lead frames with four, six, eight or more conductive leads per package.

[0059] Downset facets 321A and 321B can be used to secure flange 320 to leadframe 310 prior to placing a mold around them to inject the plastic frame or body of the package. In one example, metal rivets, pins, or bolts can be inserted through downset facets 321A and 321B to secure flange 320 to leadframe 310. However, other fastening means can be used including solder, brazing, adhesives, and other bonds.

[0060] Once secured together, the semiconductor die may be secured to the flange 320 and wire bonded to the conductive leads 312A and 312B as described below before a plastic frame is molded around the flange and die. In a later process step, a mold may be placed around the lead frame 310 and flange 320. The mold may be formed to form a solid plastic package around the flange 320 and semiconductor die, and plastic may be injected into the mold to form a continuously molded plastic frame or package body around the flange 320 and semiconductor die, up to about the size of the bounding box 330. The package thus formed may then remain attached to the lead frame 310 during the remainder of the assembly process. Exemplary process steps for the assembly or manufacture of a lead frame packaged device according to this example are described in more detail below with reference to FIG.

[0061] Alternatively, a mold can be placed around the leadframe 310 and flange 320 after the downset facets 321A and 321B are secured to the flange 320. The mold can be shaped to form a plastic package around the flange 320, with an air cavity formed above the flange 320. Plastic can be injected into the mold to form a plastic frame or body of the package around the flange 230 with the air cavity formed above the flange 320. The package thus formed can remain attached to the leadframe 310 during the remaining assembly process steps, such as securing a semiconductor die to the flange 320 within the air cavity and wire bonding the die to the conductive leads 312A and 312B. Exemplary assembly or manufacturing process steps for a leadframe packaged device according to this example are described in more detail below with reference to FIG. 13.

[0062] 11 shows a cross-sectional view of leadframe 310 disposed with flange 320, designated CC in FIG. Downset facets 321A and 321B of leadframe 310 are disposed on top of flange 320. In some cases, downset facets 321A and 321B of leadframe 310 may be secured to the top of flange 320. Downset facets 321A and 321B may be secured to flange 320 using solder, solder preforms, fasteners, or other suitable means. The fasteners may include metal rivets, pins, or bolts that are inserted through downset facets 321A and 321B into flange 320.

[0063] 11, there is shown a distance "D" between the top surface of flange 320 and the top surface of lead frame 310. Distance "D" defines the distance between the top surface of flange 320 and the exposed surfaces of the conductive leads in the formed package.

[0064] FIG. 12 illustrates an exemplary process for manufacturing and assembling a leadframe package according to embodiments described herein. The steps and arrangement of steps illustrated in FIG. 12 are provided as an example. In other embodiments, the order of the steps may differ from that shown. For example, the order of two or more steps may be altered or changed relative to the order shown. Also, in some cases, two or more steps may be performed simultaneously or partially simultaneously. Furthermore, in some cases, one or more steps may be skipped or omitted. Additionally, the process is not limited to producing packages of any particular size, shape, or style.

[0065] At reference numeral 402, the process includes forming a leadframe. For example, a leadframe similar to leadframe 210 shown in FIG. 9 or a portion of leadframe 310 shown in FIG. 10 may be formed (e.g., cut, sheared, extruded, etched, etc.) from a larger strip or sheet of conductive metal. The leadframe may include any suitable number of conductive leads, downset facets, leadframe structural supports, etc.

[0066] At reference numeral 402, the process may also include forming or providing a flange incorporating a core material as described herein. A flange or slug similar to flanges 120, 230-235, or 320 may be provided by a manufacturer or fabricated separately. The flange may include an interconnecting end surface 123, and certain surfaces of the flange may be roughened using laser etching, mechanical abrasion, chemical etching, or other techniques. For example, the peripheral edge of the flange may be roughened in some cases using laser etching, mechanical abrasion (e.g., sandblasting or abrasion with or without a mask), chemical etching, selective plating, or other techniques. Preparation of the flange helps to enhance bonding and connection with other materials in subsequent process steps, as described herein.

[0067] At 404, the process includes placing or aligning the flange to the leadframe. As an example of such placement, FIG. 10 shows flange 320 positioned in a predetermined location relative to leadframe 310. In practice, multiple flanges can be positioned at corresponding locations along the leadframe at 404, similar to that shown in FIG.

[0068] At 406, the process includes a step of fastening or fastening the flange and the leadframe together. Referring to FIG. 11 as an example, the downset facets 321A and 321B of the leadframe 310 are disposed on top of the flange 320. In some cases, the downset facets 321A and 321B of the leadframe 310 can be fastened to the top of the flange 320. The downset facets 321A and 321B can be fastened to the flange 320 using solder, solder preforms, brazing, fasteners, or other suitable means. The fasteners can include metal rivets, pins, or bolts that are inserted through the downset facets 321A and 321B into the flange 320. In some cases, the fastening at 406 can be omitted or skipped because in some cases, it is sufficient to align the flange with the leadframe without fastening them together. In some cases, the leadframe and package may be moved to other machines for picking the semiconductor die and other electrical components and placing the die and components on the flanges, if desired.

[0069] At 408, the process includes placing a semiconductor die and other electrical components on the flange and securing the semiconductor die and electrical components to the flange. This step can use an automated pick and place tool. The process also includes wire bonding the die and components to exposed conductive leads within the air cavity of the package. This step can use an automated wire bonding machine. These steps can be performed or implemented as described above with reference to FIG. 3.

[0070] At 410, the process includes positioning the lead frame and flange (with the semiconductor die and electrical components secured to the flange) in a mold to form a package frame. At 412, the process includes forming a plurality of plastic frames or bodies around the flange. As an example, bounding box 330 in FIG. 10 represents the size of the package plastic frame or body formed around the portion of lead frame 310 shown. The package frame can be formed by injecting plastic into a mold to enclose the flange, die and components, and lead frame. The frame can be molded from any suitable plastic or polymer, such as liquid crystal polymer (LCP) or polymer blends, with or without glass, carbon, or other reinforcements, among other materials.

[0071] At 414, the process includes separating the packages from the leadframe. The packages can be separated by cutting or shearing the leadframe structural supports to separate the conductive leads of each package from the larger leadframe assembly.

[0072] FIG. 13 illustrates another exemplary process for manufacturing and assembling a leadframe package according to embodiments described herein. In comparison to the process described above with reference to FIG. 12, a package formed using the process illustrated in FIG. 13 includes an air cavity, and the semiconductor die and other electrical components are secured in the air cavity of the package after the plastic frame of the package is molded. The steps and arrangement of steps illustrated in FIG. 13 are provided as an example. In other embodiments, the order of the steps can differ from the order shown. For example, the order of two or more steps can be shifted or changed relative to the order shown. Also, in some cases, two or more steps can be performed simultaneously or partially simultaneously. Furthermore, in some cases, one or more steps can be skipped or omitted. Furthermore, the process is not limited to the production of packages of any particular size, shape, or style.

[0073] At reference numeral 502, the process includes forming a leadframe. For example, a leadframe similar to leadframe 210 shown in FIG. 9 or a portion of leadframe 310 shown in FIG. 10 may be formed (e.g., cut, sheared, extruded, etched, etc.) from a larger strip or sheet of conductive metal. The leadframe may include any suitable number of conductive leads, downset facets, leadframe structural supports, etc.

[0074] At 502, the process may also include forming or preparing, in some cases, a flange incorporating a core material as described herein. Flanges or slugs similar to flanges 120, 230-235, or 320 may be provided by a manufacturer or manufactured separately. Also, flanges may be modified or prepared even when provided by a supplier. For example, flanges may be modified to include interconnecting end faces 123, and certain surfaces may be roughened using laser etching, mechanical abrasion, chemical etching, or other techniques. Preparing the flanges helps to enhance bonding and connections with other materials later in the process.

[0075] At 504, the process includes placing or aligning the flange to the leadframe. As an example of such placement, FIG. 10 shows flange 320 placed in a predetermined position relative to leadframe 310. In practice, multiple flanges can be placed at corresponding positions along the leadframe at 504, similar to that shown in FIG.

[0076] At 506, the process includes fastening or fastening the flange and the leadframe together. Referring to FIG. 11 as an example, the downset facets 321A and 321B of the leadframe 310 are disposed on top of the flange 320. In some cases, the downset facets 321A and 321B of the leadframe 310 can be fastened to the top of the flange 320. The downset facets 321A and 321B can be fastened to the flange 320 using solder, solder preforms, brazing, fasteners, or other suitable means. The fasteners can include metal rivets, pins, or bolts that are inserted through the downset facets 321A and 321B into the flange 320. In some cases, the fastening at 406 can be omitted or skipped because in some cases, it is sufficient to align the flange with the leadframe without fastening them together.

[0077] At 508, the process includes positioning the lead frame and flange in a mold to form a frame of the package. The mold can be shaped to provide an air cavity above or on the flange of the resulting package. At 510, the process includes forming a plurality of plastic frames or bodies around the flange with air cavities. As an example, bounding box 330 in FIG. 10 represents the size of the plastic frame or body of the package formed around a portion of lead frame 310. Once the frame or body is formed, the shape of the mold creates air cavities in the frame and above the flange, as described herein. The frame of the package can be formed by injection of plastic into the mold surrounding the flange and lead frame. The frame can be molded from any suitable plastic or polymer, such as liquid crystal polymer (LCP) or polymer blends, with or without glass, carbon, or other reinforcements, among other materials.

[0078] At 512, the process includes using a supporting lead frame to reposition the package formed at 510. That is, once the air cavity package at 510 is formed or molded around the lead frame and flange, the surrounding lead frame can be used to move the package without having to individually reposition it. The lead frame and package can be moved to a machine for picking the semiconductor die and other electrical components and placing the die and components into the air cavity and onto the flange.

[0079] At 514, the process includes placing one or more semiconductor dies and other electrical components onto the air cavity and the flange and securing the dies and components to the flange. An automated pick and place tool may be used for this process. The process also includes wire bonding the dies and components to the exposed conductive leads within the air cavity of the package. An automated wire bonding machine may be used for this step. These steps may be performed or implemented as described above with reference to FIG. 3.

[0080] At 516, the process includes enclosing the air cavity of the package. For example, a cover can be secured over the air cavity of the package as described herein. At 518, the process includes separating the packages from the leadframe. The packages can be separated by cutting or shearing away the leadframe structural supports to separate the conductive leads of each package from the larger leadframe assembly. In other cases, packages can be removed (e.g., cut or sheared away) from their surrounding leadframe before electrical components are secured and encapsulated within those packages, but the leadframe provides the ability to easily move multiple packages at once.

[0081] Power transistors formed on a semiconductor die can be packaged using the embodiments described herein. Among other types, the transistors described herein can be formed as high electron mobility transistors (HEMTs), pseudo-electron mobility transistors (pHEMTs), metamorphic high electron mobility transistors (mHEMTs), laterally diffused metal oxide semiconductor transistors (LDMOSs), metal insulator semiconductor field effect transistors (MISFETs or MISHFETs), and metal oxide semiconductor field effect transistors (MOSFETs).

[0082] The transistors described herein can be formed using a number of different semiconductor materials and semiconductor fabrication processes. Exemplary semiconductor materials include Group IV element semiconductor materials, including silicon (Si) and germanium (Ge), and compounds thereof, and Group III element semiconductor materials, including Al, gallium (Ga), indium (In), and compounds thereof. Semiconductor transistor amplifiers can be constructed, in certain cases, from III-V direct bandgap semiconductor technology, because the higher bandgaps and electron mobilities offered by these devices can result in higher electron velocities and breakdown voltages, among other advantages. Thus, in some examples, the concepts can be applied to III-V direct bandgap active semiconductor devices, such as III-nitride material devices (aluminum (Al)-, gallium (Ga)-, indium (In)-, and their alloy (AlGaIn)-based nitrides), GaAs, InP, InGaP, AlGaAs, and the like. However, the principles and concepts can also be applied to transistors and other active elements formed from other semiconductor materials.

[0083] As used herein, the term "III-nitride material" or "gallium nitride material" refers to any group III element-nitride compound. Non-limiting examples of group III-nitride materials include boron nitride (BN), aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), and thallium nitride (TIN), as well as aluminum gallium nitride (AlN). x Ga( 1-x) N), indium gallium nitride (In y Ga (1-y) N), Aluminum Indium Gallium Nitride (Al x In y Ga (1-x-y) N), gallium nitride arsenide phosphide (GaAs a P b N (1-a-b) ), Aluminum Indium Gallium Nitride Phosphide (Al x In y Ga (1-x-y) Asa P b N (1-a-b) and alloys containing group III and group V elements such as gallium nitride, gallium arsenic, gallium nitride (AlN), and gallium nitride alloys such as gallium nitride (AlN), ... (VN). Generally, when arsenic and / or phosphorus are present, their concentrations are low (e.g., less than 5 wt%). The term "gallium

[0084] According to certain embodiments, the substrate of the semiconductor device described herein may include silicon (Si) (i.e., a substrate that includes some form of Si). Examples of Si-containing substrates that may be used in various embodiments include, but are not limited to, SiC substrates, bulk Si wafers, silicon-on-insulator, silicon-on-sapphire (SOS) substrates, and separation by implantation of oxygen (SIMOX) substrates. Suitable silicon substrates also include composite substrates that include a Si wafer bonded to another material, such as diamond, AlN, SiC, or other polycrystalline materials. Silicon substrates with different crystal orientations may be used, although single crystal silicon substrates are preferred in certain, but not all, embodiments. In some embodiments, a silicon (111) substrate is used. III-nitride or GaN transistors may be III-nitride heterostructure FETs (III-N HFETs), metal-insulator-semiconductor FETs (MISFETs or MISHFETs), such as metal-oxide-semiconductor FETs (MOSFETs). Alternatively, when implemented as HFETs, III-nitride transistors may be HEMTs configured to generate a 2DEG.

[0085] The features, structures, and characteristics described above may be combined in any suitable manner in one or more embodiments, and features described in various embodiments are often interchangeable. Relative terms such as "above," "below," "upper," "lower," "top," "bottom," "right," "left," and the like may be used to describe the relative spatial relationships of certain structural features, but these terms are used merely for convenience as directions in the examples. When a structure or feature is described as being "on" (or formed on) another structure or feature, the structure may be disposed on the other structure, regardless of whether the other structure or feature is interposed therebetween. When two components are described as being "coupled" to one another, the components may be electrically coupled to one another, regardless of whether the other component is electrically coupled to intervene therebetween. When two components are described as being "directly coupled" to one another, the components may be electrically coupled to one another without the other component being electrically coupled therebetween.

[0086] The terms "a," "an," "the," "said," and the like are used to indicate the presence of one or more elements and components. The terms "comprise," "include," "have," "contain," and variations thereof are used open-ended and may include or encompass additional elements, components, etc. in addition to the listed elements, components, etc., unless otherwise specified. The terms "first," "second," etc. are used as designations only and not as limitations on the number of objects.

[0087] Although the embodiments are described in detail herein, the description is illustrative. The features of the embodiments described herein are representative, and alternative embodiments may add or omit certain features and elements. Furthermore, modifications to aspects of the embodiments described herein may be made by those skilled in the art without departing from the spirit and scope of the invention as defined in the following claims, which scope is to be interpreted to include modifications and equivalent structures.

Claims

1. a flange including a top surface; a frame secured to the flange, the frame defining an air cavity bounded in part by the top surface of the flange and including a platform height within the air cavity; at least one conductive lead extending from an exterior of the frame through at least a portion of the frame and exposed within the air cavity; A semiconductor device package comprising: The flange comprises a composite core material, the composite core material comprising diamond particles dispersed in a metal.

2. The semiconductor device package of claim 1 , wherein said flange further comprises at least one plated metal layer on said composite core material.

3. 3. The semiconductor device package of claim 2, wherein the at least one plated metal layer comprises at least one layer of nickel, gold, silver, palladium, and copper.

4. 4. The semiconductor device package of claim 3, wherein the top surface of the flange comprises a layer of at least one of nickel, gold, silver, palladium, and copper.

5. The semiconductor device package of claim 1 , wherein the metal in the composite core material comprises silver.

6. The semiconductor device package of claim 1 , wherein the metal in the composite core material comprises copper.

7. 10. The semiconductor device package of claim 1, wherein the flange has a thermal conductivity greater than 400 W / m·K.

8. 2. The semiconductor device package of claim 1, wherein the flange has a coefficient of thermal expansion in the range of 5-10 ppm / .degree.

9. The semiconductor device package of claim 1 , further comprising a cover mounted and secured onto the frame.

10. The semiconductor device package of claim 1 further comprising a semiconductor device die comprising gallium nitride material disposed on said top surface of said flange.

11. the semiconductor device die comprises a transistor amplifier; the source of the transistor amplifier is electrically coupled to the flange; The semiconductor device package of claim 10 , wherein the flange comprises a conductive lead for the source of the transistor amplifier.

12. The semiconductor device package of claim 1 , wherein the frame is secured to the top surface of the flange using a plastic adhesive.

13. The semiconductor device package of claim 1 , wherein the frame is molded around a side of the flange.

14. The semiconductor device package of claim 1 further comprising a leadframe downset feature on said flange.

15. The semiconductor device package of claim 1 , wherein at least a portion of a periphery of the top surface of the flange is roughened for adhesion to the frame.

16. a flange including diamond particles; A frame fixed to the flange; at least one conductive lead extending outside the frame; A semiconductor device package comprising:

17. 17. The semiconductor device package of claim 16, wherein the flange comprises the diamond particles dispersed in silver.

18. The semiconductor device package of claim 16 , wherein the flange further comprises at least one plated metal layer.

19. 20. The semiconductor device package of claim 17, wherein the at least one plated metal layer comprises at least one layer of nickel, gold, silver, palladium, and copper.

20. the flange has a thermal conductivity greater than 400 W / m K; 17. The semiconductor device package of claim 16, wherein the flange has a coefficient of thermal expansion in the range of 5-10 ppm / .degree. C.

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