Semiconductor device package with improved thermomechanical reliability

Abstract

The present disclosure relates to a semiconductor device package having a thin form factor, as well as a method and system for forming the same. Embodiments of the present disclosure include a method and apparatus for forming a semiconductor device package that includes a frame coated with a layer of binder on which subsequent layers are formed. By using a binder between the frame and the subsequently formed layers, the stress induced by any of the subsequently formed insulating layers and / or RDLs is relaxed, and by improving the bond between the layer and the relatively smooth surface of the frame, the thermo-mechanical reliability of the package frame is enhanced.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to semiconductor device packages and methods of forming the same. More specifically, the embodiments described herein relate to the structure of semiconductor device packages with a thin form factor and methods of forming the same.

Background Art

[0002]

[0002] Due to continuous trends in the development of semiconductor device technology, the size of semiconductor components has been reduced and the circuit density has increased. In accordance with the requirement to continue scaling semiconductor devices while improving performance capabilities, these components and circuits are integrated into complex 3D semiconductor device packages that facilitate a significant reduction in the footprint of the device and enable shortening and speeding up of connections between components. The package can be, for example, integrated with a semiconductor chip and a plurality of other electronic components and mounted on a circuit board of an electronic device.

[0003]

[0003] Conventionally, semiconductor device packages have been fabricated on organic package substrates due to relatively low package manufacturing costs associated with organic composite materials and the ease of forming features and connections therein. However, as the circuit density increases and semiconductor devices are further miniaturized, the use of organic package substrates becomes impractical due to limitations in the material structure resolution for maintaining device scaling and related performance requirements.

[0004]

[0004] More recently, 2.5D and / or 3D packages using silicon-based substrates have been fabricated to complement some of the limitations associated with organic package substrates. The use of silicon-based materials for such package applications is driven by their excellent thermal properties, low coefficient of thermal expansion (CTE), smooth surface, and availability in large wafer and panel formats.

[0005]

[0005] However, silicon-based material substrates also have drawbacks. For example, it is difficult and costly to form features in silicon-based substrates such as silicon through vias (TSVs). In particular, high aspect ratio silicon via etching, chemical mechanical planarization, and semiconductor back-end-of-line (BEOL) wiring are costly. Further, silicon-based substrates often crack and / or develop other defects due to stress induced when singulated from larger panels or wafers and / or by subsequently formed insulating layers and / or redistribution layers (RDLs). Further, since the adhesion between these layers is weak, they are often peeled off from the silicon-based substrate or delaminated.

[0006]

[0006] Accordingly, what is needed in the art is an improved semiconductor device package structure and method of forming the same for high-end packaging applications.

Summary of the Invention

[0007]

[0007] Embodiments of the present disclosure relate to a structure for a semiconductor device package with a thin form factor and a method of forming the same.

[0008]

[0008] In certain embodiments, a package assembly is provided, the package assembly including a frame having a first surface and an opposite second surface, the frame further including a frame material including a first material containing silicon, at least one cavity in which a semiconductor die is disposed, a via including a via surface defining an opening extending through the frame from the first surface to the second surface, a bonding layer formed on the frame, the bonding layer including a silane coupling agent and contacting at least the first surface and the second surface, an insulating layer disposed on the bonding layer on the first surface and the second surface of the frame, the insulating layer contacting at least a portion of each side surface of the semiconductor die, and an electrical wiring portion disposed in the via, an insulating layer and a bonding layer being disposed between the via surface and the electrical wiring portion.

[0009]

[0009] In certain embodiments, a package assembly is provided, the package assembly comprising an embedded die assembly including a frame comprising a first material including silicon, a bonding layer disposed on the frame and including a silane coupling agent, one or more semiconductor dies disposed within the frame and having an integrated circuit formed thereon, and an insulating layer formed on the bonding layer and including an epoxy resin material having ceramic particles disposed therein; and one or more metal wiring portions disposed within a portion of the embedded die assembly.

[0010]

[0010] In certain embodiments, a package assembly is provided, the package assembly comprising an embedded die assembly including a frame comprising a first material including silicon, a bonding layer formed on the frame and including a silane coupling agent, one or more semiconductor dies disposed within the frame, a first insulating layer formed on the frame and including an epoxy resin material having ceramic particles, and one or more electrical wiring portions disposed through the frame or the first insulating layer; and a redistribution layer formed on the embedded die assembly, the redistribution layer including a second insulating layer formed on the first insulating layer and one or more electrical redistribution connection portions disposed through the second insulating layer.

[0011]

[0011] To better understand the features of the present disclosure described above, the present disclosure summarized above will be described more specifically with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only exemplary embodiments and should not be regarded as limiting the scope thereof, and other equally effective embodiments may be acceptable.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figures 3A - 3D

Figures 4A - 4F

Figures 5A - 5F

Figures 6A - 6E

Figures 7A - 7D

Figure 8

Figure 9

Figures 10A - 10D

Figures 10E - 10H

Figures 10I - 10K

Figure 11

Figures 12A - 12D

Figures 12E - 12G

Figure 13

Figures 14A - 14D

Figures 14E - 14H

Figure 15

Figures 16A - 16C

Figures 16D - 16E

Figures 16F - 16H

Figures 16I - 16J

Figures 16K - 16L

Figure 17

Figure 18A

Figure 18B

DETAILED DESCRIPTION OF THE INVENTION

[0013]

[0030] For ease of understanding, wherever possible, the same reference numbers are used to indicate the same elements common to the drawings. It is contemplated that the elements and features of one embodiment may be beneficially incorporated into other embodiments without further elaboration.

[0014]

[0031] The methods and apparatuses disclosed herein include novel thin form factor semiconductor device packages that are intended to further improve more recent package structures that use a silicon-based substrate or a similar substrate as a frame, replacing more conventional package structures that use an organic substrate as a frame, which are limited by material structural resolution. Current package frames may have low mechanical reliability because cracks and / or other defects may occur due to stress induced by subsequently formed insulating layers and / or redistribution layers (RDLs). Further, during high temperature processing, layers directly laminated on a silicon-based substrate may peel or delaminate therefrom because the adhesion between silicon and the dielectric material is weak. The methods and apparatuses disclosed herein provide semiconductor device packages that overcome many of the drawbacks associated with the conventional package architectures described above by using a frame coated with a layer of binder such as a silane coupling agent. By using a binder between the frame and subsequently formed layers, the stress induced by all subsequently formed insulating layers and / or RDLs is alleviated, and the thermal mechanical reliability of the package frame is enhanced by improving the bond between the layers and the relatively smooth surface of the frame.

[0015]

[0032] As will be described in more detail below, FIG. 1 is a flow diagram showing a representative method 100 of forming a thin form factor semiconductor device package having a silane-coated frame. Method 100 has a plurality of steps 110, 120, 130, and 140. Each step will be described in more detail with reference to FIGS. 2-16L. The method may include one or more additional steps that are performed before any of the defined steps, between two of the defined steps, or after all of the defined steps (except where the context excludes that possibility).

[0016]

[0033] Method 100 generally includes, in step 110, which will be described in more detail with reference to FIGS. 2, 3A-3D, 4A-4F, 5A-5F, 6A-6E, 7A-7D, and 8, structuring and preparing a substrate to be used as a package frame. In step 120, which will be described in more detail with reference to FIGS. 9 and 10A-10K and FIGS. 11 and 12A-12G, an embedded die assembly having one or more embedded dies and an insulating layer is formed. In step 130, which will be described in more detail with reference to FIGS. 13 and 14A-14H, one or more wiring portions are formed within and / or through the embedded die assembly for interconnecting the embedded die-frame set. In step 140, a first redistribution layer is formed on the embedded die assembly to relocate contact points of the wiring portions to desired lateral positions on the surface of the embedded die assembly. In some embodiments, one or more additional redistribution layers can be formed in addition to the first redistribution layer before individual packages are singulated from the embedded die assembly, which will be described in more detail with reference to FIGS. 15 and 16A-16L.

[0017]

[0034] FIG. 2 is a flowchart showing a representative method 200 for structuring and preparing a substrate to be used as a package frame. FIGS. 3A-3D are cross-sectional views schematically showing the substrate 302 at different stages of the method 200 shown in FIG. 2. Thus, FIGS. 2 and 3A-3D are described together herein for clarity.

[0018]

[0035] Method 200 begins at step 210 and corresponding FIG. 3A. Substrate 302 is formed of any suitable frame material including, but not limited to, III-V compound semiconductor materials, silicon, crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped polysilicon, silicon nitride, quartz, borosilicate glass, glass, sapphire, alumina, and ceramic. In certain embodiments, substrate 302 is a single crystal p-type or n-type silicon substrate. In certain embodiments, substrate 302 is a polycrystalline p-type or n-type silicon substrate. In another embodiment, substrate 302 is a p-type or n-type silicon solar cell substrate. Substrate 302 may further have a polygonal or circular shape. For example, substrate 302 may include a substantially square silicon substrate having a lateral dimension of from about 120 mm to about 180 mm with or without chamfered edges. In another example, substrate 302 may include a circular silicon-containing wafer having a diameter of from about 20 mm to about 700 mm, such as from about 100 mm to about 500 mm, such as about 300 mm.

[0019]

[0036] Unless otherwise specified, the embodiments and examples described herein are implemented on substrates having a thickness of from about 50 μm to about 1000 μm, such as from about 90 μm to about 780 μm. For example, substrate 302 has a thickness of from about 100 μm to about 300 μm, such as from about 110 μm to about 200 μm. In another example, substrate 302 has a thickness of from about 60 μm to about 160 μm, such as from about 80 μm to about 120 μm.

[0020]

[0037] Before operation 210, the substrate 302 can be sliced and separated from the bulk material by a wire saw (wire sawing), scribing and breaking, mechanical abrasive sawing, or laser cutting. Slicing typically causes mechanical defects or deformations such as scratches, microcracks, chipping, and other mechanical defects on the substrate surface from which it is formed. Therefore, the substrate 302 is exposed to a first damage removal process in operation 210 to smooth and planarize its surface and remove any mechanical defects in preparation for subsequent structuring and packaging operations. In some embodiments, the substrate 302 can be further thinned by adjusting the process parameters of the first damage removal process. For example, the thickness of the substrate 302 can be decreased by increasing the exposure to the first damage removal process.

[0021]

[0038] The damage removal process in operation 210 includes exposing the substrate 302 to a substrate polishing process and / or an etching process, and then to a rinse and dry process. In some embodiments, operation 210 includes a chemical mechanical polishing (CMP) process. In certain embodiments, the etching process is a wet etching process that includes a buffered etching process that is selective for the removal of desired materials (e.g., contaminants and other undesirable compounds). In other embodiments, the etching process is a wet etching process using an isotropic aqueous etching process. Any suitable wet etching solution or combination of wet etching solutions can be used for the wet etching process. In certain embodiments, the substrate 302 is immersed in an aqueous HF etching solution for etching. In another embodiment, the substrate 302 is immersed in an aqueous KOH etching solution for etching.

[0022]

[0039] In some embodiments, the etching solution is heated to a temperature of from about 30°C to about 100°C, for example from about 40°C to about 90°C, during the etching process. For example, the etching solution is heated to a temperature of about 70°C. In still other embodiments, the etching process in step 210 is a dry etching process. Examples of dry etching processes include plasma-based dry etching processes. The thickness of the substrate 302 is adjusted by controlling the exposure time of the substrate 302 to the etching liquid (e.g., the etching solution) used during the etching process. For example, the final thickness of the substrate 302 decreases as the exposure to the etching liquid increases. Alternatively, the final thickness of the substrate 302 can increase as the exposure to the etching liquid decreases.

[0023]

[0040] In steps 220 and 230, the substrate 302, which is now planarized and substantially defect-free, is patterned therein to have one or more features such as smoothed vias 303 and cavities 305 (one cavity 305 and four vias 303 are shown in the lower cross-section of the substrate 302 in FIG. 3B). The vias 303 are used to form direct contact wiring portions that penetrate the substrate 302, and the cavities 305 are used to receive and enclose (i.e., embed) one or more semiconductor dies therein. FIGS. 4A-4C, FIGS. 5A-5C, FIGS. 6A-6C, and FIGS. 7A-7B are cross-sectional views showing the substrate 302 at different stages of the feature formation and damage or defect removal (e.g., smoothing) processes according to the embodiments described herein. Accordingly, steps 220 and 230 will now be described in more detail with reference to FIGS. 4A-4C, FIGS. 5A-5C, FIGS. 6A-6C, and FIGS. 7A-7B.

[0024]

[0041] Next, refer to FIGS. 4A-4C and FIGS. 5A-5C. In certain embodiments, substrate 302 can be patterned via a micro-blast process. In the above embodiments, when substrate 302 has a thickness of less than about 200 μm, for example, a thickness of about 100 μm, or a thickness of about 50 μm, substrate 302 can first be bonded to an optional carrier plate 406 as shown in FIGS. 4A and 5A. Carrier plate 406 provides mechanical support to substrate 302 during substrate structuring process 200 and prevents breakage of substrate 302. Carrier plate 406 is formed of any suitable chemically and thermally stable rigid material including, but not limited to, glass, ceramic, metal, etc. Carrier plate 406 has a thickness of from about 1 mm to about 10 mm, for example, from about 2 mm to about 5 mm. In certain embodiments, carrier plate 406 has a textured surface. In other embodiments, carrier plate 406 has a polished or smoothed surface.

[0025]

[0042] In certain embodiments, substrate 302 can be bonded to carrier plate 406 via an adhesive layer 408. Adhesive layer 408 is formed of any suitable temporary bonding material including, but not limited to, wax, glue, or similar bonding materials. Adhesive layer 408 is applied onto carrier plate 406 by mechanical rotation, pressing, lamination, spin coating, or doctor blade. In certain embodiments, adhesive layer 408 is a water-soluble or solvent-soluble adhesive layer. In other embodiments, adhesive layer 408 is a UV-release adhesive layer. In still other embodiments, adhesive layer 408 is a heat-release adhesive layer. In the above embodiments, the bonding characteristics of adhesive layer 408 deteriorate when exposed to heat treatment, for example, when adhesive layer 408 is exposed to a temperature above 110°C, for example, above 150°C. Adhesive layer 408 can further include one or more additional film layers (not shown) such as a liner, a base film, a pressure-sensitive film, and other suitable layers.

[0026]

[0043] In some embodiments, after coupling the substrate 302 to the carrier plate 406, as shown in FIGS. 4A and 5A, a resist film is applied to the substrate 302 to form a resist layer 404. In embodiments where the substrate 302 has a thickness greater than about 200 μm, for example, a thickness of about 250 μm, the resist layer 404 is formed on the substrate 302 without first coupling the substrate 302 to the carrier plate 406. During subsequent processing steps, the resist layer 404 is used to transfer a desired pattern to the substrate 302 on which the resist layer 404 is formed. After patterning, the resist layer 404 protects selected regions of the underlying substrate 302 during subsequent structuring steps.

[0027]

[0044] The substrate 302 generally has a substantially flat surface on which the resist layer 404 is formed. In some embodiments shown in FIG. 5A, the resist layer 404 is coupled to the substrate 302 via a resist adhesion layer 409. The resist adhesion layer 409 is formed of any suitable temporary bonding material including, but not limited to, polyvinyl alcohol, a triester with 2-ethyl-2-(hydroxymethyl)-1,3-propanediol, and other water-soluble or solvent-soluble materials. In certain embodiments, the resist adhesion layer 409 is formed of a material different from the adhesion layer 408. In certain embodiments, the resist adhesion layer 409 has a composition substantially similar to the adhesion layer 408. The resist adhesion layer 409 is applied onto the substrate 302 by mechanical rotation, pressing, lamination, spin coating, or doctor blading. In other embodiments, the resist layer 404 is formed of a temporary bonding material such as polyvinyl alcohol, whereby the resist layer 404 can be directly applied and bonded to the surface of the substrate 302. The resist layer 404 may include one or more layers such as, for example, a first resist layer and a second resist layer (not shown).

[0028]

[0045] In certain embodiments, such as the embodiment shown in FIG. 4A, the resist layer 404 is a photosensitive layer (e.g., a photoresist). The resist layer 404 can include a solvent, a photoresist resin, and a photoacid generator. The photoresist resin can be any positive photoresist resin or any negative photoresist resin. Representative photoresist resins include acrylates, novolak resins, poly(methyl methacrylate), and poly(olefin sulfone). Other photoresist resins can also be used. When exposed to electromagnetic radiation, the photoacid generator generates charged species such as acid cations and anions. The photoacid generator may also generate polarized species. The photoacid generator imparts photosensitivity to the resin with respect to electromagnetic radiation. Representative photoacid generators include, for example, sulfonic acid compounds such as sulfonates, sulfonic acid esters, and sulfonyloxy ketones. Other suitable photoacid generators include onium salts such as aryldiazonium salts, halonium salts, aromatic sulfonium salts, and sulfoxonium salts or selenium salts. Other representative photoacid generators include nitrobenzyl esters, s-triazine derivatives, ionic iodonium sulfonates, perfluoroalkane sulfonates, aryl triflates and their derivatives and analogs, pyrogallol derivatives, alkyldisulfones, and the like. Other photoacid generators can also be used. In certain embodiments, such as the embodiment shown in FIG. 5A, the resist layer 404 is a laser-sensitive resist.

[0029]

[0046] After forming the resist layer 404, the substrate 302 on which the resist layer 404 is formed is exposed to electromagnetic radiation to pattern the resist layer 404 as illustrated in FIGS. 4B and 5B. In the embodiment shown by FIG. 4B, the substrate 302 on which the resist layer 404 is formed is exposed to electromagnetic radiation in the ultraviolet (UV) range. A portion of the resist layer 404 is selectively exposed to the UV radiation and a portion of the resist layer 404 is not selectively exposed. When exposed to the UV radiation, the selectively exposed portions of the resist layer 404 are structurally weakened (illustrated by hatching) and the non-selectively exposed portions maintain their structural integrity. In certain embodiments, a mask 412 having a desired pattern is formed on or adjacent to the photosensitive resist layer 404 prior to exposure to the UV radiation. In other embodiments, the mask 412 is a reticle positioned between the resist layer 404 and the UV radiation source. The mask 412 is configured to transfer the desired pattern of the UV radiation to the resist layer 404. The mask 412 is formed of any suitable polymeric material including, but not limited to, PTFE, PVDF, FEP, polyimide, and the like.

[0030]

[0047] In the embodiment shown by FIG. 5B, the substrate 302 on which the laser-sensitive resist layer 404 is formed is exposed to electromagnetic radiation generated by a laser source 307 instead of a UV radiation source. In this way, patterning is achieved by targeted laser ablation without using a mask. The laser source 307 may be any type of laser suitable for patterning the resist layer 404. In some examples, the laser source 307 is a femtosecond green laser. In other examples, the laser source 307 is a femtosecond UV laser. The laser source 307 generates a continuous or pulsed laser beam 310 for patterning the resist layer 404. For example, the laser source 307 can generate a pulsed laser beam 310 having a frequency from 100 kHz to 1200 kHz, such as from about 200 kHz to about 1000 kHz. The laser source 307 is generally configured to form any desired pattern in the resist layer 404. Further, it is also contemplated that the electromagnetic radiation in the process may include an electron beam or an ion beam instead of a laser beam.

[0031]

[0048] In FIG. 4B, the resist layer 404 may be formed of any material that has an appropriate hardness after the resist layer 404 is patterned, for example, after a negative photoresist is exposed to electromagnetic radiation to cause cross-linking of the materials in the resist. Generally, the resist layer 404 needs to have one or more desirable mechanical properties after the resist layer 404 is patterned (e.g., deposited, exposed, and developed). In certain embodiments, the resist layer 404 is formed of a material having a Shore A scale hardness value of 40 to 90, for example 60 to 70, after patterning. For example, the resist layer 404 is formed of a material having a Shore A scale hardness value of about 65 after patterning. In certain embodiments, the resist layer 404 is formed of a material having a tensile strength of about 0.5 MPa to about 10 MPa, for example about 1 MPa to about 8 MPa, after patterning. For example, the resist layer 404 may be formed of a material having a tensile strength of about 7 MPa after patterning. In certain embodiments, the resist layer 404 is formed of a polydimethylsiloxane material. In other embodiments, the resist layer 404 is formed of, for example, a triester with polyvinyl alcohol, 2-ethyl-2-(hydroxymethyl)-1,3-propanediol, etc.

[0032]

[0049] Following the patterning of the resist layer 404, the substrate 302 on which the resist layer 404 is formed is micro-blasted to form a desired pattern on the substrate 302, as shown in FIGS. 4C and 5C. During the micro-blasting process, a stream of powder particles 309 is sent towards the substrate 302 using a high-pressure carrier gas to remove the exposed portions of the substrate 302 and / or the layers formed thereon. The micro-blasting process is performed using any suitable substrate polishing system.

[0033]

[0050] The micro-blast process is determined by the material properties of the powder particles 309, the momentum of the powder particles impinging on the exposed surface of the substrate 302, the material properties of the substrate 302, and, where applicable, the selectively exposed portions of the resist layer 404. To achieve the desired substrate patterning characteristics, adjustments are made to the type and size of the powder particles 309, the size of the applicator nozzle of the polishing system and the distance to the substrate 302, the pressure correlated to the velocity and flow rate of the carrier gas used to deliver the powder particles 309, and the density of the powder particles 309 in the fluid stream. For example, for a desired fixed micro-blast device nozzle opening size, the desired fluid pressure of the carrier gas used to direct the powder particles 309 towards the substrate 302 is determined based on the materials of the substrate 302 and the powder particles 309. In certain embodiments, the fluid pressure used to micro-blast the substrate 302 ranges from about 50 psi to about 150 psi, for example, from about 75 psi to about 125 psi, with a carrier gas and particle velocity of about 300 to about 1000 meters per second (m / s), and / or a flow rate of about 0.001 to about 0.002 cubic meters per second (m 3 / s). For example, the fluid pressure of an inert gas (e.g., nitrogen (N 2 ), CDA, argon) used to deliver the powder particles 309 during micro-blasting is about 95 psi to achieve a carrier gas and particle velocity of about 2350 m / s. In certain embodiments, the applicator nozzle used to micro-blast the substrate 302 has an inner diameter of about 0.1 to about 2.5 millimeters (mm) disposed at a distance of about 1 mm to about 5 mm from the substrate 302, for example, at a distance of about 2 mm to about 4 mm from the substrate 302. For example, the applicator nozzle is disposed at a distance of about 3 mm from the substrate 302 during micro-blasting.

[0034]

[0051] Generally, the micro-blast process is performed using powder particles 309 that have a hardness and high melting point sufficient to prevent particle adhesion upon contact with the substrate 302 and / or any layer formed thereon. For example, the micro-blast process is performed using powder particles 309 formed of a ceramic material. In certain embodiments, the powder particles 309 used in the micro-blast process are formed of aluminum oxide (Al 2 O 3 ). In another embodiment, the powder particles 309 are formed of silicon carbide (SiC). Other suitable materials for the powder particles 309 are also contemplated. The size range of the powder particles 309 is generally from about 15 μm to about 60 μm in diameter, such as from about 20 μm to about 40 μm in diameter. For example, the powder particles 309 have an average particle size of about 27.5 μm in diameter. In another example, the powder particles 309 have an average particle size of about 23 μm in diameter.

[0035]

[0052] The effectiveness of the micro-blast process shown in FIGS. 4C and 5C in step 220 further depends on the material properties of the resist layer 404. Using a material with too high a Shore A scale hardness causes unwanted bouncing of the powder particles 309 between the sidewalls of the resist layer 404, which reduces the speed at which the powder particles 309 collide with the substrate 302 and ultimately may reduce the effectiveness of the powder particles 309 to erode or remove the exposed area of the substrate 302. Conversely, using a material with too low a Shore A scale hardness may cause unwanted adhesion of the powder particles 309 to the resist layer 404. As described above, it is contemplated that a Shore A scale hardness value of about 40 to about 90 is used for the material of the resist layer 404.

[0036]

[0053] In an embodiment where the resist layer 404 is a photoresist, for example, the embodiment shown in FIG. 4C, the substrate 302 remains unexposed at the start of the micro-blasting process. Thus, the powder particles 309 first collide with the surface of the photoresist, stripping and removing material from the structurally weakened portions of the photoresist that have been UV-exposed. The powder particles 309 ultimately penetrate and remove the brittle UV-exposed portions, forming voids in the resist layer 404, thereby exposing the desired regions of the substrate 302 while other regions remain shielded by the unexposed portions of the photoresist. Thereafter, the micro-blasting continues until the powder particles 309 strip and remove a desired amount or depth of material from the exposed regions of the substrate 302, forming the desired pattern on the substrate 302. In an embodiment where the resist layer 404 is patterned by laser ablation, for example, the embodiment shown in FIG. 5C, the desired regions of the substrate 302 are already exposed through the voids in the resist layer 404 prior to the micro-blasting process. Thus, it is assumed that little or no removal of the resist layer 404 occurs during micro-blasting.

[0037]

[0054] The process for forming features on the substrate 302 described above in step 220 may cause undesirable mechanical defects such as chipping and cracking on the surface of the substrate 302. Thus, after performing step 220 for forming the desired features on the substrate 302, the substrate 302 is exposed in step 230 to a second damage removal and cleaning process for smoothing the surface of the substrate 302 and removing unwanted debris, and then the resist layer 404 is removed, and optionally the substrate 302 is removed from the carrier plate 406. FIGS. 4D - 4F and FIGS. 5D - 5F are cross-sectional views showing the substrate 302 at different stages of the second damage removal, cleaning, resist removal, and substrate removal processes according to the embodiments described herein. Thus, step 230 will next be described in more detail with reference to FIGS. 4D - 4F and FIGS. 5D - 5F.

[0038]

[0055] The second damage removal process in operation 230 is substantially the same as the first damage removal process in operation 210 and includes exposing the substrate 302 to an etching process and then rinsing and drying. The etching process proceeds for a predetermined duration to smooth the surface of the substrate 302, particularly the surface exposed to the micro-blasting process. In another aspect, the etching process is used to remove unwanted debris remaining from the micro-blasting process. The remaining powder particles adhering to the substrate 302 can be removed during the etching process. FIGS. 4D and 5D are diagrams showing the substrate 302 after debris removal and surface smoothing.

[0039]

[0056] In certain embodiments, the etching process is a wet etching process using a buffered etching process that preferentially etches the substrate surface relative to the resist layer 404 material. For example, the buffered etching process is selective with respect to polyvinyl alcohol. In other embodiments, the etching process is a wet etching process using an aqueous etching process. Any suitable wet etching solution or combination of wet etching solutions can be used for the wet etching process. In certain embodiments, the substrate 302 is immersed in an aqueous HF etching solution for etching. In another embodiment, the substrate 302 is immersed in an aqueous KOH etching solution for etching. The etching solution can further be heated to a temperature of from about 40° C. to about 80° C., for example from about 50° C. to about 70° C., during the etching process. For example, the etching solution is heated to a temperature of about 60° C. The etching process can be isotropic or anisotropic. In still other embodiments, the etching process in operation 230 is a dry etching process. Examples of dry etching processes include plasma-based dry etching processes.

[0040]

[0057] After the debris is removed and the substrate surface is smoothed, the substrate 302 is exposed to a resist stripping process. The stripping process is used to strip the resist layer 404 from the substrate 302, as shown in FIGS. 4E and 5E. In certain embodiments, a wet process is used to strip the resist layer 404 from the substrate 302 by dissolving / solubilizing the resist adhesive layer 409. Other types of etching processes for stripping the resist adhesive layer 409 are also contemplated. In certain embodiments, a mechanical rolling process is used to physically strip the resist layer 404 or the resist adhesive layer 409 from the substrate 302. In certain embodiments, an ashing process is used to remove the resist layer 404 from the substrate 302, for example, using an oxygen plasma process.

[0041]

[0058] After the resist stripping process, the substrate 302 is exposed to an optional carrier stripping process, as shown in FIGS. 4F and 5F. The use of the carrier stripping process depends on whether the substrate 302 is bonded to the carrier plate 406 and the type of bonding material used to bond the substrate 302 and the carrier plate 406. As described above and shown in FIGS. 4A-4F and 5A-5F, in embodiments where the substrate 302 has a thickness of less than about 200 μm, the substrate 302 is bonded to the carrier plate 406 for mechanical support during the formation of the features in step 220. The substrate 302 is bonded to the carrier plate 406 via the adhesive layer 408. Thus, after microblasting followed by substrate etching and resist stripping, the substrate 302 bonded to the carrier plate 406 is exposed to a carrier stripping process to strip the substrate 302 from the carrier plate 406 by stripping the adhesive layer 408.

[0042]

[0059] In certain embodiments, the adhesive layer 408 is removed by exposing the substrate 302 to a firing process. The substrate 302 is exposed to a temperature from about 50°C to about 300°C, such as a temperature from about 100°C to about 250°C. For example, the substrate 302 is exposed to a temperature from about 150°C to about 200°C, such as about 160°C, for a desired time to remove the adhesive layer 408. In other embodiments, the adhesive layer 408 is removed by exposing the substrate 302 to UV radiation.

[0043]

[0060] Figures 4F and 5F are diagrams showing the substrate 302 after completion of steps 210 - 230. Cross-sections of the substrate 302 in Figures 4F and 5F show a single cavity 305 formed therethrough and surrounded on both sides by two vias. A schematic top view of the substrate 302 at the completion of the steps described with reference to Figures 4A - 4F and 5A - 5F is shown in Figure 8 and will be described in more detail below.

[0044]

[0061] Figs. 6A-6E are schematic cross-sectional views showing the substrate 302 during alternative micro-blast processes of steps 220 and 230 similar to those described above. The alternative process sequences illustrated in steps 220 and 230 involve patterning the substrate 302 on two major opposing surfaces, and thus can enhance the efficiency in structuring the substrate 302 as compared to patterning only one surface. The embodiments shown in Figs. 6A-6E substantially include all of the processes as described with reference to Figs. 4A-4F and Figs. 5A-5E. For example, Fig. 6A corresponds to Figs. 4A and 5A, Fig. 6B corresponds to Figs. 4B and 5B, Fig. 6C corresponds to Figs. 4C and 5C, Fig. 6D corresponds to Figs. 4D and 5D, and Fig. 6E corresponds to Figs. 4F and 5F. However, different from the previous embodiments, the embodiment of step 220 shown in Figs. 6A-6E includes the substrate 302 having two resist layers 404 formed on its major opposing surfaces 606, 608, in contrast to one resist layer 404 formed on a single surface. Therefore, the processes executed during steps 210-230 need to be performed simultaneously (i.e., at the same time) or sequentially (i.e., one after another) on both sides of the substrate during each step. Only the formation of via 303 is illustrated in Figs. 6A-6E, but the processes described herein can also be used for the formation of cavity 305, or both cavity 305 and via 303.

[0045]

[0062] Thus, after exposing the resist layer 404 on one side of the substrate 302, such as the side surface including the surface 608, to electromagnetic radiation to pattern it, the substrate 302 can optionally be inverted so that the resist layer 404 on the opposing surface 606 is also exposed to electromagnetic radiation for patterning, as shown in FIG. 6B. Similarly, after performing a micro-blasting process on the surface 608 of the substrate 302, the substrate 302 can optionally be inverted so that micro-blasting can be performed on the opposing surface 606, as shown in FIG. 6C. Thereafter, the substrate 302 is exposed to the second damage removal and cleaning process and the resist stripping process shown in FIGS. 6D-6E. By performing the micro-blasting process on both surfaces 606 and 608 using two resist layers 404 on the main opposing surfaces 606 and 608 of the substrate 302, the possibility that the features formed therein become tapered by the micro-blasting process can be reduced or eliminated, and the efficiency of the process used to structure the substrate 302 can be increased.

[0046]

[0063] FIGS. 7A-7D are schematic cross-sectional views showing the substrate 302 during another alternative process sequence of steps 220 and 230 in which a desired pattern is formed on the substrate 302 by direct laser ablation. As shown in FIG. 7A, a substrate 302, such as a solar cell substrate or a semiconductor wafer, is placed on a stage 706 of a laser ablation system (not shown). The stage 706 can be any suitable rigid and planar or textured (e.g., structured) surface for providing mechanical support to the substrate 302 during laser ablation. In some embodiments, the stage 706 includes an electrostatic chuck for electrostatically chucking the substrate 302 to the stage 706. In some embodiments, the stage 706 includes a vacuum chuck for vacuum-chucking the substrate 302 to the stage 706. After placing the substrate 302 on the stage 706, a desired pattern is formed on the substrate 302 by laser ablation, as shown in FIG. 7B.

[0047]

[0064] The laser ablation system may include any suitable type of laser source 307 for patterning the substrate 302. In some examples, the laser source 307 is an infrared (IR) laser. In some examples, the laser source 307 is a picosecond UV laser. In other examples, the laser source 307 is a femtosecond UV laser. In still other examples, the laser source 307 is a femtosecond green laser. The laser source 307 generates a continuous or pulsed laser beam 310 for patterning the substrate 302. For example, the laser source 307 can generate a pulsed laser beam 310 having a frequency from 5 kHz to 500 kHz, such as from 10 kHz to about 200 kHz. In one example, the laser source 307 is configured to irradiate a pulsed laser beam with a wavelength from about 200 nm to about 1200 nm, a pulse duration from about 10 ns to about 5000 ns, and an output power from about 10 watts to about 100 watts. The laser source 307 is configured to form any desired pattern and features, including the cavity 305 and the vias 303, on the substrate 302.

[0048]

[0065] Similar to microblasting, the process of direct laser patterning of the substrate 302 can cause unwanted mechanical defects, including chipping and cracking, on the surface of the substrate 302. Therefore, after forming the desired features on the substrate 302 by direct laser patterning, the substrate 302 is exposed to a second damage removal and cleaning process that is substantially similar to the embodiments described above. FIGS. 7C-7D show the structured substrate 302 before and after the execution of the second damage removal and cleaning process, resulting in a smoothed substrate 302 having the cavity 305 and the four vias 303 formed therein.

[0049]

[0066] In certain embodiments, after removing mechanical defects of the substrate 302 in step 230, as shown in FIG. 3C, the substrate 302 can be exposed to an oxidation process to grow or deposit an insulating oxide film (i.e., layer) 314 on its desired surface. For example, the oxide film 314 can be formed over the entire surface of the substrate 302 so as to surround the substrate 302. The insulating oxide film 314 functions as a passivation layer on the substrate 302 and provides an outer barrier for protection against corrosion and other forms of damage. In certain embodiments, the oxidation process is a thermal oxidation process. The thermal oxidation process is carried out at a temperature of about 800°C to about 1200°C, for example about 850°C to about 1150°C. For example, the thermal oxidation process is carried out at a temperature of about 900°C to about 1100°C, for example about 950°C to about 1050°C. In certain embodiments, the thermal oxidation process is a wet oxidation process using water vapor as the oxidizing agent. In certain embodiments, the thermal oxidation process is a dry process using molecular oxygen as the oxidizing agent. The substrate 302 is assumed to be exposed to any suitable oxidation process in step 240 to form the oxide film 314 thereon. The oxide film 314 generally has a thickness of about 100 nm to about 3 μm, for example about 200 nm to about 2.5 μm. For example, the oxide film 314 has a thickness of about 300 nm to about 2 μm, for example about 1.5 μm.

[0050]

[0067] In step 240 and in FIG. 3D, a bonding layer 316 is formed on the desired surface of the substrate 302. For example, the bonding layer 316 can be formed over the entire surface of the substrate 302 as shown in FIG. 3D, or can be formed only on some surfaces, such as the major surfaces 606 and 608. In certain embodiments, the bonding layer 316 is formed on the oxide film 314.

[0051]

[0068] The bonding layer 316 generally includes a coating formed of one or more binders to facilitate improved adhesion between the substrate 302 and any insulating layer and / or redistribution layer that is subsequently formed thereon, such as the insulating layer 1018 described below with reference to FIGS. 9 and 10A-10K. Conventionally, insulating layers and / or redistribution layers containing typically organic materials and / or dielectric materials are formed directly on the frame of a semiconductor package device. However, when using a silicon-based frame, the adhesion between the frame and the subsequently formed insulating layer and / or redistribution layer is weak, allowing moisture to penetrate therebetween. Thereafter, when the package device is exposed to high-temperature conditions, for example, during subsequent processing, the moisture expands and the insulating layer and / or redistribution layer delaminate or separate from the frame, potentially significantly compromising the structural integrity and electrical performance of the semiconductor package device. By forming the bonding layer 316 between the substrate 302 and, for example, the insulating layer 1018, the adhesion of the insulating layer 1018 to the substrate 302 is improved, thereby enhancing the thermo-mechanical reliability of the final semiconductor package device. Further, the bonding layer 316 provides an additional protective barrier around the substrate 302 and relieves stresses that may occur thereon due to the expansion and / or warping of the insulating layer 1018.

[0052]

[0069] In certain embodiments, the bonding layer 316 includes one or more silane coupling agents, which can react or interact with both the substrate and the polymer, thereby creating a water-resistant contact surface between the organic polymer of the insulating layer, such as the insulating layer 1018, and the inorganic substrate, such as the substrate 302. A silane coupling agent is an organosilicon compound that includes both an organic functional group for reacting / interacting with an organic material, such as the insulating layer and / or redistribution layer, and a hydrolyzable group for reacting / interacting with an inorganic material, such as a silicon-based frame. In certain embodiments, the silane coupling agent has the general structure X 3 -Si-(CH 2)It may have n-Y. In the above formula, X is a hydrolyzable group such as methoxy or ethoxy, Y is a functional group, and n is equal to 0 to 3. Examples of suitable functional groups include a vinyl group, an epoxy group or an epoxide group, a styryl group, an acryloyl group, a methacryl group, a methacryloyl group, an amino group, a phenyl group, a ureido group, an isocyanate group, an isocyanurate group, a mercapto group, etc. In a specific embodiment, the bonding layer 316 is dodecyltrimethoxysilane, octadecyltrimethoxysilane, n-octyltriethoxysilane, methyltrimethoxysilane, methyltriethoxysilane, γ-methacryloxypropyltrimethoxysilane, vinyltriacetoxysilane, vinyltrimethoxysilane, vinyltriethoxysilane, dichloromethylvinylsilane, dimethoxymethylvinylsilane, diethoxymethylvinylsilane, chlorodimethylvinylsilane, vinyltrichlorosilane, vinyltri(2-methoxyethoxy)silane, 1,3,5,7-tetravinyl-1,3,5,7-tetramethylcyclotetrasiloxane, γ-isocyanatopropyltriethoxysilane, γ-glycidoxypropyltrimethoxysilane, β-(3,4-epoxycyclohexyl)ethyltrimethoxysilane, phenyltrichlorosilane, phenyltrimethoxysilane, phenyltrimethoxysilane, dichlorodiphenylsilane, diphenyldimethoxysilane, diphenyldiethoxysilane, methylphenyldimethoxysilane, methylphenyldiethoxysilane, 3-aminopropyltriethoxysilane, n-2-(aminoethyl)-3-aminopropyltrimethoxysilane, n-2-(aminoethyl)-3-aminopropyltriethoxysilane, n-2-(aminoethyl)-3-aminopropylmethyldimethoxysilane, 3-aminopropyltrimethoxysilane, 3-aminopropylmethyldiethoxysilane, 3-ureidopropyltrimethoxysilane, 3-ureidopropyltriethoxysilane, 3-glycidoxypropyltrimethoxysilane, 3-glycidoxypropylmethyldimethoxysilane, 3-glycidoxypropylmethyldiethoxysilane, 3-glycidoxypropyltriethoxysilane, 2-(3,4-epoxycyclohexyl)ethyltrimethoxysilane, 2-(3,It may contain (4-epoxycyclohexyl)ethyltriethoxysilane, 2-(3,4-epoxycyclohexyl)ethylmethyldimethoxysilane, 2-(3,4-epoxycyclohexyl)ethylmethyldiethoxysilane, 3-methacryloxypropyltrimethoxysilane, 3-methacryloxypropylmethyldimethoxysilane, 3-methacryloxypropylmethyldiethoxysilane, 3-methacryloxypropyltriethoxysilane, bis[3-(triethoxysilyl)propyl]tetrasulfide, bis[3-(triethoxysilyl)propyl]sulfide, 3-mercaptopropyltrimethoxysilane, 3-mercaptopropyltriethoxysilane, 1,2-bis(trimethoxysilyl)ethane, 1,2-bis(triethoxysilyl)ethane, tetramethoxysilane, tetraethoxysilane, tetrapropoxysilane, trimethoxysilane, triethoxysilane, etc.

[0053]

[0070] Generally, the bonding layer 316 can be formed by any suitable chemical process and / or deposition process, and any suitable method including self-assembly. In certain embodiments, the bonding layer 316 is formed by sol-gel or one or more other chemical processes. In certain embodiments, the bonding layer 316 is formed by chemical vapor deposition (CVD) or other deposition processes. In certain embodiments, an organic silane self-assembled monolayer (SAM) is formed on the surface of the substrate 302 via liquid phase deposition (LPD) or vapor phase deposition (VPD). In LPD, the silane can be diluted with a solvent and then the substrate 302 can be immersed in the solution for a desired time. In VPD, the silane can be evaporated, for example, by applying heat, and then the substrate 302 can be exposed to the vapor.

[0054]

[0071] After the formation of the bonding layer 316, the substrate 302 can proceed to the method 900 or method 1100 described below for forming the embedded die assembly 1002 using the substrate 302 as a frame.

[0055]

[0072] FIG. 8 is a schematic top view showing an exemplary structured substrate 302 according to one embodiment. The substrate 302 can be structured during processes 210-240 as described above with reference to FIGS. 2, 3A-3D, 4A-4F, 5A-5F, 6A-6E, and 7A-7D. The substrate 302 is illustrated as having two quadrilateral cavities 305, each cavity 305 being surrounded by a plurality of vias 303. In a particular embodiment, each cavity 305 is surrounded by two columns 801, 802 of vias 303 disposed along each side 306a-d of the quadrilateral cavity 305. Although 10 vias 303 are illustrated in each column 801, 802, it is envisioned that any desired number of vias 303 can be formed in a single column. Further, any desired number and arrangement of cavities 305 and vias 303 can be formed in the substrate 302 during process 220. For example, more than two or fewer cavities 305 may be formed therein in the substrate 302. In another example, more than two or fewer than two columns of vias 303 may be formed along each side 306a-d of the cavity 305 in the substrate 302. In another example, the substrate 302 may have more than two columns of vias 303, and the vias 303 in each column may be staggered and offset from the vias 303 in another column.

[0056]

[0073] In a particular embodiment, the cavities 305 and vias 303 have a depth equal to the thickness of the substrate 302, and thus form holes in opposite surfaces of the substrate 302 (e.g., through the thickness of the substrate 302). For example, the cavities 305 and vias 303 formed in the substrate 302 may have a depth of from about 50 μm to about 1 mm, such as from about 100 μm to about 200 μm, such as from about 110 μm to about 190 μm, depending on the thickness of the substrate 302. In other embodiments, the cavities 305 and / or vias 303 may have a depth equal to or less than the thickness of the substrate 302, and thus form holes in only one surface (e.g., a side surface) of the substrate 302.

[0057]

[0074] In certain embodiments, each cavity 305 has a lateral dimension in the range of from about 3 mm to about 50 mm, such as from about 8 mm to about 12 mm, such as from about 9 mm to about 11 mm, depending on the size of the one or more semiconductor dies 1026 (shown in FIG. 10B) embedded therein during package manufacture (described in further detail below). A semiconductor die generally includes a plurality of integrated electronic circuits formed on and / or within a substrate material, such as a portion of a semiconductor material. In certain embodiments, the cavity 305 is sized to have a lateral dimension substantially similar to the lateral dimension of the die 1026 embedded therein. For example, each cavity 305 is formed to have a lateral dimension that exceeds the lateral dimension of the die 1026 by less than about 150 μm, such as less than about 120 μm, such as less than 100 μm. By reducing the variation in the sizes of the cavity 305 and the die 1026 embedded therein, the amount of gap filling material used thereafter is reduced.

[0058]

[0075] In certain embodiments, each via 303 has a diameter in the range of from about 50 μm to about 200 μm, such as from about 60 μm to about 130 μm, such as from about 80 μm to 110 μm. The minimum pitch 807 between the centers of the vias 303 in column 801 and the centers of the adjacent vias 303 in column 802 is from about 70 μm to about 200 μm, such as from about 85 μm to about 160 μm, such as from about 100 μm to about 140 μm. Although the embodiments have been described with reference to FIG. 8, patterned features having any desired depth, lateral dimension, and configuration can be formed in the substrate 302 using the substrate structuring process described above with reference to steps 210-240 and FIGS. 2, 3A-3B, 4A-4C, 5A-5C, 6A-6C, and 7A-7B.

[0059]

[0076] FIG. 9 and FIG. 11 are flowcharts respectively showing representative methods 900 and 1100 for manufacturing an intermediate embedded die assembly 1002 around a substrate 302 before final package formation. FIGS. 10A-10K are cross-sectional views schematically showing the substrate 302 at different stages of the method 900 shown in FIG. 9, and FIGS. 12A-12G are cross-sectional views schematically showing the substrate 302 at different stages of the method 1100 shown in FIG. 11. For clarity, in this specification, FIG. 9 and FIGS. 10A-10K are described together, and FIG. 11 and FIGS. 12A-12G are described together.

[0060]

[0077] Method 900 starts with step 902 and FIG. 10A, at which point the first side 1075 of the substrate 302 having the desired features formed therein and the bonding layer 316 formed thereon is placed on the first insulating film 1016a. In certain embodiments, the first insulating film 1016a includes one or more layers formed of a polymer-based dielectric material. For example, the first insulating film 1016a includes one or more layers formed of a flowable build-up material. In the embodiment shown in FIG. 10A, the first insulating film 1016a includes a flow layer 1018a. The flow layer 1018a may be formed of a ceramic-filled epoxy resin such as an epoxy resin filled with silica (SiO 2 ) particles (e.g., containing silica (SiO 2 ) particles). Other examples of ceramic fillers or particles that may be used to form the flow layer 1018a and other layers of the insulating film 1016a include aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), silicon carbide (SiC), silicon nitride (Si 3 N 4 ), Sr 2 Ce 2 Ti 5 O 16 , zirconium silicate (ZrSiO 4 ), wollastonite (CaSiO 3 ), beryllium oxide (BeO), cerium dioxide (CeO 2 ), boron nitride (BN), calcium copper titanium oxide (CaCu 3 Ti4 O 12 )), magnesium oxide (MgO), titanium dioxide (TiO 2 ), zinc oxide (ZnO), etc. In some examples, the ceramic filler used to form the fluidized layer 1018a has particles sized in the range of about 40 nm to about 1.5 μm, such as about 80 nm to about 1 μm. For example, the ceramic filler used to form the fluidized layer 1018a has particles sized in the range of about 200 nm to about 800 nm, such as about 300 nm to about 600 nm. In some embodiments, the ceramic filler used to form the fluidized layer 1018a includes particles sized less than about 25% of the width or diameter of a desired feature (e.g., a via, a cavity, or an assembly through-via), such as less than about 15% of the width or diameter of the desired feature.

[0061]

[0078] The fluidized layer 1018a typically has a thickness of less than about 60 μm, such as from about 5 μm to about 50 μm. For example, the fluidized layer 1018a has a thickness of from about 10 μm to about 25 μm. In certain embodiments, the insulating film 1016a further includes one or more support layers. For example, the insulating film 1016a includes a polyethylene terephthalate (PET) or similar lightweight plastic support layer 1022a. However, any suitable combination of layers and insulating materials is contemplated for the insulating film 1016a. In some embodiments, the overall thickness of the insulating film 1016a is less than about 120 μm, such as less than about 90 μm.

[0062]

[0079] On its first side 1075, the substrate 302 coupled to the insulating film 1016a, specifically to the fluidized layer 1018a of the insulating film 1016a, can optionally be disposed on the carrier 1024 for mechanical support during subsequent processing steps. The carrier is formed of any suitable material that is mechanically and thermally stable. For example, the carrier 1024 is formed of polytetrafluoroethylene (PTFE). In another example, the carrier 1024 is formed of PET.

[0063]

[0080] In operation 904 and as shown in FIG. 10B, one or more semiconductor dies 1026 are disposed within cavity 305 formed in substrate 302, whereby one side of semiconductor die 1026 is coupled by insulating film 1016a (a single semiconductor die 1026 is shown in FIG. 10B). In certain embodiments, die 1026 is a multi-purpose die having an integrated circuit formed on its active face 1028. Die 1026 is disposed within cavity 305 and positioned on the surface of insulating film 1016a exposed through cavity 305. In certain embodiments, die 1026 is disposed on an adhesive layer (not shown) disposed or formed on insulating film 1016a.

[0064]

[0081] After die 1026 is disposed within cavity 305, a first protective film 1060 is disposed in operation 906 and in FIG. 10C on the second side 1077 of substrate 302 (e.g., on face 608). Protective film 1060 is coupled to the second side 1077 of substrate 302 and to the opposite side of first insulating film 1016a so as to contact and cover the active face 1028 of die 1026 disposed within cavity 305. In certain embodiments, protective film 1060 is formed of a material similar to that of support layer 1022a. For example, protective film 1060 is formed of PET such as biaxial PET. However, protective film 1060 may be formed of any suitable protective material. In some embodiments, protective film 1060 has a thickness of from about 50 μm to about 150 μm.

[0065]

[0082] At this point, the substrate 302, which is fixed to the insulating film 1016a on the first side 1075 and the protective film 1060 on the second side 1077, and in which the die 1026 is further disposed, is exposed to a lamination process in step 908 in order to bond the insulating film 1016 to the substrate 302, more particularly to a bonding layer 316 formed on the substrate 302. During the lamination process, the substrate 302 is exposed to a high temperature, and the flowable layer 1018a of the insulating film 1016a softens and flows into the open voids or regions between the insulating film 1016a and the protective film 1060, for example, the via 303 and the gap 1051 between the inner wall of the cavity 305 and the die 1026. Thus, the semiconductor die 1026 will be at least partially embedded in the materials of the insulating film 1016a and the substrate 302, as shown in FIG. 10D.

[0066]

[0083] In certain embodiments, the lamination process may be a vacuum lamination process performed in an autoclave or other suitable apparatus. In certain embodiments, the lamination process is performed using a hot press process. In certain embodiments, the lamination process is performed at a temperature of about 80° C. to about 140° C. for about 5 seconds to about 1.5 minutes, for example, about 30 seconds to about 1 minute. In some embodiments, the lamination process includes applying a pressure of about 1 psig to about 50 psig while applying a temperature of about 80° C. to about 140° C. to the substrate 302 and the insulating film 1016a for about 5 seconds to about 1.5 minutes. For example, the lamination process is performed at a pressure of about 5 psig to about 40 psig, a temperature of about 100° C. to about 120° C., for about 10 seconds to about 1 minute. For example, the lamination process is performed at a temperature of about 110° C. for about 20 seconds.

[0067]

[0084] In operation 910, the protective film 1060 is removed, and at this point, the substrate 302 having the laminated insulating material of the flow layer 1018a that at least partially surrounds the substrate 302 and one or more dies 1026 is placed on the second protective film 1062. As shown in FIG. 10E, the second protective film 1062 is coupled to the first side surface 1075 of the substrate 302 such that the second protective film 1062 is placed in contact with (e.g., adjacent to) the support layer 1022a of the insulating film 1016a. In some embodiments, the substrate 302 coupled to the protective film 1062 at this point can optionally be placed on the carrier 1024 for additional mechanical support on the first side surface 1075. In some embodiments, the protective film 1062 can be placed on the carrier 1024 before coupling the protective film 1062 to the substrate 302 on which the insulating film 1016a is laminated at this point. Generally, the protective film 1062 has a composition substantially similar to that of the protective film 1060. For example, the protective film 1062 may be formed of PET such as biaxial PET. However, the protective film 1062 may be formed of any suitable protective material. In some embodiments, the protective film 1062 has a thickness of from about 50 μm to about 150 μm.

[0068]

[0085] Once the substrate 302 is bonded to the second protective film 1062, a second insulating film 1016b substantially similar to the first insulating film 1016a is placed on the second side 1077 of the substrate 302 in step 912 and FIG. 10F to replace the protective film 1060. In certain embodiments, the second insulating film 1016b is positioned on the second side 1077 of the substrate 302 such that the flow layer 1018b of the second insulating film 1016b contacts and covers the active surface 1028 of the die 1026 within the cavity 305. In certain embodiments, placing the second insulating film 1016b on the substrate 302 may form one or more voids between the insulating film 1016b and the already deposited insulating material of the flow layer 1018a that partially surrounds the one or more dies 1026. The second insulating film 1016b may include one or more layers formed of a polymer-based flowable dielectric material. As shown in FIG. 10F, the second insulating film 1016b includes a flow layer 1018b similar to the flow layer 1018a described above. The second insulating film 1016b may further include a support layer 1022b formed of a material similar to the support layer 1022a, such as PET or other lightweight plastic material.

[0069]

[0086] In step 914, as shown in FIG. 10G, a third protective film 1064 is placed on top of the second insulating film 1016b. Generally, the protective film 1064 has a composition substantially similar to the protective films 1060, 1062. For example, the protective film 1064 is formed of PET such as biaxially oriented PET. However, the protective film 1064 may be formed of any suitable protective material. In some embodiments, the protective film 1064 has a thickness of from about 50 μm to about 150 μm.

[0070]

[0087] At this point, the substrate 302 fixed to the insulating film 1016b and the support layer 1064 on the second side 1077, as well as the protective film 1062 and the optional carrier 1024 on the first side 1075, is exposed to the second lamination process in step 916 and FIG. 10H. Similar to the lamination process in step 908, the substrate 302 is exposed to a high temperature, and the flowable layer 1018b of the insulating film 1016b softens and flows into any open void or region between the insulating film 1016b and the insulating material already laminated in the flowable layer 1018a. As a result, it integrates with the insulating material of the flowable layer 1018a. Thus, the cavity 305 and the via 303 are filled (e.g., packed and sealed) with the insulating material, and the semiconductor die 1026 pre - placed in the cavity 305 will be completely embedded in the insulating materials of the flowable layers 1018a and 1018b.

[0071]

[0088] In certain embodiments, the lamination process may be a vacuum lamination process performed in an autoclave or other suitable apparatus. In certain embodiments, the lamination process is performed using a hot - press process. In certain embodiments, the lamination process is performed at a temperature from about 80°C to about 140°C for about 1 minute to about 30 minutes. In some embodiments, the lamination process includes applying a pressure from about 10 psig to about 150 psig while applying a temperature from about 80°C to about 140°C to the substrate 302 and the insulating film 1016b for about 1 minute to about 30 minutes. For example, the lamination process is performed at a pressure from about 20 psig to about 100 psig, a temperature from about 100°C to about 120°C, for about 2 minutes to 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for about 5 minutes.

[0072]

[0089] After lamination, the substrate 302 is detached from the carrier 1024 in step 918, and the protective films 1062 and 1064 are removed, resulting in the laminated embedded die assembly 1002. As shown in FIG. 10I, the embedded die assembly 1002 includes a substrate 302 having one or more cavities 305 and / or vias 303 formed therein and filled with the insulating dielectric material of the flow layers 1018a and 1018b, and an embedded die 1026 within the cavity 305. The insulating dielectric material of the flow layers 1018a and 1018b wraps the substrate 302 (and the bonding layer 316) such that the insulating material is disposed on at least two surfaces or sides of the substrate 302, for example, the two major surfaces 606 and 608, and covers all sides of the embedded semiconductor die 1026. In some embodiments, the support layers 1022a and 1022b are also removed from the embedded die assembly 1002 in step 918. Generally, the support layers 1022a and 1022b, the carrier 1024, and the protective films 1062 and 1064 are removed from the embedded die assembly 1002 by any suitable mechanical process such as peeling therefrom.

[0073]

[0090] After removing the support layers 1022a, 1022b and the protective films 1062, 1064, the embedded die assembly 1002 is exposed to a curing process to fully cure the insulating dielectric material of the flow layers 1018a, 1018b (i.e., harden through chemical reaction and cross-linking) to form the cured insulating layer 1018. The insulating layer 1018 substantially surrounds the substrate 302 and the semiconductor die 1026 embedded therein. For example, the insulating layer 1018 contacts or encapsulates at least the sides 1075, 1077 (including the surfaces 606, 608) of the substrate 302 and at least six sides or surfaces of each semiconductor die 1026 having the right prism shape illustrated in FIG. 10H (i.e., only four surfaces 1028, 1029 are shown in the two-dimensional figure).

[0074]

[0091] In certain embodiments, the curing process is performed at an elevated temperature to fully cure the embedded die assembly 1002. For example, the curing process is performed for about 15 minutes to about 45 minutes at a temperature from about 140°C to about 220°C, such as for about 25 minutes to about 35 minutes at a temperature from about 160°C to about 200°C. For example, the curing process is performed for about 30 minutes at a temperature of about 180°C. In further embodiments, the curing process in step 916 is performed at ambient (e.g., atmospheric pressure) pressure conditions or conditions close thereto.

[0075]

[0092] After curing, one or more assembly through vias 1003 are drilled through the embedded die assembly 1002 in step 920 to form channels that extend through the entire thickness of the embedded die assembly 1002 for subsequent wiring formation. In some embodiments, the embedded die assembly 1002 can be disposed on a carrier, such as carrier 1024, for mechanical support during the formation of the assembly through vias 1003 and subsequent contact holes 1032. The assembly through vias 1003 are drilled through vias 303 formed in the substrate 302 and are then filled with an insulating layer 1018. Thus, the assembly through vias 1003 may be circumferentially surrounded by not only the bonding layer 316 and the substrate 302, but also the insulating layer 1018 filled in the vias 303. By lining the walls of the vias 303 with a ceramic filler-containing epoxy resin material of the insulating layer 1018, capacitive coupling is achieved between the conductive silicon-based substrate 302 and the wiring portion 1444 (described with reference to FIGS. 13 and 14E-14H), and thus capacitive coupling between adjacent vias 303 and / or redistribution connections 1644 (described with reference to FIGS. 15 and 16H-16L) positioned in the completed package 1602 is significantly reduced as compared to other conventional wiring structures using conventional via insulation liners or films. Further, the fluidity of the epoxy resin material allows for more consistent and reliable encapsulation and insulation, and thus improves the electrical performance by minimizing the leakage current of the completed package 1602.

[0076]

[0093] In certain embodiments, the assembly through - via 1003 has a diameter of less than about 100 μm, such as less than about 75 μm. For example, the assembly through - via 1003 has a diameter of less than about 60 μm, such as less than about 50 μm. In certain embodiments, the assembly through - via 1003 has a diameter of from about 25 μm to about 50 μm, such as from about 35 μm to about 40 μm. In certain embodiments, the assembly through - via 1003 is formed using any suitable mechanical process. For example, the assembly through - via 1003 is formed using a mechanical drilling process. In certain embodiments, the assembly through - via 1003 is formed by penetrating the embedded die assembly 1002 by laser ablation. For example, the assembly through - via 1003 is formed using an ultraviolet laser. In certain embodiments, the laser source used for laser ablation has a frequency of from about 5 kHz to about 500 kHz. In certain embodiments, the laser source is configured to supply a pulsed laser beam with a pulse energy of from about 50 microjoules (μJ) to about 500 μJ and a pulse duration of from about 10 ns to about 100 ns. During the laser ablation process, by using an epoxy resin material having small ceramic filler particles, the small ceramic filler particles therein reduce the reflection, scattering, diffraction, and transmission of the laser light to locations away from the region where the via is to be formed, thereby further facilitating more precise and accurate laser patterning of small - diameter vias such as via 1003.

[0077]

[0094] In operation 922 and FIG. 10K, one or more contact holes 1032 are drilled through the insulating layer 1018 to expose one or more contacts 1030 formed on the active surface 1028 of each embedded die 1026. The contact holes 1032 are drilled through the insulating layer 1018 by laser ablation such that all outer surfaces of the semiconductor die 1026 are covered and surrounded by the insulating layer 1018, leaving the contacts 1030 exposed. Thus, the contacts 1030 are exposed by the formation of the contact holes 1032. In certain embodiments, the laser source can generate a pulsed laser beam having a frequency from about 100 kHz to about 1000 kHz. In certain embodiments, the laser source is configured to supply a pulsed laser beam having a wavelength from about 100 nm to about 2000 nm, a pulse duration from about 10E-4 ns to about 10E-2 ns, and a pulse energy from about 10 μJ to about 300 μJ. In certain embodiments, the contact holes 1032 are drilled using a CO 2 , green, or UV laser. In certain embodiments, the contact holes 1032 have a diameter from about 5 μm to about 60 μm, for example from about 20 μm to about 50 μm.

[0078]

[0095] After the formation of the contact holes 1032, the embedded die assembly 1002 is exposed to a desmear process in operation 922 to remove any and all residues and / or debris generated by laser ablation during the formation of the assembly through vias 1003 and the contact holes 1032. In this way, the desmear process cleans the assembly through vias 1003 and the contact holes 1032, fully exposing the contacts 1030 on the active surface 1028 of the embedded die 1026 for subsequent metallization. In certain embodiments, the desmear process is a wet desmear process. Any suitable aqueous etchant, solvent, and / or combination thereof can be used in the wet desmear process. In one example, potassium permanganate (KMnO 4)The solution can be used as an etching solution. Depending on the thickness of the residue, the exposure of the embedded die assembly 1002 to the wet desmear process in step 922 can be changed. In another embodiment, the desmear process is a dry desmear process. For example, the desmear process may be a plasma desmear process using an O 2 :CF 4 mixed gas. The plasma desmear process may include applying power of about 700 W and flowing O 2 :CF 4 at a ratio of about 10:1 (e.g., 100:10 sccm) for about 60 seconds to about 120 seconds to generate a plasma. In a further embodiment, the desmear process is a combination of a wet process and a dry process.

[0079]

[0096] After the desmear process in step 922, the embedded die assembly 1002 is ready to form wiring paths therein, which will be described below with reference to FIGS. 13 and 14A-14H.

[0080]

[0097] As described above, FIGS. 9 and 10A-10K are diagrams showing a representative method 900 for forming the intermediate embedded die assembly 1002. FIGS. 11 and 12A-12G are diagrams showing an alternative method 1100 that is substantially the same as method 900 but has fewer steps. Method 1100 generally includes eight steps 1110-1180. However, steps 1110, 1120, 1160, and 1190 of method 1100 are substantially the same as steps 902, 904, 920, and 922 of method 900, respectively. Therefore, in this specification, for clarity, only steps 1130, 1140, and 1150 shown in FIGS. 12C, 12D, and 12E, respectively, will be described.

[0081]

[0098] After placing one or more semiconductor dies 1026 on the surface of the insulating film 1016a exposed through the cavity 305, a second insulating film 1016b is positioned on the second side surface 1077 of the substrate 302 in step 1130 and in FIG. 12C, prior to lamination. In some embodiments, the second insulating film 1016b is positioned on the second side surface 1077 of the substrate 302 such that the flow layer 1018b of the second insulating film 1016b contacts and covers the active surface 1028 of the die 1026 within the cavity 305. In some embodiments, a second carrier 1025 is fixed to the support layer 1022b of the second insulating film 1016b for additional mechanical support during subsequent processing steps. As shown in FIG. 12C, one or more voids 1050 are formed between the insulating films 1016a and 1016b through the vias 303, and a gap 1051 is formed between the semiconductor die 1026 and the inner wall of the cavity 305.

[0082]

[0099] In step 1140 and in FIG. 12D, the substrate 302, which is now fixed to the insulating films 1016a and 1016b and in which the die 1026 is disposed, is exposed to a single lamination process to adhere both insulating films 1016a and 1016b to the substrate 302, and more particularly to the bonding layer 316. During the single lamination process, the substrate 302 is exposed to high temperature, and the flow layers 1018a and 1018b of both insulating films 1016a, 1016b soften and flow into the open voids or regions between the insulating films 1016a and 1016b, such as within the vias 303 and the gap 1051 between the inner wall of the cavity 305 and the die 1026. Thus, the semiconductor die 1026 is embedded within the material of the insulating films 1016a, 1016b and the vias 303 are filled thereby.

[0083]

[0100] Similar to the lamination process described with reference to FIGS. 9 and 10A - 10K, the lamination process in step 1140 may be a vacuum lamination process that can be performed in an autoclave or other suitable apparatus. In another embodiment, the lamination process is performed using a hot press process. In a particular embodiment, the lamination process is performed at a temperature from about 80°C to about 140°C for about 1 minute to about 30 minutes. In some embodiments, the lamination process includes applying a pressure from about 1 psig to about 150 psig while applying a temperature from about 80°C to about 140°C to the substrate 302 and the insulating film 1016a, 1016b layers for about 1 minute to about 30 minutes. For example, the lamination process is performed at a pressure from about 10 psig to about 100 psig, a temperature from about 100°C to about 120°C, for about 2 minutes to 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for about 5 minutes.

[0084]

[0101] In step 1150, one or more support layers of the insulating films 1016a and 1016b are removed from the substrate 302, resulting in a laminated embedded die assembly 1002. As shown in FIG. 12E, the embedded die assembly 1002 includes a substrate 302 having one or more cavities 305 and / or vias 303 formed therein and filled with an insulating dielectric material of the flow layers 1018a, 1018b, and an embedded die 1026 within the cavity 305. The insulating material wraps the substrate 302 so as to cover at least two surfaces or sides of the substrate 302, such as surfaces 606, 608. In one example, the support layers 1022a, 1022b are removed from the embedded die assembly 1002, as a result of which the embedded die assembly 1002 is detached from the carriers 1024, 1025. Generally, the support layers 1022a, 1022b and the carriers 1024, 1025 are removed by any suitable mechanical process such as peeling them off.

[0085]

[0102] Once the support layers 1022a, 1022b are removed, the embedded die assembly 1002 is exposed to a curing process to fully cure the insulating dielectric materials of the fluid layers 1018a, 1018b. The curing of the insulating material forms the cured insulating layer 1018. As shown in FIG. 12E, similar to step 918 corresponding to FIG. 10I, the insulating layer 1018 substantially surrounds the substrate 302 and the semiconductor die 1026 embedded therein.

[0086]

[0103] In certain embodiments, the curing process is performed at an elevated temperature to fully cure the embedded die assembly 1002. For example, the curing process is performed at a temperature from about 140°C to about 220°C for about 15 minutes to about 45 minutes, for example, at a temperature from about 160°C to about 200°C for about 25 minutes to about 35 minutes. For example, the curing process is performed at a temperature of about 180°C for about 30 minutes. In further embodiments, the curing process in step 1150 is performed at ambient (e.g., atmospheric) pressure conditions or conditions close thereto.

[0087]

[0104] The method 1100 after curing in step 1150 is substantially similar to steps 920 and 922 of method 900. For example, the embedded die assembly 1002 has one or more assembly through vias 1003 and one or more contact holes 1032 that are drilled through the insulating layer 1018. Subsequently, the embedded die assembly 1002 is exposed to a desmear process, and then the embedded die assembly 1002 is ready to form wiring paths therein, as described below.

[0088]

[0105] FIG. 13 is a flow diagram showing a representative method 1300 for forming an electrical wiring portion through the embedded die assembly 1002. FIGS. 14A - 14H are cross-sectional views schematically showing the embedded die assembly 1002 at different stages of the process of the method 1300 shown in FIG. 13. Accordingly, FIGS. 13 and 14A - 14H are described together herein for clarity.

[0089]

[0106] In certain embodiments, the electrical wiring portion formed through the embedded die assembly 1002 is formed of copper. Thus, method 1300 can optionally start with step 1310 and FIG. 14A, where the embedded die assembly 1002 having assembly through vias 1003 and contact holes 1032 formed therein has an adhesive layer 1440 and / or a seed layer 1442 formed thereon. An enlarged view of the adhesive layer 1440 and the seed layer 1442 formed on the embedded die assembly 1002 is shown in FIG. 14H for reference. The adhesive layer 1440, which helps promote adhesion and prevent diffusion of the subsequently formed seed layer 1442 and copper wiring 1444, can be formed on the desired surfaces of the insulating layer 1018, such as the major surfaces 1005, 1007 of the embedded die assembly 1002, and the effective surfaces 1028 of the contact holes 1032 and the inner walls of the assembly through vias 1003 on each die 1026. Thus, in certain embodiments, the adhesive layer 1440 functions as an adhesive layer, and in other embodiments, the adhesive layer 1440 functions as a barrier layer. However, in both embodiments, the adhesive layer 1440 is described as an "adhesive layer" hereinafter.

[0090]

[0107] In certain embodiments, the optional adhesive layer 1440 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combinations thereof. In certain embodiments, the adhesive layer 1440 has a thickness of from about 10 nm to about 300 nm, such as from about 50 nm to about 150 nm. For example, the adhesive layer 1440 has a thickness of from about 75 nm to about 125 nm, such as about 100 nm. The adhesive layer 1440 is formed by any suitable deposition process including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc.

[0091]

[0108] The optional seed layer 1442 may be formed on the adhesive layer 1440 or may be formed directly on the insulating layer 1018 (e.g., without forming the adhesive layer 1440). The seed layer 1442 is formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In certain embodiments, the seed layer 1442 has a thickness of from about 50 nm to about 500 nm, such as from about 100 nm to about 300 nm. For example, the seed layer 1442 has a thickness of from about 150 nm to about 250 nm, such as about 200 nm. In certain embodiments, the seed layer 1442 has a thickness of from about 0.1 μm to about 1.5 μm. Similar to the adhesive layer 1440, the seed layer 1442 is formed by any suitable deposition process such as CVD, PVD, PECVD, ALD dry process, electroless plating wet process, etc. In certain embodiments, a molybdenum adhesive layer 1440 is formed on the embedded die assembly in combination with the copper seed layer 1442. The combination of the molybdenum-copper adhesive layer and the seed layer improves the adhesion to the surface of the insulating layer 1018 and reduces the undercutting of the conductive wiring during the subsequent seed layer etching process in step 1370.

[0092]

[0109] In steps 1320 and 1330 corresponding to FIGS. 14B and 14C respectively, a spin-on / spray-on or dry resist film 1450, such as a photoresist, is applied onto both major surfaces 1005, 1007 of the embedded die assembly 1002 and then patterned. In certain embodiments, the resist film 1450 is patterned via selective exposure to UV radiation. In certain embodiments, a adhesion promoter (not shown) is applied to the embedded die assembly 1002 before forming the resist film 1450. The adhesion promoter generates an interfacial bonding layer for the resist film 1450 and improves the adhesion of the resist film 1450 to the embedded die assembly 1002 by removing all moisture from the surface of the embedded die assembly 1002. In some embodiments, the adhesion promoter is formed from bis(trimethylsilyl)amine or hexamethyldisilazane (HMDS) and propylene glycol monomethyl ether acetate (PGMEA).

[0093]

[0110] In steps 1340 and FIG. 14D, the embedded die assembly 1002 is exposed to a resist film development process. As shown in FIG. 14D, as a result of developing the resist film 1450, the assembly through vias 1003 and contact holes 1032 are exposed, and an adhesion layer 1440 and a seed layer 1442 are formed thereon. In certain embodiments, the film development process is a wet process, such as a wet process that includes exposing the resist to a solvent. In certain embodiments, the film development process is a wet etching process using an aqueous etching process. In other embodiments, the film development process is a wet etching process using a buffered etching process selective to the desired material. Any suitable combination of wet solvents or wet etching solutions can be used for the resist film development process.

[0094]

[0111] In steps 1350 and 1360 corresponding to FIGS. 14E and 14F respectively, wiring portion 1444 is formed through exposed assembly through-via 1003 and contact hole 1032, and then resist film 1450 is removed. Wiring portion 1444 is formed by any suitable method including electroplating and electroless deposition. In a particular embodiment, resist film 1450 is removed via a wet process. As shown in FIGS. 14E and 14F, assembly through-via 1003 and contact hole 1032 are filled with formed wiring portion 1444 and / or their sidewalls are covered, and wiring portion 1444 protrudes from surfaces 1005, 1007, and 1028 of embedded die assembly 1002 when resist film 1450 is removed. In a particular embodiment, wiring portion 1444 is formed of copper. In other embodiments, wiring portion 1444 can be formed of any suitable conductive material including, but not limited to, aluminum, gold, nickel, silver, palladium, tin, etc.

[0095]

[0112] In steps 1370 and FIG. 14G, embedded die assembly 1002 in which wiring portion 1444 is formed is exposed to an adhesive layer and / or seed layer etching process for removing adhesive layer 1440 and seed layer 1442. In a particular embodiment, seed layer etching is a wet etching process including rinsing and drying of embedded die assembly 1002. In a particular embodiment, the seed layer etching process is a buffered etching process selective to a desired material such as copper, tungsten, aluminum, silver, or gold. In other embodiments, the etching process is an aqueous etching process. Any suitable wet etching solution or combination of wet etching solutions can be used for the seed layer etching process.

[0096]

[0113] Following the seed layer etching process in Project 1370, one or more electrically functional packages can be singulated from the embedded die assembly 1002. Alternatively, the embedded die assembly 1002 may have one or more rewiring layers 1658 and / or 1660 (shown in FIGS. 16K-16L) formed thereon as needed to enable rerouting of contact points of the wiring portion 1444 to desired locations on the surface of the embedded die assembly 1002. FIG. 15 is a flowchart showing a representative method 1500 of forming a rewiring layer 1658 on the embedded die assembly 1002. FIGS. 16A-16L are cross-sectional views schematically showing the embedded die assembly 1002 at different stages of the method 1500 shown in FIG. 15. Therefore, in this specification, FIGS. 15 and 16A-16L are described together for clarity.

[0097]

[0114] Method 1500 is substantially similar to the methods 900, 1100, and 1300 described above. Method 1500 generally starts with step 1502 and FIG. 16A, where an insulating film 1616 is placed on the embedded die assembly 1002 and then laminated. The insulating film 1616 may be substantially similar to the insulating film 1016 and include one or more layers formed of a polymer-based flowable dielectric material. In certain embodiments, as shown in FIG. 16A, the insulating film 1616 includes a flow layer 1618 and one or more support layers 1622. In certain embodiments, the insulating film 1616 may include a ceramic filler-containing epoxy resin flow layer 1618 and one or more support layers 1622. In another example, the insulating film 1616 may include a photocurable polyimide flow layer 1618 and one or more support layers 1622. The material properties of the photocurable polyimide enable the formation of smaller (e.g., narrower) vias that penetrate the final wiring layer formed therefrom. However, any suitable combination of layers and insulating materials is contemplated for the insulating film 1616. For example, the insulating film 1616 may include a non-photosensitive polyimide, polybenzoxazole (PBO), silicon dioxide, and / or silicon nitride flow layer 1618. Examples of materials suitable for the one or more support layers 1622 include PET and polypropylene (PP).

[0098]

[0115] In some examples, the flow layer 1618 includes a polymer-based flowable dielectric material different from the flow layers 1018a and 1018b described above. For example, the flow layer 1018 may include a ceramic filler-containing epoxy resin, and the flow layer 1618 may include a photocurable polyimide. In another example, the flow layer 1618 is formed of an inorganic dielectric material different from the flow layers 1018a and 1018b. For example, the flow layers 1018a and 1018b may include a ceramic filler-containing epoxy resin, and the flow layer 1618 may include a silicon dioxide layer.

[0099]

[0116] The insulating film 1616 has a thickness of less than about 200 μm, for example, a thickness of about 10 μm to about 180 μm. For example, the insulating film 1616 including the flow layer 1618 and the PET support layer 1622 has a total thickness of about 50 μm to about 100 μm. In a particular embodiment, the flow layer 1618 has a thickness of less than about 60 μm, for example, a thickness of about 5 μm to about 50 μm, for example, a thickness of about 20 μm. The insulating film 1616 is disposed on the surface of the embedded die assembly 1002 where the wiring portion 1444 is exposed, which is coupled to the contact 1030 on the active surface 1028 of the die 1026 and / or coupled to the metallized assembly through-hole 1003 such as the major surface 1005.

[0100]

[0117] After disposing the insulating film 1616, the embedded die assembly 1002 is exposed to a lamination process substantially the same as the lamination process described with reference to steps 908, 916, and 1140. When the embedded die assembly 1002 is exposed to high temperature, the flowable layer 1618 softens and bonds to the insulating layer 1018 already formed on the embedded die assembly 1002. Thus, in certain embodiments, the flowable layer 1618 becomes integrated with the insulating layer 1018 to form an extension thereof. As a result of the integration of the flowable layer 1618 and the insulating layer 1018, the expanded and integrated insulating layer 1018 comes to cover the already exposed wiring portion 1444. Therefore, herein, the combined flowable layer 1618 and insulating layer 1018 are collectively referred to as the insulating layer 1018. However, in other embodiments, a second insulating layer (not shown) is formed on the insulating layer 1018 by laminating the flowable layer 1618 and subsequent curing. In some examples, the second insulating layer is formed of a material layer different from the insulating layer 1018.

[0101]

[0118] In certain embodiments, the lamination process may be a vacuum lamination process performed in an autoclave or other suitable apparatus. In certain embodiments, the lamination process is performed using a hot press process. In certain embodiments, the lamination process is performed at a temperature of about 80°C to about 140°C for about 1 minute to about 30 minutes. In some embodiments, the lamination process includes applying a pressure of about 10 psig to about 100 psig while applying a temperature of about 80°C to about 140°C to the substrate 302 and the insulating film 1616 for about 1 minute to about 30 minutes. For example, the lamination process is performed at a pressure of about 30 psig to about 80 psig and a temperature of about 100°C to about 120°C for about 2 minutes to about 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for about 5 minutes. In a further example, the lamination process is performed at a pressure of about 30 psig to about 70 psig, such as about 50 psig.

[0102]

[0119] In operation 1504 and FIG. 16B, the support layer 1622 and the carrier 1624 are removed from the embedded die assembly 1002 by a mechanical process. After removing the support layer 1622 and the carrier 1624, the embedded die assembly 1002 is exposed to a curing process to fully cure the newly extended insulating layer 1018. In certain embodiments, the curing process is substantially similar to the curing process described with reference to operations 918 and 1150. For example, the curing process is performed at a temperature from about 140° C. to about 220° C. for about 15 minutes to about 45 minutes, for example, at a temperature from about 160° C. to about 200° C. for about 25 minutes to about 35 minutes. For example, the curing process is performed at a temperature of about 180° C. for about 30 minutes. In further embodiments, the curing process in operation 1504 is performed at ambient pressure conditions or conditions close thereto.

[0103]

[0120] The embedded die assembly 1002 is then selectively patterned by laser ablation in operations 1506 and FIG. 16C. Laser ablation in operation 1506 forms a redistribution via 1603 that penetrates the newly extended insulating layer 1018 and exposes a desired wiring portion 1444 for the re-wiring of its contact points. In certain embodiments, the redistribution via 1603 has a diameter from about 5 μm to about 60 μm, for example, from about 10 μm to about 50 μm, for example, from about 20 μm to about 45 μm. In certain embodiments, the laser ablation process in operation 1506 is performed using a 2 CO laser. In certain embodiments, the laser ablation process in operation 1506 is performed using a UV laser. In certain embodiments, the laser ablation process in operation 1506 is performed using a green laser. For example, the laser source can generate a pulsed laser beam having a frequency from about 100 kHz to about 1000 kHz. In one example, the laser source is configured to supply a pulsed laser beam with a wavelength from about 100 nm to about 2000 nm, a pulse duration from about 10E-4 ns to about 10E-2 ns, and a pulse energy from about 10 μJ to about 300 μJ.

[0104]

[0121] When patterning the embedded die assembly 1002, the embedded die assembly 1002 is exposed to a desmear process substantially similar to the desmear processes in steps 922 and 1180. During the desmear process in step 1506, all unwanted residues and fragments formed by laser ablation during the formation of the redistribution via 1603 are removed from the redistribution via 1603, and its surface is cleaned (e.g., purified) for subsequent metallization. In certain embodiments, the desmear process is a wet process. Any suitable aqueous etching solution, solvent, and / or combinations thereof can be used in the wet desmear process. In one example, KMnO 4 solution can be used as the etching solution. In another embodiment, the desmear process is a dry desmear process. For example, the desmear process can be a plasma desmear process using an O 2 / CF 4 mixed gas. In a further embodiment, the desmear process is a combination of a wet process and a dry process.

[0105]

[0122] In step 1508 and FIG. 16D, an optional adhesive layer 1640 and / or a seed layer 1642 are formed on the insulating layer 1018. In certain embodiments, the adhesive layer 1640 is formed from titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combinations thereof. In certain embodiments, the adhesive layer 1640 has a thickness of from about 10 nm to about 300 nm, such as from about 50 nm to about 150 nm. For example, the adhesive layer 1640 has a thickness of from about 75 nm to about 125 nm, such as about 100 nm. The adhesive layer 1640 can be formed by any suitable deposition process including, but not limited to, CVD, PVD, PECVD, ALD, etc.

[0106]

[0123] The optional seed layer 1642 is formed from a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combinations thereof. In certain embodiments, the seed layer 1642 has a thickness of from about 50 nm to about 500 nm, such as from about 100 nm to about 300 nm. For example, the seed layer 1642 has a thickness of from about 150 nm to about 250 nm, such as about 200 nm. In certain embodiments, the seed layer 1642 has a thickness of from about 0.1 μm to about 1.5 μm. Similar to the adhesion layer 1640, the seed layer 1642 can be formed by any suitable deposition process such as CVD, PVD, PECVD, ALD dry process, electroless plating wet process, etc. In certain embodiments, the molybdenum adhesion layer 1640 and the copper seed layer 1642 are formed on the embedded die assembly 1002 to reduce the undercut of the conductive wiring during the subsequent seed layer etching process in step 1520.

[0107]

[0124] In steps 1510, 1512, and 1514 corresponding to FIGS. 16E, 16F, and 16G respectively, a spin-on / spray-on or dry resist film 1650 such as photoresist is applied onto the adhesion surface and / or the seed surface of the embedded die assembly 1002, and then patterned and developed. In certain embodiments, an adhesion promoter (not shown) is applied to the embedded die assembly 1002 before disposing the resist film 1650. By exposure and development of the resist film 1650, the redistribution via 1603 is opened. Thus, patterning of the resist film 1650 can be performed by selectively exposing a portion of the resist film 1650 to UV radiation and then developing the resist film 1650 by a wet process such as a wet etching process. In certain embodiments, the development process of the resist film is a wet etching process using a buffered etching process selective to the desired material. In other embodiments, the resist film development process is a wet etching process using an aqueous etching process. Any suitable wet etching solution or combination of wet etching solutions can be used for the resist film development process.

[0108]

[0125] In steps 1516 and 1518 corresponding to FIGS. 16H and 16I respectively, a rewiring connection portion 1644 is formed through the exposed rewiring via 1603, and then the resist film 1650 is removed. The rewiring connection portion 1644 is formed by any suitable method including electroplating and electroless deposition. In a particular embodiment, the resist film 1650 is removed via a wet process. As shown in FIGS. 16H and 16I, the rewiring connection portion 1644 fills the rewiring via 1603 and protrudes from the surface of the embedded die assembly 1002 when the resist film 1650 is removed. In a particular embodiment, the rewiring connection portion 1644 is formed of copper. In other embodiments, the rewiring connection portion 1644 may be formed of any suitable conductive material including, but not limited to, aluminum, gold, nickel, silver, palladium, tin, etc.

[0109]

[0126] In step 1520 and FIG. 16J, the embedded die assembly 1002 on which the rewiring connection portion 1644 is formed is exposed to a seed layer etching process substantially similar to that of step 1370. In a particular embodiment, the seed layer etching is a wet etching process including rinsing and drying of the embedded die assembly 1002. In a particular embodiment, the seed layer etching process is a wet etching process using a buffered etching process selective to the desired material of the seed layer 1642. In other embodiments, the etching process is a wet etching process using an aqueous etching process. Any suitable wet etching solution or combination of wet etching solutions can be used for the seed layer etching process.

[0110]

[0127] In step 1522 shown in FIGS. 16K and 16L, one or more completed packages 1602 are singulated from the embedded die assembly 1002. However, prior to step 1522, as shown in FIG. 16L, additional redistribution layers can be formed on the embedded die assembly 1002 using the sequences and processes described above (FIG. 16K shows a completed package 1602 having another additional redistribution layer 1658). For example, one or more additional redistribution layers 1660 can be formed on a side surface or surface of the embedded die assembly 1002 opposite the first additional redistribution layer 1658, such as the major surface 1007. Alternatively, one or more additional redistribution layers 1660 can be formed on the same side surface or surface as the first additional redistribution layer 1658 (not shown), such as the major surface 1005. After all desired redistribution layers are formed, the completed package 1602 can be singulated from the embedded die assembly 1002.

[0111]

[0128] FIG. 17 is a diagram schematically showing an exemplary package manufacturing system 1700 for use with the method described herein. By using system 1700, it becomes possible to perform the steps described herein in an efficient and rational manner, thereby facilitating the improvement of the manufacture of semiconductor package devices. System 1700 may include one or more processing stations 1702, each configured to perform one or more steps for manufacturing a semiconductor package device such as package 1602. The processing stations 1702 may be arranged in order with one or more transfer robots 1704 or other transfer devices disposed therebetween, or the processing stations 1702 may be arranged around a centrally disposed transfer robot 1704 or transfer device, such as on a platform-type device, as shown in FIG. 17. In the example of FIG. 17, a system 1700 with four processing stations 1702a, 1702b, 1702c, and 1702d is illustrated, each of which can be used to perform one or more different steps. For example, processing station 1702a may include a laser ablation system for structuring a substrate used as a package frame, processing station 1702b may include a bonding layer station such as a CVD chamber for forming a bonding layer on the substrate, processing station 1702c may include a lamination / curing system such as a processing chamber or oven for performing lamination and / or curing of an insulating layer, and processing station 1702d may include a metallization station for plating or wiring. However, fewer or additional processing stations are also envisioned.

[0112]

[0129] Refer now to FIGS. 18A and 18B. A package structure formed by the method described herein, such as package 1602, can be used for any suitable packaging application and any suitable configuration. In one exemplary embodiment shown in FIG. 18A, four packages 1602 are used to form a stacked DRAM structure 1800. Thus, each package 1602 includes a memory die 1826 (i.e., a memory chip) embedded within a substrate 302 and encapsulated by an insulating layer 1018 (e.g., a portion of each side surface is in contact with the insulating layer 1018). One or more wiring portions 1444 are formed through the entire thickness of each package 1602 and are in direct contact with one or more solder bumps 1846 disposed between the major surfaces 1005 and 1007 of adjacent (i.e., vertically stacked) packages 1602. For example, as shown in the stacked DRAM structure 1800, four or more solder bumps 1846 are disposed between adjacent packages 1602, bridging (e.g., connecting, coupling) the wiring portion 1444 of each package 1602 with the wiring portion 1444 of an adjacent package 1602.

[0113]

[0130] In certain embodiments, to enhance the reliability of the solder bumps 1846, voids between adjacent packages 1602 connected by the solder bumps 1846 are filled with an encapsulating material 1848. The encapsulating material 1848 can be any suitable type of encapsulant or underfill. In one example, the encapsulating material 1848 includes a pre-assembly underfill material such as a no-flow underfill (NUF) material, a non-conductive paste (NCP) material, a non-conductive film (NCF) material, etc. In one example, the encapsulating material 1848 includes a post-assembly underfill material such as a capillary underfill (CUF) material, a mold underfill (MUF) material, etc. In certain embodiments, the encapsulating material 1848 is SiO 2 , AlN, Al 2 O 3 , SiC, Si 3 N 4 , Sr 2 Ce 2 Ti 5 O 16 , ZrSiO 4 , CaSiO3 , BeO, CeO 2 , BN, CaCu 3 Ti 4 O 12 , MgO, TiO 2 , and includes a low-expansion filler-containing resin such as an epoxy resin filled (e.g., containing) with ZnO or the like.

[0114]

[0131] In certain embodiments, the solder bump 1846 is formed of one or more intermetallic compounds such as a combination of tin (Sn) and lead (Pb), silver (Ag), Cu, or any other suitable metal. For example, the solder bump 1846 is formed of a solder alloy such as Sn-Pb, Sn-Ag, Sn-Cu, or any other suitable material or combination thereof. In certain embodiments, the solder bump 1846 includes C4 (flip chip mounting) bumps. In certain embodiments, the solder bump 1846 includes C2 (chip connection such as a Cu pillar with a solder cap) bumps. By using C2 solder bumps, the pitch between contact pads can be reduced, improving the thermal and / or electrical characteristics of the stacked DRAM structure 1800. In some embodiments, the solder bump 1846 has a diameter from about 10 μm to about 150 μm, for example, from about 50 μm to about 100 μm. The solder bump 1846 can be formed by any suitable wafer bumping process including, but not limited to, electrochemical deposition (ECD) and electroplating.

[0115]

[0132] In another exemplary embodiment shown in FIG. 18B, a stacked DRAM structure 1801 is formed by stacking four packages 1602 and directly coupling one or more wiring portions 1444 of each package 1602 to the wiring portions 1444 of one or more adjacent packages 1602. As shown, the packages 1602 can be coupled by hybrid bonding, and the major surfaces 1005 and 1007 of adjacent packages are planarized and in complete contact with each other. Thus, one or more wiring portions 1444 of each package 1602 are formed through the entire thickness of each package 1602 and are in direct contact with at least one or more wiring portions 1444 of another adjacent package 1602.

[0116]

[0133] The stacked DRAM structures 1800 and 1801 provide several advantages compared to conventional DRAM structures. The advantages include a thin form factor and a high die / package volume ratio, enabling larger I / O scaling to meet the increasing bandwidth and power efficiency requirements of artificial intelligence (AI) and high-performance computing (HPC). Using a structured silicon frame provides optimal material stiffness and thermal conductivity for improving the electrical performance, thermal management, and reliability of three-dimensional integrated circuit (3D IC) architectures. Further, the method of manufacturing the assembly through vias and via-in-via structures described herein provides high performance and flexibility for three-dimensional integration at a relatively low manufacturing cost compared to conventional TSV technology.

[0117]

[0134] The embodiments described herein advantageously provide an improved method for structuring a substrate and assembling dies for manufacturing high - density integrated circuit packages. By using the methods described above, high - aspect - ratio features can be formed on glass and / or silicon substrates, and thus, thinner and narrower semiconductor device packages can be economically formed. The thin - form - factor and small packages manufactured using the methods described above offer advantages such as improved high I / O density, bandwidth, and power, as well as improved thermo - mechanical reliability due to improved stress distribution. Further advantages of the methods described above include economical manufacturing due to dual - side metallization capabilities, and high production yields by eliminating flip - chip attachment and over - molding steps where feature damage is likely to occur in the mass production of conventional and advanced packages.

[0118]

[0135] While the foregoing is directed to embodiments of the present disclosure, it is possible to devise other additional embodiments of the present disclosure without departing from its basic scope as determined by the following claims.

Claims

1. A package assembly, comprising: a frame having a first surface and an opposite second surface, further comprising: a frame material including a first material containing silicon; at least one cavity in which a semiconductor die is disposed; a via including a via surface defining an opening extending through the frame from the first surface to the second surface; a bonding layer formed on the frame, including a silane coupling agent and contacting at least the first surface and the second surface; a frame including the above; an insulating layer disposed on the bonding layer on the first surface and the second surface of the frame, contacting at least a part of each side surface of the semiconductor die; an electrical wiring portion disposed in the via; wherein the insulating layer and the bonding layer are disposed between the via surface and the electrical wiring portion. The package assembly.

2. The package assembly according to claim 1, wherein the first material includes silicon carbide or silicon nitride.

3. The package assembly according to claim 1, wherein the at least one cavity extends from the first surface to the second surface.

4. The package assembly according to claim 1, wherein the insulating layer extends through the via and the at least one cavity from the first surface to the second surface.

5. The package assembly according to claim 1, wherein the insulating layer includes an epoxy resin material.

6. The package assembly according to claim 5, wherein the epoxy resin material further includes ceramic particles sized in the range of about 40 nm to about 1.5 μm.

7. The ceramic particles include one or more of aluminum nitride (AlN), aluminum oxide (Al ２ O ３ ), silicon carbide (SiC), silicon nitride (Si ３ N ４ ), Sr ２ Ce ２ Ti ５ O １６ ceramic, zirconium silicate (ZrSiO ４ ), wollastonite (CaSiO ３ ), beryllium oxide (BeO), cerium dioxide (CeO ２ ), boron nitride (BN), calcium copper titanium oxide (CaCu ３ Ti ４ O １２ ), magnesium oxide (MgO), titanium dioxide (TiO ２ ), and zinc oxide (ZnO), and the package assembly according to claim 6.

8. The package assembly according to claim 1, wherein the bonding layer further contacts one or more sidewalls of the at least one cavity and the via surface.

9. The package assembly according to claim 1, wherein the silane coupling agent includes a vinyl functional group, an epoxy functional group, a styryl functional group, an acryloyl functional group, a methacryl functional group, a methacryloyl functional group, an amino functional group, a phenyl functional group, a ureido functional group, an isocyanate functional group, an isocyanurate functional group, or a mercapto functional group.

10. A package assembly, comprising: an embedded die assembly, comprising: a frame including a first material containing silicon; A bonding layer disposed on the frame, the bonding layer including a silane coupling agent; One or more semiconductor dies disposed within the frame, an integrated circuit being formed thereon; An insulating layer formed on the bonding layer, the insulating layer including an epoxy resin material having ceramic particles disposed therein; An embedded die assembly including; One or more metal wiring portions disposed within a part of the embedded die assembly; A package assembly comprising.

11. The frame further includes: One or more cavities extending from a first surface of the frame to a second surface of the frame, one or more semiconductor dies being embedded therein; One or more vias formed within the frame, each of the one or more vias including a via surface defining an opening extending through the frame from the first surface to the second surface, the one or more metal wiring portions being disposed through the one or more vias; The package assembly according to claim 10, including.

12. The package assembly according to claim 11, wherein the bonding layer contacts at least the first surface and the second surface.

13. The package assembly according to claim 12, wherein the bonding layer further contacts one or more sidewalls of the one or more cavities and the via surface.

14. The package assembly according to claim 11, wherein the insulating layer extends through the one or more vias and the one or more cavities from the first surface to the second surface.

15. The ceramic particles include one or more of aluminum nitride (AlN), aluminum oxide (Al ２ O ３ ), silicon carbide (SiC), silicon nitride (Si ３ N ４ ), Sr ２ Ce ２ Ti ５ O １６ ceramic, zirconium silicate (ZrSiO ４ ), wollastonite (CaSiO ３ ), beryllium oxide (BeO), cerium dioxide (CeO ２ ), boron nitride (BN), calcium copper titanium oxide (CaCu ３ Ti ４ O １２ ), magnesium oxide (MgO), titanium dioxide (TiO ２ ), and zinc oxide (ZnO), and the package assembly according to claim 10.

16. The package assembly according to claim 10, wherein the silane coupling agent includes a vinyl functional group, an epoxy functional group, a styryl functional group, an acryloyl functional group, a methacryl functional group, a methacryloyl functional group, an amino functional group, a phenyl functional group, a ureido functional group, an isocyanate functional group, an isocyanurate functional group, or a mercapto functional group.

17. A package assembly, comprising: An embedded die assembly, comprising: A frame including a first material containing silicon; A bonding layer formed on the frame, the bonding layer including a silane coupling agent; One or more semiconductor dies disposed within the frame; A first insulating layer formed on the frame, the first insulating layer including an epoxy resin material containing ceramic particles; One or a plurality of electrical wiring portions disposed through the frame or the first insulating layer; An embedded die assembly including; A rewiring layer formed on the embedded die assembly, A second insulating layer formed on the first insulating layer; One or a plurality of electrical rewiring connection portions disposed through the second insulating layer; A rewiring layer including; A package assembly comprising.

18. The package assembly according to claim 17, wherein the silane coupling agent includes a vinyl functional group, an epoxy functional group, a styryl functional group, an acryloyl functional group, a methacryl functional group, a methacryloyl functional group, an amino functional group, a phenyl functional group, a ureido functional group, an isocyanate functional group, an isocyanurate functional group, or a mercapto functional group.

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