Power semiconductor device having a moisture barrier

Abstract

The power semiconductor device includes a package, a power semiconductor die within the package, and a moisture barrier on an upper surface and a side surface of an outer surface of the package.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 17 / 747,128, filed on May 18, 2022, the entire content of which is incorporated herein by reference.

[0002] The present invention relates to power semiconductor devices, and more particularly to packaged power semiconductor devices.

Background Art

[0003] A power semiconductor device refers to a device that includes one or more power semiconductor dies designed to carry a large current and / or one or more power semiconductor dies capable of blocking a high voltage. In this specification, a power semiconductor die refers to a semiconductor die that can pass a current of at least 1 Amp during normal operation and / or block at least 100 volts during reverse blocking operation. Power semiconductor dies are often made from wide bandgap semiconductor materials such as silicon carbide (「SiC」) or gallium nitride (「GaN」) based semiconductor materials. Various power semiconductor dies are known in the art, including, for example, power metal oxide semiconductor field effect transistors (「MOSFETs」), power insulated gate bipolar junction transistors (「IGBTs」), power Schottky diodes, and the like. Power semiconductor dies are often packaged to provide packaged power semiconductor devices.

[0004] The power MOSFET is one of the widely used power semiconductor dies. The power MOSFET is a three-terminal device having a gate terminal, a drain terminal, and a source terminal, and a semiconductor layer structure often called a semiconductor body. A source region and a drain region separated by a channel region are formed in the semiconductor body, and a gate electrode (which can act as the gate terminal or be electrically connected to the gate terminal) is disposed adjacent to the channel region. The MOSFET may be turned on by applying a bias voltage to the gate electrode (to conduct current through the channel region between the source region and the drain region), or may be turned off by removing the bias voltage (or reducing the bias voltage below the threshold value) (to cut off the current flowing through the channel region).

[0005] Both discrete power-packaged power semiconductor devices and multi-chip power-packaged power semiconductor devices are commercially available. Discrete power-packaged power semiconductor devices include a single power semiconductor die such as a packaged MOSFET, a Schottky diode, an IGBT, etc. A multi-chip power-packaged power semiconductor device refers to a power semiconductor module including two or more power semiconductor dies provided (typically interconnected) within a common package. Discrete packaged power semiconductor devices can be realized at a very low cost and can be easily combined to form more complex circuits, thus constituting most of the power electronics industry.

[0006] Packaged power semiconductor devices typically generate a large amount of heat during device operation. To prevent this heat from damaging the device, the semiconductor die is typically attached to a submount that serves as a heat sink for dissipating heat from the package. For example, copper or aluminum lead frames and / or copper-coated ceramic substrates are commonly used as submounts. The upper side of the submount may be plated with nickel or silver, or another metal that facilitates attaching the semiconductor die to the submount.

Prior Art Documents

Non-Patent Documents

[0007]

Non-Patent Document 1

Summary of the Invention

Means for Solving the Problems

[0008] According to some embodiments of the present invention, there is provided a packaged power semiconductor device including a package, a power semiconductor die within the package, and a moisture barrier on an upper surface and a side surface of an outer surface of the package.

[0009] In some embodiments, the package includes an outer plastic coating. In some embodiments, the moisture barrier is located directly on the outer plastic coating. In some embodiments, the moisture barrier is a conformal moisture barrier that conforms to the outer plastic coating. In some embodiments, the moisture barrier is further located on at least a portion of a bottom of the outer surface of the package.

[0010] In some embodiments, the semiconductor die has a first terminal and a second terminal, and the package further comprises a first lead electrically connected to the first terminal and extending out from the plastic outer coating, and a second lead electrically connected to the second terminal and extending out from the plastic outer coating. In some embodiments, the first lead includes a wide segment extending through the outer surface of the plastic outer coating and a narrow segment extending outward from the wide segment, and the moisture barrier covers at least a portion of the wide segment.

[0011] In some embodiments, the package further comprises a submount, and the semiconductor die is disposed on the upper surface of the submount.

[0012] In some embodiments, the submount comprises a lead frame or a power substrate, and the plastic outer coating and the submount encapsulate the semiconductor die together.

[0013] In some embodiments, the semiconductor die further includes a third terminal located on the side opposite to the first and second terminals of the semiconductor layer structure of the semiconductor die, and the third terminal is electrically connected to the submount.

[0014] In some embodiments, the package includes a submount and a housing, and the moisture barrier completely covers the bottom surface of the submount.

[0015] In some embodiments, the moisture barrier includes at least one of perylene, silicone, polyurethane, or an acrylic material.

[0016] In some embodiments, the moisture barrier comprises a coating having a thickness of 1 to 10 microns.

[0017] In some embodiments, the power semiconductor device is provided in combination with a printed circuit board, the power semiconductor device is installed on the printed circuit board, and a part of the moisture barrier is located between the package and the printed circuit board.

[0018] In some embodiments, the packaged electronic device is installed on a metal pad on the printed circuit board, and the moisture barrier electrically insulates the semiconductor die from the metal pad.

[0019] In some embodiments, the moisture barrier is a first moisture barrier, and the power semiconductor device further includes a second moisture barrier covering the upper surface and the side surfaces of the semiconductor die. In some embodiments, the second moisture barrier further covers a part of the first and second leads.

[0020] In some embodiments, the semiconductor die is a silicon carbide-based vertical MOSFET or a Schottky diode.

[0021] In some embodiments, the semiconductor die is a first semiconductor die, and the power semiconductor device further includes a second semiconductor die in the package.

[0022] In some embodiments, the moisture barrier covers a part but not all of the portions of the first and second leads outside the plastic outer coating.

[0023] According to a further embodiment of the present invention, there is provided a power semiconductor device including a housing, a semiconductor die having a first terminal and a second terminal, and a moisture barrier on the upper surface and the side surfaces of the semiconductor die, and the moisture barrier is positioned between the semiconductor die and the housing.

[0024] In some embodiments, the housing includes a plastic outer coating.

[0025] In some embodiments, the housing and the submount comprise a package for a power semiconductor device, and the semiconductor die is disposed on the top surface of the submount.

[0026] In some embodiments, the submount comprises a lead frame or a power substrate, and the plastic outer coating and the submount encapsulate the semiconductor die together.

[0027] In some embodiments, the package further comprises a first lead electrically connected to a first terminal and a second lead electrically connected to a second terminal, and the moisture barrier further covers portions of the first and second leads located within the plastic outer coating.

[0028] In some embodiments, the moisture barrier is in direct contact with both the semiconductor die and the plastic outer coating.

[0029] In some embodiments, the moisture barrier is a conformal moisture barrier that conforms to the semiconductor die.

[0030] In some embodiments, the moisture barrier and the housing are made of different materials.

[0031] In some embodiments, the moisture barrier is a second moisture barrier, and the power semiconductor device further comprises a first moisture barrier located on the outer surface of the plastic outer coating.

[0032] In some embodiments, the plastic outer coating is located on the top and side surfaces of the submount, and at least a portion of the bottom surface of the submount is free of the plastic outer coating.

[0033] In some embodiments, the first moisture barrier covers the bottom surface of the submount.

[0034] In some embodiments, the moisture barrier comprises at least one of perylene, silicone, polyurethane, or an acrylic material.

[0035] In some embodiments, the moisture barrier comprises a coating having a thickness of 1 to 10 microns.

[0036] In some embodiments, the power semiconductor device is provided in combination with a printed circuit board, the power semiconductor device is installed on the printed circuit board, and a portion of the moisture barrier is located between the plastic outer coating and the printed circuit board.

[0037] In some embodiments, the power semiconductor device is installed on a printed circuit board and includes terminals installed on a heat sink, and the moisture barrier electrically insulates the semiconductor die from the heat sink.

[0038] According to still further embodiments of the present invention, there is provided a manufacturing method for providing a preliminary power semiconductor device in which a semiconductor die having a first terminal and a second terminal is packaged in a package including a submount and a housing. A moisture barrier is formed on the preliminary power semiconductor device to form a power semiconductor device configured to be installed on a printed circuit board.

[0039] In some embodiments, the housing comprises a plastic outer coating. In some embodiments, the moisture barrier is located directly on the outer surface of the plastic outer coating. In some embodiments, the moisture barrier is a conformal moisture barrier that conforms to the outer surface of the plastic outer coating.

[0040] In some embodiments, the package further comprises a first lead and a second lead, and the method further includes electrically connecting the first lead extending outward from the plastic outer coating to the first terminal and electrically connecting the second lead extending outward from the plastic outer coating to the second terminal.

[0041] In some embodiments, the first lead includes a wide segment extending through the outer surface of the plastic outer coating and a narrow segment extending outwardly from the wide segment, and the moisture barrier covers at least a portion of the wide segment.

[0042] In some embodiments, the submount comprises a lead frame or a power substrate, and the plastic outer coating and the submount encapsulate the semiconductor die together.

[0043] In some embodiments, the moisture barrier is formed to completely cover the bottom surface of the package.

[0044] In some embodiments, forming the moisture barrier includes forming the moisture barrier via chemical vapor deposition. In some embodiments, forming the moisture barrier includes forming the moisture barrier by immersing a pre-power semiconductor device in a solution of the moisture barrier material. In some embodiments, forming the moisture barrier includes spraying the moisture barrier material onto the pre-power semiconductor device.

[0045] In some embodiments, the method further includes baking the plastic outer coating at a temperature of at least 120°C to remove moisture from the plastic outer coating prior to forming the moisture barrier.

[0046] In some embodiments, the moisture barrier is formed within 2 hours of the formation of the outer coating plastic or the completion of the baking process applied to the outer coating plastic to remove moisture from the outer coating plastic.

[0047] In some embodiments, the moisture barrier includes at least one of perylene, silicone, polyurethane, or an acrylic material.

[0048] In some embodiments, the moisture barrier comprises a coating having a thickness of 1 to 10 microns.

[0049] In some embodiments, the method further includes placing the power semiconductor device on a printed circuit board such that a portion of the moisture barrier is located between the package and the printed circuit board.

[0050] In some embodiments, the power semiconductor device is placed on a metal pad on the printed circuit board, and the moisture barrier electrically insulates the semiconductor die from the metal pad.

[0051] In some embodiments, the moisture barrier is a first moisture barrier, and the method further includes forming a second moisture barrier that covers the upper and side surfaces of the semiconductor die and portions of the first and second leads, and the second moisture barrier is positioned between the semiconductor die and a second portion of the package.

Brief Description of the Drawings

[0052]

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Figure 8

Best Mode for Carrying Out the Invention

[0053] Note that when multiple similar elements are shown in the figures, they may be identified using reference numerals consisting of two parts. Such elements may be individually referred to herein by their complete reference numerals (e.g., floating lead 136-1), or they may be collectively referred to by the first part of their reference numerals (e.g., floating lead 136).

[0054] Power semiconductor devices are designed to block high voltages during reverse blocking operation and to pass high current levels during on-state operation. For example, a power semiconductor device may need to block hundreds or thousands of volts and / or pass tens or hundreds of amperes. Operation at these voltage and current levels can generate significant heat within the power semiconductor die. Due to the high heat levels, many discrete power semiconductor devices are packaged within a ceramic air cavity package, in which the power semiconductor die is placed on a metal submount and sealed within an air cavity of a ceramic housing (these packages are referred to as ceramic air cavity packages). The ceramic housing and metal submount can withstand the heat generated by the power semiconductor die during operation and can efficiently dissipate this heat. However, the use of ceramic air cavity packages increases both the size and cost of the packaged power semiconductor device.

[0055] Most semiconductor devices operating at low power levels are packaged by enclosing the semiconductor die in a plastic overmold. In recent years, plastic overmold encapsulants suitable for use with power semiconductor devices have been developed. When a plastic overmold encapsulant is used, the semiconductor die is typically placed on a submount and leads are electrically connected to corresponding terminals on the semiconductor die. Then, a plastic overmold material, such as an epoxy molding compound, is injection molded to encapsulate at least a portion of the power semiconductor die and the submount. The leads extend through the plastic overmold encapsulant so that electrical connections can be made between the semiconductor die and external devices (e.g., input, output, bias voltage source, etc.). The submount, leads, and plastic overmold encapsulant together provide a package for the power semiconductor die.

[0056] Discrete packaged power semiconductor devices are typically installed on the printed circuit boards of larger electronic systems. Unfortunately, standard epoxy molding compounds are susceptible to moisture absorption from the environment. This moisture absorption can primarily be in the form of direct diffusion of moisture through the epoxy resin. Moisture absorption into the plastic outer-coated encapsulated power semiconductor die can be problematic. Specifically, the moisture absorbed into the plastic outer coating expands during the soldering reflow process used to attach the discrete power semiconductor device to the printed circuit board of the larger electronic system. As the plastic outer coating expands, it may delaminate from the semiconductor die. In some cases, the plastic outer coating may instead crack or even rupture. Generally speaking, delamination of the outer coating encapsulant can lead to early device failure (e.g., when the device experiences thermal cycles during normal operation, delamination may increase, which can weaken or break the connection between the power semiconductor die terminals and the package leads), while cracking (or rupture) of the plastic outer coating typically results in immediate device failure.

[0057] To reduce the likelihood that moisture absorption can lead to device failure, plastic outer-coated encapsulated power semiconductor devices can be evaluated based on industry-standardized moisture sensitivity criteria published by IPC International, a worldwide association of entities engaged in electronic device manufacturing. This moisture sensitivity criteria is described in Non-Patent Document 1. Non-Patent Document 1 specifies eight different moisture sensitivity levels and, for each level, the maximum length of time that the packaged semiconductor device can be maintained outside of a moisture barrier bag before being soldered to a printed circuit board. For example, an electronic device with a moisture sensitivity rating of "3" in Non-Patent Document 1 should not be maintained outside of a moisture barrier bag for more than one week at a temperature below 30 °C and a relative humidity below 60% in accordance with the standards of Non-Patent Document 1 in order to ensure that there is no increased risk of moisture-induced failure in the device before it is soldered to a printed circuit board.

[0058] A higher moisture sensitivity evaluation level can severely limit the time that an electronic device can be located outside of a moisture barrier bag before being soldered to a printed circuit board of a larger system. For example, an electronic device having the moisture sensitivity evaluation level of "5a" in Non-Patent Document 1 can only be maintained outside of a moisture barrier bag for 24 hours. Electronic equipment manufacturers assembling electronic devices including discrete-packaged power semiconductor devices must take into account the moisture sensitivity evaluation level of the discrete-packaged power semiconductor devices during the manufacturing process to ensure that the devices are not exposed to excessive moisture absorption that could cause damage or destruction of the packaged power semiconductor devices, especially during the solder reflow operation. This can potentially complicate the manufacturing process and increase the risk that a larger electronic system can fail prematurely due to failures induced by moisture absorption of power semiconductor devices included in the larger electronic system.

[0059] According to an embodiment of the present invention, a packaged power semiconductor device including a package and a separate moisture barrier is provided. The outer encapsulant can be formed of a plastic material such as, for example, an epoxy molding compound. The moisture barrier can be conformally coated on the plastic outer encapsulant. As is known in the art, a conformal coating refers to a layer of material that is generally applied (e.g., formed or deposited) on the surface of a underlying structure that conforms to or "follows" the shape of the surface of the underlying structure. A conformal coating generally has a uniform thickness (e.g., less than 10 - 15% variation for portions on a flat surface of the underlying structure, although slightly larger variations can occur at corners or other non-planar regions). The moisture barrier can include any material that significantly or completely prevents moisture ingress into the outer encapsulant. For example, acrylic materials, polyurethanes, silicones, and / or parylene are all materials that can be conformally formed or deposited as coatings that act as such moisture barriers. The moisture barrier can be formed on the plastic outer encapsulant, for example, by automated ovary removal, dipping, condensation processes, or chemical vapor deposition. Adding this moisture barrier to the packaged power semiconductor device can significantly extend the time that the device can remain outside of a moisture barrier bag before being soldered to a customer printed circuit board. The moisture barrier can also reduce the likelihood of device failure induced by moisture during normal operation of the device. The moisture barrier can be applied immediately after formation of the plastic outer encapsulant (e.g., following a baking operation used to cure the plastic outer encapsulant), or can be applied during a subsequent processing step. The packaged power semiconductor device can optionally undergo a slow baking operation designed to remove moisture from the device prior to application of the moisture barrier.

[0060] In some embodiments, the moisture barrier may be applied to substantially or completely cover the plastic outer coating encapsulant material. As used herein, reference to "substantially" means within + / - 10%. The moisture barrier may not be applicable or may only be partially applicable to the exposed metallic elements of a packaged power semiconductor device designed to be soldered to external elements such as metal pads. In other embodiments, the moisture barrier may completely encapsulate the entire body of the packaged power semiconductor device, and only the distal portions of the leads may be moisture-barrier free. In such embodiments, the moisture barrier may be part of the main heat dissipation path from the semiconductor die to an external heat sink, such as a heat sink surface-mounted on a customer printed circuit board. The moisture barrier may be sufficiently thin to have good thermal conductivity and electrically isolate the packaged power semiconductor device from the heat sink.

[0061] As described above, the package leads of a plastic outer-coated encapsulated packaged power semiconductor device extend through the plastic outer coating such that each lead has an encapsulated segment and an exposed segment. In some embodiments, the moisture barrier may extend over a portion of the exposed segment of the lead adjacent to the plastic outer coating encapsulant. This can help ensure that the lead itself does not provide a path for moisture ingress into the outer coating encapsulant. Further, as discussed below, the moisture barrier can advantageously increase the "creepage distance" between adjacent leads, which can improve device performance.

[0062] The above-described moisture barrier is provided (e.g., conformally formed) on the outer surface of the plastic outer coating encapsulant, but the teachings of the present invention are not limited thereto. For example, in other embodiments, the moisture barrier can be formed on the semiconductor die, the submount, and the leads (and optionally the bond wires) after the leads are electrically connected to the terminals of the semiconductor die but before the plastic outer coating is formed to encapsulate the semiconductor die. In such embodiments, the moisture barrier will be located between the semiconductor die and the plastic outer coating encapsulant. This “internal” moisture barrier can be provided as a stand-alone moisture barrier or can be combined with the above-described moisture barrier formed on the outer surface of the plastic outer coating encapsulant.

[0063] Next, embodiments of the present invention will be discussed in further detail with reference to the accompanying figures. It will be appreciated that the features of the various embodiments disclosed herein can be combined in any manner to provide many additional embodiments. Accordingly, while the various features of the present invention are described below with respect to specific examples, it will be appreciated that those features can be added to other embodiments and / or used in place of the exemplary features of other embodiments to provide many additional embodiments. Accordingly, the present invention should be understood to encompass these various combinations. Further, the exemplary embodiments focus on MOSFET embodiments, but it will be appreciated that the same techniques can be used in other packaged electronic devices such as IGBTs, Schottky diodes, gate-controlled thyristors, and the like.

[0064] Figures 1A-1C schematically illustrate a packaged power semiconductor device according to some embodiments of the present invention. Specifically, FIG. 1A is a top perspective view of a packaged power semiconductor device 100, FIG. 1B is a perspective view of the packaged power semiconductor device 100 with the moisture barrier and plastic outer coating removed, and FIG. 1C is a schematic vertical cross-sectional view of the device 100.

[0065] Referring to FIGS. 1A - 1C, the packaged power semiconductor device 100 includes a power semiconductor die 110 disposed on the upper surface of a submount, and the submount in this embodiment comprises a lead frame 130. The power semiconductor die 110 can be a semiconductor device designed to block high voltage levels (e.g., several hundred volts or more) and / or carry large currents. The power semiconductor die 110 can include a semiconductor layer structure, and the semiconductor layer structure can be formed using, for example, silicon, and / or wide bandgap semiconductor materials such as silicon carbide, and / or gallium nitride - based and / or aluminum nitride - based semiconductor systems (e.g., GaN, AlGaN, InGaN, AlN, etc.). Other wide bandgap materials such as devices formed in other III - V group semiconductor systems or II - VI group semiconductor systems may also be used. The power semiconductor die 110 can include, for example, MOSFETs, MISFETs, IGBTs, Schottky diodes, gate - controlled thyristors, etc. The power semiconductor die 110 can have a vertical structure where the upper side of the die includes at least one terminal and the lower side of the die also includes at least one terminal.

[0066] In the illustrated embodiment, the power semiconductor die 110 is a discrete power MOSFET having a vertically extending drift region, and current flows through the drift region during on - state operation. As shown in FIG. 1C, the MOSFET includes a semiconductor layer structure 112. The semiconductor layer structure 112 can be formed of a wide bandgap semiconductor material such as silicon carbide, for example. A gate terminal 114 and a source terminal 116 are provided on the upper surface of the semiconductor layer structure 112, and a drain terminal 118 is disposed on the lower surface of the semiconductor layer structure 112. Each of the terminals 114, 116, 118 can be implemented as an exposed metal pad. Typically, the gate terminal / pad 114 is smaller than the source terminal / pad 116, and the drain terminal 118 can be approximately the same size as or larger than the source terminal / pad 116. Since the source terminal 116 and the drain terminal 118 are located on opposite sides of the semiconductor layer structure 112, the MOSFET 110 is a vertical device.

[0067] The lead frame 130 includes a die attachment region 132 on its upper surface and integrated leads 134. The bottom surface of the MOSFET 110 can be attached to the die attachment region 132 of the lead frame 130 using any suitable bonding material or technique. In the illustrated embodiment, the MOSFET 110 is coupled to the lead frame 130 using a die attach material 122. The drain terminal 118 of the MOSFET 110 is electrically connected to the integrated lead 134 through the die attach material 122 and the lead frame 130. A pair of floating leads 136-1, 136-2 are provided, and one or more bond wires 124 physically and electrically connect the gate terminal 114 and the source terminal 116 on the upper side of the MOSFET 110 to the respective floating leads 136-1, 136-2. In the illustrated embodiment, a single bond wire 124 connects the gate terminal 114 to the floating lead 136-1 while three bond wires 124 connect the source terminal 116 to the floating lead 136-2. It should be noted that, as used herein, the term "bond wire" is used broadly to cover other functionally equivalent structures such as ribbons or clips that can be used in place of a pure wire in addition to a conventional bond wire.

[0068] The plastic outer coating encapsulant 150 encapsulates at least the upper surfaces of the power semiconductor die 110 and the lead frame 130, as well as at least a portion of each side surface of the lead frame 130. The leads 134, 136 extend through the plastic outer coating encapsulant 150 such that each lead 134, 136 has a first segment located within the plastic outer coating encapsulant 150 and a second segment located outside the plastic outer coating encapsulant 150. The plastic outer coating encapsulant 150 covers and protects the MOSFET 110. Although embodiments of the present invention are mainly described with respect to devices including an epoxy molding compound as the outer coating encapsulant, it will be recognized that embodiments of the present invention are not limited thereto. For example, in other embodiments, the encapsulant may include a silicone gel, or another compound. The encapsulant 150 can hold the floating leads 136 in their proper positions.

[0069] The lead frame 130, the leads 134, 136, and the outer coating encapsulant 150 together form a package 120 for the power semiconductor die 110. Although one integrated lead 134 and two floating leads 136 are provided, it will be recognized that embodiments of the present invention are not limited thereto. For example, in other embodiments, three floating leads 136 may be provided and no integrated lead 134 may be provided. It will also be recognized that a plurality of leads may be provided for one or more of the terminals 114, 116, 118 of the power semiconductor die 110. For example, the source terminal 116 and / or the drain terminal 118 may each be connected to two leads. It will also be recognized that the number of terminals and / or the number of leads may be varied according to the type of the semiconductor die 110. For example, a Schottky diode includes only two terminals (an anode terminal and a cathode terminal), and thus, only two leads may be provided for a packaged Schottky diode. The floating leads 136 may initially be integral with the lead frame 130, but may be separated from the lead frame 130 during the manufacturing process and held in place by the outer coating encapsulant 150.

[0070] As best seen in FIG. 1C, a moisture barrier 160 is provided on the outer surface of the plastic outer coating encapsulant 150. The moisture barrier 160 can be formed after the outer coating encapsulant 150 is formed and cured. In some embodiments, the moisture barrier 160 can be conformally formed on the plastic outer coating encapsulant 150. The plastic outer coating encapsulant 150 can include a rigid material that protects the MOSFET 110 during handling. In contrast, the moisture barrier 160 can be a low-rigidity material, and such a material can be applied with a continuous coating that provides a barrier against moisture ingress into the outer coating encapsulant, significantly or completely preventing moisture ingress into the outer coating encapsulant and having good coatability. In an exemplary embodiment, the moisture barrier can include an acrylic material, a polyurethane material, a silicone material, and / or a parylene material. All of these materials can be conformally formed or deposited as a coating, significantly or completely preventing moisture ingress into the outer coating encapsulant.

[0071] The moisture barrier 160 can comprise a thin layer that can be formed / deposited on the outer surface of the plastic outer coating encapsulant 150 and also, optionally, on selected portions of the lead frame 130 and / or leads 134, 136 that extend outside the outer coating encapsulant 150. For example, as shown in FIG. 1C, the moisture barrier 160 can extend over some or all of the side surfaces of the lead frame 130. The moisture barrier 160 can also extend partially over portions of each lead 134, 136 that extend outward from the outer coating encapsulant 150. In an exemplary embodiment, the moisture barrier 160 can have a thickness between 1 and 10 microns. In some embodiments, the moisture barrier 160 can be conformally coated on the plastic outer coating encapsulant.

[0072] The moisture barrier 160 can be formed on the plastic outer coating encapsulant 150, for example, by a spraying or sputtering process. For example, the moisture barrier may be sprayed in liquid form onto the outer coating encapsulant 150 using an automated spraying process that ensures a substantially consistent thickness of the moisture barrier coating (it should be noted that variation in the thickness of the coating at the corners would be expected), and the material can be cured to form the moisture barrier 160. Alternatively, the packaged electronic device 100 may be immersed in a vat of moisture barrier material to form the moisture barrier 160 after the plastic outer coating encapsulant 150 has been formed. Since the distal ends of the leads 134, 136 are typically not coated with the moisture barrier 160 so that the leads 134, 136 can be connected to an external device (e.g., by bond wires), the packaged power semiconductor device 100 can be held by one or more of the leads 134, 136 during this immersion process.

[0073] In still other embodiments, the moisture barrier 160 can be formed by a chemical deposition process. Specifically, after the plastic outer coating encapsulant 150 is formed (including curing), the packaged power semiconductor device 100 can be placed in a chemical vapor deposition chamber, and a source material for the moisture barrier 160 can be injected into the chamber in gaseous form. The packaged power semiconductor device 100 can be positioned in another part of the chamber at a lower temperature and / or pressure, and the gaseous material can condense on the outer surface of the packaged power semiconductor device 100 to form the moisture barrier 160. During any of the fabrication processes discussed above, portions of the packaged power semiconductor device 100 where the moisture barrier should not be applied can be covered with a mask (e.g., Kapton tape, photoresist, etc.). The mask can be removed later, along with any moisture barrier material deposited on the mask. In other cases, fixtures that act as masks can be provided. For example, when chemical vapor deposition is used to form the moisture barrier 160, a fixture can be provided in the chemical vapor deposition chamber that includes openings sized to precisely receive the respective ends of the leads 134, 136 of the packaged power semiconductor device 100. The packaged power semiconductor device 100 can be installed in the chamber by inserting the ends of the leads 134, 136 into the fixture. Thus, all portions of the packaged power semiconductor device 100 except for the leads 134, 136 will be exposed, and the moisture barrier 160 can be formed by chemical vapor deposition to cover the entire exterior of the packaged power semiconductor device except for the ends of the leads 134, 136.

[0074] The moisture barrier 160 can be applied immediately after the formation (including curing) of the plastic outer coating encapsulant 150. This can help ensure that moisture does not penetrate into the plastic outer coating encapsulant 150 prior to the formation of the moisture barrier 160. The packaged power semiconductor device 100 may optionally undergo a slow baking operation designed to remove moisture from the device 100 prior to the application of the moisture barrier 160. For example, the packaged power semiconductor device 100 may be baked at a temperature of 125° C. for at least 8 hours to remove moisture therefrom, and then the moisture barrier 160 may be formed over the outer coating encapsulant 150. Alternatively, the packaged power semiconductor device 100 may be baked at a lower temperature for a longer time, or at a higher temperature for a shorter time. Generally speaking, the longer the baking operation and the higher the temperature, the higher the ability of the baking operation to remove moisture present within the device. The slow bake can be performed, for example, when the moisture barrier 160 is not applied immediately after the formation of the outer coating encapsulant 150.

[0075] It will be appreciated that the materials discussed above that can be used to form the moisture barrier 160, and the techniques for forming the moisture barrier 160 discussed above, can be used to form any of the moisture barriers discussed below that are included in a packaged power semiconductor device according to an embodiment of the present invention.

[0076] As shown in FIG. 1C, leads 134, 136 extend through plastic outer coating encapsulant 150 such that each of leads 134, 136 has an encapsulated segment and an exposed segment. In some embodiments, moisture barrier 160 may extend over portions of the exposed segments of leads 134, 136 adjacent to plastic outer coating encapsulant 150. This can help ensure that leads 134, 136 themselves do not provide a path for moisture ingress into outer coating encapsulant 150. Further, moisture barrier 160 can advantageously increase the "creepage distance" between adjacent leads, where creepage distance refers to the shortest distance along the surface of the dielectric material between two conductive components. In this case, the creepage distance is the distance between the exposed portions of adjacent leads 134, 136 along the surface of the intervening dielectric material. Since moisture barrier 160 covers a portion of leads 134, 136, the creepage distance is increased. This can enable packaged power semiconductor device 100 to be rated for higher operating voltages and / or enable device operation in more demanding contamination environments.

[0077] As the above discussion makes clear, packaged power semiconductor device 100 includes semiconductor die 110 having at least first terminal 114 and second terminal 116. A package including plastic outer coating 150 at least partially covers semiconductor die 110. The package may also include first lead 136-1 electrically connected to first terminal 114 and second lead 136-2 electrically connected to second terminal 116. First and second leads 136-1, 136-2 each extend outwardly from plastic outer coating 150. Moisture barrier 160 is located on the top and side surfaces of plastic outer coating 150.

[0078] In some embodiments, the moisture barrier 160 may be located directly on the top, side, and bottom surfaces of the outer encapsulation package 150. In some embodiments, the first and second terminals 114, 116 may be located on the first surface of the semiconductor layer structure 112 of the semiconductor die 110, and the semiconductor die 110 may further include a third terminal 118 located on the side opposite the first and second terminals 114, 116 of the semiconductor layer structure 112. The package 120 may also include a submount 130, and the semiconductor die 110 may be installed on the top surface of the submount 130. In some embodiments, the moisture barrier 160 may completely cover the bottom surface of the package 120.

[0079] In some embodiments, the moisture barrier 160 includes at least one of parylene, silicone, polyurethane, or an acrylic material, and / or the moisture barrier 160 may have a thickness between 1 and 10 microns. As shown in FIGS. 1A-1B, in some embodiments, the first lead 136-1 can include a wide segment extending through the outer surface of the outer encapsulation package 150 and a narrow segment extending outward from the first wide segment, and the moisture barrier 160 can cover at least a portion of the wide segment.

[0080] In some embodiments, the packaged electronic device 100 may be installed on a printed circuit board such as a custom printed circuit board, and a portion of the moisture barrier 160 may be located between the outer encapsulation package 150 and the printed circuit board. For example, the packaged electronic device 100 may be installed (e.g., using screws or clips) on a metal pad on a custom printed circuit board, and the moisture barrier 160 can electrically insulate the semiconductor die 110 from the metal pad.

[0081] As described above, a packaged power semiconductor device such as device 100 is typically installed on a printed circuit board of a larger electronic system. Those larger printed circuit boards are often referred to as custom motherboards. The packaged power semiconductor device 100 should typically be installed on a heat sink on the custom motherboard so that heat dissipated through the main thermal interface of the packaged power semiconductor device 100 (here, the path through the drain terminal 118 and the lead frame 130) can also be dissipated from the custom motherboard. In many cases, the heat sink is surface-mounted on the custom motherboard. In some cases, the exposed metal portion of the packaged power semiconductor device 100 (e.g., the bottom surface of the submount 130) can be installed on the heat sink. In some cases, the leads 134, 136 of the packaged power semiconductor device 100 can be installed in respective plated through holes of the custom motherboard. In some cases, the exposed metal portion of the packaged power semiconductor device 100 may be installed on the heat sink, and the leads 134, 136 may also be installed in respective plated through holes of the custom motherboard.

[0082] As can be seen from FIG. 1C, the main thermal interface cannot be electrically isolated from the power semiconductor die 110 because the drain terminal 118 is electrically connected to the bottom of the lead frame 130. It is often necessary to electrically isolate the semiconductor die 110 from a heat sink on a customer mother board. This can be achieved by interposing a so-called “thermal pad” in the form of a thin dielectric layer (e.g., a silicone layer) that electrically isolates the power semiconductor die 110 from the heat sink between the packaged power semiconductor device 100 and the heat sink on the customer mother board. The packaged power semiconductor device may be mechanically attached to the customer mother board (e.g., a heat sink for the mother board) with a thermal pad between them using, for example, screws or spring clips, and the device leads may be soldered to the mother board. Using such a thermal pad to electrically isolate the power semiconductor die 110 from the customer mother board is acceptable and convenient for packaged power semiconductor devices operating at low voltage levels (e.g., tens of volts) and current levels. However, for power semiconductor devices designed to block hundreds or even thousands of volts, the capacitive coupling across the thermal pad may be strong enough to adversely affect the performance of the semiconductor device and / or degrade the material of the thermal pad, thereby potentially causing a short circuit between the main thermal interface and the metal pad on the customer mother board. Such a short circuit typically renders the packaged power semiconductor device inoperable and may also damage or even destroy the device.

[0083] FIG. 2 is a schematic cross-sectional view of a discrete-packaged power semiconductor device 200 according to a further embodiment of the present invention. The packaged power semiconductor device 200 is similar to the packaged power semiconductor device 100 discussed above in connection with FIGS. 1A-1C, but further includes a power substrate 240. As will be discussed below, the power substrate 240 includes an insulating substrate that electrically isolates the power semiconductor die 110 from a customer motherboard.

[0084] As can be seen by comparing FIG. 1C and FIG. 2, the difference between the packaged power semiconductor device 200 and the packaged power semiconductor device 100 is that the packaged power semiconductor device 200 further includes (1) a power substrate 240 attached to the bottom surface of the lead frame 130, and (2) a plastic outer coating 250 and a moisture barrier 260 that extend to cover the side surface of the power substrate 240. Accordingly, elements of the packaged power semiconductor device 200 that correspond to or substantially correspond to the corresponding elements of the packaged power semiconductor device 100 are labeled using the same reference numerals as used in FIGS. 1A-1C, and further description of those similar elements is generally omitted. The same convention applies throughout this application.

[0085] As shown in FIG. 2, the power substrate 240 includes a ceramic substrate 242. A lower metal clad layer 246-1 is formed on the lower side of the ceramic substrate 242, and an upper metal clad layer 246-2 is formed on the upper side of the ceramic substrate 242. The lead frame 130 is installed on the upper metal clad layer 246-2 using a substrate mounting material 126. As used herein, the term "power substrate" refers to a dielectric substrate having metal clad layers on both sides thereof. There are two main types of power substrates. The first type is known as an active metal brazed (AMB) power substrate, which includes first and second metal brazing layers 244-1, 244-2 used to bond the first and second metal clad layers 246-1, 246-2 to the ceramic substrate 242 respectively. In contrast to soldering, brazing can be used to bond metals to a dielectric surface. The metal brazing material has some similarities to solder, but the bonding process is carried out at a higher temperature, most typically in a vacuum. The resulting bond is more reliable compared to conventional solder attachment. The second type of power substrate is called a direct bonded substrate (or more typically, a direct bonded copper (DBC) power substrate since the metal clad layers 246-1, 246-2 are typically copper layers). The DBC power substrate is formed by directly pressing the metal clad layers 246-1, 246-2 against the dielectric substrate 242 while heat-treating in a controlled atmosphere. The DBC power substrate is not as reliable as the AMB power substrate.

[0086] The plastic outer coating 250 differs from the plastic outer coating 150 in that it extends to cover the side surfaces of the power substrate 240. The moisture barrier 260 is conformally coated over the plastic outer coating 250 and over selected portions of the power substrate 240 and the leads 134, 136. The lead frame 130, the leads 134, 136, the power substrate 240, and the plastic outer coating 250 form a package 220 for the power semiconductor die 110. The moisture barrier 260 protects the package 220 from moisture ingress. The power substrate 240 functions as a main thermal interface for releasing heat generated in the power semiconductor die 110 from the device package 220.

[0087] The packaged power semiconductor device 200 includes both the lead frame 130 and the power substrate 240, although it will be recognized that the lead frame 130 may be omitted in other embodiments and the integrated lead 134 of the lead frame may be replaced by a third floating lead 136. In such embodiments, the power semiconductor die 110 may be placed directly on the upper cladding layer 246-2 via the die attach material 122.

[0088] The packaged power semiconductor devices 100, 200 of FIGS. 1A-1C and 2 include moisture barriers 160, 260 that do not cover most of the exposed bottom surfaces of the submounts 130, 240. FIG. 3 is a schematic vertical cross-sectional view of a discrete packaged power semiconductor device 300 according to a further embodiment of the present invention that includes a moisture barrier 360 that completely covers the exposed bottom surface of the submount 130.

[0089] As can be seen by comparing FIGS. 1C and 3, the packaged power semiconductor device 300 may be identical to the packaged power semiconductor device 100, except that it includes a moisture barrier 360 that extends to substantially or completely cover the bottom surface of the lead frame 130. Thus, the moisture barrier 360 can completely enclose the entire body of the package 120 such that the moisture barrier 360 may not be present only in the distal portions of the leads 134, 136. The moisture barrier 360 may be part of a heat dissipation path from the semiconductor die 110 to an external heat sink such as a heat sink on a customer printed circuit board. Since the moisture barrier 360 completely encloses the lead frame 130 (other than the integrated lead 134), the moisture barrier 360 electrically isolates the packaged electronic device 300 from a printed circuit board or heat sink (not shown) on which the packaged electronic device 300 is installed. Further, since the moisture barrier 360 can be very thin, the moisture barrier 360 can exhibit good thermal conductivity and thus does not interfere with the heat dissipation path extending therethrough. In some embodiments, the moisture barrier 360 can eliminate the need for a thermal pad between the packaged power semiconductor device and the heat sink and can also eliminate the need to include a power substrate in the packaged power semiconductor device. In other words, in some embodiments, the lead frame of the packaged power semiconductor device can be directly attached to the heat sink without an intervening thermal pad since the moisture barrier 360 can electrically isolate the lead frame 130 from the customer motherboard / heat sink.

[0090] It will be understood that the packaged power semiconductor device 300 includes a lead frame 130, but the packaged power semiconductor device 300 can also include a power substrate 240 (as in the case of the packaged power semiconductor device 200 of FIG. 2), or the packaged power semiconductor device 300 can include a power substrate that replaces the lead frame 130.

[0091] As discussed above, a packaged power semiconductor device that includes a plastic outer coating encapsulant can be particularly susceptible to damage associated with moisture during the solder reflow process often used to install the device on a customer printed circuit board. As noted above, the accumulation of moisture within the plastic outer coating can result in delamination of the plastic outer coating from the semiconductor die or cracking of the plastic outer coating encapsulant. Further, if moisture enters the power semiconductor die, even a much smaller amount of moisture can cause problems. Power semiconductor dies typically include a passivation layer that acts as a moisture barrier, but the top surface of most power semiconductor dies includes metal bond pads that serve as terminals of the device. The passivation layer does not cover these pads so that bond wires or leads can be soldered to the pads. The seam between the metal bond pads and the passivation on the top surface of the semiconductor die can be vulnerable to moisture ingress.

[0092] The moisture barriers 160, 260, 360 described above are provided (e.g., conformally formed) on the outer surface of the plastic outer coating encapsulant, but the teachings of the present invention are not so limited. Specifically, according to further embodiments of the present invention, a packaged power semiconductor device is provided that includes an internal moisture barrier, which is conformally coated on the semiconductor die and the submount after electrical connection to the terminals of the power semiconductor die has been made, but prior to the application of the plastic outer coating encapsulant. The internal moisture barrier can be positioned between the power semiconductor die and the outer coating encapsulant.

[0093] Figure 4A is a schematic vertical cross-sectional view of a packaged power semiconductor device 400 according to a further embodiment of the present invention that includes such an internal moisture barrier 470. As shown in Figure 4A, the packaged power semiconductor device 400 can be very similar to the packaged power semiconductor device 100 discussed above in connection with Figures 1A - 1C. The packaged power semiconductor device 400 differs from the packaged power semiconductor device 100 in two respects. First, the packaged power semiconductor device 400 does not include the external moisture barrier 160 included in the packaged electronic device 100. Second, the packaged power semiconductor device 400 includes an internal moisture barrier 470 that is conformally and directly coated over the semiconductor die 110, the lead frame 130, a portion of the bond wires 124, and the leads 134, 136. The internal moisture barrier 470 is formed after the power semiconductor die 110 is attached to the lead frame 130 and the wire bonds 124 are coupled to the terminals 114, 116 and the floating lead 136. Thus, the internal moisture barrier 470 does not adversely affect the electrical connection to the device 400. The internal moisture barrier 470 can completely cover the upper and side surfaces of the power semiconductor die 110. The internal moisture barrier 470 may also cover a part or all of the upper and / or side surfaces of the lead frame 130. The internal moisture barrier 470 may also cover a portion of the leads 134, 136 and the bond wires 124 (the internal moisture barrier covering the bond wires 124 is not shown in Figures 4A - 4B).

[0094] Accordingly, the packaged power semiconductor device 400 includes a semiconductor die 110 having a first terminal 114 and a second terminal 116, a first lead 136 - 1 electrically connected to the first terminal 114 and a second lead 136 - 2 electrically connected to the second terminal 116, an internal moisture barrier 470 covering the upper and side surfaces of the semiconductor die 110 and a portion of the first and second leads 136 - 1, 136 - 2, and a plastic outer coating 150 covering the internal moisture barrier 470. The internal moisture barrier 470 can be a conformal internal moisture barrier 470 in some embodiments.

[0095] FIG. 4B is a schematic cross-sectional view of a modified version 400' of the packaged power semiconductor device 400 of FIG. 4A. The packaged power semiconductor device 400' is identical to the packaged power semiconductor device 400 except that it further includes the external moisture barrier 160 discussed above in connection with FIGS. 1A-1C. Accordingly, further description of the packaged power semiconductor device 400' is omitted.

[0096] FIG. 5 is a schematic vertical cross-sectional view of a packaged power semiconductor device 500 according to a further embodiment of the present invention. The packaged power semiconductor device 500 is similar to the packaged power semiconductor device 200 except that leads 136-1, 136-2 are directly soldered to their respective terminals 114, 116, eliminating the need for bond wires. Leads 136-1 and 136-2 are shown as extending from different sides of the device 500, as can be better seen in the cross-sectional view of FIG. 5. It will be recognized that any of the embodiments of the present invention discussed herein may have such directly soldered leads used in place of the floating leads 136 that are physically and electrically connected to the terminals 114, 116 through bond wires 124.

[0097] FIG. 6 is a schematic vertical cross-sectional view of a packaged power semiconductor device 600 according to a further embodiment of the present invention. The packaged power semiconductor device 600 is similar to the packaged power semiconductor device 100 except that the integrated lead 134 is replaced by a third floating lead 136-3. The electrical connection between the drain of the power semiconductor die 110 and the third floating lead 136-3 is through the drain terminal 118, die attachment material 122, lead frame 130, and bond wire 124. It will be recognized that any of the embodiments of the present invention discussed herein may have the lead arrangement shown in FIG. 6.

[0098] Embodiments of the present invention have been mainly discussed in relation to a discrete packaged power semiconductor device including a single semiconductor die 110, although it will be recognized that embodiments of the present invention are not so limited. For example, FIG. 7 shows a packaged power semiconductor device 700 in the form of a power semiconductor module including two power semiconductor dies 110-1, 110-2. In an exemplary embodiment, the two power semiconductor dies 110-1, 110-2 can be power MOSFETs electrically connected, for example, in series or in parallel. As shown in FIG. 7, a pair of floating gate leads 136-1, 136-2 are electrically connected by bond wires 124 to the gate terminals 114-1, 114-2 of their respective power semiconductor dies 110-1, 110-2 (in other embodiments, both gate terminals 114 can be connected to a single floating gate lead 136). The source terminals 116-1, 116-2 of each die 110 can be connected to one or more floating source leads 136. The drain terminals 118-1, 118-2 are connected to their respective integrated drain leads 134-1, 134-2 (in other embodiments, a single drain lead 134 electrically connected to the drain terminals of both power semiconductor dies 110-1, 110-2 can be provided). The power semiconductor dies 110-1, 110-2 are encapsulated within an outer coating package 150, and a moisture barrier 160 (e.g., a conformal moisture barrier 160) covers at least the upper and side surfaces of the plastic outer coating enclosure 150. The moisture barrier 160 may also extend partially (or completely cover) over the bottom surface of the plastic outer coating 150. Thus, it will be recognized that the moisture barrier according to embodiments of the present invention can also be applied to a multi-chip module. It will also be recognized that the multi-chip module can alternatively or additionally include the internal moisture barrier 470 discussed above in relation to FIGS. 4A-4B.

[0099] When a packaged power semiconductor device according to an embodiment of the present invention includes a plurality of power semiconductor dies 110, it will be appreciated that the semiconductor dies 110 may be the same or different and may be electrically connected to each other and to the package leads 134, 136 in various ways. Thus, in an exemplary embodiment, a plurality of power MOSFETs connected in series or in parallel may be provided, a plurality of power Schottky diodes connected in series or in parallel may be provided, one or more power MOSFETs and one or more power Schottky diodes may be connected in series or in parallel, and so on.

[0100] FIG. 8 is a flowchart of a method of fabricating a packaged power semiconductor device according to an embodiment of the present invention. As shown in FIG. 8, the process begins with a semiconductor die having a first terminal and a second terminal being placed on a submount (block 800). A first lead is electrically connected to the first terminal and a second lead is electrically connected to the second terminal (block 810). A plastic outer coating is formed that encapsulates at least a portion of the semiconductor die and the submount (block 820). Thus, blocks 800-820 illustrate providing a preliminary power semiconductor device by packaging a semiconductor die within a package that includes a submount, leads, and a housing (here, a plastic outer coating). A moisture barrier is formed on the preliminary power semiconductor device to provide a power semiconductor device configured for installation on a printed circuit board such as a customer motherboard (block 830).

[0101] In some cases, a moisture barrier is formed on the custom motherboard to protect the motherboard from the surrounding environment. This can help protect components on the motherboard (including any packaged power semiconductor device installed on the motherboard) from subsequent moisture ingress, but does not provide protection from damage due to moisture that may occur during the solder reflow process used to install the packaged electronic device on the motherboard. Further, in many cases, it may be desirable to perform a slow baking operation on the electronic device that serves to remove moisture from the device prior to applying any moisture protection. In some cases, the printed circuit board may include components that cannot undergo such a slow bake process, so it may not be possible to perform such a slow baking operation on the printed circuit board.

[0102] Embodiments of the present invention have been discussed above in relation to packaged power semiconductor devices including power semiconductor dies, but it will be recognized that embodiments of the present invention are not so limited. For example, all of the embodiments disclosed herein can include one or more radio frequency (RF) semiconductor dies instead of power semiconductor dies. For example, the semiconductor die included in the packaged power semiconductor device can comprise a high power high electron mobility transistor (HEMT) designed to amplify RF signals.

[0103] The packaged power semiconductor device according to an embodiment of the present invention may be designed to block a voltage of 500 volts or more and may be rated for a current of at least 25 amps. In some embodiments, the packaged power semiconductor device may be designed to block a voltage of at least 750 volts, 1000 volts, or 1500 volts and / or may be rated for a current of at least 50 amps, at least 75 amps, or at least 100 amps. In some embodiments, the packaged power semiconductor device according to an embodiment of the present invention may be designed to block a voltage between 650 volts and 1700 volts and may be rated for a current between 25 amps and 100 amps.

[0104] The embodiments of the present invention have been described above with reference to the accompanying drawings that illustrate the embodiments of the present invention. However, it will be recognized that the present invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth above. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Throughout, like numbers refer to like elements.

[0105] The terms first, second, etc. are used throughout the specification to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present invention, the first element may be referred to as the second element and, similarly, the second element may be referred to as the first element. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0106] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", and / or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0107] When an element such as a layer, region, or substrate is considered to be located "on" another element or to extend "onto" another element, it will be understood that such an element can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is considered to be located "directly on" another element or to extend "directly onto" another element, no intervening elements are present. When an element is considered to be "attached to", "connected to", or "coupled to" another element, it will be understood that the element can be directly attached, directly connected, or directly coupled to the other element, or intervening elements may be present. In contrast, when an element is considered to be "directly attached to", "directly connected to", or "directly coupled to" another element, no intervening elements are present.

[0108] As used herein, relative terms such as "beneath", "above", "upper", "lower", "top", "bottom", etc. may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms are intended to encompass various orientations of the device in addition to the orientation shown in the figures.

[0109] As used herein, the term "plurality" means "two or more".

[0110] Embodiments of the present invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Further, variations from the shapes of the figures are to be expected, for example as a result of manufacturing techniques and / or tolerances.

[0111] In the drawings and in the specification, typical embodiments of the present invention are disclosed, and specific terms are used, but they are used in a merely general and descriptive sense and not for purposes of limitation, and the scope of the present invention is set forth in the following claims.

Claims

1. A package, a power semiconductor die within the package, and a moisture barrier on an upper surface and a side surface of an outer surface of the package A power semiconductor device comprising the above components.

2. The power semiconductor device according to claim 1, wherein the package comprises a plastic outer coating.

3. The power semiconductor device according to claim 2, wherein the moisture barrier is directly located on the plastic outer coating.

4. The power semiconductor device according to claim 3, wherein the moisture barrier is a conformal moisture barrier conforming to the plastic outer coating.

5. The power semiconductor device according to claim 4, wherein the moisture barrier is further located on at least a part of a bottom of the outer surface of the package.

6. The semiconductor die has a first terminal and a second terminal, and the package has a first lead electrically connected to the first terminal and extending out from the plastic outer coating, a second lead electrically connected to the second terminal and extending out from the plastic outer coating The power semiconductor device according to any one of claims 2 to 5, further comprising the above components.

7. The first lead includes a wide segment extending through an outer surface of the plastic outer coating and a narrow segment extending outward from the wide segment, and the moisture barrier covers at least a part of the wide segment. The power semiconductor device according to claim 6.

8. The power semiconductor device according to claim 6 or 7, wherein the package further comprises a submount, and the semiconductor die is installed on an upper surface of the submount.

9. The power semiconductor device according to claim 8, wherein the submount comprises a lead frame or a power substrate, and the plastic outer coating and the submount enclose the semiconductor die together.

10. The semiconductor die further includes a third terminal located on a side opposite to the first and second terminals of the semiconductor layer structure of the semiconductor die, and the third terminal is electrically connected to the submount. The power semiconductor device according to claim 8 or 9.

11. The power semiconductor device according to any one of claims 1 to 7, wherein the package includes a submount and a housing, and the moisture barrier completely covers the bottom surface of the submount.

12. The power semiconductor device according to any one of claims 1 to 11, wherein the moisture barrier includes at least one of parylene, silicone, polyurethane, or an acrylic material.

13. The power semiconductor device according to any one of claims 1 to 12, wherein the moisture barrier comprises a coating having a thickness of 1 to 10 microns.

14. The power semiconductor device according to any one of claims 1 to 13, which is combined with a printed circuit board, is installed on the printed circuit board, and a part of the moisture barrier is located between the package and the printed circuit board.

15. The power semiconductor device according to claim 14, which is installed on a metal pad on the printed circuit board, and the moisture barrier electrically insulates the semiconductor die from the metal pad.

16. The power semiconductor device according to any one of claims 1 to 15, wherein the moisture barrier is a first moisture barrier, and the power semiconductor device further comprises a second moisture barrier that covers the upper surface and the side surface of the semiconductor die.

17. The power semiconductor device according to claim 16, wherein the second moisture barrier further covers a part of the first and second leads.

18. The power semiconductor device according to any one of claims 1 to 17, wherein the semiconductor die is a silicon carbide-based vertical MOSFET or a Schottky diode.

19. The power semiconductor device according to any one of claims 1 to 18, wherein the semiconductor die is a first semiconductor die, and the power semiconductor device further comprises a second semiconductor die in the package.

20. The power semiconductor device according to claim 6, wherein the moisture barrier covers a part but not all of the portions of the first and second leads located outside the plastic outer coating.

21. A housing, A semiconductor die having a first terminal and a second terminal, A moisture barrier on the upper surface and the side surface of the semiconductor die, the moisture barrier being positioned between the semiconductor die and the housing A power semiconductor device comprising.

22. The power semiconductor device according to claim 21, wherein the housing comprises a plastic outer coating.

23. The power semiconductor device according to claim 22, wherein the housing and the submount comprise a package for the power semiconductor device, and the semiconductor die is installed on the upper surface of the submount.

24. The power semiconductor device according to claim 23, wherein the submount comprises a lead frame or a power substrate, and the plastic outer coating and the submount encapsulate the semiconductor die together.

25. The package further comprises a first lead electrically connected to the first terminal, and a second lead electrically connected to the second terminal ; and the moisture barrier further covers portions of the first and second leads located within the plastic outer coating. The power semiconductor device according to claim 24.

26. The power semiconductor device according to any one of claims 22 to 25, wherein the moisture barrier is in direct contact with both the semiconductor die and the plastic outer coating.

27. The power semiconductor device according to any one of claims 21 to 26, wherein the moisture barrier is a conformal moisture barrier that conforms to the semiconductor die.

28. The power semiconductor device according to any one of claims 21 to 27, wherein the moisture barrier and the housing are made of different materials.

29. The power semiconductor device according to claim 24, wherein the moisture barrier is a second moisture barrier, and the power semiconductor device further comprises a first moisture barrier located on the outer surface of the plastic outer coating.

30. The power semiconductor device according to claim 29, wherein the plastic outer coating is located on the top surface and the side surface of the submount, and at least a portion of the bottom surface of the submount is not covered by the plastic outer coating.

31. The power semiconductor device according to claim 29, wherein the first moisture barrier covers the bottom surface of the submount.

32. The power semiconductor device according to any one of claims 21 to 31, wherein the moisture barrier contains at least one of parylene, silicone, polyurethane, or an acrylic material.

33. The power semiconductor device according to any one of claims 21 to 32, wherein the moisture barrier comprises a coating having a thickness of 1 to 10 microns.

34. The power semiconductor device according to any one of claims 21 to 33, which is combined with a printed circuit board, is installed on the printed circuit board, and a part of the moisture barrier is located between the plastic outer coating and the printed circuit board.

35. The power semiconductor device according to claim 34, which is installed on a printed circuit board and includes terminals installed on a heat sink, and the moisture barrier electrically insulates the semiconductor die from the heat sink.

36. Packaging a semiconductor die having a first terminal and a second terminal in a package including a submount and a housing to provide a preliminary power semiconductor device; Forming a moisture barrier on the preliminary power semiconductor device to form a power semiconductor device configured to be installed on a printed circuit board A manufacturing method comprising:

37. The method according to claim 36, wherein the housing comprises a plastic outer coating.

38. The method according to claim 37, wherein the moisture barrier is directly located on the outer surface of the plastic outer coating.

39. The method according to claim 37 or 38, wherein the moisture barrier is a conformal moisture barrier that conforms to the outer surface of the plastic outer coating.

40. The package further comprises a first lead and a second lead, and the method comprises: Electrically connecting the first lead extending outward from the plastic outer coating to the first terminal; Electrically connecting the second lead extending outward from the plastic outer coating to the second terminal The method according to claim 39, further comprising:

41. The first lead includes a wide segment extending through the outer surface of the plastic outer coating and a narrow segment extending outward from the wide segment, and the moisture barrier covers at least a part of the wide segment. The method according to claim 40.

42. The method according to any one of claims 37 to 41, wherein the submount comprises a lead frame or a power substrate, and the plastic outer coating and the submount enclose the semiconductor die together.

43. The method according to any one of claims 36 to 42, wherein the moisture barrier is formed to completely cover the bottom surface of the package.

44. The method according to any one of claims 36 to 43, wherein the step of forming the moisture barrier includes forming the moisture barrier via chemical vapor deposition.

45. The method according to any one of claims 36 to 43, wherein the step of forming the moisture barrier includes forming the moisture barrier by immersing the preliminary power semiconductor device in a solution of a moisture barrier material.

46. The method according to any one of claims 36 to 43, wherein the step of forming the moisture barrier includes spraying a moisture barrier material onto the preliminary power semiconductor device.

47. The method according to any one of claims 37 to 46, further comprising the step of baking the plastic outer coating at a temperature of at least 120 °C to remove moisture from the plastic outer coating prior to forming the moisture barrier.

48. The method according to any one of claims 37 to 47, wherein the moisture barrier is formed within 2 hours of the formation of the outer coating plastic or the completion of the baking process applied to the outer coating plastic to remove moisture from the outer coating plastic.

49. The method according to any one of claims 36 to 48, wherein the moisture barrier includes at least one of parylene, silicone, polyurethane, or an acrylic material.

50. The method according to any one of claims 36 to 49, wherein the moisture barrier comprises a coating having a thickness of 1 to 10 microns.

51. The method according to any one of claims 36 to 50, further comprising the step of installing the power semiconductor device on the printed circuit board such that a portion of the moisture barrier is located between the package and the printed circuit board.

52. The method according to claim 51, wherein the power semiconductor device is installed on a metal pad on the printed circuit board, and the moisture barrier electrically insulates the semiconductor die from the metal pad.

53. The moisture barrier is a first moisture barrier, and the method further includes the step of forming a second moisture barrier that covers the upper surface and the side surfaces of the semiconductor die and a portion of the first and second leads, the second moisture barrier being positioned between the semiconductor die and the second portion of the package, the method according to any one of claims 36 to 52.

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