Vertical power device having a mesa and etched trenches therebetween

Abstract

A vertical semiconductor and a method for fabricating a vertical semiconductor are disclosed. In one embodiment, the fabrication involves providing a precursor comprising a substrate and a drift region covering the substrate. A plurality of trenches are etched from the top surface of the drift region into the drift region such that a plurality of mesas remain on top of the drift region. The plurality of trenches are then filled with a first material. The vertical semiconductor device includes a plurality of mesas extending from the top of the drift region, and there is no regrowth interface between the drift region and the plurality of mesas. The first material fills the trenches between each of the plurality of mesas. At least one first contact is on at least one of the plurality of mesas. At least one second contact covers the bottom surface of the substrate.

Description

Technical Field

[0001] This application claims the priority of U.S. Patent Application No. 17 / 744,604, filed on May 13, 2022, the disclosure of which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to vertical field effect devices having improved performance and efficient fabrication techniques for making such vertical field effect devices.

Background Art

[0003] There are several types of vertical semiconductor devices, each of which can be used for different applications. One notable use of vertical semiconductor devices is for high-power applications. Specifically, devices such as PiN diodes, Schottky diodes, metal-oxide semiconductor field-effect transistors (MOSFETs), and junction field-effect transistors (JFETs) can be rated for high blocking voltages and on-currents and are thus often used for such power applications. Given the continuing pressure to provide devices with lower cost and higher performance, there is a continuing need for new device structures and fabrication techniques that result in higher performance, lower cost, or both.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Means for Solving the Problems

[0005] A vertical semiconductor and a method for manufacturing a vertical semiconductor are disclosed. In one embodiment, the manufacturing involves first providing a precursor comprising a substrate and a drift region covering the substrate, where the substrate and the drift region are doped with a first type of dopant and are formed from a first material system. A plurality of trenches are etched from the top surface of the drift region into the drift region such that a plurality of mesas remain on top of the drift region. The plurality of trenches are then filled with a first material doped with a second type of dopant, the second type having a polarity opposite to that of the first type. At least one first contact is provided on at least one of the plurality of mesas, and at least one second contact is provided covering the bottom surface of the substrate.

[0006] In other embodiments, the vertical semiconductor device includes a substrate and a drift region covering the substrate. The substrate and the drift region are doped with a first type of dopant and are formed from a first material system. A plurality of mesas extend from the top of the drift region, and there is no regrowth interface between the drift region and the plurality of mesas. A first material doped with a second type of dopant fills the trenches between each of the plurality of mesas, and the second type has a polarity opposite to that of the first type. At least one first contact is formed on at least one of the plurality of mesas. At least one second contact is formed covering the bottom surface of the substrate.

[0007] The first material system may be silicon carbide, and the first material may be silicon carbide, silicon, or a metal. During fabrication, the step of filling the plurality of trenches may include providing a first layer of the first material covering the top surface of the drift region such that the plurality of trenches are filled and the plurality of mesas are covered, and planarizing the first layer to expose the plurality of mesas.

[0008] The vertical semiconductor device may be a transistor or a diode. For the transistor, the remainder of the first layer filling the plurality of trenches forms a plurality of gate regions, at least one first contact is a source contact, and at least one second contact is a drain contact. At least one gate contact is provided on at least a portion of the gate layer after planarizing the first layer.

[0009] In some embodiments, at least one gate contact is not provided on at least one gate region, and in other embodiments, at least one gate contact includes a plurality of gate contacts each provided on a corresponding one of the plurality of gate regions.

[0010] In one embodiment, after planarizing the first layer, a second layer is formed from a first material system to cover the plurality of mesas and the remainder of the first layer, and at least one first contact is provided on a portion of the first layer.

[0011] The drift region and the plurality of mesas may be continuously grown such that there is no regrowth interface between the drift region and the plurality of mesas. Further, in some embodiments, the first type of dopant may be an N-type dopant, the second type of dopant may be a P-type dopant, and in other embodiments the reverse is true.

[0012] In one embodiment, each of the plurality of mesas is an elongated stripe such that one of the plurality of trenches is provided between adjacent pairs of the plurality of mesas. Alternatively, each of the plurality of mesas may be a pillar having a horizontal cross-section of substantially any shape such as circular, square, rectangular, polygonal, etc.

[0013] The drift region may have a plurality of regions with different doping concentrations. Each of the plurality of mesas may have a plurality of regions with different doping concentrations. One or more of the plurality of mesas or the drift region may have at least one region with a graded doping profile. The drift region may have at least one charge diffusion layer below the plurality of mesas and at least one drift layer.

[0014] In one embodiment, the doping concentration of the second type with respect to the first material is at least twice the doping concentration of the first type in the plurality of mesas.

[0015] In one embodiment, the width of the narrowest portion of each of the plurality of mesas is between 1 times and 2 times the height of each of the plurality of mesas.

[0016] Those skilled in the art will understand the scope of the present disclosure and notice its additional aspects after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings.

[0017] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate some aspects of the present disclosure and serve to explain the principles of the present disclosure together with the description. For the sake of simplicity and readability, the drawings identify exemplary doping polarities or types (N-type and P-type) for various layers, regions, and / or sections of a vertical semiconductor device. These polarities or types may be reversed in alternative embodiments.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0019] The following examples represent the information necessary for those skilled in the art to implement the examples and show the best mode of implementing the examples. By reading the following description in consideration of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and recognize the uses of these concepts not dealt with in detail herein. These concepts and uses are within the scope of the present disclosure and the appended claims.

[0020] The terms "first", "second", etc. may be used herein to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] When an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it is understood that it may be directly on the other element, or directly extend onto the other element, or intervening elements may further be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, no intervening elements are present. Similarly, when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it is understood that it may directly cover the other element, or directly extend over the other element, or intervening elements may further be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, no intervening elements are present. When an element is referred to as being "connected" or "coupled" to another element, it is further understood that it may be directly connected or directly coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0022] Relative terms such as "below", "above", "upper", "lower", "horizontal", or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the drawings. It is understood that these terms and the matters discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the drawings.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. The terms "comprises", "comprising", "includes", and / or "including", when used herein, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein should be interpreted in a manner that is consistent with the context of this specification and the meaning of the words in the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein. Doping concentration is referred to using the nomenclature aEbcm -3 which represents a × 10 b cm -3 where cm is centimeters. For example, 5E16cm -3 is equal to 5 × 10 16 cm -3 where a is 5 and b is 16. The drawings identify exemplary doping polarities or types (N-type and P-type) for the various layers, regions, and / or sections of the vertical semiconductor device for simplicity and readability. These polarities or types may be reversed in alternative embodiments.

[0025] The present disclosure relates to vertical semiconductor devices such as transistors, diodes, and fabrication techniques for manufacturing the same. In one embodiment, fabrication involves first providing a precursor comprising a substrate and a drift region covering the substrate, wherein the substrate and the drift region are doped with a first type of dopant and are formed from a first material system. A plurality of trenches are etched from the top surface of the drift region into the drift region such that a plurality of mesas remain on top of the drift region. The plurality of trenches are then filled with a first material doped with a second type of dopant, the second type having a polarity opposite to that of the first type. At least one first contact is provided on at least one of the plurality of mesas, and at least one second contact is provided covering the bottom surface of the substrate.

[0026] In other embodiments, a vertical semiconductor device includes a substrate and a drift region covering the substrate. The substrate and the drift region are doped with a first type of dopant and are formed from a first material system. A plurality of mesas extend from the top of the drift region, and there is no regrowth interface between the drift region and the plurality of mesas. A first material doped with a second type of dopant fills trenches between each of the plurality of mesas, the second type having a polarity opposite to that of the first type. At least one first contact is formed on at least one of the plurality of mesas. At least one second contact is formed covering the bottom surface of the substrate. The first material system may be silicon carbide, and the first material may be silicon carbide, silicon, or metal.

[0027] Details of these fabrication techniques and device structures are provided below. Specific examples of junction field effect transistors (JFETs) are shown, but the concepts provided are applicable to other implanted regions of other types of transistors, such as MOSFETs and IGBTs, as well as junction barrier Schottky (JBS) diodes, merged PiN Schottky (MPS) diodes, and similar diodes, by modifying the contact structures and arrangements, as will be understood by those skilled in the art. The figures related to the following text relate to a striped device structure of a conductive channel extending in the plane of the drawing, but the layout is not limited to such a structure. The surface layout may be striped, rectangular, circular, polygonal, etc.

[0028] Figure 1A shows a cross-sectional view of a junction field effect transistor (JFET) 10A of the related art. JFET 10A is a vertical JFET in which current flows vertically through the device between source (S) and drain (D) based on the voltage applied to gate (G). In the illustrated embodiment, JFET 10A includes a substrate 12, a drift region 14 covering the substrate 12, and a channel region 16 covering the drift region 14. The upper portion of the body of JFET 10A is etched to form a mesa 18. Gate regions 20 are formed on both sides of the mesa 18 and extend downward and outward along the upper portion of the body of JFET 10A. Accordingly, the channel region 16 exists between the gate regions 20 in the mesa 18 and between the bottom of each gate region 20 and the top of the drift region 14.

[0029] An ohmic region 22 is formed on the top of the mesa 18, and a source contact 24 is provided on the top of the ohmic region 22. A gate contact 26 is formed in a recess existing on one side of the mesa 18. The gate contact 26 exists covering the horizontal section of each gate region 20. A drain contact 28 exists along the bottom of the substrate 12.

[0030] As shown, the body of JFET 10A is silicon carbide (SiC), but other semiconductor material systems such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga 2 O 3 ), and diamond are applicable. The substrate 12, drift region 14, channel region 16, and gate region 20 may be SiC, and each section is formed by implanting N-type or P-type dopants at different positions and concentrations within the body of JFET 10A. In the example shown, the substrate 12 is moderately doped with an N-type dopant, the drift region 14 is moderately doped with an N-type dopant, the channel region 16 is moderately doped with an N-type dopant, the gate region 20 is heavily doped with a P-type dopant, and the ohmic region 22 is heavily doped with an N-type dopant. As will be understood by those skilled in the art, the actual and relative doping levels for each region of JFET 10A depend on the desired characteristics of JFET 10A and may vary from one application to another. The polarity of the doping for each region may be reversed from that shown in the following examples. The source contact 24, gate contact 26, and drain contact 28 may be formed from a suitable metal or other highly conductive material.

[0031] The vertical portion of mesa 18 that exists between gate regions 20 provides a JFET conducting gap (CG). The section shown is a cross-section of a complete repeating cell in a larger device comprising a number of cells, and the number of cells is striped in the Z direction (into the page). Mesa 18 is formed by an etching process, and gate regions 20 are formed using inclined implants at different orientations. In the example shown, the implants are performed at four different angles. Thus, fabrication of this embodiment is a complex process, and the more complex the process, the more expensive the device fabrication becomes. Adding further complication to the problem, the amount of P-type dopant required along the sides of mesa 18 to form gate regions 20 correlates with the angle of the sidewalls of mesa 18. Inclined implants are performed in four incident directions to achieve P+ type gate regions 20, and the P+ type gate regions 20 generally surround each stripe of the N-type channel region 16 within mesa 18. Thus, etching control for the formation of mesa 18 is a critical, complex, and relatively expensive process.

[0032] FIG. 1B is a cross-sectional SEM image of the device showing gate contact 26 and source finger S running in the z direction. Further information can be found in Non-Patent Document 1, which is hereby incorporated by reference in its entirety.

[0033] FIG. 2 shows another JFET structure 10B of the related art including a P+-type gate stripe 30 embedded in an N-type drift region 32. The drift region 32 exists covering an N+-type SiC substrate 34, and this N+-type SiC substrate 34 includes a drain contact 36 at its bottom. The gate stripe 30 is made by forming a P-type layer (not shown) and etching the layer to leave the shown gate stripe 30. Then, N-type material is used to fill the trenches between the gate stripes 30, providing a layer of N-type material covering the gate stripe 30 and providing the remainder (i.e., the upper part) of the drift region 32 such that the gate stripe 30 is embedded in the drift region 32. The upper part of the drift region 32 between the gate stripes 30 is the channel region. A drawback of this kind of process is that the channel region and the drift region 32 through which current flows in the JFET 10B are not continuously grown. Each time current needs to flow through an interface that was reopened after the growth process was stopped, inefficiencies are induced by breaks in the lattice structure of the interface between the two regions.

[0034] An ohmic contact 38 is formed on top of the layer where the source contact 40 exists. A gate contact 42 is connected to a gate region 30A formed in the gate stripe 30, and thus all gate regions 30A or gate stripes 30 are connected. Long gate stripes result in high resistance, slowing down the switching speed, and a portion of the drift region 32 is formed by epi regrowth after etching. Unfortunately, the drift region 32 is a critical semiconductor portion through which all device current flows and should be as defect-free as possible to optimize performance. Further information can be found in Non-Patent Document 2, the entirety of which is hereby incorporated by reference into this specification. As provided in the following examples, the improvement from the related art is brought about by having a channel region formed in the original epitaxial layer to avoid defects inherent in the regrowth process.

[0035] Figures 3A to 3F show a first exemplary process for fabricating a vertical semiconductor device according to an embodiment of the present disclosure. First, as shown in FIG. 3A, a precursor 50 is provided. The precursor 50 may be continuously grown SiC or the like having a substrate 52 doped with an N-type dopant at a high concentration (N+), a drift region 54 covering the substrate doped with an N-type dopant at a moderate concentration (N), and an ohmic layer 56 covering the drift region 54 doped with an N-type dopant at a high concentration (N+). The ohmic layer 56 may be continuously grown together with the precursor 50 as described above, or may be grown as a separate epitaxial layer.

[0036] Next, a trench 58 is etched into the top surface of the precursor 50, and the trench 58 is located at a position where a gate region 64 (FIGS. 3D and 3E) will be formed in a later step, as shown in FIG. 3B. The unetched portions of the precursor 50 between the trenches 58 are referred to as mesas 60. Each mesa 60 provides a channel region 62 and an ohmic region 64 on top of the channel region 62. The ohmic region 64 of each mesa 60 is formed from the unetched portion of the ohmic layer 56, while each channel region 62 is formed from the unetched portion of the drift region 54.

[0037] When the trench 58 is formed, as shown in FIG. 3C, a gate layer 66 is formed in the trench 58 and covering the top of the ohmic region 64 of the mesa 60. The gate layer 66 is doped with a P-type dopant. In the illustrated embodiment, the gate layer 66 is P-type silicon carbide, but a suitable P-type conductor such as P-type silicon or nickel oxide may also be used. For P-type silicon, the use of an epitaxial film is not essential. The trench 58 may simply be filled with P-type silicon by chemical vapor deposition or other similar film-forming methods. Other materials for the gate layer and / or the gate region 68 include any other P-type material that is chemically compatible with SiC. At this point, if necessary, as shown in FIG. 3D, the gate layer 66 is then planarized using an etching process or the like to remove the upper portion of the gate layer 66 that extends above the top surface of the mesa 60 so that the ohmic region 64 is exposed. The remaining portion of the gate layer 66 that fills the trench 58 provides the gate region 68.

[0038] After planarization, as shown in FIG. 3E, a gate contact 70 is formed on the top of each gate region 68, and a source contact 72 is formed on the ohmic region 64 that is on the channel region 62 of each mesa 60. If the drain contact 74 has not already been provided on the precursor 50, the drain contact 74 is formed at the bottom of the substrate 52 at this point. In one embodiment, the mesa 60, the channel region 62, the gate region 68, the source contact 72, and the gate contact 70 are straight stripes that extend in FIG. 3E. These features may assume various shapes, as will be further described below.

[0039] An alternative process for forming the source contact 72 is provided in FIG. 3F. The process up to FIG. 3D remains the same as described above. Thus, the gate contact 70 is formed on top of each gate region 68, but the source contact 72 is not formed as a stripe at this stage. Instead, a dielectric 83, such as a suitable gate oxide 83, is formed covering the gate contact 70 such that the ohmic region 64 on top of the channel region 62 remains exposed. Next, a metal or other conductive material is formed covering the top of the precursor 50 to form an integrated source contact 72'. This integrated source contact 72' covers the dielectric 83 and the ohmic region 64 such that the integrated source contact 72' is in electrical contact with the ohmic region 64 and electrically insulated from the gate contact 70.

[0040] For these embodiments, no tilt implantation as required for the JFET 10A of FIGS. 1A and 1B is necessary, and instead of the P-type layer as done in the JFET of FIG. 2, trench etching is used on the N-type SiC of the precursor 50. Thus, instead of the regrown epitaxial structure as required for the JFET 10B of FIG. 2, current flows through the continuously grown N-type epitaxial channel region 62 and drift region 54.

[0041] In a selected embodiment, the substrate 52 is heavily doped with an N-type dopant at an exemplary concentration in the range of 1E18 to 1E19 cm -3 , 1E19 to 1E20 cm -3 , or 1E18 to 1E19 cm -3 , the drift region 54 is moderately doped with an N-type dopant at an exemplary concentration in the range of 1E15 to 2E16 cm -3 , 1E16 to 2E17 cm -3 , or 1E15 to 2E17 cm -3 , and the channel region 62 is doped at an exemplary concentration in the range of 1E15 to 2E16 cm -3 , 1E16 to 2E17 cm -3 , or 1E15 to 2E17 cm -3At an exemplary concentration within the range, it is moderately doped with an N-type dopant. The gate region 68 has a concentration in the range of 5E16 to 1E18 cm -3 , 1E18 to 1E20 cm -3 , or 5E16 to 1E20 cm -3 At an exemplary concentration within the range, it is highly doped with a P-type dopant. The ohmic region 64 has a concentration in the range of 1E18 to 1E19 cm -3 , 1E19 to 1E21 cm -3 , or is highly doped with an N-type dopant at an exemplary concentration in the range of 1E18 to 1E21.

[0042] In one embodiment, the doping concentration level of the gate region 68 is at least 1.5 times, 2 times, or 2.5 times that of the channel region 62. The channel region 62 is provided by a mesa 60 that extends vertically upward from the top of the drift region 54. Generally, the doping of the gate region 68 should be high enough to deplete the channel region 62 under reverse bias conditions. The height of the mesa 60 (channel region 62) may be from 1 times to 2 times (1X to 2X) the width of the mesa 60 (channel region 62). The width of the trench 58 may be in the range of 0.5 micron to 5 microns, 0.75 micron to 4 microns, 1 micron to 3.5 microns, 1 micron to 4 microns, and 1.5 to 3.5 microns.

[0043] The concepts provided are particularly beneficial for power applications. Such applications are defined as having a blocking voltage greater than 400V during reverse bias, being able to pass a current greater than 1A during forward bias, and / or having a power rating of at least 2 watts.

[0044] These are merely exemplary doping levels and dimensions, and embodiments incorporating the inventive concepts described herein and within the scope of the appended claims may fall anywhere within or outside the ranges described above, depending on the desired performance parameters of the device. Unless otherwise specified, these exemplary doping concentrations apply to the following examples. When graded doping levels are considered, the graded doping profile may span the range from the lower limit to the upper limit of the specified range, and the concentration may be increased or decreased from the bottom to the top of a particular region.

[0045] Other embodiments are shown in FIGS. 4A - 4C. The process is the same as the process of FIGS. 3A - 3D, except that the ohmic region 64 at the top of the mesa 60 is optional. When the gate layer 66 is planarized to form various gate regions 68, as shown in FIG. 4A, an insulating layer 79 is added to cover a portion of the top surface of the precursor 50 using deposition and etching processes, etc., and an ohmic layer 80 is added to cover the top surface of the insulating layer 79. The insulating layer 79 and the ohmic layer 80 cover the gate regions 68 and a portion of the channel region 62, and one or more source contacts 82 will be added thereto. Next, as shown in FIG. 4B, one or more source contacts 82 are formed on the ohmic layer 80. As shown in FIG. 4C, in this step or a separate step, the gate contact 84 may be formed directly on the exposed gate region 68G. The gate contact 84 makes an ohmic contact with the P - type gate region 68G, and the P - type gate region 68G is an extension of the gate region 68 but does not make an ohmic contact with the source contact 82. In other words, the metals of each source contact 82 and the gate contact 84 are insulated from each other. The insulating layer 79 and the ohmic layer 80 may be formed as an integral layer having different N - type doping levels or formed in separate steps.

[0046] In this embodiment, as shown in FIG. 4C, the gate connector region 68G is formed perpendicular to the various gate regions 68 and intersects the various gate regions 68, and the various gate regions 68 are elongated stripes in this embodiment. The gate contact 84 is present on the gate connector region 68G, and there is no N-type material such as the ohmic layer 80 between the gate contact 84 and the gate connector region 68G. In order to provide an ohmic region to facilitate the electrical connection between the gate contact 84 and the gate connector region 68G, the upper part of the gate connector region 68G or an additional layer on the gate connector region 68G may be doped (P-type) at a high concentration. The gate region 68 may also be epitaxially grown together with the rest of the precursor 50, or may be formed from deposited silicon or other P-type materials. This is possible because the P-type gate material does not conduct the primary device current.

[0047] For any of the embodiments described herein, by using uniform and / or graded doping profiles, any of the various regions and layers can have the same or different doping levels. FIG. 5 shows some of these concepts, and these concepts may be provided individually or in combination. The drift region 54 may be divided into a plurality of layers 88, 90, and the charge diffusion layer 86 may be provided near the upper part of the drift region 54 and directly below the mesa 60 such that the mesa 60 effectively extends from the charge diffusion layer 86. One or more drift layers 88, 90 may be provided below the charge diffusion layer 86. Each of these layers may have a uniform or graded doping profile. Further, the channel region 62 may have a uniform or graded doping profile 62P in combination with any of the doping combinations of the drift region 54. These doping options provide the designer with the ability to adjust the electrical characteristics of the device, such as the on-state characteristics and the off-state characteristics.

[0048] Figures 6 and 7A - 7J show an embodiment in which the N - type mesa 60 and the channel region 62 have a pillar shape, as opposed to the elongated stripe of the foregoing embodiments. The pillar - shaped channel region 62 may have a horizontal cross - section of virtually any shape, such as square, rectangular, circular, octagonal, hexagonal, triangular, etc. This grid - like layout can reduce the gate resistance by reducing the contact connection distance. Such an embodiment can provide a larger source contact 82, as shown for the foregoing embodiments, while at the same time reducing the layout issues associated with having to accommodate a large number of elongated gate contacts 84. The N - type insulating layer 79 and the ohmic layer 80 effectively insulate the source contact 82 from the gate region 68.

[0049] Figures 7A - 7K show the notable steps of an exemplary fabrication process of the embodiment of FIG. 6. FIG. 7A is a top view of the precursor 50 after the etching step, and FIG. 7B is a side view of the precursor 50 after the etching step. In this embodiment, the mesa 60 has a square cross - section and is aligned in a grid pattern. FIG. 7C is a top view of the precursor 50 after the gate layer 66 (not shown) has been planarized to form the gate region 68, and FIG. 7D is a side view of the precursor 50 after the gate layer 66 (not shown) has been planarized to form the gate region 68. In this embodiment, there is a gate area 68G in the precursor reserved for the gate contact 84 (not shown) without having the mesa 60. Notably, the portion of the gate region 68 in the gate area 68G is integrally formed and is connected to those portions surrounding the mesa 60. The mesa 60 provides the channel region 62, and the upper part of the mesa 60 is highly doped to provide the ohmic contact 64.

[0050] FIG. 7E is a top view of the precursor 50 after the insulating layer 79 is formed to cover the active region of the device, and FIG. 7F is a side view of the precursor 50 after the insulating layer 79 is formed to cover the active region of the device. FIG. 7G is a top view of the precursor 50 after the N-type ohmic layer 80 is provided to cover the insulating layer 79 such that the N-type insulating layer 79 and the ohmic layer 80 do not cover the gate region 68G, and FIG. 7H is a side view of the precursor 50 after the N-type ohmic layer 80 is provided to cover the insulating layer 79 such that the N-type insulating layer 79 and the ohmic layer 80 do not cover the gate region 68G. As shown in FIGS. 7I to 7K, after the N-type ohmic layer 80 is provided, the source contact 82 is provided on the ohmic layer 80, and the gate contact 84 is provided on the gate region 68G. The source contact 82 and the gate contact 84 are separated from each other. FIGS. 8A, 8B, and 8C show mesas having a hexagonal cross section and corresponding to FIGS. 7A, 7C, and 7E.

[0051] Regarding the source contact configuration as shown in FIG. 3F, FIGS. 9A to 9K are referred to. FIG. 9A is a top view of the precursor 50 after the etching step, and FIG. 9B is a side view of the precursor 50 after the etching step. In this embodiment, the mesa 60 has a square cross section and is aligned with the grid pattern. FIG. 9C is a top view of the precursor 50 after the gate layer 66 (not shown) is planarized to form the gate region 68, and FIG. 9D is a side view of the precursor 50 after the gate layer 66 (not shown) is planarized to form the gate region 68. In this embodiment, there is a gate region 68G in the precursor secured for the gate contact 84 (not shown) without the mesa 60. It should be noted that the portion of the gate region 68 in the gate region 68G is integrally formed and is connected to those portions surrounding the mesa 60. The mesa 60 provides the channel region 62, and the upper part of the mesa 60 is doped at a high concentration to provide the ohmic contact 64.

[0052] FIG. 9E is a top view of the precursor 50 after the dielectric layer 83' is formed covering the active region of the device, and FIG. 9F is a side view of the precursor 50 after the dielectric layer 83' is formed covering the active region of the device. FIG. 9G is a top view of the precursor 50 after the opening 85 is formed in the dielectric layer 83 to expose the ohmic region 64 of the channel region 62, and FIG. 9H is a side view of the precursor 50 after the opening 85 is formed in the dielectric layer 83 to expose the ohmic region 64 of the channel region 62. The dielectric layer 83 is formed or etched so as not to cover the gate region 68G. As shown in FIGS. 9I - 9K, the source contact 82 is provided on the dielectric layer 83 and within the opening 85 to cover the exposed surface of the ohmic layer 64. The gate contact 84 is provided on the gate region 68G.

[0053] As described above, embodiments such as those discussed in FIG. 5 may have various doping profiles and additional layers. Such embodiments are shown in FIG. 10. Note that the charge diffusion layer 86 and the drift layers 88, 90 are present in the drift region 54. Each of those layers, as well as the mesa 60 or the source region 62, may also have a graded doping profile. FIG. 11 shows a deformed form in which the mesa 60 / source region 62 has an elongated rectangular cross - section and various regions are doped as described above in relation to FIGS. 5, 6, and 10.

[0054] As described above, the concepts provided herein may be applied to various types of vertical semiconductor devices. FIGS. 12 and 13 show exemplary vertical diode structures of vertical diodes 90A and 90B, respectively. The fundamental differences between the above - described transistor devices and the vertical diodes 90A and 90B are the absence of a gate contact and the extension of the source contact 92 and the underlying active region. The details and structure of the precursor 50 are essentially the same.

[0055] The diode 90A of FIG. 12 provides a grid of the mesa 60 for the source region 62. The mesa 60 is formed using an etching process, and the resulting trench is filled with P-type material using a deposition process or a growth process, generating a P region 96 (i.e., the gate region). The trench and the resulting P region 96 result in a cross-hatch pattern surrounding most of the mesa 60.

[0056] The diode 90B of FIG. 13 is further different in that the mesas 60 are interconnected to form a cross-hatch pattern. The P region 96 is formed in a hole etched in the drift region 54 and filled with P-type material. The hole, and thus the P region 96, may assume virtually any geometric shape, such as having a horizontal cross-section that is square, rectangular, round, hexagonal, octagonal, triangular, etc. In this embodiment, the mesas 60 form a cross-hatch pattern surrounding individual P regions and P regions 96 that are mostly unconnected. The doping and additional layers provided in FIGS. 9 and 10 may be applied to the embodiments of FIGS. 12 and 13.

[0057] Those skilled in the art will recognize additional improvements and modifications to the disclosed embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the scope of the appended claims.

Claims

1. A method of fabricating a vertical semiconductor device, comprising: providing a precursor comprising a substrate and a drift region covering the substrate, wherein the substrate and the drift region are doped with a dopant of a first type; etching a plurality of trenches from a top surface of the drift region into the drift region such that a plurality of mesas remain on top of the drift region; filling the plurality of trenches with a first material doped with a dopant of a second type, wherein the second type has a polarity opposite to that of the first type; providing at least one first contact on at least one of the plurality of mesas; providing at least one second contact covering a bottom surface of the substrate and including.

2. The method according to claim 1, wherein the drift region is silicon carbide.

3. The method according to claim 2, wherein the first material is silicon carbide.

4. The method according to claim 3, wherein the first material is silicon.

5. The method according to claim 4, wherein the first material is a metal.

6. The step of filling the plurality of trenches includes: providing a first layer of the first material covering the top surface of the drift region such that the plurality of trenches are filled and the plurality of mesas are covered; and planarizing the first layer to expose the plurality of mesas. The method according to claim 1.

7. The vertical semiconductor device is a transistor, a remaining portion of the first layer filling the plurality of trenches forms a plurality of gate regions, the at least one first contact is a source contact, the at least one second contact is a drain contact, and further comprising providing at least one gate contact on at least a portion of the first layer after planarizing the first layer. The method according to claim 6.

8. The method according to claim 7, wherein the at least one gate contact is not provided on the plurality of gate regions.

9. The method according to claim 7, wherein the at least one gate contact includes a plurality of gate contacts respectively provided on a corresponding one of the plurality of gate regions.

10. After planarizing the first layer, further comprising the step of providing a second layer covering the plurality of mesas and the remainder of the first layer, wherein the at least one first contact is provided on a portion of the first layer, the method according to claim 6.

11. The method according to claim 1, wherein the drift region and the plurality of mesas are continuously grown such that no regrowth interface exists between the drift region and the plurality of mesas.

12. The method according to claim 1, wherein the dopant of the first type is an N-type dopant and the dopant of the second type is a P-type dopant.

13. The method according to claim 1, wherein each of the plurality of mesas is an elongated stripe such that one of the plurality of trenches is provided between adjacent pairs of the plurality of mesas.

14. The method according to claim 1, wherein each of the plurality of mesas is a pillar.

15. The method according to claim 14, wherein each of the pillars has a circular horizontal cross-section.

16. The method according to claim 15, wherein each of the pillars has a square horizontal cross-section.

17. The method according to claim 16, wherein each of the pillars has a polygonal horizontal cross-section.

18. The method according to claim 1, wherein the drift region includes a plurality of regions having different doping concentrations.

19. The method according to claim 1, wherein each of the plurality of mesas has a plurality of regions having different doping concentrations.

20. The method according to claim 1, wherein at least one of the plurality of mesas or the drift region has at least one region with a graded doping profile.

21. The method according to claim 1, wherein the drift region includes at least one charge diffusion layer below the plurality of mesas and at least one drift layer.

22. The method according to claim 1, wherein the vertical semiconductor device is a diode.

23. The method according to claim 1, wherein the doping concentration of the second type with respect to the first material is at least twice the doping concentration of the first type in the plurality of mesas.

24. The method according to claim 1, wherein the width of the narrowest portion of each of the plurality of mesas is between 1 times and 2 times the height of each of the plurality of mesas.

25. The method according to claim 1, wherein the substrate and the drift region include a first material system.

26. A vertical semiconductor device, a substrate, a drift region covering the substrate, wherein the substrate and the drift region are doped with a first-type dopant, the drift region, a plurality of mesas extending from the upper part of the drift region, wherein no regrowth interface exists between the drift region and the plurality of mesas, the plurality of mesas, a first material doped with a second-type dopant and filling trenches between respective ones of the plurality of mesas, wherein the second type has a polarity opposite to that of the first type, the first material, at least one first contact on at least one of the plurality of mesas, and at least one second contact covering the bottom surface of the substrate comprising a vertical semiconductor device.

27. The vertical semiconductor device according to claim 26, wherein the drift region is silicon carbide.

28. The vertical semiconductor device according to claim 27, wherein the first material is silicon carbide.

29. The vertical semiconductor device according to claim 28, wherein the first material is silicon.

30. The vertical semiconductor device according to claim 29, wherein the first material is a metal.

31. Further comprising a first layer of the first material filling a plurality of trenches, wherein the vertical semiconductor device is a transistor, the first material filling the plurality of trenches forms a plurality of gate regions, the at least one first contact is a source contact, the at least one second contact is a drain contact, and further comprising at least one gate contact on at least a part of the first layer, the vertical semiconductor device according to claim 26.

32. The vertical semiconductor device according to claim 31, wherein the at least one gate contact is not provided on the plurality of gate regions.

33. The vertical semiconductor device according to claim 31, wherein the at least one gate contact includes a plurality of gate contacts respectively provided on a corresponding one of the plurality of gate regions.

34. The vertical semiconductor device according to claim 26, wherein the drift region and the plurality of mesas are continuously grown so that no regrowth interface exists between the drift region and the plurality of mesas.

35. The vertical semiconductor device according to claim 26, wherein the dopant of the first type is an N-type dopant and the dopant of the second type is a P-type dopant.

36. The vertical semiconductor device according to claim 26, wherein each of the plurality of mesas is an elongated stripe such that one of the plurality of trenches is provided between adjacent pairs of the plurality of mesas.

37. The vertical semiconductor device according to claim 26, wherein each of the plurality of mesas is a pillar.

38. The vertical semiconductor device according to claim 37, wherein each of the pillars has a circular horizontal cross-section.

39. The vertical semiconductor device according to claim 38, wherein each of the pillars has a square horizontal cross-section.

40. The vertical semiconductor device according to claim 39, wherein each of the pillars has a polygonal horizontal cross-section.

41. The vertical semiconductor device according to claim 26, wherein the drift region includes a plurality of regions having different doping concentrations.

42. The vertical semiconductor device according to claim 26, wherein each of the plurality of mesas has a plurality of regions having different doping concentrations.

43. The vertical semiconductor device according to claim 26, wherein at least one of the plurality of mesas or the drift region has at least one region with a graded doping profile.

44. The vertical semiconductor device according to claim 26, wherein the drift region includes at least one charge diffusion layer and at least one drift layer below the plurality of mesas.

45. The vertical semiconductor device according to claim 26, wherein the vertical semiconductor device is a diode.

46. The vertical semiconductor device according to claim 26, wherein the doping concentration of the second type with respect to the first material is at least twice the doping concentration of the first type in the plurality of mesas.

47. The vertical semiconductor device according to claim 26, wherein the width of the narrowest portion of each of the plurality of mesas is between 1 and 2 times the height of each of the plurality of mesas.

48. The vertical semiconductor device according to claim 26, wherein the substrate and the drift region include a first material system.

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