Double-sided cooled package for double-sided bidirectional junction transistors.

Abstract

A double-sided cooled package for double-sided bidirectional junction transistors can include a double-sided bidirectional junction transistor chip (collectively DSTA) with individual double-sided bidirectional power switches. The DSTA can be sandwiched between heat sinks. Each heat sink can include a direct plated copper (DPC) structure, a direct copper bonded (DCB) structure, or a direct aluminum bonded (DAB) structure. Additionally, each heat sink can have opposing first and second copper layers on a substrate and copper contacts extending from the respective second copper layers through vias in each substrate to the exterior of the cooled package.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63 / 345,711, filed May 25, 2022, which is incorporated by reference herein as if reproduced in its entirety below.

[0002] This application relates generally to cooling packages for integrated circuit devices, and more particularly to a double-sided cooling package for a double-sided bi-directional junction transistor. [Background technology]

[0003] Ideal Power Inc. of Austin, Texas, the assignee of this application, owns U.S. Patent Nos. 9,029,909, 9,059,710, and 9,035,350. These patents disclose double-sided bidirectional junction transistors with separate double-sided bidirectional power switches. Such products provide significant performance improvements over conventional power semiconductors, including low on-state collector-emitter voltage drop (VCEon), oscillation-free turn-off, and very low switching losses.

[0004] After wafer fabrication is complete, the products need to be packaged for use as individual power devices, co-packed power devices, or multi-chip power modules. Traditional packages such as TO, flip-flop, etc. are not suitable for this type of product. Thus, improved cooling packages are of continuing interest. Summary of the Invention

[0005] Disclosed are embodiments of a system, method, and apparatus for a double-sided cooling package for a double-sided bidirectional junction transistor. For example, a cooling package for a double-sided chip can include a double-sided bidirectional junction transistor chip with individual double-sided bidirectional power switches (collectively, a double-sided transistor assembly (DSTA)). The DSTA can be sandwiched between heat sinks. Each heat sink can, in some versions, include a direct plated copper (DPC) structure, a direct copper bond (DCB) structure, or a direct aluminum bond (DAB) structure. Additionally, each heat sink can have opposing first and second copper layers on a substrate and copper contacts extending from the respective second copper layers through vias in each substrate to the exterior of the cooling package.

[0006] In another embodiment, a method for soldering a transistor includes the steps of preparing a double-sided bidirectional junction transistor chip, or double-sided transistor assembly (DSTA); attaching the DSTA to the die; printing sintered Ag on a first side pad of the DSTA; aligning a first side layer of a first heat sink to match the pattern of the first side pads on the DSTA; sintering the sintered Ag to convert it to pure Ag; and then flipping the die and repeating these steps with a second side pad of the DSTA and a second heat sink. [Brief description of the drawings]

[0007] For a detailed description of example embodiments, reference is made to the accompanying drawings. [Figure 1] 1 is a side cross-sectional view of an embodiment of a cooling package for a transistor. [Diagram 2] FIG. 2 is an exploded view of the embodiment of FIG. [Diagram 3] FIG. 1 is a perspective view of an embodiment of a discrete package. [Figure 4] FIG. 4 is an exploded view of the embodiment of FIG. [Diagram 5]1 is a side cross-sectional view of another embodiment of a cooling package for a transistor. [Figure 6] FIG. 2 is a plan view of an embodiment of a patterned DPC structure. [Figure 7] FIG. 1 is a plan view of an embodiment of a pattern of a DSTA. [Figure 8] 1 is an optical microscope image of an embodiment of a linewidth / space of a DPC substrate. [Figure 9] FIG. 1 is a schematic diagram of an embodiment of a module in series mode. [Figure 10] FIG. 1 is a schematic diagram of an embodiment of a module in parallel mode. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] 1-10 show various embodiments of a cooling package 21 for double-sided transistors. For example, the cooling package 21 can include at least one double-sided bidirectional junction transistor chip (collectively, a double-sided transistor assembly (DSTA) 23, e.g., four shown in FIG. 2) with individual double-sided bidirectional power switches. The DSTAs 23 can be symmetrical on both sides. The DSTAs 23 can be sandwiched between heat sinks 31. Each heat sink 31 can include a direct plated copper (DPC) structure having opposing first and second copper layers 33, 35 on a substrate 37. The heat sinks 31 can also have copper contacts 39 (FIG. 1) that extend from the respective second copper layers 35 through vias 41 in each substrate 37 to the exterior of the cooling package 21.

[0009] Embodiments of the cooling package 21 may include, by way of example, a multi-chip power module (FIG. 2), a discrete power device (FIGS. 3-4), or a co-pack power device (different devices packed together, such as IGBTs + diodes). As noted above, the cooling package 21 may further include a second DSTA 23 that is identical to the DSTA 23 and packaged side-by-side with the DSTA and sandwiched between the heat sinks 31. The cooling package 21 may further include an additional DSTA 23 (similar to FIG. 2) that is identical to the DSTA 23 and packaged side-by-side with the DSTA and sandwiched between the heat sinks 31.

[0010] Versions of the cooling package 21 may further include asymmetrical temperature soldering on each side of the cooling package 21. For example, a first solder may be applied to one side and have a higher melting temperature than a second solder that is applied to the opposite side after the first solder. The first solder and the second solder may each include Ag in some versions. As shown in FIG. 5, one embodiment of the cooling package 21 may include sintered Ag51 for bonding each DSTA 23 to a respective heat sink 31. The sintered Ag51 may be converted to pure Ag during sintering. Each layer of pure Ag may include a thickness of at least 1 mm to facilitate leads between the inner sides of the respective heat sinks 31.

[0011] Embodiments of the DSTA 23 can be configured to operate at currents of at least 50 A, with parasitic resistance from the cooling package 21 of less than 1 mOhm, and switching frequencies up to 100 kHz. The DSTA 23 can be configured to operate at powers in excess of 60 kW. Versions of the DSTA 23 can include wafer thicknesses ranging from 40 μm to 750 μm.

[0012] 2, the opposing first and second copper layers 33, 35 of each DPC structure may include a solid copper outer layer 33 on a respective substrate 37 and a patterned copper inner layer 35 on the opposite side of the solid copper outer layer 33. The patterned copper inner layer 35 may match the respective patterns of the DSTA 23. Examples of patterns are shown in FIGS. 6-7, such as the emitter region (E) and base region (B1).

[0013] In some versions, each copper layer 33, 35 of the DPC structure can include a thickness in the range of about 1 μm to about 150 μm to be compatible with various currents flowing through the copper. Alternatively, each copper layer 33, 35 of the DPC structure can include a thickness in the range of greater than 75 μm to about 150 μm. The overall thickness of the entire cooling package 21 can be compatible with any wafer thickness currently in mass production, ranging from about 45 μm to about 750 μm. Even thinner wafer thicknesses, e.g., less than 45 μm, can be accommodated. This is one advantage of the DPC design. That is, the wafer thickness is not limited in the bidirectional power switch with double-sided cooling package 21, since wiring can be routed to the outer copper layer 33 through one or more vias 41.

[0014] In some embodiments, the substrate 37 of the DPC structure is Al 2 O 3 , ZTA, AlN, silicon, BeO, or other materials with high electrical resistance and low thermal resistance, i.e., the material contributes to lowering electrical impedance and allows for improved thermal conductivity. The DPC structures may include a thermal resistance of about 0.001° C. / Watt to about 0.1° C. / Watt in some examples. The cooling package 21 may further include a molding compound or epoxy encapsulation 43 between the DPC structures and surrounding the DSTA 23. As shown in FIG. 8, each DPC structure may include a line pitch with a fine line width / line spacing resolution of 2 mils / 2 mils. Each via 41 in each substrate 37 may include a diameter ranging from 25 μm or more to 150 μm in some versions.

[0015] The embodiment of the cooling package 21 may further include a second cooling package 21, and each cooling package 21 may include a micromodule. The cooling package 21 may further include multiple cooling packages 21 stacked in series with the emitter region E and base region B to extend the blocking voltage (FIG. 9). For example, four 1200V micromodules may be stacked together to support a blocking voltage of 4800V. In another example, the cooling package 21 may further include multiple cooling packages 21 configured to operate in parallel with the emitter region E and base region B (FIG. 10) to extend the operating current (for example, four 100A micromodules in parallel may support a current of 400A).

[0016] Another version of the cooling package 21 may include a double-sided bidirectional junction transistor chip with individual double-sided bidirectional power switches (collectively DSTA 23) sandwiched between heat sinks 31. Each heat sink 31 may include a direct copper bonding (DCB) structure having opposing first and second copper layers 33, 35 on a substrate 27. Copper contacts 39 may extend from the respective second copper layers 35 through vias 41 in each substrate 37 to the exterior of the cooling package 21.

[0017] Yet another version of the cooling package 21 may include one or more heat sinks 31 including a direct aluminum bond (DAB) structure having opposing first and second aluminum layers 33, 35 on a substrate 37 (similar to FIG. 2). Aluminum contacts 39 may extend from each second aluminum layer 35 through vias 41 in each substrate 37 to the exterior of the cooling package 21.

[0018] A method of soldering a transistor is also contemplated. For example, the method may include the steps of preparing a double-sided bidirectional junction transistor chip (DSTA), attaching the DSTA to the die, printing sintered Ag on a first side pad of the DSTA, aligning a first side layer of a first heat sink to match the pattern of the first side pads on the DSTA, sintering the sintered Ag to convert it to pure Ag, and then flipping the die and repeating these steps for a second side pad of the DSTA and a second heat sink. In some embodiments, each heat sink may include a direct plated copper (DPC) structure, a direct copper bonded (DCB) structure, or a direct aluminum bonded (DAB) structure.

[0019] Combined with the package described herein, DSTA can have many advantages. For example, if there is a heat sink on both sides of the DSTA, both sides of the DSTA can operate at high power. DSTA has a symmetrical structure on both sides. The package material and performance are also symmetrical. In contrast, a traditional TO package has a lead frame with a heat sink on one side and a molding compound on the other side. DSTA chips are thinner than traditional 500 μm or 750 μm chips. The new double-sided cooling package disclosed herein can help realize the potential of DSTA, meet the unique structural requirements of DSTA, and improve the performance of DSTA. Other advantages and benefits include:

[0020] - Double-sided cooling of DSTA both as individual and multi-chip power modules.

[0021] - DSTA double-sided cooling with Direct Bonded Copper (DBC).

[0022] - DSTA double sided cooling with Direct Aluminum Bond (DAB).

[0023] - DSTA double-sided cooling with Direct Plated Copper (DPC).

[0024] - Double sided high output.

[0025] - Symmetry, reduced thermal resistance, reduced electrical impedance, improved reliability.

[0026] - DSTA double-sided cooling with asymmetric soldering, i.e. the temperature of the first soldering, such as Tin (Sn) soldering, is higher than the second soldering (such as SAC305) on the other side, thus preventing the second soldering from loosening the first soldering.

[0027] - DSTA double-sided cooling with sintered silver (Ag) eliminates the problem of asymmetric soldering for double-sided cooled packages. Sintered Ag can be used on both sides. After conversion to pure Ag, the second soldering temperature has negligible effect on the first Ag soldering.

[0028] - Easy connection to external heat sink.

[0029] Directly plated copper (DPC) is a packaging technology that overcomes traditional shortcomings and offers higher resolution, higher reliability, and better thermal and electrical performance. DPC boards offer several advantages:

[0030] - Fine line pitch such as 2 / 2 mil or finer line width / spacing in MP.

[0031] - Via sizes can be small, such as 25 μm in diameter, and constructed with highly conductive copper plating.

[0032] The copper thickness can be in the range of 1 μm to about 150 μm, for example 50 μm to 75 μm.

[0033] - Excellent thermal conductivity.

[0034] - Very high electrical insulation.

[0035] - Low electrical capacitance.

[0036] - Extremely high pattern accuracy.

[0037] - High design flexibility.

[0038] - Through vias can connect the front and back of the DPC board. The via design allows for high density circuitry and more heat transfer.

[0039] - The circuit is Al 2 O 3 , ZTA, AlN, BeO, and a variety of other substrates.

[0040] - Various surface finish options include Electroless Ag, ENEPIG, ENIG, Electrolytic Ni / Ag, Electrolytic Ni / Au, Electrolytic Ni / Pd / Au.

[0041] The DPC-based double-sided cooling design and manufacturing method can improve the performance of the DSTA by matching the symmetrical structure of the DSTA, conducting high current on both sides, improving thermal resistance and electrical impedance, symmetrical soldering, etc.

[0042] A typical multi-chip structure includes a DPC-based double-sided DSTA cooled package. The DSTA chip is sandwiched between an upper DPC and a lower DPC. Leads or pins can be connected to the DSTA chip pads, in one example, through a symmetrical pattern of vias.

[0043] Traditionally, soldering the top side is different from the bottom side, which can result in asymmetric performance and increased process complexity. To solve this problem, the DSTA chip can be soldered to the copper pattern of the DPC using sintered Ag technology such as Argomax Ag.

[0044] The sintering temperature of Ag is below 300°C to form pure Ag. However, the melting point of Ag is 962°C. This solves the problem of asymmetric soldering for double-sided cooling packages. An exemplary procedure for DSTA double-sided cooling soldering includes printing sintered Ag onto the DSTA front pads, aligning the top DPC to the DSTA pattern, and sintering at 300°C to convert the sintered Ag into pure Ag. The pure Ag tightly bonds the DSTA pads to the top DPC and will not melt or loosen until 962°C. The die is then flipped over and these procedures are repeated on the bottom side using sintered Ag. Because the sintering temperature (300°C) is much lower than the melting point of Ag on the front side (962°C), the soldering process on the bottom side has negligible effect on the structure of the soldering on the front side.

[0045] Additionally, compared to traditional SAC or lead solder, sintered Ag has over 10 times lower electrical resistance and over 7 times higher thermal conductivity, which increases package power dissipation and reduces the junction temperature of the DSTA chip, improving reliability and further reducing excess impedance from the package.

[0046] The Cu layer on the DPC can be patterned to match the DSTA chip pattern. Take one chip as an example, the Cu patterns on the upper DPC and the lower DPC can match the DSTA chip pattern.

[0047] With proper lead connections, the same DPC double-sided cooled package can be manufactured as a discrete package such as TO264. The DSTA chip can be placed on the top and bottom DPC with two leads connected to the bottom DPC Cu and connected to the DSTA bottom E,B pads. Two extra lead positions are left for the top DPC to connect to the DSTA top E,B pads.

[0048] Other embodiments include one or more of the following items.

[0049] 1. Cooling package for double-sided chips. The cooling package includes:

[0050] The cooling package includes a double-sided bidirectional junction transistor chip with individual double-sided bidirectional power switches, or a double-sided transistor assembly (collectively DSTA) sandwiched between heat sinks, each of which includes a direct plated copper (DPC) structure having opposing first and second copper layers on a substrate, and copper contacts extending from the respective second copper layers through vias in each substrate to the exterior of the cooling package.

[0051] 2. In the above cooling package, the cooling package includes one of a discrete power device, a co-pack power device, or a multi-chip power module.

[0052] 3. The cooling package is identical to the DSTA and further includes a second DSTA packaged alongside the DSTA and sandwiched between the heat sinks.

[0053] 4. The cooling package is identical to the DSTA and further includes a second, third, and fourth DSTA packaged alongside the DSTA and sandwiched between the heat sinks.

[0054] 5. In the above cooling package, the DSTA is symmetrical on both sides.

[0055] 6. The cooling package further includes asymmetric temperature soldering on each side of the cooling package, a first solder applied to one side having a higher melting point than a second solder applied to the opposite side after the first solder.

[0056] 7. In the above cooling package, the first and second solders each contain Ag.

[0057] 8. The cooling package further includes sintered Ag for bonding each DSTA to a respective heat sink, the sintered Ag being converted to pure Ag during sintering.

[0058] 9. In the above cooling package, each layer of pure Ag comprises a thickness of at least 1 mm to facilitate leads between the inner surfaces of the respective heat sinks.

[0059] 10. In the above cooled package, the DSTA is configured to operate at a current of at least 50A with a parasitic resistance from the cooled package of less than 1mOhm and a switching frequency of up to 100kHz.

[0060] 11. In the above cooling package, the DSTA is configured to operate at power levels in excess of 60 kW.

[0061] 12. In the above cooling package, the DSTA has a wafer thickness in the range of 40 μm to 750 μm.

[0062] 13. In the above cooling package, the opposing first and second copper layers of each DPC structure include a solid copper outer layer on the respective substrate and a patterned copper inner layer opposite the solid copper outer layer.

[0063] 14. In the above cooling package, the patterned copper inner layer matches the pattern of each DSTA.

[0064] 15. In the above cooling package, the thickness of each copper layer of the DPC structure ranges from about 1 μm to about 150 μm to be compatible with various currents flowing through the copper.

[0065] 16. In the above cooling package, the thickness of each copper layer of the DPC structure is in the range of greater than 75 μm to about 150 μm.

[0066] 17. In the above cooling package, the substrate of the DPC structure is Al 2 O 3 , ZTA, AlN, silicon, or BeO.

[0067] 18. In the above cooling package, the DPC structure includes a thermal resistance of about 0.001° C. / Watt to about 0.1° C. / Watt.

[0068] 19. The cooling package above, further comprising molding compound or epoxy encapsulation between the DPC structures and around the DSTA.

[0069] 20. In the above cooling package, each DPC structure contains a line pitch with a fine line width / line space resolution of 2 mil / 2 mil.

[0070] 21. In the above cooling package, each via in each substrate includes a diameter ranging from 25 μm to 150 μm.

[0071] 22. The cooling package further includes a second cooling package, each cooling package including a micro-module.

[0072] 23. The cooling package further includes multiple cooling packages stacked in series to extend the blocking voltage.

[0073] 24. The cooling package further includes multiple cooling packages configured to operate in parallel to expand operating current.

[0074] 25. A cooling package for a double-sided chip, the cooling package including:

[0075] The cooling package includes a double-sided bidirectional junction transistor chip with individual double-sided bidirectional power switches, or a double-sided transistor assembly (collectively DSTA) sandwiched between heat sinks, each of which includes a direct copper bonding (DCB) structure having opposing first and second copper layers on a substrate and copper contacts extending from the respective second copper layers through vias in each substrate to the exterior of the cooling package.

[0076] 26. A cooling package for a double-sided chip, the cooling package including:

[0077] The cooling package includes a double-sided bidirectional junction transistor chip with individual double-sided bidirectional power switches, or a double-sided transistor assembly (collectively DSTA) sandwiched between heat sinks, each of which includes a direct aluminum bond (DAB) structure having opposing first and second aluminum layers on a substrate and aluminum contacts extending from the respective second aluminum layers through vias in each substrate to the exterior of the cooling package.

[0078] 27. A method of soldering a transistor, the method comprising:

[0079] (a) A double-sided bidirectional junction transistor chip, or a double-sided transistor assembly (DSTA), is provided.

[0080] (b) Attach the DSTA to the die.

[0081] (c) Printing sintered Ag on the first side pad of the DSTA.

[0082] (d) Aligning a first side layer of a first heat sink to match the pattern of first side pads on the DSTA.

[0083] (e) Sintering the sintered Ag to convert the sintered Ag to pure Ag.

[0084] Next, (f) flip the die and repeat steps (c)-(e) for the second side pad of the DSTA and the second heat sink.

[0085] 28. In the above method, each heat sink includes a direct copper plated (DPC) structure.

[0086] 29. In the above method, each heat sink includes a direct copper bonding (DCB) structure.

[0087] 30. In the above method, each heat sink includes a direct aluminum bond (DAB) structure.

[0088] The terms used herein are for the purpose of describing specific exemplary embodiments only and are not limiting. As used herein, the singular forms "a," "an," and "the" may be intended to include the plural unless the context clearly indicates otherwise. The terms "comprises," "comprising," "including," and "having" are inclusive and thus specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein should not be construed as necessarily having to be performed in the particular order discussed or illustrated, unless specifically identified as such. It should also be understood that additional or alternative steps may be employed.

[0089] When an element or layer is referred to as being "on," "engaged," "connected," or "coupled" to another element or layer, it may be directly on, engaged, connected, or coupled to the other element or layer, or there may be intervening elements or layers present. In contrast, when an element is referred to as being "directly on," "directly engaged," "directly connected," or "directly coupled" to another element or layer, there may not be intervening elements or layers present. Other words used to describe relationships between elements should be interpreted similarly (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.). As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0090] In this specification, terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Terms such as "first", "second", etc., as used herein, and other numerical terms, do not imply any order or sequence unless clearly indicated by the context. Thus, a first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings of the exemplary embodiments.

[0091] For ease of description, spatially relative terms such as "inside," "outside," "below," "lower," "down," "above," "upper," "lower," and the like may be used herein to describe the relationship of one element or feature to another element or feature as depicted in the figures. The spatially relative terms may be intended to encompass various orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "below" other elements or features would be oriented "above" the other elements or features. Thus, the example term "lower" can encompass both an orientation of above and below. The device may be oriented in other directions (rotational angles or other orientations) and the spatially relative descriptions used herein would be interpreted accordingly.

[0092] This written description uses examples to disclose embodiments, including the best mode, and to enable any person skilled in the art to make and use the invention. The patentable scope is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are within the scope of the claims if they have no structural elements that differ from the claim language, or if they include equivalent structural elements that do not differ insubstantial from the claim language.

[0093] In the foregoing specification, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made without departing from the scope of the invention as set forth in the following claims. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention.

[0094] It may be helpful to provide definitions of certain words and phrases used throughout this patent document. The term "communicate" and its derivatives encompass both direct and indirect communication. The terms "include" and "comprise" and its derivatives mean an inclusion without limitation. The term "or" is inclusive and means "and / or". The word "associated with" and its derivatives may mean "including", "contained within", "interconnected with", "including", "contained within", "connected to or with", "coupled to or with", "capable of communicating with", "cooperating with", "alternating with", "juxtaposing", "adjacent to", "bound to or with", "having", "having a characteristic", or "related to or with", and the like. The phrase "at least one", when used in conjunction with a list of items, means that one or more different combinations of the listed items may be used and only one item in the list may be required. For example, "at least one of A, B, and C" includes one of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.

[0095] Additionally, the use of "a" or "an" is used to describe elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. This description should be interpreted to include one or at least one, and the singular also includes the plural, unless otherwise specified.

[0096] The description in this application should not be construed to imply that any particular element, step, or function is essential or critical to inclusion in the scope of the claims. The scope of patented subject matter is defined solely by the allowed claims. Moreover, none of the claims invoke 35 U.S.C. 112(f), which does not apply with respect to any of the appended claims or claim elements, unless the precise words "means" or "step" are expressly used in a particular claim, followed by a participial phrase identifying the function.

[0097] Advantages, other benefits, and solutions to problems have been described above with respect to specific embodiments. However, the advantages, benefits, solutions to problems, and features by which the advantages, benefits, or solutions may occur or become more pronounced should not be construed as critical, essential, sacrosanct, or required features of one or all of the claims.

[0098] After reading the specification, those skilled in the art will appreciate that certain features that are, for clarity, described herein in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Further, references to values ​​specified in ranges include all values ​​within that range.

Claims

1. 1. A cooling package for a double-sided chip, the cooling package comprising: a double-sided bidirectional junction transistor chip (DSTA) having separate double-sided bidirectional power switches sandwiched between heat sinks; Each heat sink includes a direct plated copper (DPC) structure having opposing first and second copper layers on a substrate, and copper contacts extending from the respective second copper layers through vias in each substrate to an exterior of the cooling package; Cooling package.

2. The cooling package of claim 1 , wherein the cooling package comprises one of a discrete power device, a co-pack power device, or a multi-chip power module.

3. 10. The cooling package of claim 1 further comprising a second DSTA identical to the DSTA, packaged alongside the DSTA and sandwiched between the heat sinks.

4. 2. The cooling package of claim 1, further comprising second, third and fourth DSTAs identical to said DSTA and packaged alongside said DSTA and sandwiched between said heat sinks.

5. The cooling package of claim 1 , wherein the DSTA is symmetric on both sides.

6. 10. The cooling package of claim 1, further comprising asymmetric temperature soldering on each side of the cooling package, a first solder applied to one side having a higher melting point than a second solder applied to the opposite side after the first solder.

7. The cooling package of claim 6 , wherein the first solder and the second solder each comprise Ag.

8. 10. The cooling package of claim 1, further comprising sintering Ag to bond each DSTA to a respective heat sink, the sintered Ag being converted to pure Ag during sintering.

9. 9. The cooling package of claim 8, wherein each layer of pure Ag has a thickness of at least 1 mm to facilitate leads between the interior surfaces of the respective heat sinks.

10. 10. The cooling package of claim 1, wherein the DSTA is configured to operate at a current of at least 50A with a parasitic resistance from the cooling package of less than 1 mOhm and a switching frequency of up to 100 kHz.

11. The cooling package of claim 1 , wherein the DSTA is configured to operate at greater than 60 kW of power.

12. The cooling package of claim 1 , wherein the DSTA has a wafer thickness in the range of 40 μm to 750 μm.

13. 2. The cooling package of claim 1, wherein the opposing first and second copper layers of each DPC structure include a solid copper outer layer on a respective substrate and a patterned copper inner layer opposite the solid copper outer layer.

14. The cooling package of claim 13 , wherein the patterned copper innerlayer matches a pattern of each of the DSTAs.

15. The cooling package of claim 1 , wherein the thickness of each copper layer of the DPC structure ranges from about 1 μm to about 150 μm to be compatible with various currents flowing through the copper.

16. The cooling package of claim 1 , wherein the thickness of each copper layer of the DPC structure ranges from greater than 75 μm to about 150 μm.

17. The substrate of the DPC structure is Al ２ O ３ 5. The cooling package of claim 1 comprising at least one of the following: AlN, ZTA, AlN, silicon, or BeO.

18. The cooling package of claim 1 , wherein the DPC structure comprises a thermal resistance of about 0.001° C. / Watt to about 0.1° C. / Watt.

19. The cooling package of claim 1 , further comprising a molding compound or epoxy encapsulation between said DPC structures and around said DSTA.

20. The cooling package of claim 1 , wherein each DPC structure includes a line pitch with a fine line width / line space resolution of 2 mil / 2 mil.

21. The cooling package of claim 1 , wherein each via in each substrate comprises a diameter in the range of 25 μm to 150 μm.

22. The cooling package of claim 1 further comprising a second cooling package, each cooling package including a micromodule.

23. The cooling package of claim 1 further comprising a plurality of cooling packages stacked in series to extend blocking voltage.

24. The cooling package of claim 1 , further comprising a plurality of cooling packages configured to operate in parallel to scale operating current.

25. 1. A cooling package for a double-sided chip, the cooling package comprising: a double-sided bidirectional junction transistor chip (DSTA) having separate double-sided bidirectional power switches sandwiched between heat sinks; Each heat sink includes a direct copper bonding (DCB) structure having opposing first and second copper layers on a substrate, and copper contacts extending from the respective second copper layers through vias in each substrate to the exterior of the cooling package; Cooling package.

26. 1. A cooling package for a double-sided chip, the cooling package comprising: a double-sided bidirectional junction transistor chip (DSTA) having separate double-sided bidirectional power switches sandwiched between heat sinks; Each heat sink includes a direct aluminum bond (DAB) structure having opposing first and second aluminum layers on a substrate, and aluminum contacts extending from the respective second aluminum layers through vias in each substrate to the exterior of the cooling package. Cooling package.

27. 1. A method of soldering a transistor, the method comprising the steps of: (a) providing a double-sided bidirectional junction transistor chip (DSTA); (b) attaching the DSTA to a die; (c) printing sintered Ag onto a first side pad of the DSTA; (d) aligning a first side layer of a first heat sink to match the pattern of the first side pads on the DSTA; (e) sintering the sintered Ag to convert it to pure Ag; and then (f) flipping the die and repeating steps (c)-(e) for a second side pad of the DSTA and a second heat sink. method.

28. 30. The method of claim 27, wherein each heat sink comprises a direct plated copper (DPC) structure.

29. 30. The method of claim 27, wherein each heat sink comprises a direct copper bond (DCB) structure.

30. 30. The method of claim 27, wherein each heat sink comprises a direct aluminum bond (DAB) structure.

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