Method and circuit for efficient management of a local branch history register

Abstract

A method and circuit for efficient management of a local branch history register are described. An exemplary processor includes a pipeline having a plurality of stages and a bit vector associated with each of the in-flight branches associated with the pipeline. The processor includes a recovery counter for tracking the number of bits that require recovery before a local branch history register becomes enabled to participate in branch prediction. The processor includes a branch predictor circuit configured to set a bit in a corresponding bit vector indicating an update to the local branch history register in response to an update to the local branch history register by a branch. The branch predictor circuit is configured to determine, when a flush occurs, a value indicating the extent of recovery required for each local branch history register affected by the flush and set the corresponding recovery counter to the value indicating the extent of recovery required.

Description

Background Art

[0001] A multi-threaded processor can fetch and execute instructions belonging to a thread. During the execution of a thread's instructions, the processor may execute an instruction that references a register or a memory location. Due to the latency associated with accessing the referenced memory location, the processor may have to wait until the referenced memory location is accessed. Similarly, if an instruction requires multiple cycles to execute, subsequent instructions that depend on that instruction will have to wait. To maintain efficiency, the processor can fetch instructions from another thread and start their execution. In this way, the processor can execute instructions more efficiently. This type of parallelism is sometimes referred to as thread-level parallelism. Another way to improve the performance of a processor is to utilize instruction-level parallelism.

[0002] Speculative instruction fetch supplies the instructions necessary to exploit the instruction-level parallelism of a program. Whether the next instruction to be fetched can be accurately predicted may depend on the analysis of the program history by a branch predictor. Such predictions may turn out to be inaccurate, and the processor may have to recover from an incorrectly predicted branch, including discarding the results of the dependency of the incorrectly predicted instruction and re-executing the instructions in the correct order. Recovery from an incorrectly predicted branch may not be optimal.

Summary of the Invention

[0003] In one example, the present disclosure relates to a processor that includes a pipeline having a plurality of stages. The processor may further include a bit vector associated with each in-flight branch associated with the pipeline, where each bit vector has bits corresponding to each local branch history register associated with the respective in-flight branch. The processor may further include a recovery counter associated with each local branch history register for tracking the number of bits that require recovery before the local branch history register becomes enabled to participate in branch prediction.

[0004] The processor may further include a branch predictor circuit configured to set the bits in the corresponding bit vector indicating an update to the local branch history register by the branch in response to an update to the local branch history register by the branch. The branch predictor circuit may be further configured to determine, when a flush occurs, a value indicating the degree of recovery required for each local branch history register affected by the flush and set the corresponding recovery counter to the value indicating the degree of recovery required.

[0005] In another example, the present disclosure relates to a processor that includes a pipeline having a plurality of stages. The processor may further include a bit vector associated with each in-flight branch associated with the pipeline, where each bit vector has bits corresponding to each local branch history register associated with the respective in-flight branch. The processor may further include a recovery counter associated with each local branch history register for tracking the number of bits that require recovery before the local branch history register becomes enabled to participate in branch prediction.

[0006] The processor may further include a branch predictor circuit configured to set bits in a corresponding bit vector indicating an update of a local branch history register due to a branch in response to the update of the local branch history register due to the branch. The branch predictor circuit may be further configured to identify all local branch history registers that require recovery by performing a logical OR operation on the bit vector corresponding to the mis-speculated branch and all branches younger than the mis-speculated branch when a flush occurs. The branch predictor circuit may be further configured to discard all bits of all identified local branch history registers that require recovery and set the value of each respective recovery counter of all identified local branch history registers that require recovery to the maximum value of the recovery counter.

[0007] In yet another example, the present disclosure relates to a processor that includes a pipeline having a plurality of stages. The processor may further include a bit vector associated with each in-flight branch associated with the pipeline, each bit vector having bits corresponding to each local branch history register associated with the respective in-flight branch. The processor can further include a recovery counter associated with each local branch history register for tracking the number of bits that require recovery before the local branch history register becomes enabled to participate in branch prediction.

[0008] The processor may further include a branch predictor circuit configured to perform the following in response to updates to the local branch history register for each branch: (1) set bits in a corresponding bit vector indicating the updates to the local branch history register for each branch, and (2) set bits in each of the bit vectors corresponding to all in-flight branches older than each branch. The branch predictor circuit may be further configured to identify all local branch history registers that require recovery based on the bit vectors corresponding to mis-speculated branches that occur when a flush occurs. The branch predictor circuit may further be configured to discard all bits of all identified local branch history registers that require recovery and set the value of each respective recovery counter of all identified local branch history registers that require recovery to the maximum value of the recovery counter.

[0009] This summary is provided to introduce, in a simplified form, a selection of concepts that are further described below in the "Detailed Description." This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.

[0010] This disclosure is illustrated by way of example and is not limited by the accompanying drawings. In the accompanying drawings, like reference numerals indicate like elements. Elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2A

Figure 2B

Figure 2C

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DETAILED DESCRIPTION OF THE INVENTION

[0012] The examples described in this disclosure relate to methods and circuits for efficient management of a local branch history register. As described above, speculative instruction fetching supplies the instructions necessary to exploit the instruction-level parallelism of a program. Whether the next instruction to be fetched can be successfully predicted may depend on the analysis of the program history by a branch predictor. Such predictions can turn out to be inaccurate, and as a result, the processor has to discard the results of the dependencies of the mispredicted instructions and re-execute the instructions in the correct order. In a multi-threaded processor, many threads running in parallel may need to re-execute instructions based on mispredictions.

[0013] Despite the risk of mispredictions, branch prediction is a performance-improving microarchitecture feature used in the front ends of many high-performance processors. When encountering a branch instruction (e.g., an instruction that changes the program control flow from sequential to non-sequential), the processor either stalls until the branch is executed and supplies the next fetch program counter (PC), or alternatively, the processor employs hardware that can predict the branch result ahead of time (before the branch is executed) and can drive the instruction fetch using the predicted result. Such hardware is commonly referred to as a branch predictor (BP).

[0014] The branch predictor can accurately predict the branch result by using the program history. The prediction made by the branch predictor is used to advance the instruction fetch unit before the branch is executed. The branch predictor can correlate the program history by tracking information about previously executed branches. The program history may be captured using a history register. The history register can be a local history register (e.g., a history register for each branch) or a global history register (e.g., a history register based on the results of the last X branches). To enhance the prediction, the state of the history register may be speculatively updated (using the predicted branch result) at the time of prediction so that the next prediction follows the history of all preceding branches (e.g., the prediction made using a consistent but speculative history state). Since the state is speculatively updated, if an incorrect speculation occurs, all instructions younger than the incorrectly predicted branch need to be flushed and the speculatively updated history register needs to be rolled back. This can be achieved by checkpointing the information before speculatively updating the history register.

[0015] By using local history, the branch prediction accuracy can be significantly improved. However, since the branch predictor may have multiple local history registers (e.g., 256 registers, or even 512 registers), the recovery process from incorrect speculation is complex and slow. One implementation of recovery may require walking through a list of flushed branches to unwind the history updates made to the corresponding history register. Such a process (referred to as the "slow-and-iterative" recovery process) may require an arbitrary number of cycles depending on the number of flushed branches. Another implementation of recovery may invalidate all local history registers when a flush occurs and may re-populate the local history registers over time. This recovery process (referred to as the "invalidate-all" recovery process) may result in a faster recovery, but since all local program history is lost, it greatly affects the accuracy of the branch predictor. In the present disclosure, techniques and structures that enable efficient management of local branch history registers are described.

[0016] FIG. 1 is a diagram of a processor 100 including a branch predictor 150 for efficient management of a local branch history register, according to an example. The processor 100 may be implemented as part of an integrated circuit. The processor 100 can include a pipeline 110 for processing instructions. The pipeline 110 can include a plurality of stages for processing instructions in a pipelined manner. In this example, the pipeline 110 may include stage 0 112, stage 1 114, stage 2 116, and stage N 118, where N is a positive integer. In this example, the branch predictor 150 may be included in stage 0 112. The branch predictor 150 may be coupled to other specific stages of the pipeline 110 depending on the specific architecture of the processor. In this example, stage 1 114 may be implemented as an instruction cache. Stage 0 112 including the branch predictor 150 may be configured as a fetch stage. The branch predictor 150 can include hardware that can predict a branch result in advance and drive instruction fetch using the predicted result. Stage 2 116 may be implemented as a decoder configured to decode the next instruction fetched by stage 0 112. Stage N 118 may be implemented as an execution stage for executing instructions.

[0017] Continuing to refer to FIG. 1, in this example, the branch predictor 150 can include a local branch history table 152 and circuitry 154 for efficient management of local branch history registers. The circuitry 154 may be implemented using digital logic. As an example, the circuitry 154 can include various types of logic gates, registers, counters, multiplexers, finite state machines, combinational logic, flip - flops, or other digital logic circuits for implementing various tasks for branch prediction. The branch predictor 150 can accurately predict branch results using program history. The prediction made by the branch predictor 150 can then be used to advance the instruction fetch process. The branch predictor 150 can correlate the program history by tracking information regarding previously executed branches. The program history may be captured using history registers. The history registers can be local history registers (e.g., branch - specific history registers stored as part of the local branch history table 152) or global history registers (e.g., history registers based on the results of the last X branches). FIG. 1 shows a specific number of components of the processor 100 arranged in a particular way, but the number of components arranged differently may be more or fewer. In one example, the pipeline 110 of the processor 100 can include other stages including stages for implementing a micro - ops morphing logic block, a rename / assignment logic block, an instruction scheduler, and a register file.

[0018] Figures 2A - 2D illustrate the training and use of a local branch history register associated with a single branch (branch_A) according to an example. This example focuses on a single branch and the local branch history register associated with it. In this example, the local branch history register can include an 8 - bit history associated with a single branch (branch_A). Before making a prediction regarding branch_A, a branch predictor (e.g., branch predictor 150 of FIG. 1) can access the content 202 of the local branch history register associated with branch_A. Assuming the prediction result is a branch (represented by a logical value 1), the content 202 of the local branch history register can be updated to content 204 (e.g., by shifting the bits in the register to the left and inserting a logical 1 as the least significant bit, as shown in FIG. 1). The update may occur immediately after the prediction, before the instruction passes through the rest of the processor pipeline (e.g., pipeline 110 of processor 100 of FIG. 1).

[0019] Figure 2B shows the change in the content of the local history register in response to the arrival of another instance of branch_A. Before making a prediction regarding the second instance of branch_A, a branch predictor (e.g., branch predictor 150 of FIG. 1) can access the content 212 of the local branch history register associated with branch_A. Assuming the prediction result is a branch (represented by a logical value 1), the content 212 of the local branch history register can be updated to content 214 (e.g., by shifting the bits in the register to the left and inserting a logical 1 as the least significant bit, as shown in FIG. 1). As before, the update may occur immediately after the prediction, before the instruction passes through the rest of the processor pipeline (e.g., pipeline 110 of processor 100 of FIG. 1).

[0020] Figure 2C shows the change in the content of the local history register in response to the arrival of yet another instance of branch A. Before making a prediction regarding the third instance of branch_A, the branch predictor (e.g., branch predictor 150 in FIG. 1) can access the content 222 of the local branch history register associated with branch_A. Assuming the prediction result is not taken (represented by the logical value 0), the content 222 of the local branch history register can be updated to content 224 (e.g., by shifting the bits in the register to the left and inserting a logical 0 as the least significant bit, as shown in FIG. 1). As before, the update may be performed immediately after the prediction, before the instruction passes through the rest of the processor pipeline (e.g., pipeline 110 of processor 100 in FIG. 1).

[0021] Figure 2D shows the change in the content of the local history register in response to the arrival of yet another instance of branch A. Before making a prediction regarding the fourth instance of branch_A, the branch predictor (e.g., branch predictor 150 in FIG. 1) can access the content 232 of the local branch history register associated with branch_A. Assuming the prediction result is not taken (represented by the logical value 0), the content 232 of the local branch history register can be updated to content 234 (e.g., by shifting the bits in the register to the left and inserting a logical 0 as the least significant bit, as shown in FIG. 1). As before, the update may be performed immediately after the prediction, before the instruction passes through the rest of the processor pipeline (e.g., pipeline 110 of processor 100 in FIG. 1).

[0022] FIG. 3 is a block diagram of an example of a related circuit for identifying a local branch history register (LBHR) and registers affected by a flash. The local branch history table 310 can include local branch history registers (one for each inflight branch). Assuming there are N such inflight branches, the local branch history table 310 can include N local branch history registers (e.g., LBHR1 312, LBHR2 314, LBHR3 316, LBHR4 318, and LBHRN 320). In this example, the related circuit for identifying registers affected by a flash can include a branch bit vector 330. As used in this disclosure, the term "bit vector" means any data structure implemented in hardware for storing bits. To implement a bit vector, a hardware structure such as a register can be used. In this example, each inflight branch within a processor pipeline (e.g., pipeline 110 associated with processor 100 of FIG. 1) has an associated bit vector. Each bit within the bit vector corresponds to one local branch history register. In this example, bit 332 corresponds to LBHR1 312, bit 334 corresponds to LBHR2 314, bit 336 corresponds to LBHR3 316, bit 338 corresponds to LBHR4 318, and bit 340 corresponds to LBHRN 320. As an example, the branch bit vector 330 can correspond to a particular inflight branch (e.g., branch_A described with respect to FIGS. 2A-2D). In this example, when the local branch history register corresponding to a branch (e.g., as previously described with respect to FIGS. 2A-2D) is updated, the branch predictor (e.g., branch predictor 150 of FIG. 1) sets the corresponding bit within the bit vector of that branch. When a flash occurs, the branch predictor uses the bit vectors of the branches to be flashed (and all branches younger than it) to identify the local branch history registers that need recovery.In this example, if a bit in the bit vector corresponding to a local branch history register has a logical value of 1, indicating that the bit has been set by the branch predictor, then that local branch history register and all local branch history registers associated with branches younger than it require recovery. As described above, the circuit 154 associated with the branch predictor 150 of FIG. 1 can include various types of logic gates, registers, counters, multiplexers, finite state machines, combinatorial logic, flip-flops, or other digital logic circuits for implementing various tasks for branch prediction, including management of the bit vector and local branch history registers.

[0023] Figure 4 is a block diagram of an example of a local branch history register and associated circuitry for tracking the effectiveness of registers participating in branch prediction. The local branch history table 410 can include local branch history registers (one for each in-flight branch). Assuming there are N such in-flight branches, the local branch history table 410 can include N local branch history registers (e.g., LBHR1 412, LBHR2 414, LBHR3 416, LBHR4 418, and LBHRN 420). In this example, the associated circuitry for tracking the effectiveness of registers participating in branch prediction can include a recovery counter 430. In this example, each local branch history register has an associated unsigned recovery counter. In this example, recovery counter C1 432 corresponds to LBHR1 412, recovery counter C2 434 corresponds to LBHR2 314, recovery counter C3 436 corresponds to LBHR3 416, recovery counter C4 438 corresponds to LBHR4 418, and recovery counter CN 440 corresponds to LBHRN 420. Each recovery counter corresponding to a local branch history register indicates the number of bits that need to be re-input (i.e., recovered) before the local branch history register becomes valid or is ready to participate in the next prediction. Thus, in this example, the maximum value of the recovery counter, i.e., its bit width, represents the length of the history. Regardless of the value of the recovery counter, as described above, the local branch history registers are updated speculatively. Only when the value of the recovery counter is zero may the corresponding local branch history register be used for branch prediction. Otherwise, each time a branch updates the local history register speculatively, the recovery counter is decremented by 1. As described above, the circuitry 154 associated with the branch predictor 150 of FIG. 1 can include various types of logic gates, registers, counters, multiplexers, finite state machines, combinational logic, flip-flops, or other digital logic circuits for implementing various tasks for branch prediction, including management of bit vectors and local branch history registers.

[0024] Using the aforementioned local branch history register, the associated circuitry for identifying registers affected by the flash, and the associated circuitry for tracking the effectiveness of registers for participating in branch prediction, the present disclosure provides different techniques for the efficient management of the local branch history register. One technique saves the stage of the local branch history register to enable faster recovery. Another technique is simpler but results in slower recovery of the local branch history register.

[0025] FIG. 5 shows an example of a first technique for saving and recovering the state of the local branch history register to enable faster recovery. To explain this technique, in one example, the local branch history table 510 shows the state of the local branch history register before detecting a mis-speculated branch that requires a flash. The recovery counter 520 includes a counter for each local branch history table shown as part of the local branch history table 510. In this example, assume six in-flight branches (e.g., branches B_1, B_2, B_1, B_3, B_4, and B_2). The local branch history table 530 shows the state of the local branch history register after flushing as a result of a mis-speculated branch. The recovery counter 550 includes a counter for each local branch history register shown as part of the local branch history table 530. When the local branch history register is used for branch prediction, the branch predictor sets the corresponding bits in the bit vector as indicated with respect to the bit vector of the flushed branch 560 (similar to what was previously explained with respect to FIG. 3).

[0026] When a flush occurs for an in-flight branch (e.g., branches B_1, B_2, B_1, B_3, B_4, and B_2), the exact number of bits that need to be re-entered into each local history register is calculated by adding the bit vectors of the branch being flushed and all branches younger than it. The sum of the corresponding bits within the bit vector, the value of the maximum local history length, and the value of the current corresponding recovery counter are used to next reset the recovery counter of the local branch history register: quantity "A" = min(max_local_hist_length, (sum_of_corresponding_bits_in_all_bit_vectors + corresponding_recovery_counter_current_value)). When the value of the recovery counter is set to the length of the local branch history register (e.g., 6 bits in the example of Figure 5), the branch predictor invalidates all bits within the corresponding local branch history register. Otherwise, the branch predictor right-shifts the affected local branch history register by the amount "A" calculated earlier. As the branch predictor continues to update these registers (further branches are predicted) and all suspect bits of the invalidated local branch history register are replaced with new bits (effectively, when the value of the corresponding recovery counter becomes zero), the branch predictor re-enables that register.

[0027] Continuing to refer to Figure 5, in this example, the third bit from the top of the bit vector corresponds to branch B_1, the bottom bit of the bit vector corresponds to branch B_2, the second bit from the top of the bit vector corresponds to branch B_3, and the bit further from the top of the bit vector corresponds to branch B_4. The sum of the corresponding bits within the bit vector is shown to the left of the bit vector. Thus, in this example, Table 1 below shows the calculated history lengths for each affected local history register that requires recovery.

[0028] [Table 1] Based on the calculated amount of the length of the history that requires recovery, the bits of the local branch history table 530 are shown as strike-through lines. As shown in this example, since the local branch history register 532 was not affected by the flush, no recovery is required. Therefore, the entire history of this register is saved, and the local branch history register 532 can be used by the branch predictor in the next prediction cycle. As another example, the local branch history register 534 requires recovery of the least significant bit of the register. The branch predictor right-shifts the bits of the local branch history register 534 by only 1 bit. The updated recovery count is set to 1, and until it becomes 0, the local branch history register 534 is not used by the branch predictor for any prediction. However, it should be noted that the remaining bits of the local branch history register 534 are saved. The local branch history register 536 and the local branch history register 538 require 3-bit recovery. Therefore, each of the values of the associated recovery counters is updated to 3. However, in each of the local branch history register 536 and the local branch history register 536, the remaining 3 bits are still saved. As a final example, the recovery counter value corresponding to the local branch history register 540 is set to the length of the history register (6 bits in this example), and all 6 bits in the register are invalidated by the branch predictor.

[0029] As the branch predictor continues to update these registers (and more branches are predicted), if all the suspect bits of the invalidated local branch history register are replaced with new bits (for example, when the value of the corresponding recovery counter effectively becomes zero), the branch predictor re-enables that register. Advantageously, instead of rolling back all local branch history registers, which is a slow and costly process, a more practical approach is used that provides a fast and accurate recovery. Moreover, the recovery counter enables a self-healing local branch history rollback process that runs in the background. This eliminates the need for a complex recovery mechanism or invalidating the entire local branch history stored in the local branch history table in case of a mis-speculation.

[0030] Figure 6 shows an example of a first implementation form of a second method for recovery. The implementation form of this second method is easier to implement than the first method described with respect to FIG. 5, but takes time for recovery. To explain this method, the local branch history table 610 shows the state of the local branch history register after being flushed as a result of a mis-speculated branch. In this example, assume five in-flight branches (branches B_1, B_2, B_1, B_2, and B_3). The recovery counter 620 includes a counter for each of the local branch history tables shown as part of the local branch history table 610. When the local branch history register is used for branch prediction, the branch predictor sets the corresponding bits in the bit vector as shown with respect to the bit vector of the flushed branch 640 (similar to that previously explained with respect to FIG. 3).

[0031] When an in-flight branch (e.g., branches B_1, B_2, B_1, B_2, and B_3) is flushed, the affected local history registers are identified by performing a logical "OR" operation on the bit vectors of the flushed branch and all younger branches. The result is a single bit vector 650 that indicates which local history registers need recovery. The branch predictor invalidates any local history register whose corresponding bit is set in bit vector 650. As shown in FIG. 6, in this example, bits 652, 654, and 656 of bit vector 650 are set after performing a logical "OR" operation on the bit vectors of the flushed branch and all younger branches (e.g., the bit vector of flushed branch 640). Thus, the branch predictor invalidates local branch history register 612, local branch history register 614, and local branch history register 616. In addition, the branch predictor sets the recovery counter of any invalidated local history register to the maximum possible value (e.g., the local history register length) for the recovery counter. As shown in FIG. 6, in this example, the branch predictor sets the value of each of recovery counter 622, recovery counter 624, and recovery counter 626 to 6, which is equal to the bit width of the local branch history registers shown in FIG. 6. As the branch predictor continues to update these registers (as more branches are predicted) and all suspect bits of the invalidated local branch history registers are replaced with new bits (effectively, when the value of the corresponding recovery counter becomes zero), the branch predictor re-enables that register.

[0032] FIG. 7 shows an example of a second implementation form of a second method for recovery. This implementation form of the second method is also simpler to implement than the first method described with respect to FIG. 5, but it takes time for recovery. To explain this method, the local branch history table 710 shows the state of the local branch history register after it has been flushed as a result of a mis-speculated branch prediction. This example also assumes, as shown in FIG. 6, five in-flight branches (branches B_1, B_2, B_1, B_2, and B_3). The recovery counter 720 includes a counter for each of the local branch history tables shown as part of the local branch history table 710. Different from the first implementation form of the second method described with respect to FIG. 6, when the local branch history register is used for branch prediction, the branch predictor sets not only the corresponding bits in the bit vector of the predicted branch (similar to what was previously explained with respect to FIG. 3), but also the corresponding bits in the bit vectors of all older in-flight branches. As an example, assuming that the branch B_3 shown in FIG. 6 is the branch for which the prediction is made, the branch predictor sets bits for each of the older in-flight branches (e.g., branches B_1, B_2, B_1, and B_2).

[0033] When an in-flight branch (e.g., branches B_1, B_2, B_1, B_2, and B_3 shown in FIG. 6) is flushed, the affected local history registers are identified by checking only the bit vector associated with the flushed branch (e.g., the mis-speculated branch bit vector 750). In this example, this single mis-speculated branch bit vector 750 indicates which local history registers need recovery. The branch predictor invalidates any local history register whose corresponding bit is set in the mis-speculated branch bit vector 750. As shown in FIG. 7, in this example, bits 752, 754, and 756 of the mis-speculated branch bit vector 750 are set. Accordingly, the branch predictor invalidates local branch history register 712, local branch history register 714, and local branch history register 716. In addition, the branch predictor sets the recovery counter of any invalidated local history register to the maximum possible value for the recovery counter (e.g., the local history register length). As shown in FIG. 7, in this example, the branch predictor sets the value of each of recovery counter 722, recovery counter 724, and recovery counter 726 to 6, which is equal to the bit width of the local branch history register shown in FIG. 7. As the branch predictor continues to update these registers (as more branches are predicted) and all suspect bits of the invalidated local branch history register are replaced with new bits (effectively, when the value of the corresponding recovery counter becomes zero), the branch predictor re-enables that register.

[0034] FIG. 8 is a flowchart 800 of a method for efficient management of the local branch history registers of the processor 100 of FIG. 1 according to an example. This method relates to a first technique for recovery (described with respect to FIG. 5) that saves the stages of each local branch history register to enable faster recovery. Each of the steps described in this method may be performed by the branch predictor circuit as described above. Step 810 can include setting the bits in the corresponding bit vector indicating the update of the local branch history register by the branch in response to the update of the local branch history register by the branch. As previously explained with respect to FIG. 3, when the local branch history register corresponding to a branch is updated (e.g., as previously described with respect to FIGS. 2A-2D), the branch predictor circuit sets the corresponding bit in the bit vector of the branch.

[0035] Step 820 can include determining a value indicating the degree of recovery required for each local branch history register affected by the flush when a flush occurs, and setting the corresponding recovery counter to the value indicating the degree of recovery required. As previously explained with respect to FIG. 5, the value indicating the degree of recovery for each local branch history register affected by the flush is determined by the branch predictor circuit by performing operations including: (1) calculating the sum of the bits of all bit vectors associated with mis-speculated branches and all in-flight branches younger than the mis-speculated branches as respective first values, (2) adding each first value to the current value of the corresponding recovery counter to determine a respective second value, and (3) determining the value indicating the degree of recovery for each local branch history register affected by the flush as the minimum of the maximum value of the recovery counter and each second value.

[0036] FIG. 9 is a flowchart of another method for efficient management of the local branch history register of the processor of FIG. 1 according to an example. This method relates to a first implementation form of a second technique for recovery (described with respect to FIG. 6). Each of the steps described in this method may be performed by the branch predictor circuit as described above. Step 910 may include setting bits in a corresponding bit vector indicating the update of the local branch history register by the branch in response to the update of the local branch history register by the branch. As previously explained with respect to FIG. 3, when the local branch history register corresponding to a branch is updated (e.g., as previously described with respect to FIGS. 2A-2D), the branch predictor circuit sets the corresponding bit in the bit vector of the branch.

[0037] Step 920 may include identifying all local branch history registers that require recovery by performing a logical OR operation on the bit vectors corresponding to the mispredicted speculative branches and all branches younger than the mispredicted speculative branches when a flush occurs. As previously explained with respect to FIG. 6, when in-flight branches (e.g., branches B_1, B_2, B_1, B_2, and B_3) are flushed, the affected local history registers are identified by performing a logical "OR" operation on the bit vectors of the flushed branches and all branches younger than it. The result is a single bit vector (e.g., bit vector 650 of FIG. 6) indicating which local history registers require recovery.

[0038] Step 930 can include discarding all bits of all identified local branch history registers that require recovery and setting the value of each respective recovery counter of all identified local branch history registers that require recovery to the maximum value of the recovery counter. With respect to FIG. 6, additional details related to the discarding of bits and the setting of the recovery counter are provided. Further, as described above, as the branch predictor continues to update these registers (and further branches are predicted), if all suspect bits of the invalidated local branch history register are replaced with new bits (in effect, when the value of the corresponding recovery counter becomes zero), the branch predictor re-enables that register.

[0039] FIG. 10 is a flowchart 1000 of another method for efficient management of the local branch history register of the processor of FIG. 1, according to an example. This method relates to a second implementation of a second technique for recovery (described with respect to FIG. 7). Each of the steps described in this method may be performed by a branch predictor circuit, as described above. Step 1010 can include, in response to the update of the local branch history register by each branch: (1) setting a bit in the corresponding bit vector indicating the update of the local branch history register by each branch, and (2) setting a bit in each of the bit vectors corresponding to all in-flight branches older than each branch. As previously explained with respect to FIG. 6, when the local branch history register is used for branch prediction, the branch predictor sets not only the corresponding bit in the bit vector of the predicted branch (similar to that previously explained with respect to FIG. 3), but also the corresponding bits in the bit vectors of all in-flight branches older than it. As an example, assuming that branch B_3 shown in FIG. 6 is the branch for which prediction is made, the branch predictor sets a bit for each of the older in-flight branches (e.g., branches B_1, B_2, B_1, and B_2 as previously explained with respect to FIG. 6).

[0040] Step 1020 can include identifying all local branch history registers that require recovery based on the bit vector corresponding to the mis-speculated branch when a flush occurs. As previously explained with respect to FIG. 7, when an in-flight branch (e.g., branches B_1, B_2, B_1, B_2, and B_3 shown in FIG. 6) is flushed, the affected local history registers are identified by examining only the bit vector associated with the flushed branch (e.g., the mis-speculated branch bit vector 750 of FIG. 7).

[0041] Step 1030 can include discarding all bits of all identified local branch history registers that require recovery and setting the value of each respective recovery counter of all identified local branch history registers that require recovery to the maximum value of the recovery counter. Additional details related to bit discarding and recovery counter setting are provided with respect to FIG. 7. Further, as described above, as the branch predictor continues to update these registers (as more branches are predicted) and all suspect bits of the invalidated local branch history registers are replaced with new bits (effectively, when the value of the corresponding recovery counter becomes zero), the branch predictor re-enables that register.

[0042] In conclusion, in one example, the present disclosure relates to a processor including a pipeline having a plurality of stages. The processor can further include a bit vector associated with each in-flight branch associated with the pipeline, each bit vector having bits corresponding to each local branch history register associated with the respective in-flight branch. The processor can further include a recovery counter associated with each local branch history register for tracking the number of bits that require recovery before the local branch history register becomes enabled to participate in branch prediction.

[0043] The processor may further include a branch predictor circuit configured to set bits in a corresponding bit vector indicating an update of the local branch history register due to a branch in response to the update of the local branch history register due to a branch. The branch predictor circuit may be further configured to determine, when a flush occurs, a value indicating the degree of recovery required for each local branch history register affected by the flush, and set the corresponding recovery counter to the value indicating the degree of recovery required.

[0044] A flush may be associated with mis-speculated branches and all in-flight branches younger than the mis-speculated branches. The value indicating the degree of recovery for each local branch history register affected by the flush may be determined by the branch predictor circuit by performing operations including: (1) calculating the sum of the bits of all bit vectors associated with the mis-speculated branches and all in-flight branches younger than the mis-speculated branches as respective first values; (2) adding each first value to the current value of the corresponding recovery counter to determine respective second values; and (3) determining the value indicating the degree of recovery for each local branch history register affected by the flush as the maximum value of the recovery counter and the minimum value of the respective second values.

[0045] The branch predictor circuit may be configured to discard an equal number of bits as the value indicating the degree of recovery for each local branch history register affected by the flush. The branch predictor circuit may be configured to discard all bits of each local branch history register when it is determined that the value indicating the degree of recovery of each local branch history register has the maximum value of the recovery counter. The branch predictor circuit may be configured to update each local branch history register affected by the flush when each additional branch is predicted.

[0046] The branch predictor circuit may be configured to decrement each recovery counter when updating each local branch history register. The branch predictor circuit may be configured to re-enable the use of each local branch history register when each recovery counter is decremented to the value 0. Each local branch history register may be used for branch prediction by the branch predictor circuit only when the value of the corresponding recovery counter is zero.

[0047] In another example, the present disclosure relates to a processor including a pipeline having a plurality of stages. The processor may further include a bit vector associated with each in-flight branch associated with the pipeline, and each bit vector has bits corresponding to each local branch history register associated with the respective in-flight branch. The processor may further include a recovery counter associated with each local branch history register for tracking the number of bits that require recovery before the local branch history register becomes enabled to participate in branch prediction.

[0048] The processor may further include a branch predictor circuit configured to set the bits in the corresponding bit vector indicating the update of the local branch history register by the branch in response to the update of the local branch history register by the branch. The branch predictor circuit may be further configured to identify all local branch history registers that require recovery by performing a logical OR operation on the bit vectors corresponding to the mis-speculated branches and all branches younger than the mis-speculated branches when a flush occurs. The branch predictor circuit may be further configured to discard all bits of all identified local branch history registers that require recovery and set the value of each respective recovery counter of all identified local branch history registers that require recovery to the maximum value of the recovery counter.

[0049] The branch predictor circuit may be configured to update each local branch history register affected by the flush when each additional branch is predicted. The branch predictor circuit may be configured to decrement each recovery counter when updating each local branch history register.

[0050] The branch predictor circuit may be configured to re-enable the use of each local branch history register when each recovery counter is decremented to the value 0. Each local branch history register may be used for branch prediction by the branch predictor circuit only if the value of the corresponding recovery counter is zero.

[0051] In yet another example, the present disclosure relates to a processor including a pipeline having a plurality of stages. The processor may further include a bit vector associated with each in-flight branch associated with the pipeline, each bit vector having bits corresponding to each local branch history register associated with the respective in-flight branch. The processor may further include a recovery counter associated with each local branch history register for tracking the number of bits that require recovery before the local branch history register becomes enabled to participate in branch prediction.

[0052] The processor may further include a branch predictor circuit configured to perform the following in response to an update of the local branch history register for each branch: (1) set bits in a corresponding bit vector indicating the update of the local branch history register for each branch, and (2) set bits in each of the bit vectors corresponding to all in-flight branches older than each branch. The branch predictor circuit may be further configured to identify all local branch history registers that require recovery based on the bit vectors corresponding to the branches mis-speculatively predicted when a flush occurs. The branch predictor circuit may further be configured to discard all bits of all identified local branch history registers that require recovery and set the value of each respective recovery counter of all identified local branch history registers that require recovery to the maximum value of the recovery counter.

[0053] The branch predictor circuit may be configured to update each local branch history register affected by a flush when an additional respective branch is predicted. The branch predictor circuit may be configured to decrement each recovery counter when updating each local branch history register. The branch predictor circuit may be configured to re-enable the use of each local branch history register when each recovery counter is decremented to the value 0.

[0054] Each local branch history register may be used for branch prediction by the branch predictor circuit only if the value of the corresponding recovery counter is zero. The plurality of stages includes a fetch stage, and the branch predictor circuit may be included in the fetch stage.

[0055] It should be understood that the methods, modules, and components described in this specification are merely illustrative. Alternatively, or in addition, the functionality described in this specification may be performed, at least in part, by one or more hardware logic components. By way of example, and not limitation, illustrative types of hardware logic components that may be used include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system on chip systems (SOCs), complex programmable logic devices (CPLDs), and the like. Although abstract, it is nonetheless clear that any arrangement of components for realizing the same functionality is effectively "associated" so that the desired functionality is achieved. Thus, in this specification, any two components combined to realize a particular functionality may be considered to be "associated" with each other so that the desired functionality is achieved, regardless of architecture or intermediate components. Similarly, any two components so associated may also be considered to be "operably connected" or "coupled" to each other to achieve the desired functionality. A component that may be any other implementation of a device, structure, system, or certain functionality is not necessarily meant to be a separate component simply by being described in this specification as being coupled to another component. In one example, component A, described as being coupled to another component B, may be a sub-component of component B, or component B may be a sub-component of component A.

[0056] The functionality associated with some of the examples described in this disclosure can also include instructions stored on a non-transitory medium. As used herein, the term "non-transitory medium" refers to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Exemplary non-transitory media include non-volatile media and / or volatile media. Non-volatile media include, for example, hard disks, solid state drives, magnetic disks or tapes, optical disks or tapes, flash memory, EPROM, NVRAM, PRAM, or other such media, or networked versions of such media. Volatile media include, for example, dynamic memory such as DRAM, SRAM, cache, or other such media. A non-transitory medium is different from a transmission medium but can be used in conjunction with a transmission medium. A transmission medium is used to transfer data and / or instructions between machines. Exemplary transmission media include coaxial cables, fiber optic cables, copper wire, wireless media such as radio waves, and the like.

[0057] Furthermore, those skilled in the art will recognize that the boundaries of the functionality of the operations described above are merely illustrative. The functionality of multiple operations may be integrated into a single operation and / or the functionality of a single operation may be distributed over additional operations. Additionally, alternative embodiments may include multiple instances of a particular operation, and in various other embodiments, the order of the operations may be varied.

[0058] Although this disclosure provides specific examples, various modifications and changes may be made without departing from the scope of the disclosure as set forth in the following claims. Accordingly, this specification and the drawings are to be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the disclosure. None of the benefits, advantages, or solutions to problems described herein with respect to specific examples are intended to be construed as critical, required, or essential features or elements of any or all of the claims.

[0059] Furthermore, as used herein, the terms "a" or "an" are defined as one or more. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to mean that the introduction of another claim element by the indefinite article "a" or "an" limits any particular claim containing the claim element thus introduced to an invention having only one such element. This is the same even when the same claim contains an introductory phrase such as "one or more" or "at least one" and an indefinite article such as "a" or "an". The same is true for the use of the definite article.

[0060] Unless otherwise specified, terms such as "first" and "second" are used to arbitrarily distinguish the elements described by such terms. Thus, these terms are not necessarily intended to indicate a temporal or other priority of such elements.

Claims

1. A pipeline comprising multiple stages, A bit vector associated with each of the in-flight branches associated with the pipeline, wherein each bit vector has bits corresponding to each local branch history register associated with each in-flight branch, Each local branch history register and its associated recovery counter track the number of bits that need to be recovered before the local branch history register becomes active in order to participate in branch prediction. A branch prediction circuit, In response to the update of the local branch history register due to a branch, set a bit in the corresponding bit vector indicating the update of the local branch history register due to the branch, When a flash occurs, a value indicating the degree of recovery required for each local branch history register affected by the flash is determined, and the corresponding recovery counter is set to the value indicating the required degree of recovery. A branch predictor circuit configured to perform the following: A processor that includes this.

2. A processor according to claim 1, wherein the flash is related to a falsely speculative predicted branch and all in-flight branches younger than the falsely speculative predicted branch.

3. The processor according to claim 2, wherein the value indicating the degree of recovery for each local branch history register affected by the flash is determined by the branch predictor circuit, The first value is calculated as the sum of the bits of all bit vectors associated with the incorrectly speculative branch and all in-flight branches younger than the incorrectly speculative branch. The first value is added to the current value of the corresponding recovery counter to determine the second value. The value indicating the degree of recovery for each local branch history register affected by the flash is determined as the minimum of the maximum value of the recovery counter and the respective second values. A processor determined by performing operations that include the following.

4. The processor according to claim 3, wherein the branch predictor circuit is configured to discard a number of bits equal to the value indicating the extent of recovery for each local branch history register affected by flash.

5. A processor according to claim 3, wherein the branch predictor circuit is configured to discard all bits of each local branch history register when it is determined that the value indicating the degree of recovery of each local branch history register has the maximum value of the recovery counter.

6. The processor according to claim 4, wherein the branch predictor circuit is configured to update each local branch history register affected by the flash when each additional branch is predicted.

7. A processor according to claim 6, wherein the branch predictor circuit is configured to decrement each recovery counter when each of the local branch history registers is updated.

8. A processor according to claim 7, wherein the branch predictor circuit is configured to re-enable the use of each local branch history register when each of the recovery counters is decremented to a value of 0.

9. A processor according to claim 1, wherein each local branch history register can be used for branch prediction by the branch predictor circuit only when the value of the corresponding recovery counter is zero.

10. A pipeline including multiple stages, A bit vector associated with each of the in-flight branches associated with the pipeline, wherein each bit vector has bits corresponding to each local branch history register associated with each in-flight branch, Each local branch history register and its associated recovery counter track the number of bits that need to be recovered before the local branch history register becomes active in order to participate in branch prediction. A branch prediction circuit, In response to the update of the local branch history register due to a branch, set a bit in the corresponding bit vector indicating the update of the local branch history register due to the branch, When a flash occurs, all local branch history registers requiring recovery are identified by performing a logical OR operation on the bit vectors corresponding to the incorrectly speculative predicted branch and all branches younger than the said incorrectly speculative predicted branch. Discard all bits in all identified local branch history registers that require recovery, and set the value of each recovery counter in all identified local branch history registers that require recovery to the maximum value of the recovery counter. A branch predictor circuit configured to perform the following: A processor that includes this.

11. A processor according to claim 10, wherein the branch predictor circuit is configured to update each local branch history register affected by flash when each additional branch is predicted.

12. A processor according to claim 11, wherein the branch predictor circuit is configured to decrement each recovery counter when each of the local branch history registers is updated.

13. A processor according to claim 12, wherein the branch predictor circuit is configured to re-enable the use of each local branch history register when each of the recovery counters is decremented to a value of 0.

14. A processor according to claim 10, wherein each local branch history register can be used for branch prediction by the branch predictor circuit only when the value of the corresponding recovery counter is zero.

15. A pipeline including multiple stages, A bit vector associated with each of the in-flight branches associated with the pipeline, wherein each bit vector has bits corresponding to each local branch history register associated with each in-flight branch, Each local branch history register and its associated recovery counter track the number of bits that need to be recovered before the local branch history register becomes active in order to participate in branch prediction. A branch prediction circuit, In response to the update of the local branch history register by each branch, (1) set a bit in the corresponding bit vector indicating the update of the local branch history register by each branch, and (2) set a bit in each of the bit vectors corresponding to all in-flight branches older than each branch. When a flash occurs, all local branch history registers that require recovery are identified based on the bit vector corresponding to the incorrectly speculative predicted branch, Discard all bits in all identified local branch history registers that require recovery, and set the value of each recovery counter in all identified local branch history registers that require recovery to the maximum value of the recovery counter. A branch predictor circuit configured to perform the following: A processor that includes this.

16. The processor according to claim 15, wherein the branch predictor circuit is configured to update each local branch history register affected by flash when each additional branch is predicted.

17. A processor according to claim 16, wherein the branch predictor circuit is configured to decrement each recovery counter when each of the local branch history registers is updated.

18. A processor according to claim 17, wherein the branch predictor circuit is configured to re-enable the use of each local branch history register when each of the recovery counters is decremented to a value of 0.

19. A processor according to claim 15, wherein each local branch history register can be used for branch prediction by the branch predictor circuit only when the value of the corresponding recovery counter is zero.

20. A processor according to claim 15, wherein the plurality of stages include a fetch stage, and the branch predictor circuit is included in the fetch stage.

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