Partial cache collapse considering performance

Abstract

Aspects of the present disclosure relate to systems and methods for improving the performance of partial cache collapse by a processing device. Some embodiments provide a method for performing a partial cache collapse procedure, the method comprising counting, in each cache way of a group of cache ways, the number of cache lines that meet an eviction criterion based on a deterministic cache eviction policy; selecting at least one cache way from the group for collapse based on the corresponding number of cache lines that meet the eviction criterion; and performing a partial cache collapse procedure based on at least one cache way selected from the group for collapse.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority to U.S. Patent Application No. 17 / 827,302, filed May 27, 2022, which was assigned to the assignee of this application and is hereby incorporated by reference in its entirety as if fully set forth herein and for all applicable purposes.

Background Art

[0002] Field of Disclosure Aspects of the present disclosure relate to memory devices, and more particularly, to systems and methods for improving the performance of partial cache collapse by a processing device.

[0003] Description of Related Art Generally, main memory in a computing system may use a random access memory (RAM) device as a volatile memory source. RAM is particularly useful as memory because of its density and speed. One drawback is that in RAM, errors can sometimes occur due to, for example, neutrons or alpha particles crossing the die, defective components, inaccurate system timing, etc. This drawback can be particularly problematic in computing systems that communicate important data or data for which an error - free state is required.

[0004] For this reason, a computer system may include an error correction device that generates and stores one or more error correction code (ECC) bits corresponding to data stored in a RAM. In this case, when the stored data is read from the main memory, the associated ECC bits are also read and sent to the error correction device for proper evaluation and error correction if necessary. In some RAM devices, the ECC bits are stored "inline" with the corresponding data. In one example, for every 512-bit payload data stored in a RAM device, there are associated ECC bits stored in the same DRAM at a different location (address) from the payload data.

[0005] However, to perform certain memory functions (e.g., partial data writes), the RAM regions storing the data and its corresponding ECC bits must be initialized to matching values. For example, an application or processor may need to execute a process to initialize the RAM regions storing both the data and the ECC bits by writing zeros to the regions. However, such a process may require a relatively large amount of time and power. In one example, this can pose a problem for battery-powered RAM devices. As RAM devices are used more, there is a need for further improvements to such devices. SUMMARY OF THE INVENTION

[0006] The systems, methods, and devices of the present disclosure each have several aspects, none of which alone contribute to the desirable attributes thereof. Without limiting the scope of the present disclosure as expressed by the following claims, some features are briefly described herein. After considering this discussion and in particular after reading the section entitled "DETAILED DESCRIPTION OF THE INVENTION," it will be understood how the features of the present disclosure provide advantages.

[0007] Some embodiments provide a method of performing a partial cache collapse procedure. The method generally includes counting, at each cache way of a group of cache ways, the number of cache lines that meet an eviction criterion based on a deterministic cache eviction policy, selecting at least one cache way from the group for collapse based on the corresponding number of cache lines that meet the eviction criterion, and performing a partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

[0008] The following description and associated drawings detail some exemplary features of one or more embodiments.

[0009] The accompanying figures illustrate some aspects of one or more embodiments and, thus, should not be considered as limiting the scope of the disclosure.

Brief Description of the Drawings

[0010]

Figure 1

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[0011] For ease of understanding, where possible, the same reference numbers are used to designate identical elements common to the drawings. Advantageously, it is contemplated that elements and features of one embodiment can be incorporated into other embodiments without further recitation.

DETAILED DESCRIPTION OF THE INVENTION

[0012] Aspects of the present disclosure provide methods and apparatus for improving the performance of partial cache collapse by a processing device.

[0013] In a device that executes computer processing (e.g., a computer, smartphone, system-on-chip (SoCs), etc.), cache memory is an auxiliary memory system that temporarily stores frequently used instructions and data so as to speed up the processing by the device's processor (e.g., a central processing unit (CPU)). By using cache memory, the average time and / or energy used by the processor to access data can be reduced compared to when the processor accesses data from the device's main memory. In other words, when data is found in the cache memory (referred to as a cache hit), that data is accessed much faster than when the data is retrieved from the main memory. The number of cache hits relative to the total number of searches is called the cache hit rate.

[0014] Some devices can be configured to perform partial cache collapse, which generally refers to a mechanism for saving power by selectively applying power (power-gating) to a portion of a shared cache. Processors based on the advanced reduced instruction set computer (RISC) machine (ARM) architecture are examples of devices that can execute partial cache collapse procedures. When a device executes a partial cache collapse procedure, the portion of the cache to be collapsed is typically checked for cache lines for which the dirty bit (i.e., a bit indicating whether the corresponding cache line has been updated) is set. That is, each dirty line of the way to be collapsed is written to main memory to capture the updated data, and that way is collapsed (i.e., the way is power-gated).

[0015] In the conventional partial cache collapse procedure, the selection of the way to be collapsed and the writing of dirty cache lines to the main memory proceed without considering the freshness of the collapsed cache lines with respect to other cache ways. Therefore, generally, the number of main memory accesses during collapse is equal to the number of dirty lines in the collapsed way without considering the replacement policy (the policy applied to determine which cache entry to delete and what to retain). Unfortunately, this results in a decrease in the cache hit rate and a loss of performance.

[0016] However, aspects of the present disclosure provide techniques that can result in an improved partial cache collapse procedure. For example, by considering the freshness of the collapsed cache lines with respect to other cache ways, the cache hit rate can be increased, and correspondingly, the performance is improved.

[0017] Overview of the Memory System The following description provides examples and is not intended to limit the scope, applicability, or embodiments set forth in the claims. Modifications may be made to the functions and configurations of the elements described without departing from the scope of the present disclosure. Various examples may omit, substitute, or add various procedures or components as necessary. For example, the methods described may be performed in an order different from the order described, and various steps may be added, omitted, or combined. Also, the features described for some examples may be combined with those of some other examples. For example, the apparatus may be implemented or the method may be practiced using any number of aspects described herein. In addition, the scope of the present disclosure is intended to include apparatuses or methods that are practiced using other structures, functions, or a combination of structures and functions in addition to or other than the various aspects of the present disclosure described herein. It should be understood that any aspect of the present disclosure disclosed herein may be embodied by one or more elements of the claims.

[0018] Some teachings of the present disclosure are shown with respect to a dynamic random access memory (DRAM) device as an exemplary memory device, but the present teachings are applicable in other areas, such as other volatile memory devices (e.g., static RAM (SRAM), synchronous SRAM (SDRAM), Rambus DRAM (RDRAM)). Further, some teachings of the present disclosure are shown with respect to a system on chip (SoC), but the present teachings are applicable to any suitable computing device that utilizes memory. Accordingly, the disclosed teachings should not be construed as being limited to DRAM devices or SoCs or the illustrated embodiments. The illustrated embodiments are merely means for explaining and illustrating examples of the teachings of the present invention disclosed herein.

[0019] FIG. 1 shows exemplary components and interconnections in a system on chip (SoC) 100 coupled to a volatile memory 124 (e.g., DRAM) suitable for implementing various aspects of the present disclosure. SoC 100 may include several heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 can include one or more cores, and each processor / core can execute operations independently of other processors / cores. Processors 102, 104, 106, 108 can be arranged in very close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.), and thus these processors can operate at much higher frequencies / clocks than would be possible if signals had to travel outside the chip. The proximity of the cores can also enable sharing of on-chip memory and resources (e.g., voltage rails), as well as more coordinated cooperation between the cores.

[0020] Processors 102, 104, 106, 108 can be interconnected to memory controller 114 and other system components (not shown) via an interconnect / bus module 122, and the interconnect / bus module 122 can include an array of reconfigurable logic gates and / or implement a bus architecture (e.g., CoreConnect, advanced microcontroller bus architecture (AMBA), etc.). Communication may be provided by advanced interconnects such as high-performance networks on a chip (NoCs).

[0021] Memory controller 114 may include a dedicated hardware module configured to receive various memory transactions from one or more masters, address the memory transactions, and communicate them to memory 124. The one or more masters may include one or more of processors 102, 104, 106, 108 and / or applications operating on processors 102, 104, 106, 108. Memory controller 114 may also schedule and / or initiate refresh cycles and manage the maintenance of memory 124, such as clear content (e.g., data and / or code) commands, as described herein. In some examples, memory controller 114 may include one or more processors configured to perform the operations disclosed herein. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gate logic, individual hardware circuits, and other suitable hardware configured to perform the various functions described throughout this disclosure. Memory 124 and memory controller 114 may be on-chip components of SoC 100 (e.g., on a substrate, die, integrated chip, etc.). However, note that in some examples, one or more of memory 124 and memory controller 114 may be located off-chip.

[0022] Memory 124 is a computer-readable storage medium having an interface to processors 102, 104, 106, 108 via bus module 122. As described, memory 124 may be an on-chip component or, as shown, an off-chip component. Memory 124 can provide volatile storage, such as DRAM, for processors 102, 104, 106, 108 and / or other functional aspects of SoC 100. As shown, memory controller 114 includes ECC module 130. ECC module 130 is configured to implement ECC logic for detecting and correcting errors within memory 124, as described and known in the art. In some aspects, ECC module 130 is configured to execute in-line ECC logic.

[0023] Memory 124 may also include a hierarchy of one or more ranks 134 and a plurality of banks 132a - 132j (collectively referred to as banks 132) within each rank 134. For example, memory 124 can include multiple ranks, and each rank can include a plurality of internal bank structures. In some examples, each bank structure can include a plurality of memory pages or "rows". Generally, one row of memory can be accessed on each bank at a given time. Each of the banks 132 of a given rank 134 can share a bus (not shown) for reading / writing data. Memory controller 114 can support the simultaneous operation of different ranks 134 and banks 132 that can be accessed independently. Since each bank 132 operates as an independent entity, banks 132 can process multiple memory requests in parallel, providing bank-level parallelism.

[0024] Overview of Cache Architecture with Partial Cache Collapse FIG. 2 is a schematic diagram showing an exemplary cache architecture 200 that can be configured using a conventional partial cache collapse procedure. The cache architecture 200 can be included in the memory controller 114 of the SoC 100, or can be incorporated into any of the CPU 102, modem processor 104, GPU 106, or application processor 108 all shown in FIG. 1. The cache 200 includes a cache controller 202 and a cache memory 220. The cache memory 220 stores cache lines, and each cache line includes a cache tag (indicated by 222), a validity bit (indicated by 224), a dirty bit (indicated by 226), and data (indicated by 228). The cache tag within each cache line indicates the memory location in the main memory that is the source of the copy of that cache line. The validity bit indicates whether valid data is loaded into the cache line.

[0025] During the operation of the cache, a processor core (e.g., any of CPU 102, modem processor 104, GPU 106, or application processor 108) issues a memory address 210 of the memory that the processor core needs to access for reading or writing. In an exemplary cache, the cache controller compares the tag portion 212 of the memory address with the cache tag (shown as 222) of the cache line stored in the cache memory. If the cache controller finds that the tag portion matches the cache tag in the cache memory, a cache hit has occurred. However, if the cache controller does not find a cache tag in the cache memory that matches the tag portion, a cache miss has occurred. In the case of a cache hit, the cache controller immediately reads or writes the data of the corresponding cache line. When the processor core issues a read for a memory location, the cache controller supplies the data of the corresponding cache line to the processor core via the data bus 230. In the case of a cache miss, the cache controller allocates a new cache line in the cache memory, copies the data from the main memory to the new cache line, and then the request from the processor core is satisfied from the content of the new cache line.

[0026] An exemplary cache is a 4-way cache, and thus each main memory location corresponds to one location in each of the 4 ways 240, and the data for any particular main memory location can be stored at the corresponding location in each of the 4 ways. Each of the 4 cache memory locations (i.e., one cache memory location per way) where the data for a main memory location can be stored can be referred to as a member of a set of cache memory locations, and each such set has a corresponding set index. Each way has a corresponding way mask 270. When a cache miss occurs, the cache controller attempts to allocate a new cache line to a location within the currently unused cache memory. Thus, in an exemplary 4-way cache, when the cache controller is allocating a new cache line, the cache controller checks up to 4 locations (one per way) to determine if there is an unused one. If there is no unused location, the cache controller examines the replacement policy 260 to determine which of the 4 locations can evict the current data so that a new cache line can be allocated.

[0027] When a device including an exemplary cache determines to perform a partial cache collapse, one of the 4 ways is selected to be power gated. The cache controller executes corresponding way collapse logic (denoted by 280) when collapsing the selected way. Each of the way collapse logic includes sequentially executing dirty line search logic 250, which seeks dirty and marked cache lines (i.e., cache lines for which the dirty bit 226 is set), searches the selected way, and writes those cache lines to the corresponding main memory location known from the cache tag of the cache line.

[0028] As described previously, in the conventional partial cache collapse procedure, the selection of the way to be collapsed and the writing of dirty cache lines to the main memory proceed without considering the freshness of the collapsed cache lines with respect to other cache ways. For this reason, generally, without considering the eviction policy (the policy applied to determine which cache entries to delete and which cache entries to retain), the number of main memory accesses during collapse is equal to the number of dirty lines in the collapsed way, the cache hit rate decreases, and the performance deteriorates.

[0029] Exemplary Techniques for Partial Cache Collapse Considering Performance However, aspects of the present disclosure provide techniques that can result in an improved partial cache collapse procedure. For example, by considering the freshness of the collapsed cache lines with respect to other cache ways, the cache hit rate can increase relative to systems that utilize the conventional partial cache collapse procedure.

[0030] The partial collapse mechanism described herein can help optimize the partial cache collapse procedure with respect to performance by increasing the cache hit rate. This increased cache hit rate can lead to improved performance.

[0031] The operations performed during the partial cache collapse procedure considering performance proposed herein may be referred to herein as sequential way processing. As shown in FIG. 3A, a cache architecture 300 configured to execute the partial cache collapse procedure considering performance proposed herein can include cache line replacement logic 350 that includes sequential search logic, the details of which are described below.

[0032] This sequential way processing can be started when a specific collapse criterion is met. If such a collapse criterion is not met, the cache can behave as a conventional cache (e.g., without sequential way processing logic). Depending on the specific implementation, the collapse criterion can be based on the number of active cores or on dedicated requirements for partial cache collapse by the core or software. For example, the collapse criterion can be that the number of active cores is greater than a threshold number before partial cache collapse is executed. As another example, the number of ways to be collapsed can depend on the number of active cores.

[0033] If the collapse criterion is met, the sequential way processing logic and additional hardware (e.g., logic 350 in FIG. 3A) can activate and implement the selected collapse policy.

[0034] In some cases, the cache architecture 300 may include logic 380 configured to count the number of cache lines that meet the eviction criteria based on a deterministic cache eviction policy 360 in each cache way of a group of cache ways. Any suitable deterministic cache eviction policy can be used. For example, the deterministic cache eviction policy can instruct that the least recently used (LRU) cache line or the least frequently used (LFU) cache line is evicted. Thus, the logic 380 can include a counter ("crit - sat") for each way to count the number of cache lines that meet the eviction criteria, such as the number of LRU or LFU cache lines for a given way.

[0035] The cache controller can then select at least one cache way from the group for collapse (and can execute a partial cache collapse procedure based on the at least one cache way selected from the group for collapse) based on the corresponding number of cache lines that meet the eviction criteria.

[0036] In the example shown in FIG. 3B, way 0 is selected for collapse because, for example, it has the most cache lines that meet the deterministic cache eviction policy criteria (e.g., the most LRU lines or the most LFU lines).

[0037] Logic 350 can then sequentially check the (one or more) collapse cache ways selected for non-LRU cache lines. When a non-LRU cache line is found, the least recently used cache line from the corresponding non-collapse ways of the same set can be evicted and replaced by the non-LRU line from the collapse way. This technique can help avoid eviction of non-LRU cache lines, leading to an increase in cache hits and a decrease in DDR reads (and thus an improvement in performance).

[0038] This technique can be understood with reference to FIGS. 4A and 4B. As shown in FIG. 4A, the way selected for collapse (e.g., way 0 from FIG. 3B) can have one or more non-LRU cache lines 410 (which means they have been accessed relatively recently), while the ways not selected for collapse can have one or more LRU cache lines 420 (which means they have not been accessed relatively recently).

[0039] As shown in Figure 4B, an LRU cache line 420 from a non-collapsed way can be evicted and replaced by a non-LRU cache line 410 from a collapsed way. In other words, the evicted LRU cache line 420 from a non-collapsed way is assigned to the non-LRU cache line 410 from a collapsed way.

[0040] As shown in Figure 4B, in some cases, when selecting which LRU cache line to evict from a non-collapsed way, if possible, a cache line without a dirty bit can be selected. This technique can result in eviction (flushing) of cache lines without the need for writes, saving memory transactions, and further saving time and power.

[0041] The above example considered a single-way collapse, but in some cases, it may be necessary (or desirable) to collapse two or more ways (e.g., N ways). In such cases, the techniques described above can be implemented to select the N ways with the most lines that meet the eviction criteria. For example, the N ways with the N highest counts of LRU lines can be selected and excluded from the replacement operations from the first-way collapse. When the collapse is performed, the N ways include LRU, LRU-1, LRU-2,..., LRU-(N-1) cache lines.

[0042] The performance-aware partial collapse procedure described herein can have several advantages. For example, by selecting the (one or more) ways with the most LRU lines for collapse, the amount of activity during collapse can be reduced. Instead of lines from the collapse way, a collapse policy for evicting available LRU lines from the active ways can avoid disruption of locality. A collapse policy for retaining the MRU line (or at least the cache lines that are temporarily important) according to the cache eviction policy implemented can help reduce potential DDR transactions by increasing the cache hit rate.

[0043] Potential performance improvements can be understood by considering exemplary memory access latencies at different memory levels. For example, as shown in FIG. 5, the latency of a memory access to DDR memory (510) can be, on average, 128 CPU cycles per memory access, the latency of a memory access to level 3 (L3) cache (520) can be 26 CPU cycles per memory access, the latency of a memory access to level 2 (L2) cache (530) can be 7 CPU cycles per memory access, and the latency of a memory access to level 1 (L1) cache (540) can be 2 CPU cycles per memory access. Given these exemplary values, increasing the cache hit rate using the performance-aware partial collapse procedure described herein can help avoid a potential time penalty of approximately 5 times the DDR accesses during collapse.

[0044] Performing sequential processing for the performance-aware partial collapse procedure described herein can take some time, for example, to complete the replacement (swapping) described with reference to FIGS. 4A and 4B. In some cases, if a read or write request (to L3) arrives during this time, the sequential processing can be stopped until the request is processed.

[0045] In some cases, all ways (including the way being considered for collapse) may remain visible for reading. If a read request is for an already processed index and results in a cache hit on a cache line in one of the ways not selected for partial collapse, it may not be necessary to process the index. On the other hand, if the read request hits a collapse way, the index can be reprocessed.

[0046] In some cases, sequential processing can be stopped upon arrival of a write request. Thus, the write request can essentially view an L3 cache where only non-collapse ways are active. In other words, the way being considered for collapse may not be visible for writing. When writing to an already processed index, since the write request evicts one of the non-collapse ways, the evicted line can be rewritten to the DDR (if dirty) or swapped with a collapse way line (e.g., if the collapse line is non-dirty depending on what is prioritized). Writing to an unprocessed index can be handled like a normal L3 write where all ways are visible.

[0047] In some cases, the collapse policy can use information about speculative traffic and, with the help of existing logic such as address pattern detection, random address pattern detectors, and prefetch block addresses, start sequential processing using the selected collapse policy. In such cases, it may be possible to create an address access pattern that can maintain sequential processing so that the same index is stalled or processed iteratively. To avoid such locking, a timer-based sequential processing cancelation can be implemented. Alternatively, a limit can be set on the number of sweeps for sequential processing. In such cases, when the timer expires or the sweep limit is reached, since it may indicate high traffic, either the collapse process can be stopped or the L3 transaction can be stopped to complete the collapse process.

[0048] Exemplary method FIG. 6 is a flowchart showing exemplary operation 600 for performing a partial cache collapse procedure according to a particular aspect of the present disclosure. For example, the steps of the operation in FIG. 6 can be performed by a memory controller (e.g., memory controller 114 of FIG. 1) or another suitable circuit.

[0049] Operation 600 begins at step 605 and counts the number of cache lines that meet the eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways.

[0050] Operation 600 can proceed to step 610 and select at least one cache way from the group for collapse based on the corresponding number of cache lines that meet the eviction criteria.

[0051] Operation 600 can proceed to step 615 and execute a partial cache collapse procedure based on at least one cache way selected from the group for collapse.

[0052] In some embodiments, the deterministic cache eviction policy includes at least one of a least recently used (LRU) cache line eviction policy or a least frequently used (LFU) cache line eviction policy.

[0053] In some embodiments, operation 600 includes determining that one or more collapse criteria are met before executing a partial cache collapse procedure.

[0054] In some embodiments, the collapse criteria are based on at least one of the number of active cores or a request for partial cache collapse.

[0055] In some embodiments, executing a partial cache collapse procedure includes identifying one or more sets, each including at least one cache line that does not meet an eviction criterion in a cache way selected from a group for collapse, and in each of the identified sets, evicting a cache line that meets an eviction criterion from another cache way from a group of ways not selected for collapse, and allocating the evicted cache line to a cache line that does not meet an eviction criterion from a cache way selected from a group for collapse.

[0056] In some embodiments, cache lines from at least one other cache way meet additional criteria.

[0057] In some embodiments, operation 600 includes selecting a cache line that meets an additional criterion from one or more non-dirty cache lines of at least one other cache way.

[0058] In some aspects, selecting at least one cache way from a group for collapse includes selecting, for collapse, the one cache way having the largest number of cache lines that meet the eviction criteria.

[0059] In some aspects, selecting at least one cache way from a group for collapse includes selecting a plurality of cache ways having the largest number of cache lines that meet the eviction criteria.

[0060] In some aspects, performing a partial collapse procedure includes excluding cache lines of a plurality of cache ways that meet the eviction criteria from the replacement operation.

[0061] FIG. 7 shows a processing system 700 that may include various components configured to perform operations for techniques disclosed herein, such as the operations shown in FIG. 6. The processing system 700 includes a processor 704 coupled via a bus 706 to a computer-readable medium / memory 712. In some aspects, the computer-readable medium / memory 712 is configured to store computer-executable instructions (e.g., computer-executable code) that, when executed by the processor 704, cause the processor 704 to perform the operations shown in FIG. 6 or other operations for performing various techniques described herein for performing a partial cache collapse.

[0062] In some aspects, the computer-readable medium / memory 712 stores code 714 for counting the number of cache lines that meet an eviction criterion based on a deterministic cache eviction policy at each cache way of a group of cache ways, code 716 for selecting at least one cache way from the group for collapse based on the corresponding number of cache lines that meet the eviction criterion, and code 717 for performing a partial cache collapse procedure based on at least one cache way selected from the group for collapse.

[0063] In some aspects, the processor 704 has circuitry configured to implement the code stored within the computer-readable medium / memory 712. The processor 704 includes circuitry 720 for counting the number of cache lines that meet an eviction criterion based on a deterministic cache eviction policy at each cache way of a group of cache ways, circuitry 722 for selecting at least one cache way from the group for collapse based on the corresponding number of cache lines that meet the eviction criterion, and circuitry 724 for performing a partial cache collapse procedure based on at least one cache way selected from the group for collapse.

[0064] Exemplary Clauses In the following numbered clauses, implementation examples are described.

[0065] Clause 1: A method of performing a partial cache collapse procedure, the method comprising: counting, at each cache way of a group of cache ways, the number of first cache lines that meet an eviction criterion based on a deterministic cache eviction policy; selecting, based on the corresponding number of cache lines that meet the eviction criterion, at least one cache way from the group for collapse; and performing a partial cache collapse procedure based on at least one cache way selected from the group for collapse.

[0066] Clause 2: The method according to clause 1, wherein the deterministic cache eviction policy includes at least one of a least recently used (LRU) cache line eviction policy or a least frequently used (LFU) cache line eviction policy.

[0067] Clause 3: The method according to clause 1, further comprising determining that one or more collapse criteria are met before executing the partial cache collapse procedure.

[0068] Clause 4: The method according to clause 3, wherein the collapse criteria are based on at least one of the number of active cores or the request for partial cache collapse.

[0069] Clause 5: Executing the partial cache collapse procedure includes identifying one or more sets, each including at least one cache line that does not meet the eviction criteria in the cache way selected from the group for collapse, and in each of the identified sets, evicting a cache line that meets the eviction criteria from another cache way from the group of ways not selected for collapse, and assigning the evicted cache line to a cache line that does not meet the eviction criteria from the cache way selected from the group for collapse.

[0070] Clause 6: The method according to clause 5, wherein the cache line from another cache way meets an additional criterion.

[0071] Clause 7: The method according to clause 6, further comprising selecting a cache line that meets the additional criterion from one or more non-dirty cache lines of another cache way.

[0072] Clause 8: Selecting at least one cache way from a group for collapse includes selecting, for collapse, the one cache way with the largest number of cache lines that meet the eviction criteria, as described in Clause 1.

[0073] Clause 9: Selecting at least one cache way from a group for collapse includes selecting, for collapse, a plurality of cache ways with the largest number of cache lines that meet the eviction criteria, as described in Clause 1.

[0074] Clause 10: Performing a partial collapse procedure includes excluding, from the replacement operation, the cache lines of a plurality of cache ways that meet the eviction criteria, as described in Clause 9.

[0075] An apparatus comprising a memory including executable instructions and a processor configured to execute the executable instructions to cause the apparatus to perform the method according to any one of Clauses 1 to 10.

[0076] An apparatus comprising means for performing the method according to any one of Clauses 1 to 10.

[0077] A non-transitory computer-readable medium comprising computer-executable instructions that, when executed by a processor of an apparatus, cause the apparatus to perform the method according to any one of Clauses 1 to 10.

[0078] A computer program product embodied on a computer-readable storage medium comprising code for performing the method according to any one of Clauses 1 to 10.

[0079] Additional Information The foregoing description is provided to enable any person skilled in the art to practice the various embodiments described herein. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments as well. For example, the functions and arrangements of the elements described may be changed without departing from the scope of the disclosure. The various examples may omit, substitute, or add various procedures or components as necessary. Also, the features described for some embodiments may be combined with those of some other embodiments. For example, the apparatus may be implemented or the method may be practiced using any number of aspects described herein. In addition, the scope of the disclosure is intended to encompass apparatuses or methods practiced using other structures, functions, or a combination of structures and functions in addition to, or other than, the various aspects of the disclosure described herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the claims.

[0080] As used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects.

[0081] As used herein, the phrase referring to an enumeration of items "at least one of" refers to any combination of those items, including a single member. By way of example, "at least one of a, b, or c" is intended to include a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination having multiple of the same elements (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c, or any other order of a, b, and c).

[0082] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, database, or another data structure), ascertaining, and the like. Also, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Further, "determining" may include resolving, selecting, choosing, establishing, and the like.

[0083] The methods disclosed herein include one or more steps or actions for achieving the methods. The steps and / or actions of those methods can be interchanged with each other without departing from the scope of the claims. In other words, unless a particular order of steps or actions is specified, the order of particular steps and / or actions, and / or the use of those steps and / or actions, can be modified without departing from the scope of the claims. Furthermore, the various operations of the methods described above can be implemented by any suitable means capable of performing the corresponding functions. Those means can include, but are not limited to, circuits, application specific integrated circuits (ASICs), or processors, and can include various hardware components and / or software components (singular or plural), and / or various hardware modules and / or software modules (singular or plural). Generally, when operations are shown in figures, those operations can have corresponding equivalent means-plus-function components with similar numbers.

[0084] The various illustrative logical blocks, modules, and circuits described in connection with the present disclosure may be implemented or executed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gates or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0085] The processing system may be implemented using a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and overall design constraints. The bus may link together various circuits including, among other things, a processor, a machine-readable medium, and an input / output device. A user interface (e.g., keypad, display, mouse, joystick, etc.) may also be coupled to the bus. The bus may also link together various other circuits such as a timing source, peripheral devices, voltage regulators, power management circuits, etc., which are well known in the art and will not be described any further. The processor may be implemented using one or more general purpose and / or dedicated processors. By way of example, a microprocessor, a microcontroller, a DSP processor, and other circuits capable of executing software are included. Those of ordinary skill in the art will recognize how best to implement the described functions of the processing system depending on the particular application and overall design constraints imposed on the overall system.

[0086] When implemented in software, the functions may be stored on a computer-readable medium as one or more instructions or code, or may be transmitted via a computer-readable medium. Software is broadly construed to mean instructions, data, or any combination thereof, whether called software, firmware, middleware, microcode, hardware description language, or by any other name. Computer-readable media includes both computer storage media and communication media such as any medium that facilitates transfer of a computer program from one place to another. A processor may be in charge of general processing, including managing buses and executing software modules stored on a computer-readable storage medium. The computer-readable storage medium may be coupled to the processor so that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. By way of example, the computer-readable media may include transmission lines, carrier waves modulated by data, and / or computer-readable storage media having instructions stored thereon separate from a wireless node, all of which may be accessed by the processor via a bus interface. Alternatively, or in addition, the computer-readable media or any part thereof may be integrated with the processor, as cache and / or general purpose register files may be. Examples of machine-readable storage media may include, by way of example, random access memory (RAM), flash memory, read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), registers, magnetic disk, optical disk, hard drive, or any other suitable storage medium, or any combination thereof. The machine-readable media may be embodied in a computer program product.

[0087] A software module may comprise a single instruction or multiple instructions and may be distributed across different programs, across multiple storage media, and across several different code segments. A computer-readable medium may comprise several software modules. A software module contains instructions that, when executed by an apparatus such as a processor, cause the processing system to perform various functions. A software module may include a sending module and a receiving module. Each software module may reside within a single storage device or may be distributed across multiple storage devices. By way of example, a software module may be loaded from a hard drive into RAM when a trigger event occurs. During execution of a software module, the processor may load some of the instructions into a cache to increase access speed. One or more cache lines may then be loaded into a general-purpose register file for execution by the processor. When referring to the functionality of a software module, it will be understood that such functionality is implemented by the processor when executing instructions from that software module.

[0088] The following claims are not intended to be limited to the embodiments shown in this specification, but rather should be given the full scope consistent with the language of the claims. In the claims, the reference to an element in the singular is not intended to mean "one and only one" unless so stated, but rather is intended to mean "one or more." The term "some," unless otherwise specified, refers to one or more. An element of a claim should not be construed under 35 U.S.C. § 112(f) unless the element is expressly recited using the phrase "means for" or, in the case of a method claim, the element is expressly recited using the phrase "step of." All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is expressly recited in the claims.

Claims

1. A method for performing a partial cache collapse procedure, comprising: counting, in each cache way of a group of cache ways, the number of cache lines that meet an eviction criterion based on a deterministic cache eviction policy; selecting at least one cache way from the group for collapse based on the corresponding number of cache lines that meet the eviction criterion; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse. A method comprising the above steps.

2. The method according to claim 1, wherein the deterministic cache eviction policy includes at least one of a least recently used (LRU) cache line eviction policy or a least frequently used (LFU) cache line eviction policy.

3. The method according to claim 1, further comprising determining that one or more collapse criteria are met before performing the partial cache collapse procedure.

4. The method according to claim 3, wherein the collapse criteria are based on at least one of the number of active cores or a request for partial cache collapse.

5. The step of performing the partial cache collapse procedure includes: identifying one or more sets, each including at least one cache line that does not meet the eviction criterion in the cache way selected from the group for collapse; and in a set among the identified sets under consideration, evicting a cache line that meets the eviction criterion from another cache way of the group of cache ways not selected for collapse, and allocating the evicted cache line to the cache line that does not meet the eviction criterion from the cache way selected from the group for collapse. The method according to claim 1, including the above steps.

6. The method according to claim 5, wherein the cache line from the other cache way meets an additional criterion.

7. The method according to claim 6, further comprising selecting the cache line that meets the additional criterion from one or more non-dirty cache lines of the other cache way.

8. The step of selecting at least one cache way from the group for collapse includes the step of selecting one cache way having the largest number of cache lines satisfying the eviction criterion for collapse, according to the method of Claim 1.

9. The step of selecting at least one cache way from the group for collapse includes the step of selecting a plurality of cache ways having the largest number of cache lines satisfying the eviction criterion, according to the method of Claim 1.

10. The step of executing the partial cache collapse procedure includes the step of excluding the cache lines of the plurality of cache ways satisfying the eviction criterion from the replacement operation, according to the method of Claim 9.

11. An apparatus for executing a partial cache collapse procedure, including a memory containing computer-executable instructions, executing the computer-executable instructions to cause the apparatus to count the number of cache lines satisfying an eviction criterion based on a deterministic cache eviction policy at each cache way of a group of cache ways, select at least one cache way from the group for collapse based on the corresponding number of cache lines satisfying the eviction criterion, and execute the partial cache collapse procedure based on the at least one cache way selected from the group for collapse a processor configured to perform the above and an apparatus comprising the processor.

12. The apparatus of Claim 11, wherein the deterministic cache eviction policy includes at least one of a least recently used (LRU) cache line eviction policy or a least frequently used (LFU) cache line eviction policy.

13. The apparatus of Claim 11, wherein the processor is further configured to determine that one or more collapse criteria are satisfied before executing the partial cache collapse procedure.

14. The apparatus of Claim 13, wherein the collapse criteria are based on at least one of the number of active cores or a request for partial cache collapse.

15. The processor being configured to execute the partial cache collapse procedure means that the processor Identifying one or more sets, each including at least one cache line in the cache way selected from the group that does not meet the eviction criteria for collapse; In the set among the identified sets under consideration, evicting a cache line of another cache way from the group of cache ways not selected for collapse that meets the eviction criteria, and allocating this evicted cache line to the cache line that does not meet the eviction criteria from the cache way selected from the group for collapse; The apparatus according to claim 11, comprising being configured to perform.

16. The apparatus according to claim 15, wherein the processor is further configured to determine that the cache line from the other cache way meets an additional criterion.

17. The apparatus according to claim 16, wherein the processor is further configured to select the cache line that meets the additional criterion from one or more non-dirty cache lines of the other cache way.

18. The apparatus according to claim 11, wherein the processor being configured to select at least one cache way from the group for collapse includes that the processor is configured to select, for collapse, the cache way with the largest number of cache lines that meet the eviction criteria.

19. The apparatus according to claim 11, wherein the processor being configured to select at least one cache way from the group for collapse includes that the processor is configured to select a plurality of cache ways with the largest number of cache lines that meet the eviction criteria.

20. The apparatus according to claim 19, wherein the processor being configured to execute the partial cache collapse procedure includes that the processor is configured to exclude the cache lines of the plurality of cache ways that meet the eviction criteria from the replacement operation.

21. A non-transitory computer-readable medium comprising computer-executable instructions that, when executed by a processor of a device, cause the device to perform a partial cache collapse procedure, the partial cache collapse procedure comprising: counting, in each cache way of a group of cache ways, the number of cache lines that meet an eviction criterion based on a deterministic cache eviction policy; selecting at least one cache way from the group for collapse based on the corresponding number of cache lines that meet the eviction criterion; performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse comprising a non-transitory computer-readable medium. **Claim 22** The non-transitory computer-readable medium of claim 21, wherein the deterministic cache eviction policy includes at least one of a least recently used (LRU) cache line eviction policy or a least frequently used (LFU) cache line eviction policy. **Claim 23** The non-transitory computer-readable medium of claim 21, wherein the partial cache collapse procedure further includes determining that one or more collapse criteria are met before performing the partial cache collapse procedure. **Claim 24** The non-transitory computer-readable medium of claim 23, wherein the collapse criteria are based on at least one of the number of active cores or a request for partial cache collapse. **Claim 25** Performing the partial cache collapse procedure includes: identifying one or more sets, each including at least one cache line that does not meet the eviction criterion in the cache way selected from the group for collapse; in a set among the identified sets under consideration, evicting a cache line that meets the eviction criterion from another cache way of the group of cache ways not selected for collapse, and allocating the evicted cache line to the cache line that does not meet the eviction criterion from the cache way selected from the group for collapse The non-transitory computer-readable medium according to claim 21, comprising

26. The non-transitory computer-readable medium according to claim 25, wherein the cache line from the other cache way meets an additional criterion.

27. The non-transitory computer-readable medium according to claim 26, wherein the partial cache collapse procedure further comprises selecting the cache line that meets the additional criterion from one or more non-dirty cache lines of the other cache way.

28. Selecting at least one cache way from the group for collapse comprises selecting the cache way with the largest number of cache lines that meet the eviction criterion for collapse, as described in claim 21 of the non-transitory computer-readable medium.

29. Selecting at least one cache way from the group for collapse comprises selecting a plurality of cache ways with the largest number of cache lines that meet the eviction criterion, as described in claim 21 of the non-transitory computer-readable medium.

30. An apparatus for performing a partial cache collapse procedure, means for counting the number of cache lines that meet an eviction criterion based on a deterministic cache eviction policy at each cache way of a group of cache ways; means for selecting at least one cache way from the group for collapse based on the corresponding number of cache lines that meet the eviction criterion; means for performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse; An apparatus comprising

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