Variable Capacitor Device Using Differential Voltage Control

Abstract

The variable capacitor device includes first and second control paths, and the first and second control paths are configured to enable differential control by using first and second transistors of the same doping type in the first and second control paths, respectively. The first and second transistors are configured as voltage variable resistors for adjusting the capacitance of the variable capacitor device.

Description

Technical Field

[0001] The present disclosure generally relates to voltage-controlled variable capacitor devices, and more particularly to differential voltage control for use in continuously tuning the frequency of oscillator circuits such as voltage-controlled oscillator (VCO) circuits, or other types of systems that implement a resonant load using a variable capacitor device.

Background Art

[0002] A voltage-controlled variable capacitor (alternatively referred to herein as a varactor) is an important component used for continuously tuning the frequency of an oscillator circuit (also known as analog tuning). Conventional varactor devices may exhibit undesirable characteristics that lead to performance degradation in continuous frequency tuning applications.

[0003] For example, a varactor device has a minimum capacitance (C MIN ) to a maximum capacitance (C MAX)It may have undesirable transfer characteristics, such as a capacitance versus control voltage transfer curve with a steep transition to (). In such a case, when differentiating the capacitance versus control voltage transfer curve of a varactor device, for example, the gain of a VCO having an LC resonance tank implemented using a varactor becomes extremely non-uniform. In this regard, an effective and flexible technique for linearizing the response of a varactor device is desirable. Further, since the differential control method provides resistance to common mode noise, it is desirable to implement a differential control method to adjust the capacitance of a varactor device. Usually, regardless of the implementation of the varactor, the differential control of the varactor is implemented using complementary transistor structures (for example, N-type and P-type field effect transistor (FET) devices) in the control path. However, the differential control method using complementary NFET and PFET devices has poor consistency between the NFET and PFET devices under process and temperature variations, and as a result, the performance may deteriorate. Another drawback associated with conventional varactor devices is that there is no mechanism for independently controlling the differential varactor gain with respect to the common mode varactor gain.

Summary of the Invention

[0004] Exemplary embodiments of the present disclosure include a voltage-variable capacitor device implementing a voltage-variable resistor-adjusted capacitor architecture with differential control. In an exemplary embodiment, the variable capacitor device includes first and second control paths, and the first and second control paths are configured to enable differential control by using first and second transistors of the same doping type in the first and second control paths, respectively, and the first and second transistors are configured as voltage variable resistors for adjusting the capacitance of the variable capacitor device.

[0005] Advantageously, the variable capacitor device includes an architecture that enables differential control of the variable capacitor device using transistor devices having the same transistor type (e.g., N-type or P-type) in order to achieve uniformity and symmetry in the transfer characteristics of the variable capacitor device. The architecture of the variable capacitor device eliminates the need to use complementary transistor devices (e.g., an N-type and a P-type transistor pair) in the control path to enable differential control of the variable capacitor device. When using complementary transistor devices, the matching between the complementary transistor devices is poor, and as a result, the performance of the variable capacitor device deteriorates.

[0006] In an exemplary embodiment of the variable capacitor device, a first control path includes a first transistor and at least one capacitor connected in series between a first terminal and a second terminal of the variable capacitor device, and a second control path includes a second transistor and at least one capacitor connected in series between the first terminal and the second terminal of the variable capacitor device. The variable capacitor device further includes differential control terminals including a first control terminal and a second control terminal, where the first control terminal is coupled to the gate terminal of the first transistor and the second control terminal is coupled to the first and second source / drain terminals of the second transistor. The variable capacitor device further includes a first adjustment terminal and a second adjustment terminal, where the first adjustment terminal is coupled to the first and second source / drain terminals of the first transistor and the second adjustment terminal is coupled to the gate terminal of the second transistor.

[0007] Advantageously, the implementation of the adjustment terminal of the variable capacitor device allows an adjustment voltage (e.g., a static adjustment voltage) to be applied to the variable capacitor device. Such an adjustment voltage provides a mechanism for independently setting the common-mode gain and differential-mode gain of the variable capacitor device. In addition, the implementation of the adjustment terminal of the variable capacitor device provides a mechanism for adjusting the effective threshold voltages of the first and second transistors of the first and second control paths, and thus two or more instances of the variable capacitor device having appropriately offset effective threshold voltages can be combined in parallel to form a composite variable capacitor structure with improved linearization.

[0008] Another exemplary embodiment includes a device comprising an oscillator circuit including a resonant tank circuit. The resonant tank circuit includes a variable capacitor device including first and second control paths, the first and second control paths being configured to enable differential control by using first and second transistors of the same doping type in the first and second control paths respectively, and the first and second transistors being configured as voltage variable resistors for adjusting the capacitance of the variable capacitor device.

[0009] Another exemplary embodiment includes a device comprising a voltage-controlled oscillator circuit including a resonant tank circuit. The resonant tank circuit includes a variable capacitor circuit including a plurality of variable capacitor devices connected in parallel to the first and second tank nodes of the resonant tank circuit. Each variable capacitor device includes first and second control paths, the first and second control paths being configured to enable differential control by using first and second transistors of the same doping type in the first and second control paths respectively, and the first and second transistors being configured as voltage variable resistors for adjusting the capacitance of the variable capacitor device.

[0010] Another exemplary embodiment includes a system comprising a voltage controlled oscillator and an analog differential regulation control system. The analog differential regulation control system includes a differential charge pump and a loop filter. The analog differential regulation control system is configured to generate a differential control voltage to adjust the output frequency of the voltage controlled oscillator. The voltage controlled oscillator includes a resonant tank circuit. The resonant tank circuit includes a variable capacitor circuit including a plurality of variable capacitor devices connected in parallel to first and second tank nodes of the resonant tank circuit. Each variable capacitor device includes first and second control paths, and the first and second control paths are configured to enable differential control using first and second transistors of the same doping type in the first and second control paths, respectively, and the first and second transistors are configured as voltage variable resistors for adjusting the capacitance of the variable capacitor device in response to the differential control voltage.

[0011] Another exemplary embodiment includes a system comprising a plurality of qubits, an arbitrary waveform generator system, and a phase-locked loop system. The arbitrary waveform generator system comprises a plurality of arbitrary waveform generator channels, each arbitrary waveform generator channel being coupled to a respective one of the plurality of qubits and configured to generate a high-frequency signal for controlling the operation of the qubit. The phase-locked loop system is configured to generate a local oscillator signal utilized by the modulation system of each arbitrary waveform generator channel. The phase-locked loop system comprises a voltage-controlled oscillator and an analog differential regulation control system including a differential charge pump and a loop filter. The analog differential regulation control system is configured to generate a differential control voltage for adjusting the output frequency of the voltage-controlled oscillator. The voltage-controlled oscillator comprises a resonant tank circuit. The resonant tank circuit comprises a variable capacitor circuit including a plurality of variable capacitor devices connected in parallel to first and second tank nodes of the resonant tank circuit. Each capacitor device comprises first and second control paths, the first and second control paths being configured to enable differential control using first and second transistors of the same doping type in the first and second control paths, the first and second transistors being configured as voltage variable resistors for adjusting the capacitance of the variable capacitor device in response to the differential control voltage.

[0012] Other embodiments are described in the detailed description of the following exemplary embodiments, which description is to be read in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0013]

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DETAILED DESCRIPTION OF THE INVENTION

[0014] Next, for exemplary embodiments of the present disclosure, a voltage-controlled variable capacitor device (or varactor) implementing the architecture of a voltage-variable resistor-tuned capacitor (VVRTC) with differential control will be described in more detail. In a voltage-controlled variable capacitor device having a VVRTC circuit architecture, a voltage-independent capacitance (e.g., a fixed capacitor) is implemented in series with a voltage-variable resistor device (e.g., a field-effect transistor (FET) device configured to operate in the linear region) to enable voltage-variable capacitance adjustment. Exemplary embodiments of the present disclosure further include systems and circuits implementing an adjustable resonant load or resonant tank circuit (such as an oscillator circuit) comprising one or more VVRTC varactor devices for capacitance adjustment.

[0015] It should be understood that the various features shown in the accompanying drawings are schematic diagrams not drawn to scale. Further, to denote the same or similar features, elements, or structures, the same or similar reference numerals are used throughout the drawings, and thus, detailed descriptions of the same or similar features, elements, or structures are not repeated for each drawing. Further, as used herein, the term "exemplary" means "serving as an example, instance, or illustration." Embodiments or designs described herein as "exemplary" should not be construed as preferred or advantageous over other embodiments or designs.

[0016] Furthermore, the phrase "configured to" when used with a circuit, structure, element, component, etc. that performs one or more functions or otherwise provides some functionality is intended to encompass embodiments in which the circuit, structure, element, component, etc. is implemented in hardware, software, and / or combinations thereof. In an implementation with hardware, the hardware may comprise discrete circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., application specific integrated circuit (ASIC) chips, field programmable gate array (FPGA) chips, etc.), processing devices (e.g., central processing unit (CPU), graphics processing unit (GPU), etc.), one or more integrated circuits, and / or combinations thereof. Thus, by way of example only, when a circuit, structure, element, component, etc. is defined as being configured to provide a particular functionality, embodiments are covered that are composed of elements, processing devices, or integrated circuits, or combinations thereof, that enable the circuit, structure, element, component, etc. to perform the particular functionality when in an operating state (e.g., connected to or otherwise disposed in, powered on, receiving an input, or generating an output, or combinations thereof), as well as embodiments when the circuit, structure, element, component, etc. is in a non-operating state (e.g., not connected to or otherwise disposed in, not powered on, not receiving an input, or not generating an output, or combinations thereof) or a partial operating state, although not limited thereto.

[0017] FIG. 1 schematically shows a variable capacitor device according to an exemplary embodiment of the present disclosure. More specifically, FIG. 1 schematically shows a voltage variable capacitor device 100 (or varactor 100) having a differential control VVRTC circuit structure according to an exemplary embodiment of the present disclosure. The varactor 100 includes a first terminal 101 (or positive P terminal) and a second terminal 102 (or negative N terminal). The first and second terminals 101 and 102 function as varactor input / output (I / O) terminals for connecting the varactor 100 to a given circuit (e.g., the tank circuit of a VCO). The varactor 100 further includes a differential control terminal 111 / 112 including a first control terminal 111 (or negative control terminal) and a second control terminal 112 (or positive control terminal). The first and second control terminals 111 and 112 are configured to be connected to a control system (e.g., the charge pump of a phase lock loop (PLL) circuit) to receive respective differential control voltage signals VCON_N and VCON_P for adjusting the capacitance of the varactor 100, which will be described in more detail below. Further, the varactor 100 includes an adjustment terminal including a first adjustment terminal 121 and a second adjustment terminal 122. The first adjustment terminal 121 and the second adjustment terminal 122 are configured to be connected to, for example, a calibration control system to receive a first reference voltage VREF_N (or first adjustment voltage) and a second reference voltage VREF_P (or second adjustment voltage) for adjusting specific operating characteristics of the varactor 100, which will be described in more detail below.

[0018] As further shown in FIG. 1, the varactor 100 includes a parallel control path including: (i) a first control path (or negative path) including a first transistor N1, a first capacitor C1, and a second capacitor C2 connected in series between a first terminal 101 and a second terminal 102 of the varactor 100; and (ii) a second control path (or positive path) including a second transistor N2, a third capacitor C3, and a fourth capacitor C4 connected in series between the first terminal 101 and the second terminal 102 of the varactor 100. In the first path, the first capacitor C1 is connected between the first terminal 101 and the first source / drain terminal of the first transistor N1, and the second capacitor C2 is connected between the second terminal 102 and the second source / drain terminal of the first transistor N1. In the second path, the third capacitor C3 is connected between the first terminal 101 and the first source / drain terminal of the second transistor N2, and the fourth capacitor C4 is connected between the second terminal 102 and the second source / drain terminal of the second transistor N2.

[0019] The varactor 100 further includes a plurality of resistors R1, R2, R3, R4, R5, and R6. The first control terminal 111 is coupled to the gate terminal of the first transistor N1 by the first resistor R1. The first adjustment terminal 121 is coupled to the first and second source / drain terminals of the first transistor N1 by the third resistor R3 and the second resistor R2, respectively. The second control terminal 112 is coupled to the first and second source / drain terminals of the second transistor N2 by the sixth resistor R6 and the fifth resistor R5, respectively. The second adjustment terminal 122 is coupled to the gate terminal of the second transistor N2 by the fourth resistor R4.

[0020] In some embodiments, the first and second transistors N1 and N2 comprise FET devices of the same doping type (e.g., metal-oxide-semiconductor field-effect transistor (MOSFET) devices). For example, in some embodiments, the first and second transistors N1 and N2 are N-type FET devices. In other embodiments, the first and second transistors N1 and N2 are P-type FET devices. The first and second transistors N1 and N2 can be implemented using state-of-the-art FET technologies such as FinFETs. In some embodiments, the capacitors C1, C2, C3, and C4 include fixed capacitors (or voltage-independent capacitor devices) having the same capacitance value. In some embodiments, the capacitors C1, C2, C3, and C4 include metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, or other types of capacitor structures suitable for a given application. In some embodiments, the resistors R1, R2, R3, R4, R5, and R6 include any suitable type of passive resistor device for semiconductor integrated circuits, including but not limited to thin-film resistors, polysilicon resistors, and the like.

[0021] In the exemplary embodiment of FIG. 1, the voltage variable capacitance of each path of the balun 100 is realized by a series connection of a fixed capacitance and the parasitic impedance (e.g., parasitic capacitance) of the MOSFET device, and the parasitic capacitance of the MOSFET device changes as the MOSFET device operates in the linear region. For example, a control voltage signal VCON_N is applied to the first control terminal 111 to change the on-resistance (or channel resistance) of the first transistor N1 in the linear region between the non-conducting state (fully off) and the conducting state (fully on), thereby changing the capacitance of the negative path between the first terminal 101 and the second terminal 102. More specifically, when the first transistor N1 is in the non-conducting state (e.g., when the first transistor N1 is in the cut-off region), the first transistor N1 has a relatively small parasitic capacitance (denoted as C_Off in this specification) connected in series with the capacitors C1 and C2, whereby the effective capacitance of the negative path (the C of the path) is reduced due to the small parasitic capacitance of the first transistor N1. On the other hand, when the first transistor N1 reaches the fully conducting state (e.g., when the first transistor N1 reaches saturation), the effective capacitance of the negative path is substantially based on the capacitance of the capacitors C1 and C2 connected in series (the C of the path). For example, when C1 = C2 = C, the total capacitance of the negative path is approximately 1 / 2C. When the first transistor N1 operates in the linear region, the effective capacitance of the negative path transitions within a range between (the C of the path) based on the control voltage signal VCON_N and (the C of the path). min ) is reduced. On the other hand, when the first transistor N1 reaches the fully conducting state (e.g., when the first transistor N1 reaches saturation), the effective capacitance of the negative path is substantially based on the capacitance of the capacitors C1 and C2 connected in series (the C of the path). max ) For example, when C1 = C2 = C, the total capacitance of the negative path is approximately 1 / 2C. When the first transistor N1 operates in the linear region, the effective capacitance of the negative path is based on the control voltage signal VCON_N (the C of the path) min and C max and transitions within the range between

[0022] Similarly, a control voltage signal VCON_P is applied to the second control terminal 112 to vary the on-resistance (or channel resistance) of the second transistor N2 in the linear region between the non-conducting state (fully off) and the conducting state (fully on), thereby changing the capacitance of the positive path between the first terminal 101 and the second terminal 102. More specifically, when the second transistor N2 is in the non-conducting state (e.g., when the second transistor N2 is in the cut-off region), the second transistor N2 has a relatively small parasitic capacitance connected in series with capacitors C3 and C4, whereby the total capacitance of the positive path is reduced due to the small parasitic capacitance of the second transistor N2. On the other hand, when the second transistor N2 is in the conducting state, the total capacitance of the positive path is substantially based on the capacitances of capacitors C3 and C4 connected in series. For example, when C3 = C4 = C, the total capacitance of the positive path is approximately 1 / 2C. When the second transistor N2 operates in the linear region, the effective capacitance of the positive path transitions in the range between (path's) C min and C max and C

[0023] The first reference voltage VREF_N is applied to the first adjustment terminal 121 to adjust / shift the effective threshold voltage of the first transistor N1, thereby adjusting the point at which the first transistor N1 transitions between the conductive state and the non-conductive state. Similarly, the second reference voltage VREF_P is applied to the second adjustment terminal 122 to adjust / shift the effective threshold voltage of the second transistor N2, thereby adjusting the point at which the second transistor N2 transitions between the conducting state and the non-conducting state. At this point, the first and second reference voltages VREF_N and VREF_P are used to set the effective threshold voltages of the respective first and second transistors N1 and N2. In addition, the first and second reference voltages VREF_N and VREF_P are the common-mode voltages of the differential control voltage signals VCON_N and VCON_P applied to the varactor 100 (V CM) is effectively set. In some embodiments, the first and second reference voltages VREF_N and VREF_P include static voltages that can be in the range from a negative power supply voltage (e.g., 0V or GND) to a positive power supply voltage V DD up to. In some embodiments, the first and second reference voltages VREF_N and VREF_P are generated using a digital - to - analog (DAC) circuit implemented by a calibration / adjustment system.

[0024] As an example, assume that VREF_N is set to 0V (GND) and VREF_P is set to V DD (e.g., V DD = 800mV). In this case, the common - mode voltage is (VREF_P - VREF_N) / 2=(V DD - GND) / 2 = V DD / 2. Further, in this case, the transition between the conductive state and the non - conductive state of the first transistor N1 occurs at the actual threshold voltage of the first transistor N1, and the transition between the conductive state and the non - conductive state of the second transistor N2 occurs at the actual threshold voltage of the second transistor N2. When VREF_N increases up to a voltage greater than 0V (e.g., 100mV), the effective threshold voltage of the first transistor N1 shifts by the same amount. Similarly, when VREF_P decreases to a voltage less than V DD (e.g., V DD - 100mV), the effective threshold voltage of the second transistor N2 also decreases accordingly.

[0025] As described above, the control voltage signals VCON_N and VCON_P are used to adjust the capacitance of the varactor 100. Generally, as the control voltage signal VCON_P increases, the capacitance of the varactor 100 decreases. On the other hand, as the control voltage VCON_N increases, the capacitance of the varactor 100 increases. In some embodiments, the control voltage signals VCON_N and VCON_P are generated by an analog control system (e.g., a charge pump circuit) configured to adjust the capacitance of the varactor 100 for a given application. For example, in the context of an LC oscillator circuit (e.g., the LC tank circuit of a VCO) having a capacitor C and an inductor L connected in parallel, the varactor 100 can be used to implement the capacitance C, and by changing the capacitance of the varactor 100, the total capacitance of the LC tank can be adjusted. The oscillation frequency of the LC oscillator is generally expressed as

Number

[0026] As described above, the first and second reference voltages VREF_N and VREF_P are statically adjusted to adjust the behavior of the varactor 100 in order to optimize for specific characteristics (e.g., linearity, transition characteristics, etc.). The first and second reference voltages VREF_N and VREF_P can be individually set to any analog voltage level within the range of [GND, V DD . In some embodiments, the first and second transistors N1 and N2 (and other transistors of other exemplary differential varactor devices as discussed herein) are biased to operate in the triode region (or ohmic region).

[0027] The balun 100 comprises a VVRTC structure that (i) enables differential control while optimizing the on-resistances of first and second transistor devices N1 and N2 of the same type (e.g., N-type or P-type) in both positive and negative control paths, (ii) supports means for controlling the gate-source bias voltages of the first and second transistor devices N1 and N2, and thus can form a composite linearized structure by combining two or more instances of a core VVRTC balun structure having appropriately offset gate-source control voltages, and (iii) supports means for independently setting the common-mode gain and differential-mode gain for desired frequency control.

[0028] As described above, since the differential control scheme provides immunity to common-mode noise, it is desirable to implement the differential control scheme to adjust the capacitance of the balun device. Typically, differential control of a balun is implemented using a complementary transistor pair. For example, in the exemplary embodiment of FIG. 1, in a conventional implementation, the first and second transistors N1 and N2 are complementary NFET and PFET devices in the control path, and the first and second control terminals 111 and 112 are coupled to the gate terminals of the respective NFET and PFET devices. However, in such a conventional scheme, the matching between the NFET device and the PFET device is poor (e.g., mismatch between the two types of transistors), and as a result, the performance may deteriorate. The device mismatch can be balanced by the relative ratio of the device sizes for a given technology, but even this approach does not solve the mismatch due to process variations.

[0029] Exemplary varactor embodiments such as those shown in FIG. 1 eliminate the use of complementary PFET and NFET devices in the VVRTC varactor framework by utilizing the same transistor type (or dopant type) for the first and second transistor devices N1 and N2 that operate as voltage variable resistor devices (e.g., NFET devices or PFET devices). As shown in FIG. 1, to implement the same transistor type for the first and second transistors N1 and N2 that operate as voltage variable resistor devices, the second control terminal 112 is coupled to the first and second source / drain elements of the second transistor N2, and the second adjustment terminal 122 is coupled to the gate of the second transistor N2. This is opposite to the negative control path where the first adjustment terminal 121 is coupled to the first and second source / drain elements of the first transistor N1 and the first control terminal 111 is coupled to the gate of the first transistor N1. By using the same type of transistor devices for N1 and N2, it becomes possible to match the on-resistances of the transistor devices N1 and N2, thereby achieving symmetry in the adjustment characteristics of the varactor 100, for example, symmetry in the capacitance versus control voltage characteristics of the positive and negative control paths of the varactor 100, and symmetry in the frequency versus control voltage characteristics of the positive and negative control paths of the varactor 100 when used in the LC tank of a VCO.

[0030] FIG. 2 schematically shows a variable capacitor device according to another exemplary embodiment of the present disclosure. More specifically, FIG. 2 shows a voltage variable capacitor device 200 (or varactor 200) having a differential control VVRTC circuit structure that is similar to the voltage variable capacitor device 100 of FIG. 1, except that resistors R1, R2, R3, R4, R5, and R6 are each replaced by transistors N10, N11, N12, N13, N14, and N15. As shown in FIG. 2, transistors N10, N11, N12, N13, N14, and N15 are configured to function as high impedance resistive elements, and the gate terminals of transistors N10, N11, N12, N13, N14, and N15 are connected to ground (GND) so that the transistors are maintained in a non-conducting (cut-off) state. Transistors N10, N11, N12, N13, N14, and N15 comprise the same transistor type (e.g., N-type FET devices) and are made significantly small so as to function as high impedance resistive elements within the operating frequency range of a given application that utilizes varactor 200, maintaining the high quality factor of varactor 200 with respect to the use of varactor 200 in a resonator or oscillator circuit. By using small FET devices as resistive elements, the footprint of varactor 200 is reduced (compared to varactor 100 of FIG. 1), and thus more compact implementation in advanced semiconductor technology is made possible. In other embodiments, transistors N10, N11, N12, N13, N14, and N15 comprise P-type FET devices having gate terminals coupled to a power supply voltage and are configured so that the P-type FET devices are maintained in a non-conducting (cut-off) state. DD comprise P-type FET devices having gate terminals coupled to a power supply voltage and are configured so that the P-type FET devices are maintained in a non-conducting (cut-off) state.

[0031] FIG. 3 schematically shows a system 300 that can be implemented using a variable capacitor device according to an exemplary embodiment of the present disclosure. The system 300 includes an oscillator circuit 310 including an LC tank circuit 320. The LC tank circuit 320 includes an inductor element 322 and a varactor circuit 324. The inductor element 322 and the varactor circuit 324 are connected in parallel to LC tank nodes P and N connected to differential output terminals VP and VN. The system 300 further includes a calibration system 330 and an analog differential adjustment control system 340.

[0032] It should be understood that the system 300 of FIG. 3 is a high-level representation of any type of system that utilizes an adjustable oscillator that generates an output frequency in response to a control input (e.g., a control voltage), or any adjustable circuit (e.g., a low-noise amplifier, mixer, etc.) that utilizes one or more VVRTC varactor devices with differential control as described herein. For example, the system 300 may include a communication system (wired or wireless) such as a receiver, transmitter, transceiver, etc., and the oscillator circuit 310 may be utilized to generate a local oscillator (LO) signal for a mixer circuit utilized in frequency modulation, I / Q modulation, etc. As a further example, the system 300 may be a frequency synthesizer, or a phase-locked loop (PLL) system, etc.

[0033] Furthermore, oscillator circuit 310 can comprise any type of LC oscillator framework that utilizes an LC tank having a variable capacitance to adjust the frequency output of oscillator circuit 310. For example, in some embodiments, oscillator circuit 310 is a voltage controlled oscillator (VCO) circuit in which a control voltage signal (e.g., a differential control voltage signal) is used as a control input for adjusting the capacitance of LC tank circuit 320, thereby varying the output frequency generated by oscillator circuit 310. In LC tank circuit 320, the variable capacitance is implemented using a varactor circuit 324 that includes a plurality of VVRTC varactors. Varactor circuit 324 can be implemented using, for example, any of the exemplary embodiments discussed herein in connection with FIGS. 1, 2, 7, 8, and 9.

[0034] Calibration system 330 is configured to calibrate varactor circuit 324 using techniques such as those discussed herein. Analog differential adjustment control system 340 is configured to generate control voltage signals (e.g., differential control voltage signals VCON_N and VCON_P) to adjust the capacitance of varactor circuit 324 of LC tank circuit 320 to adjust the frequency output of oscillator circuit 310. In some embodiments, in a PLL implementation, analog differential adjustment control system 340 includes a differential charge pump and loop filter circuit.

[0035] FIG. 4 schematically shows a voltage controlled oscillator circuit implemented using a variable capacitor device according to an exemplary embodiment of the present disclosure. In particular, FIG. 4 schematically shows a VCO circuit 400 that constitutes a complementary cross-coupled LC tank VCO framework. VCO circuit 400 has a mutual conductance (g m) It includes a cell 410 and an LC tank circuit 420. The mutual conductance cell 410 includes a pair of cross-coupled PFET devices 412 and a pair of cross-coupled NFET devices 414. The mutual conductance cell 410 is configured to provide a negative resistance that reduces, for example, the consumption current and circuit losses and increases the Q factor of the VCO circuit 400, as is known in the art. The LC tank circuit 420 is configured to set the oscillation frequency of the VCO circuit 400.

[0036] As schematically shown in FIG. 4, the LC tank circuit 420 includes an inductor L, a varactor bank 430, and a varactor circuit 440, which are connected in parallel between the LC tank nodes P and N. The varactor bank 430 includes a plurality (n) of varactor segments 430-1, ···, 430-n. For illustrative purposes, FIG. 4 shows a varactor circuit 440 implemented using the varactor 100 of FIG. 1. However, it should be understood that the varactor circuit 440 can be implemented using any of the exemplary VVRTC varactor circuit embodiments discussed herein in connection with FIGS. 1, 2, 7, 8, and 9.

[0037] In an exemplary framework of the VCO circuit 400, a digital code (band_selectcode) is applied to the varactor bank 430 to achieve coarse frequency adjustment by activating one or more of the varactor segments 430-1, …, 430-n. In particular, as shown in FIG. 4, each varactor segment 430-1, …, 430-n is selectively activated by its respective band selection control signal Band_Select_1, …, Band_Select_n, and includes a transistor device (e.g., an NFET device) that roughly increases the capacitance of the LC tank circuit 420 to obtain a desired operating frequency band of the VCO circuit 400. On the other hand, fine adjustment of the frequency within a given frequency band is achieved by applying a differential control voltage signal (e.g., VCON_P, VCON_N) to the VVRTC varactor circuit 440 to adjust the capacitance of the VVRTC varactor circuit 440, thereby finely adjusting the frequency output of the VCO circuit 400 to a target frequency within the selected frequency band.

[0038] In the case of an LC VCO as shown in FIG. 4, the oscillation frequency is generally

Equation

[0039] In the case of a differential VCO that implements a differential varactor having a differential control voltage for adjusting the capacitance of the differential varactor, the VCO circuit is

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[0040] Figures 5A and 5B graphically illustrate ideal and exemplary actual representations of the frequency characteristics and gain characteristics of a voltage-controlled oscillator implementing a varactor for continuous frequency adjustment. More specifically, Figure 5A shows a graph 500 depicting the VCO frequency (denoted as F VCO ) as a function of the differential control voltage (denoted as V DIFF ) applied to the differential varactor. In Figure 5A, the VCO has an operating frequency band (F min denoted) and a maximum oscillation frequency (F max denoted) defined by (i) a minimum oscillation frequency (F max - F minto provide a frequency adjustment range), and (ii) a control voltage range defined by a minimum differential control voltage (V DIFF_min denoted as) and a maximum differential control voltage (V DIFF_max denoted as), and the oscillation frequency F VCO is assumed to increase as the differential control voltage V DIFF increases.

[0041] FIG. 5A shows an exemplary representation of a typical achieved frequency versus differential control voltage transfer curve 502 that shows the VCO frequency characteristics obtained by utilizing a single VVRTC varactor in a VCO circuit due to the steep turn-on characteristics of the FET device of the VVRTC varactor. In this situation, there is a limit to the linear adjustment range of a single VVRTC varactor. This is in contrast to an ideal (and desirable) frequency versus differential control voltage transfer curve 504 that represents the ideal VCO frequency characteristics that cover the entire differential control voltage range from V DIFF_min to V DIFF_max . In this regard, it is desirable to configure the VCO to be effectively adjustable over the entire operating frequency range.

[0042] Furthermore, FIG. 5B shows, as shown in FIG. 5A, a graph 510 showing the VCO gain (K max -F min frequency adjustment range and from V DIFF_min to V DIFF_max as a function of the differential control voltage V DIFF applied to the differentially controlled varactor based on the differential voltage range up to. More specifically, FIG. 5B shows an exemplary representation of a typical achieved gain versus differential control voltage transfer curve 512 of the VCO based on the exemplary frequency versus differential control voltage transfer curve 502 of FIG. 5A. The VCO gain K VCO (or VCO adjustment gain) is measured in volts per hertz (e.g., mV / MHz, mV / GHz, etc.), which represents the unit change in frequency with respect to the unit change in the differential control voltage V VCO . As shown in FIG. 5B, the VCO gain K DIFF is variable over the entire adjustment range. This means that the VCO gain K VCO ​VCO This is in contrast to the ideal (and desirable) VCO gain characteristic that is essentially constant over the entire adjustment range, represented by the ideal gain-versus-differential control voltage transfer curve 514 (as shown in FIG. 5B). Additionally, the slope of the ideal frequency-versus-differential control voltage transfer curve 504 is smaller compared to the slope of the frequency-versus-differential control voltage transfer curve 502, so the maximum Kvco of the ideal gain-versus-differential control voltage transfer curve 514 is lower than the maximum Kvco of the gain-versus-differential control voltage transfer curve 512.

[0043] According to an exemplary embodiment of the present disclosure, by adding two or more VVRTC varactor devices in parallel and changing / shifting the capacitance-versus-differential control voltage characteristics of the two or more VVRTC varactor devices, an improvement in the linearity of the frequency-versus-differential control voltage response of an oscillator (e.g., a VCO) over a target adjustment range, as well as a reduction in the variation of the oscillator gain over the target adjustment range, are achieved. FIGS. 6A and 6B schematically illustrate a linearization process implemented by adding two or more VVRTC varactor devices in parallel and changing / shifting the capacitance-versus-differential control voltage characteristics of such varactor devices according to an exemplary embodiment of the present disclosure to enhance the linearity of adjustment and reduce gain variation over a given adjustment range.

[0044] More specifically, FIG. 6A graphically depicts the varactor capacitance-versus-differential control voltage transfer characteristics of two differential varactor devices connected in parallel within the tank circuit of a VCO to achieve a wider range of linearity over the adjustment range of the VCO. More specifically, FIG. 6A shows a graph 600 of the varactor capacitance (denoted as C DIFF and denoted) as a function of the differential control voltage (denoted as V VAR applied to two differentially controlled and parallel-connected VVRTC varactor devices. In FIG. 6A, the first curve 602 schematically shows the capacitance-versus-differential control voltage transfer characteristic of the first VVRTC varactor device with differential control, and the second curve 604 schematically shows the capacitance-versus-differential control voltage transfer characteristic of the second VVRTC varactor device with differential control.

[0045] FIG. 6A shows a linearization technique that shifts capacitance-versus-differential control voltage transfer curves 602 and 604 relative to each other and then combines them to provide an overall capacitance-versus-differential control voltage transfer curve 606, which represents an overall more linearized capacitance-versus-differential control voltage response of a VVRTC varactor circuit implementing two differentially-controlled, parallel-connected VVRTC varactor devices. In this regard, by combining the capacitor-versus-differential control voltage characteristic responses of a plurality of parallel-connected differential varactor devices, the frequency-versus-differential control voltage response of a VCO is improved, and thus the linearity of the VCO tuning is improved over the target tuning range of the VCO.

[0046] Further, FIG. 6B shows a graph 610 of the VCO gain K DIFF as a function of the differential control voltage V VCO applied to a differential varactor circuit having two parallel-connected differential varactor devices, based on the capacitor-versus-voltage characteristics of FIG. 6A. More specifically, FIG. 6B schematically shows a gain-versus-differential control voltage curve 612 obtained from the overall capacitance-versus-differential control voltage transfer curve 606 of FIG. 6A. As shown in FIG. 6B, the gain-versus-differential control voltage curve 612 of the VCO shows that the gain variation is reduced over the target tuning range as compared to the gain-versus-differential control voltage curve 512 of FIG. 5B. Next, the linearization technique according to an exemplary embodiment of the present disclosure will be described in further detail with respect to, for example, FIGS. 7, 8, and 9.

[0047] FIG. 7 schematically shows a variable capacitor circuit according to another exemplary embodiment of the present disclosure. More specifically, FIG. 7 schematically shows a VVRTC varactor circuit 700 including a plurality (n) of VVRTC varactor devices 700-1, 700-2, ···, 700-n connected in parallel to a first terminal 701 (or positive P terminal) and a second terminal 702 (or negative N terminal) of the VVRTC varactor circuit 700. The first and second terminals 701 and 702 function as common input / output (I / O) terminals for connecting the VVRTC varactor devices 700-1, 700-2, ···, 700-n to, for example, the tank nodes P and N of a VCO. In addition, the VVRTC varactor circuit 700 includes first and second control terminals 711 and 712 that function as common control voltage terminals for applying differential control voltage signals VCON_N and VCON_P to the VVRTC varactor devices 700-1, 700-2, ···, 700-n, respectively.

[0048] Furthermore, the VVRTC varactor circuit 700 includes a plurality of independent adjustment terminals coupled to each of the VVRTC varactor devices 700-1, 700-2, ···, 700-n. In particular, as shown in FIG. 7, the first VVRTC varactor device 700-1 includes a first adjustment terminal 121-1 and a second adjustment terminal 122-1 for receiving a first reference voltage VREF_N-1 and a second reference voltage VREF_P-1, respectively, to adjust specific operating characteristics of the first VVRTC varactor device 700-1. In addition, the second VVRTC varactor device 700-2 includes a first adjustment terminal 121-2 and a second adjustment terminal 122-2 for receiving a first reference voltage VREF_N-2 and a second reference voltage VREF_P-2, respectively, to adjust specific operating characteristics of the second VVRTC varactor device 700-2. Furthermore, the nth VVRTC varactor device 700-n includes a first adjustment terminal 121-n and a second adjustment terminal 122-n for receiving a first reference voltage VREF_N-n and a second reference voltage VREF_P-n, respectively, to adjust specific operating characteristics of the nth VVRTC varactor device 700-n.

[0049] The VVRTC varactor devices 700-1, 700-2, …, 700-n can be implemented using any of the exemplary VVRTC varactor architectures with differential control as shown, for example, in FIGS. 1, 2, 8, or 9. For illustrative purposes, FIG. 7 schematically shows an exemplary VVRTC varactor device 700-x that can be used to implement each of the VVRTC varactor devices 700-1, 700-2, ···, 700-n connected in parallel in the VVRTC varactor circuit 700. Each VVRTC varactor device 700-x includes respective input and output terminals 101-x and 102-x, differential control terminals 111-x and 112-x, adjustment terminals 121-x and 122-x, transistors N1-x and N2-x, capacitors C1-x, C2-x, C3-x, and C4-x, and resistive elements R1-x, R2-x, R3-x, R4-x, R5-x, and R6-x. Each VVRTC varactor device 700-x has the same or similar structure and operation as the varactor device 100 in FIG. 1, and its details will not be repeated.

[0050] In some embodiments, linearization of the frequency tuning characteristics of the VCO is achieved by applying different (offset) sets of the adjustment voltage pairs VREF_N-x, VREF_P-x to each of the VVRTC varactor devices 700-1, 700-2, …, 700-n, and different offsets are generated in the transfer characteristics of each of the VVRTC varactor devices 700-1, 700-2, …, 700-n. For example, as described above, the effective threshold voltages of the first and second transistors N1-x and N2-x (which control the voltage-variable on-resistance of the control path) are shifted by the adjustment reference voltages VREF_N-x and VREF_P-x applied to a given VVRTC varactor device 700-x, and as a result, the capacitance-to-voltage transfer characteristic of the given VVRTC varactor device 700-x is shifted. By shifting the capacitance-to-voltage response characteristics of two or more of the VVRTC varactor devices 700-1, 700-2, ···, 700-n relative to each other, different (offset) capacitance-to-voltage responses of two or more of the VVRTC varactor devices 700-1, 700-2, ···, 700-n are essentially combined to provide the overall capacitance-to-voltage response of the VVRTC varactor circuit 700 (as schematically shown in FIG. 6A), and this response as a whole exhibits a more linearized capacitance-to-voltage response over a wider range of differential control voltages within the tuning range of the VCO. Additionally, as explained above in connection with FIG. 6B, the linearization serves to reduce the variation in the differential gain of the VCO over the target tuning range.

[0051] Another approach to achieving linearization is to design the VVRTC varactor devices 700-1, 700-2, ..., 700-n such that the transistor pairs N1-x and N2-x of each capacitor-varactor device 700-x have different threshold voltages. For example, the transistors N1-1 and N2-1 of the VVRTC varactor device 700-1 can have a first threshold voltage Vth-1, the transistors N1-2 and N2-2 of the VVRTC varactor device 700-2 can have a second threshold voltage Vth-2, and the transistors N1-n and N2-n of the VVRTC varactor device 700-n can have a threshold voltage Vth-n, where Vth-1 < Vth-2 < Vth-n, etc. However, this approach of varying only Vth can be problematic for various reasons. For example, in the case of small FET devices, it is difficult to construct FET devices with different threshold voltages due to process variations and mismatches, especially when the required ΔVth (e.g., 100 mV) for a given application is relatively small.

[0052] Advantageously, by using different adjustment reference voltages VREF_N-x and VREF_P-x applied to different VVRTC varactor devices 700-x, the effective threshold voltages of the first and second transistors N1-x and N2-x of a given VVRTC varactor device 700-x can be shifted / adjusted in a controlled manner, independent of FET technology and device mismatches. Additionally, by using the adjustment reference voltages VREF_N-x and VREF_P-x, the effective threshold voltages of the first and second transistors N1-x and N2-x of a given VVRTC varactor device 700-x can be shifted / adjusted in small increments (e.g., 100 mV) over substantially the entire range of a given supply voltage V DD .

[0053] In other embodiments, the different adjustment reference voltages VREF_N-x and VREF_P-x applied to different VVRTC varactor devices 700-x can be used in combination with designing the first and second transistors N1-x and N2-x of the different VVRTC varactor devices 700-x to have different threshold voltages. In this example, while different threshold voltages of FET devices can be used to achieve coarse adjustment, the adjustment reference voltages VREF_N-x and VREF_P-x can be utilized to finely adjust the operating characteristics of different VVRTC varactor devices 700-x in consideration of device mismatches and the like.

[0054] An exemplary linearization technique achieved by changing the capacitance-to-voltage transfer characteristics of the first and second transistors N1-x and N2-x of different VVRTC varactor devices 700-x using different (offset) sets of the pair of adjustment reference voltages VREF_N-x and VREF_P-x applied to the adjustment terminals 121-x and 122-x may lead to changing the on-resistances of the first and second transistors N1-x and N2-x, as well as changing the effective capacitance connected to the tank circuit when the control is in the OFF state. In particular, in the OFF state, the C_Off of the first and second transistors N1-x and N2-x can be significantly different if the shifts in the effective threshold voltages of the first and second transistors N1-x and N2-x resulting from changing the adjustment voltages VREF_N-x and VREF_P-x are different. In this regard, it is desirable to maintain the impedance (e.g., C_Off) of the first and second transistors N1-x and N2-x the same regardless of whether the effective threshold voltages of the first and second transistors N1-x and N2-x are shifted when the first and second transistors N1-x and N2-x are in the non-conducting state (OFF state).

[0055] In some embodiments, with respect to the exemplary varactor framework of FIG. 7, variations in the OFF impedance of the first and second transistors N1-x and N2-x of different VVRTC varactor devices 700-x can be mitigated, for example, by changing the transistor widths of the first and second transistors N1-x and N2-x and / or the capacitances of the capacitors C1-x, C2-x, C3-x, and C4-x of different VVRTC varactor devices 700-2, …, 700-n with respect to the transistor widths of the first and second transistors N1-1 and N2-1 and the capacitance values of the capacitors C1-1, C2-1, C3-1, and C4-1 of the first VVRTC varactor 700-1. However, in the case of FinFET technology where the NFET width is coarsely quantized, sufficient accuracy may not be obtained even by adjusting the relative transistor widths of the first and second transistors N1-x and N2-x (e.g., the necessary small changes in transistor width required for proper adjustment may not be obtained).

[0056] Furthermore, in some embodiments, the variation in the OFF impedance of the first and second transistors N1-x and N2-x of different VVRTC varactor devices 700-x is mitigated by adding resistive elements (e.g., voltage-variable resistive elements) in parallel with the first and second transistors N1-x and N2-x of different segments of the VVRTC varactor device 700-x. The resistive elements enable adjustment of the resistive degradation of such transistors when the first and second transistors N1-x and N2-x are in the OFF mode. The use of adjustable resistive degradation in different VVRTC varactor devices 700-x is configured such that the first and second transistors N1-x and N2-x of different VVRTC varactor devices 700-x have the same or substantially the same impedance (e.g., C_Off) when the first and second transistors N1-x and N2-x of different VVRTC varactor devices 700-x are in the OFF state, regardless of whether the threshold voltages of the first and second transistors N1-x and N2-x of different VVRTC varactor devices 700-x are shifted by different (offset) adjustment reference voltage pairs VREF_N-x and VREF_P-x applied to the adjustment terminals 121-x and 122-x. Next, an exemplary embodiment of adjusting the OFF impedance of the first and second transistors N1-x and N2-x using adjustable degenerate resistance will be described in further detail with respect to FIGS. 8 and 9.

[0057] For example, FIG. 8 schematically shows a variable capacitor device according to another exemplary embodiment of the present disclosure. More specifically, FIG. 8 schematically shows a variable capacitor device 800 (or varactor 800) having a VVRTC circuit configuration, in which resistive elements are utilized to adjust the effective impedance of the transistors of the varactor 800. The varactor 800 includes a VVRTC circuit with differential control and is similar to the varactor 200 of FIG. 2, except that the varactor 800 includes additional adjustment terminals 801 and 802, as well as resistive elements 810 and 812.

[0058] In particular, the resistance element 810 includes transistors N20 and N21 connected in series, and the gates of these transistors are commonly connected to the adjustment terminal 801. The adjustment terminal 801 receives the analog adjustment voltage V ADJ _N (or V ADJ _Nx for a given varactor segment x). In addition, the resistance element 812 includes transistors N22 and N23 connected in series, and the gates of these transistors are commonly connected to the adjustment terminal 802. The adjustment terminal 802 receives the analog adjustment voltage V ADJ _P (or V ADJ _Px for a given varactor segment x). The resistance element 810 is connected in parallel with the first transistor N1, and the adjustable resistance element 812 is connected in parallel with the second transistor N2. In operation, by applying the adjustment voltages V ADJ _N and V ADJ _P to the respective adjustment terminals 801 and 802 to adjust the on-resistances of the transistors N20 and N21 connected in series in the resistance element 810 and the on-resistances of the transistors N22 and N23 connected in series in the resistance element 812, the effective resistances of the first and second transistors N1 and N2 can be adjusted. Note that the transistors N11, N12, N14, N15 are equivalent to fixed bias resistors used to provide a minimum bias resistance. In an alternative embodiment, the transistors N11, N12, N14, N15 can be removed and the transistor pairs N20 / N21, N22 / N23 can be directly connected to the source / drain terminals of the transistors N1, N2, respectively. In such an embodiment, the minimum bias resistance is controlled by restricting the voltage ranges of V ADJ _N and V ADJ _P.

[0059] When the varactor 800 is used to implement the VVRTC varactor devices 700-1, 700-2,..., 700-n (or generally, 700-x) in the exemplary embodiment of FIG. 7, each analog adjustment voltage V ADJ_N-x and V ADJ _P-x can be adjusted based on the shifted effective threshold voltages of the first and second transistors N1-x and N2-x obtained by applying different adjustment reference voltages VREF_N-x and VREF_P-x to different VVRTC varactor devices 700-x. Further, in some embodiments, when the varactor 800 is utilized to implement the VVRTC varactor devices 700-1, 700-2, …, 700-n (or generally, 700-x) in the exemplary embodiment of FIG. 7, the capacitance values of the capacitors C1-x, C2-x, C3-x, and C4-x of the different varactor devices 700-x can be adjusted to be different in the different varactor devices 700-x such that the effective OFF impedance (e.g., C_Off) is substantially ensured to be the same for all varactor devices 700-x.

[0060] FIG. 9 schematically shows a variable capacitor device according to another exemplary embodiment of the present disclosure. More specifically, FIG. 9 schematically shows a variable capacitor device 900 (or varactor 900) having a VVRTC circuit structure in which an adjustable resistive element is utilized to adjust the effective impedance of the transistors of the varactor 900. The varactor 900 is similar to the varactor 800 of FIG. 8 except that the varactor 900 implements first and second resistor banks 910 and 912 having a plurality of resistive elements connected in parallel that are digitally controlled to adjust the effective OFF impedance (e.g., C_Off) of the first and second transistors N1 and N2.

[0061] More specifically, as shown in FIG. 9, the first resistor element bank 910 includes a plurality of resistor elements 910-1, 910-2, ..., 910-i connected in parallel to the first transistor N1, and a plurality of digital control signal terminals 901-1, 901-2, ..., 901-i. The resistor element 910-1 includes transistors N30 and N31 connected in series having a gate terminal commonly connected to the digital control signal terminal 901-1. The resistor element 910-2 includes transistors N32 and N33 connected in series having a gate terminal commonly connected to the digital control signal terminal 901-2. The resistor element 910-i includes transistors N34 and N35 connected in series having a gate terminal commonly connected to the digital control signal terminal 901-i.

[0062] Similarly, the second resistor element bank 912 includes a plurality of resistor elements 912-1, 912-2, ..., 912-i connected in parallel to the second transistor N2, and a plurality of digital control signal terminals 902-1, 902-2, ..., 902-i. The resistor element 912-1 includes transistors N40 and N41 connected in series having a gate terminal commonly connected to the digital control terminal 902-1. The resistor element 912-2 includes transistors N42 and N43 connected in series having a gate terminal commonly connected to the digital control signal terminal 902-2. The resistor element 912-i includes transistors N44 and N45 connected in series having a gate terminal commonly connected to the digital control signal terminal 902-i.

[0063] The digital control signal terminals 901-1, 901-2, …, 901-i of the first resistor bank 910 are configured to receive i-bit digital signals RN1, RN2, ···, RNi as inputs, and selectively activate one or more of the resistors 910-1, 910-2, …, 910-i of the first resistor bank 910 as needed to adjust the effective impedance of the first transistor N1. Similarly, the digital control signal terminals 902-1, 902-2, …, 902-i of the second resistor bank 912 are configured to receive i-bit digital signals RP1, RP2, …, RPi as inputs, and selectively activate one or more of the resistors 912-1, 912-2, …, 912-i of the second resistor bank 912 as needed to adjust the effective impedance of the second transistor N2. In the embodiment of FIG. 9, the effective resistance to the control node can be changed, and thus C_Off presented to the resonant tank can be adjusted.

[0064] In some embodiments, the first resistor bank 910 can be configured such that the resistors 910-1, 910-2, ..., 910-i have (i) the same resistance R (unweighted resistance value) when activated, or (ii) weighted resistance values (e.g., the first resistor 910-1 has a resistance of R, the second resistor 910-2 has a resistance of R×2, and the i-th resistor 910-i has a resistance of R×i). The same applies to the resistors 912-1, 912-2, ..., 912-i of the second resistor bank 912.

[0065] In the exemplary embodiment of FIG. 9, note that when transistors N30~N35 and N40~N45 are turned on, the equivalent resistance may become too small, so transistors N11, N12, N14, and N15 (equivalent to fixed bias resistors) are used to provide a minimum bias resistance. Depending on the technology used for transistors N1 and N2 and the relative transistor sizes, transistors N11, N12, N14, and N15 may be required to provide a fixed bias impedance.

[0066] The exemplary embodiment of FIG. 8 provides an analog approach that uses an adjustable resistive element controlled by an analog signal to adjust the effective capacitance (e.g., C_off) of the VVRTC varactor device, while FIG. 9 provides a digital approach that uses an adjustable resistive element controlled by a digital signal to adjust the effective capacitance (e.g., C_off) of the VVRTC varactor device. Note that in other embodiments, the analog and digital schemes of FIGS. 8 and 9 can be combined to provide both analog and digital adjustment of the resistive element.

[0067] FIG. 10 schematically shows a phase-locked loop system including a voltage-controlled oscillator implemented using a differential-controlled VVRTC varactor device according to an exemplary embodiment of the present disclosure. In particular, FIG. 10 schematically shows a PLL system 1000 that constitutes a PLL circuit, such as a feedback path including a phase-frequency detector 1010, a differential charge pump 1020, a loop filter 1030, a VCO 1040, an output buffer 1050, and a frequency divider 1060. The PLL system 1000 is a closed-loop control system configured to compare the phase of a reference clock signal REF_CLK (having a reference clock signal f REF ) with the phase of a feedback clock signal FB_CLK corresponding to a high-frequency (RF) output signal RF_OUT at the output of the PLL system 1000, and to adjust the VCO 1040 such that the phase of the RF_OUT is locked to the phase of the REF_CLK. The frequency of the RF output signal RF_OUT is equal to the output frequency (f VCO ) of the VCO 1040.

[0068] In some embodiments, the PLL system 1000 is such that the VCO output frequency f VCO is an integer N times the reference frequency f REF of the REF_CLK, i.e., f VCO = N × f REFso that the frequency divider 1060 of the feedback loop divides the frequency of RF_OUT (i.e., the VCO output frequency f VCO ) by the division ratio N, an integer-type NPLL system is provided. In other embodiments, the PLL system 1000 is such that the frequency divider 1060 of the feedback loop divides the output frequency f VCO of RF_OUT by the reference frequency f REF of REF_CLK in a non-integer multiple as follows,

Number

[0069] In some embodiments, as shown in FIG. 10, the PLL system 1000 includes differential interfaces (i) between the phase-frequency detector 1010 and the differential charge pump 1020, (ii) between the differential charge pump 1020 and the loop filter 1030, (iii) between the loop filter 1030 and the VCO 1040, and (iv) between the VCO 1040 and the output buffer 1050. In some embodiments, the output buffer 1050 includes a differential-differential buffer amplifier, in which case the RF_OUT signal includes a differential signal. In some embodiments, the output buffer 1050 includes a differential-single-ended buffer amplifier, in which case the RF_OUT signal includes a single-ended signal. Note that the phase-frequency detector 1010, the differential charge pump 1020, the loop filter 1030, the output buffer 1050, and the frequency divider 1060 can be implemented using various types of conventional or state-of-the-art circuit architectures suitable for a given application. Further, the VCO 1040 can be implemented using any suitable VCO framework that implements the exemplary VVRTC varactor devices and circuits disclosed herein.

[0070] The operation of a PLL system is well known to those skilled in the art. Here, a brief description of the operation of the PLL system 1000 in FIG. 10 is provided for illustrative purposes. In normal operation, the phase-frequency detector 1010 is configured to compare the arrival edge of the reference clock REF_CLK signal with the arrival edge of the feedback clock FB_CLK signal to determine whether there is a frequency difference, a phase difference, or both between REF_CLK and FB_CLK. The phase-frequency detector 1010 generates complementary "up" control signals (UP,

Number

Number

[0071] For example, when the rising edge of the reference signal REF_CLK precedes the rising edge of the feedback signal FB_CLK (e.g., the divided output signal RF_OUT), the phase-frequency detector 1010 asserts the UP control signal to logic 1 (logic high state) and maintains the DN control signal at logic 0 (logic low state). On the other hand, when the rising edge of the reference signal REF_CLK lags behind the rising edge of the feedback signal FB_CLK, the phase-frequency detector 1010 asserts the DN control signal to logic 1 and maintains the UP control signal at logic 0. When the rising edge of the reference signal REF_CLK aligns with the rising edge of the feedback signal FB_CLK, the phase-frequency detector 1010 maintains both the UP and DN control signals at logic 0.

[0072] The differential charge pump 1020 generates respective control signals CHP and [Number] to control the operation of the loop filter 1030 in response to complementary UP and DN control signals, and causes the loop filter 1030 to generate / adjust differential control signals VCON_P and VCON_N applied to the control voltage input of the VCO 1040, and adjusts / regulates the frequency f VCO of the differential output signals VP and VN of the VCO 1040. In some embodiments, the loop filter 1030 includes one or more capacitors that are charged and discharged in response to the respective control signals CHP and [Number] to adjust the differential control signals VCON_P and VCON_N output from the loop filter 1030.

[0073] For example, in response to a logic 1 UP control signal (DN is set to logic 0), the differential charge pump 1020 generates a control signal CHP that increases the charge of the capacitor of the loop filter 1030 by an amount proportional to the magnitude of the phase difference. In some embodiments, the control signal CHP includes a charging current (e.g., a current pulse) supplied by a current source of the differential charge pump 1020. As the charge of the capacitor increases, the differential control voltages VCON_P and VCON_N applied to the VCO 1040 increase proportionally. As the differential control voltages VCON_P and VCON_N increase, the output frequency f VCO of the VCO increases.

[0074] On the other hand, in response to a logic 1 DN control signal (UP is set to logic 0), the differential charge pump 1020 generates a control signal that decreases the charge of the capacitor of the loop filter 1030 by an amount proportional to the magnitude of the phase difference [Number] is generated. In some embodiments, the control signal [Number] includes the discharge current (current pulse) absorbed by the current source of the differential charge pump 1020. As the charge of the capacitor decreases, the differential control voltages VCON_P and VCON_N applied to the VCO 1040 decrease proportionally. When the differential control voltages VCON_P and VCON_N decrease, the output frequency f of the VCO VCO decreases.

[0075] Furthermore, in the case of the configuration of the differential charge pump 1020 and the loop filter 1030, the differential charge pump 1020 or the loop filter 1030 or both implement some type of common mode control circuit to set and maintain the common mode voltages of the differential control voltages VCON_P and VCON_N. In this regard, as described above, the differential charge pump 1020 and the loop filter 1030 can be implemented using any circuit architecture suitable for a given application.

[0076] In some embodiments, the VCO 1040 includes an LC tank circuit, and the variable capacitance of the LC tank circuit is implemented using a VVRTC varactor circuit including at least one or more VVRTC varactor devices connected in parallel to the LC tank circuit nodes P and N as described above in connection with FIGS. 4 and 7. In some embodiments, the adjustment terminals 121 and 122 of a given VVRTC varactor device are coupled to a calibration control system configured to generate the adjustment voltages VREF_N and VREF_P applied to the adjustment terminals 121 and 122 of the given VVRTC varactor device to adjust the operating characteristics of the VVRTC varactor device and thus the operating characteristics of the VCO 1040.

[0077] For example, FIG. 11 schematically shows a system for calibrating a phase-locked loop system comprising a voltage-controlled oscillator implementing a VVRTC varactor with differential control according to an exemplary embodiment of the present disclosure. In particular, FIG. 11 schematically shows a system 1100 including a PLL system 1000 and a calibration system 1110 configured to calibrate the VCO of the PLL system 1000. The structure and operation of the PLL system 1000 are the same as or similar to those described above in connection with FIG. 10, and the details thereof will not be repeated. The calibration system 1110 includes a calibration controller 1120, a plurality of digital-to-analog converter (DAC) circuits denoted as DAC0, DAC1, and DAC2, and a counter 1130.

[0078] The calibration controller 1120 is configured to execute a calibration process (e.g., an open-loop calibration process) that generates digital calibration codes, such as CAL_CODE_X, CAL_CODE_P, and CAL_CODE_N, to be applied to the respective DAC circuits DAC0, DAC1, and DAC2. The DAC0 circuit generates a DC calibration voltage V_X proportional to the digital code CAL_CODE-X. The calibration voltage V_X is input to the loop filter 1030. In addition, the DAC1 and DAC2 circuits generate respective DC calibration voltages V_P and V_N based on the respective digital codes CAL_CODE_P and CAL_CODE_N. The calibration voltages V_P and V_N are applied to the VCO1040 (e.g., applied to the adjustment terminals 122-x and 121-x of the VVRTC varactor device 700-x of FIG. 7). As will be described in more detail below, the calibration process generally includes (i) measuring the open-loop output frequency of the VCO1040 in response to the calibration voltage, (ii) using the measured open-loop output frequency of the VCO1040 to determine open-loop VCO adjustment characteristic data (e.g., an estimated transfer curve (or characteristic curve) of the VCO frequency as a function of the calibration voltage), and (iii) determining the VCO gain based on the curve of the VCO frequency as a function of the calibration voltage.

[0079] In some embodiments, the calibration voltage V_X, together with the configuration of the output stage of the differential charge pump 1020, generates two voltages denoted as VC_P and VC_N. For example, in some embodiments, VC_P = (α * V DD ) + (0.5 * ΔV), and VC_N = (α * V DD ) - (0.5 * ΔV), where 0 < α < 1. Thus, by changing the digital code CAL_CODE-X applied to DAC0, the differential voltage ΔV can be changed, and by changing α, the common-mode voltage is changed, and α is adjusted by changing the output stage of the differential charge pump 1020.

[0080] Furthermore, in some embodiments, the reference voltage V_P generated by DAC1 is given by V_P = V DD - β, and the value of β corresponds to the digital code CAL_CODE-P. Furthermore, in some embodiments, the reference voltage V_N generated by DAC2 is given by V_N = γ, and the value of γ corresponds to the digital code CAL_CODE-N. In this regard, the parameters β and γ are generated by the calibration controller 1120 and are independently controlled using the digital codes CAL_CODE-P and CAL_CODE-N output to DAC1 and DAC2, respectively.

[0081] Calibration system 1110 utilizes counter 1130 to determine the VCO output frequency for a given calibration code applied to phase-locked loop 1000 for each iteration of the calibration process. For example, counter 1130 is initialized each time the calibration code is changed and performs a counting operation. In some embodiments, counter 1130 is configured to measure, within a known period of a known accurate frequency derived from reference clock frequency REF_CLK, the VCO frequency divided by K (lower frequency). For example, assuming that VCO 1040 is configured to operate at 10 GHz, the VCO output frequency can be divided by 1000 to obtain a 10 MHz clock, which can be measured by an accurate 100 kHz reference clock derived from the reference clock signal REF_CLK. For example, if the frequency of REF_CLK is 20 MHz, the VCO output frequency is divided by 200.

[0082] Figures 12A, 12B, and 12C illustrate calibration processing executed by the calibration system 1110 of FIG. 11, according to an exemplary embodiment of the present disclosure. More specifically, FIG. 12A shows a flowchart of calibration processing implemented by the calibration system 1110 of FIG. 11 to calibrate a VCO implementing a VVRTC varactor circuit, according to an exemplary embodiment of the present disclosure. When the calibration processing is started (block 1200), the calibration system 1110 configures the phase-locked loop system 1000 for open-loop calibration processing (block 1201). In the normal operation mode, the phase-frequency detector 1010, the differential charge pump 1020, the loop filter 1030, the VCO 1040, the output buffer 1050, and the divider 1060 are active and function in the manner described above in connection with FIG. 10. In the calibration mode (e.g., open-loop calibration mode), the PLL system 1000 operates in an open loop, the phase-frequency detector 1010 is not active, and the differential charge pump 1020, the loop filter 1030, the VCO 1040, the output buffer 1050, and the divider 1060 are active. In some embodiments, the divider 1060 is programmed to provide an integer N-division with N set to K to divide the VCO output frequency to a low frequency for calibration analysis. In some embodiments, the differential charge pump 1020 includes a multiplexer circuit configured to (i) select the PLL path during normal operation and (ii) or select the calibration path during the calibration mode. In the calibration mode, the DAC0 supplies a DC voltage V_X proportional to the calibration digital code X to the loop filter 1030.

[0083] The calibration controller 1120 sets the calibration code for DAC0 to its initial value (block 1202), then sweeps the calibration code for DAC0 across the set of calibration codes and determines the VCO frequency generated for each DAC0 calibration code (block 1203). For example, in an exemplary embodiment, DAC0 may be a 9-bit DAC, providing codes from 0 to 511, and the high / mid / low values may be 63, 127, 191, 255, 319, 383, 447, with an increment of 64. To more accurately estimate the VCO gain KVCO, additional calibration codes can be repeatedly utilized at the expense of calibration time.

[0084] When the digital code to DAC0 is swept from a high value to a low value, the counter 1130 determines the VCO output frequency for each DAC0 code and provides digital data Y representing the determined VCO frequency for each DAC0 code to the calibration system 1110. The calibration system 1110 utilizes the determined VCO frequency data to estimate the open-loop transfer curve of the VCO frequency versus the DAC0 calibration code (block 1204). In some embodiments, the transfer curve is estimated using a piecewise linear approximation of the data to determine the adjustment characteristics of the open-loop VCO. Next, the calibration system 1110 estimates the VCO gain (KVC) as a function based on the slope of the estimated open-loop transfer curve, for example, by calculating the derivative of the VCO frequency versus the DAC0 code data, to determine the VCO gain KVCO (block 1205).

[0085] Once the KVCO value is determined, the DAC1 and DAC2 codes are adjusted based on a mathematical formula so that a desired KVCO variation is obtained across the entire usable range of the control voltage, or so that the control voltage range of the desired linear VCO gain is maximized for optimal phase-locked loop stability (block 1206). The common-mode voltage output of the differential charge pump 1020 is adjusted so that symmetry of the transfer curve of the VCO gain versus the DAC1 and DAC2 calibration codes is obtained (block 1207). The calibration is carried out so that the ratio of the differential-mode gain to the common-mode gain is surely maximized (block 1208).

[0086] Figures 12B and 12C diagrammatically illustrate various stages of the calibration process of FIG. 12A. For example, FIG. 12B shows a graph 1210 of the VCO output frequency as a function of VC_P (common-mode calibration). The graph 1210 includes a first transfer curve 1212 of the VCO frequency (common mode) versus VC_P (common mode) and a second transfer curve 1214 of the VCO frequency (differential mode) versus VC_P (common mode). As described above, during the calibration process, the control voltage VC_P is set to VC_P = (α * V DD )+(0.5 * ΔV), where only (α * V DD ) = VCTRLcom is swept from 0 to VDD in the common-mode control calibration (by varying α). On the other hand, VC_N = (α * V DD )-(0.5 * ΔV), and only (0.5 * ΔV) = VCTRLdiff is swept from -V DD to V DD in the differential-mode control calibration.

[0087] Furthermore, FIG. 12B shows a graph 1220 of the VCO gain as a function of VC_P (common-mode calibration). The graph 1220 includes a first transfer curve 1222 of the VCO common-mode gain versus VC_P (common mode) and a second transfer curve 1224 of the VCO differential gain versus VC_P (common mode). The graph 1220 shows that after KVCO calibration, the linear adjustment range is narrow and the gain is not centered around V DD / 2. On the other hand, FIG. 12C shows a graph 1230 of the VCO gain as a function of VC_P after the linearization calibration process (common-mode calibration). The graph 1230 includes a first transfer curve 1232 of the VCO common-mode gain versus VC_P (common mode) and a second transfer curve 1234 of the VCO differential gain versus VC_P (common mode). The graph 1230 shows that after linearization, the linear adjustment range expands and the gain is centered around V DD / 2.

[0088] Next, FIG. 13 schematically shows a system for calibrating a phase-locked loop system comprising a voltage-controlled oscillator implementing a VVRTC varactor with differential control, according to another exemplary embodiment of the present disclosure. In particular, FIG. 13 schematically shows a system 1300 including a PLL system 1000 and a calibration system 1310 configured to calibrate the VCO of the PLL system 1000. The configuration and operation of the PLL system 1000 are the same or similar to those described above in connection with FIG. 10, and the details thereof will not be repeated. The calibration system 1310 includes a calibration controller 1320, a plurality of digital-to-analog converter (DAC) circuits denoted as DAC1 and DAC2, and a counter 1330. The calibration system 1310 is similar to the calibration system 1110 of FIG. 11, except that the calibration system 1310 excludes the use of DAC0 (e.g., an area-saving option) and uses only DAC1 and DAC2.

[0089] During the open-loop calibration mode, the output voltage of the differential charge pump 1020 is set to 0.5*VDD (which is the middle of the rails), and the calibration codes CAL_CODE-P and CAL_CODE-N applied to the respective DAC circuits DAC1 and DAC2 are swept to determine the slope of the KVCO gain versus control voltage curve. Using a mathematical model, the calibration code CAL_CODE-P and the calibration code CAL_CODE-N are adjusted such that the linear analog adjustment range of the VVRTC varactor of the VCO 1040 is maximized.

[0090] Figures 14A and 14B illustrate a calibration process executed by the calibration system 1310 of FIG. 13 according to an exemplary embodiment of the present disclosure. More specifically, FIG. 14A shows a flowchart of a calibration process implemented by the calibration system 1310 of FIG. 13 to calibrate a VCO implementing a VVRTC varactor circuit according to an exemplary embodiment of the present disclosure. When the calibration process is started (block 1400), the calibration system 1310 configures the phase-locked loop system 1000 for open-loop calibration processing as described above in connection with FIG. 12A (block 1401), except that the output voltage of the differential charge pump 1020 is set to 0.5*VDD (mid-rail) during code calibration sweeps.

[0091] The calibration controller 1320 initializes the calibration codes for DAC1 and DAC2 to their minimum and maximum values (block 1402), and then sweeps the calibration codes for DAC1 and DAC2 to determine the VCO frequency versus control voltage for the calibration codes of DAC1 and DAC2 (block 1403). When the digital codes to DAC1 and DAC2 are swept, the counter 1330 determines the VCO output frequency for the DAC1 and DAC2 codes and provides digital data Y representing the VCO frequencies determined for each of the DAC1 and DAC2 codes to the calibration system 1310. The calibration system 1310 uses the determined VCO frequency data to estimate the open-loop transfer curve of the VCO frequency versus the DAC1 and DAC2 calibration codes, for example using piecewise linear approximation (block 1404), and determines the open-loop VCO adjustment characteristics. The calibration system 1310 then estimates the VCO gain (KVC) based on the slope of the estimated open-loop transfer curve, for example by calculating the derivative of the VCO frequency versus the DAC1 and DAC2 code data, to determine the VCO gain KVCO (block 1405).

[0092] Once the KVCO value is determined, the DAC1 and DAC2 codes are adjusted based on equations so that the desired KVCO variation is obtained across the entire usable range of the control voltage, or so that the control voltage range of the desired linear VCO gain is maximized for optimal phase lock loop stability (block 1406). In some embodiments, this process prioritizes the lowest estimated slope between DAC1 and DAC2 and includes adjusting the DAC with the higher slope (see FIG. 14B). The common mode voltage output of the differential charge pump 1020 is adjusted so that symmetry of the transfer curve of the VCO gain versus the DAC1 and DAC2 calibration codes is obtained (block 1407). Calibration is carried out so that the ratio of the differential mode gain to the common mode gain is surely maximized (block 1408).

[0093] FIG. 14B illustrates various stages of the calibration process of FIG. 14A. For example, FIG. 14B shows a graph 1410 of the VCO output frequency as a function of VC_P (common mode calibration). The graph 1410 includes a first transfer curve 1412 of VCO frequency (common mode) versus VC_P (common mode) and a second transfer curve 1414 of VCO frequency (differential mode) versus VC_P (common mode). As described above, during the calibration process, the control voltage VC_P is set to VC_P = (α * V DD )+(0.5*ΔV), where only (α * V DD ) = VCTRLcom is maintained at V DD / 2 in the common mode control calibration. On the other hand, VC_N = (α * V DD )-(0.5*ΔV), and only (0.5*ΔV) = VCTRLdiff is swept from -V DD to V DD in the differential mode control calibration.

[0094] Further, FIG. 14B shows a graph 1420 of the VCO gain as a function of VC_P (common-mode calibration). The graph 1420 includes a first transfer curve 1422 of the VCO common-mode gain versus VC_P (common-mode) and a second transfer curve 1424 of the VCO differential gain versus VC_P (common-mode). The graph 1420 shows that after KVCO calibration, there is an asymmetric adjustment curve that does not center around V DD / 2, and that there are two sloped portions (i) and (ii) of the first transfer curve 1422.

[0095] There are also many other ways to perform calibration, and each method provides its own trade-off between accuracy, complexity, power consumption, area requirements, and the calibration time required to find a unique solution for the desired calibration. At the end of the calibration process, a KVCO-VCTRL transfer curve is obtained that (a) is symmetric about half the supply voltage to maximize the charge pump output common-mode range, (b) maximizes the ratio of the VCO common-mode gain (KVCO,DM) to the VCO common-mode gain (KVCO,DM), thereby achieving high common-mode noise immunity, and (c) minimizes KVCO,DM,max / KVCO,DM,min over the operating range such that the PLL phase margin is approximately constant within the operating range in the locked state.

[0096] The exemplary embodiments discussed herein primarily utilize a DAC for calibration purposes, but in other embodiments, the DAC can be used for dynamic adjustment configurations and a desired pattern can be used to change the digital code over time to generate spectral spreading, frequency chirping, or other types of frequency-versus-time characteristics within the loop bandwidth of the PLL such that sufficient signal fidelity is obtained.

[0097] FIG. 15 schematically shows a quantum computing system implementing a phase-locked loop system having a voltage-controlled oscillator implemented using a differential control VVRTC varactor device, according to an exemplary embodiment of the present disclosure. In particular, FIG. 15 schematically shows a quantum computing system 1500 comprising an arbitrary waveform generator (AWG) 1502 including a plurality of AWG channels 1502-1, ..., 1500-n for controlling respective qubits Q1, ..., Qn. Each of the AWG channels 1502-1, ..., 1500-n comprises a baseband signal generator 1510, a digital-to-analog converter stage 1520 (or DAC stage 120), a filter stage 1530, a modulation stage 1540, and an impedance matching network 1550. The AWG 1502 further comprises a phase-locked loop system 1504, a buffer 1506, and a plurality of dividers 1508-1, 1508-n, one for each of the AWG channels 1502-1, ..., 1502-n, to generate local oscillator (LO) signals (LO_1 and LO_Q) for respective modulation stages 1540 of the respective AWG channels 1502-1, ..., 1502-n.

[0098] In the exemplary embodiment of FIG. 15, the AWG 1502 comprises a quadrature AWG system configured to process quadrature signals (referred to as IQ signals). As is known in the art, a quadrature signal includes an in-phase (I) signal component and a quadrature-phase (Q) signal component. A pair of orthogonal signals have the same frequency but differ in phase by 90 degrees. In each AWG channel, the baseband signal generator 1510 is configured to receive baseband data as input and generate digital quadrature signals I and Q representing the input baseband data. In this process, the baseband data input to the baseband signal generator 1510 is separated into two orthogonal digital components including an in-phase (I) baseband component and a quadrature-phase (Q) baseband component. In some embodiments, the baseband signal generator 1510 implements digital signal processing techniques based on a combination of hardware and software to generate digital quadrature baseband signals I and Q. The baseband signal generator 110 generates the essential digital quadrature baseband IQ signals necessary to operate or otherwise control a given qubit coupled to the output of a given AWG channel to generate an analog waveform (e.g., a sine wave voltage waveform) having a target center frequency.

[0099] The DAC stage 1520 is configured to convert a digital baseband signal (e.g., the digital IQ signal output from the baseband signal generator 1510) into an analog baseband signal having a baseband frequency. The DAC stage 1520 comprises a first DAC circuit 1521 and a second DAC circuit 1522. The first DAC circuit 1521 is configured to convert the digital baseband component I into an analog baseband component I(t) having a baseband frequency, and the second DAC circuit 1522 is configured to convert the digital baseband component Q into an analog baseband component Q(t) having the same baseband frequency but phase-shifted by 90 degrees with respect to I(t). The DAC stage 1520, in some embodiments, has a given sampling rate (f within the range of baseband frequencies from about 100 kHz to about 100 MHz. S)Or at a sampling frequency, generate and output analog baseband signals I(t) and Q(t). In some embodiments, the DAC circuits 1521 and 1522 can be digitally configured to adjust the operating parameters of the DAC, including but not limited to the sampling rate, analog output gain, etc.

[0100] Filter stage 1530 is configured to filter the IQ analog signal components output from the DAC stage 1520, thereby generating a filtered analog IQ signal. Filter stage 1530 includes a first filter circuit 1531 and a second filter circuit 1532. The first filter circuit 1531 is configured to filter the in-phase analog signal I(t) output from the first DAC circuit 1521, and the second filter circuit 1532 is configured to filter the quadrature-phase analog signal Q(t) output from the second DAC circuit 1522. In some embodiments, the first and second filter circuits 1531 and 1532 include low-pass filters configured to pass the fundamental spectral components of the respective analog signals I(t) and Q(t) while suppressing the image components of the respective analog signals I(t) and Q(t). In other embodiments, the first filter circuit 1531 and the second filter circuit 1532 can be configured as band-pass filters for passing the higher-frequency image components of the desired bands of the respective analog baseband components I(t) and Q(t) while suppressing the fundamental spectral components and other image components of the respective analog baseband components I(t) and Q(t). In other embodiments, the first and second filter circuits 1531 and 1532 are configured as high-pass filters as may be desired for a given application.

[0101] In some embodiments, the filter stage 1530 comprises a configurable filter circuit that can, for example, adjust the cut-off frequencies of the first and second filter circuits 1531 and 1532, or be configured such that the first and second filter circuits 1531 and 1532 have different filter types (e.g., low-pass, band-pass, etc.) as desired for a given application. For example, in some embodiments, a band-pass filter can be configured using two low-pass filters that use known signal filtering techniques and architectures. In some embodiments, the filter configuration is digitally controlled by a digital control signal input to the filter stage 1530.

[0102] In some embodiments, the modulation stage 1540 is configured to perform modulation of the analog IQ signals (e.g., single-sideband (SSB) modulation) by mixing the filtered analog signals I(t) and Q(t) output from the filter stage 1530 with quadrature LO signals (e.g., in-phase LO signal (LO_I) and quadrature-phase LO signal (LO_Q)), and generate and output an analog RF signal (e.g., a single-sideband modulated RF output signal). The local oscillator signals LO_I and LO_Q each have the same LO frequency, but the LO_Q signal is phase-shifted by 90 degrees with respect to the LO_I signal.

[0103] More specifically, the modulation stage 1540 comprises a first mixer circuit 1541, a second mixer circuit 1542, and a signal combiner circuit 1543. The first mixer circuit 1541 is configured to mix the filtered analog signal I(t) with the LO_I signal to generate a first RF signal output. The second mixer circuit 1542 is configured to mix the filtered analog signal Q(t) with the LO_Q signal to generate a second RF signal output. The first and second RF signals output from the first and second mixer circuits 1541 and 1542 are input to the signal combiner circuit 1543 and combined (e.g., added) to generate a single-sideband RF signal output.

[0104] In some embodiments, the dividers 1508-1, …, 1508-n include quadrature phase shifter circuits for generating quadrature LO_I and LO_Q signals. For example, the quadrature phase shifter circuit receives, as an input, the LO signal (generated by the phase-locked loop system 1504) and is configured to output the quadrature LO signals LO_I and LO_Q based on the LO input signal. In this configuration, the LO_I signal has the same frequency and phase as the input LO signal, and the LO_Q signal has the same frequency as the input LO signal but with a 90-degree phase shift. The quadrature phase shifter circuit can be implemented using one of various quadrature phase shift techniques known to those skilled in the art.

[0105] The impedance matching network 1550 is configured to match the source impedance or load impedance of the output of the modulation stage 1540 to the characteristic impedance Z0 of the output of a given AWG channel. In some embodiments, the impedance matching network 1550 includes a balun that converts the differential / balanced output of the AWG channel to a single-ended / unbalanced output. In the exemplary embodiment of FIG. 15, the output of the impedance matching network 1550 is coupled to respective qubits.

[0106] The phase-locked loop system 1504 generates an LO clock signal based on a reference clock signal REF_CLK and supplies the LO clock signal to all AWG channels via a buffer 1506. The LO clock signal is differentially routed to each of the dividers 1508-1, …, 1508-n of the respective AWG channels 1502-1, …, 1502-n. As described above, the dividers 1508-1, …, 1508-n supply an in-phase LO signal and a quadrature LO signal to the respective mixer circuits 1541 and 1542. In some embodiments, the phase-locked loop system 1504 implements a differential topology such as the phase-locked loop system 1000 shown and discussed above in connection with FIG. 10. The phase-locked loop system 1504 includes a VCO that implements any of the differentially controlled VVRTC varactor circuits, as discussed herein. An alternative configuration can be formed by driving the I and Q phases of the LO clock via a buffer coupled to the phase-locked loop system (e.g., a single divider can be used to supply the I and Q signals to all AWG channels via a buffer).

[0107] FIG. 16 schematically shows a quantum computing system implementing a phase-locked loop system having a voltage-controlled oscillator implemented using a differential-control VVRTC varactor device, according to another exemplary embodiment of the present disclosure. In particular, FIG. 16 schematically shows a quantum computing system 1600 that is similar to the quantum computing system 1500 of FIG. 15, except that the AWG 1502 of FIG. 16 receives a reference clock signal REF_CLK that is distributed through an AWG array and supplied to individual phase-locked loop systems 1604-1, …, 1604-n of respective AWG channels 1502-1, …, 1502-n. In this example, the reference clock REF_CLK is synchronized to the LO clock phase of all AWG channels. In some embodiments, each phase-locked loop system 1604-1, …, 1604-n implements a differential topology such as the phase-locked loop system 1000 shown and discussed above in connection with FIG. 10, and each phase-locked loop system 1604-1, …, 1604-n includes a VCO that implements any of the differential-control VVRTC varactor circuits as discussed herein. Exemplary embodiments of the VVRTC varactor devices and circuits discussed herein are capable of sufficient and stable operation over a wide temperature range including cryogenic temperatures, and thus can be readily utilized as cryogenic electronics components for implementing control circuits for quantum computing systems.

[0108] Exemplary embodiments of the invention may be a system, a method, or a computer program product, or any combination thereof, at any possible technical detail level of integration. The computer program product may include a computer-readable storage medium having computer-readable program instructions for causing a processor to execute aspects of the invention.

[0109] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction-executing device. The computer-readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or raised structures in grooves in which instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed to be a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or an electrical signal transmitted through an electrical wire.

[0110] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network or a combination thereof. The network may include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers or a combination thereof. A network adapter card or network interface of each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within each respective computing / processing device.

[0111] The computer-readable program instructions for carrying out the operations of the present invention may be written in any combination of one or more programming languages, including assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or object-oriented programming languages such as Smalltalk(R), C++, and procedural programming languages such as the "C" programming language or similar programming languages, and may be either source code or object code. The computer-readable program instructions may be executed entirely on the user's computer, partly on the user's computer as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute the computer-readable program instructions to customize the electronic circuit by utilizing the state information of the computer-readable program instructions to implement aspects of the present invention.

[0112] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0113] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowchart(s) and / or block diagram(s). These computer-readable program instructions may also be stored in a computer-readable storage medium that contains instructions for a manufacturing article comprising instructions for implementing the aspects of the functions / operations specified in one or more blocks of the flowchart(s) and / or block diagram(s), the computer-readable storage medium being stored in the computer-readable storage medium and being configured to direct a computer, programmable data processing apparatus, or other device or combination thereof to function in a particular manner.

[0114] The computer-readable program instructions may also be loaded onto a computer, other programmable apparatus, or other device to produce a computer-implemented process such that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / operations specified in one or more blocks of the flowchart(s) and / or block diagram(s), causing a series of operational steps to be performed on the computer, other programmable apparatus, or other device.

[0115] The flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, segment, or portion of instructions that include one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions represented by the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be performed as one step, executed simultaneously, substantially simultaneously, partially or wholly in a temporally overlapping manner, or the blocks may sometimes be executed in the reverse order depending on the functionality involved. It should also be noted that each block of the block diagram or flowchart diagram, or both, and combinations of blocks of the block diagram or flowchart diagram, or both, can be implemented by a special purpose hardware-based system that performs the specified function or acts, or executes a combination of special purpose hardware and computer instructions.

[0116] These concepts are illustrated with reference to FIG. 17, which schematically shows an exemplary architecture of a computing node that can be used to implement a software-based control system for any of the exemplary systems discussed herein. FIG. 17 shows a computing node 1700 comprising a computer system / server 1712 operable in a number of other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations or combinations thereof that might be suitable for use with computer system / server 1712 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems or devices.

[0117] Computer system / server 1712 can be described in the general context of computer system executable instructions, such as program modules, being executed by a computer system. Generally, program modules can include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. Computer system / server 1712 may be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

[0118] In FIG. 17, the computer system / server 1712 of the computing node 1700 is shown in the form of a general-purpose computing device. The components of the computer system / server 1712 may include, but are not limited to, one or more processors or processing units 1716, a system memory 1728, and a bus 1718 that couples various system components including the system memory 1728 to the processor 1716.

[0119] The bus 1718 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor bus or local bus using any of a variety of bus architectures. By way of example and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0120] The computer system / server 1712 typically includes various computer system readable media. Such media may be any available media accessible by the computer system / server 1712, and includes both volatile and nonvolatile media, removable and non-removable media.

[0121] System memory 1728 can include a computer system readable medium in the form of volatile memory such as random access memory (RAM) 1730 or cache memory 1732 or both. Computer system / server 1712 can further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 1734 can be provided for reading from and writing to a non-removable non-volatile magnetic medium (not shown, typically called a "hard drive"). Although not shown, a magnetic disk drive for reading from and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading from and writing to a removable non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media can be provided. In such cases, each can be connected to bus 1718 by one or more data media interfaces. As shown and described herein, memory 1728 can include at least one program product having a set (e.g., at least one) of program modules configured to execute the functions of embodiments of the present invention.

[0122] Program / utility 1740 having a set (at least one) of program modules 1742 can store, by way of example, but not limited to, an operating system, one or more application programs, other program modules, and program data in memory 1728. Each of the operating system, one or more application programs, other program modules, and program data, or some combination thereof, can include an implementation of a networking environment. Program modules 1742 generally execute the functions or methodologies of embodiments of the present disclosure as described herein, or both.

[0123] Computer system / server 1712 can also communicate with one or more external devices 1714 such as a keyboard, a pointing device, a display 1724, one or more devices that enable a user to interact with computer system / server 1712, or any device (e.g., network card, modem, etc.) that enables computer system / server 1712 to communicate with one or more other computing devices, or a combination thereof. Such communication can be performed via input / output (I / O) interface 1722. Nevertheless, computer system / server 1712 can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet) or a combination thereof via network adapter 1720. As shown, network adapter 1720 communicates with other components of computer system / server 1712 via bus 1718. Although not shown, it should be understood that other hardware or software components or both can be used in combination with computer system / server 1712. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, SSD drives, and data archive storage systems.

[0124] Furthermore, although this disclosure includes a detailed description regarding cloud computing, it should be understood that the implementation forms of the teachings described herein are not limited to a cloud computing environment. Rather, embodiments of the present invention can be implemented in combination with any other type of computing environment known currently or developed in the future.

[0125] Cloud computing is a service - delivery model that enables convenient on - demand network access to a shared pool of configurable computing resources (such as networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services), which can be rapidly provisioned and released with minimal management effort or service - provider interaction. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0126] The characteristics are as follows.

[0127] On - demand self - service: Cloud consumers can unilaterally provision computing capabilities such as server time and network storage automatically as needed, without the need for human interaction with the service provider.

[0128] Broad network access: Cloud capabilities are available over a network and can be accessed using standard mechanisms, facilitating use by heterogeneous thin - client or thick - client platforms (such as mobile phones, laptops, and PDAs).

[0129] Resource pooling: The provider's computing resources are pooled and provided to multiple users using a multi - tenant model, where various physical and virtual resources are dynamically assigned and re - assigned according to demand. Users generally have a sense of location independence in that they can neither control nor know the exact location of the provided resources, although at a higher level of abstraction, the location can be specified (e.g., country, state, or data center).

[0130] Rapid adaptability: The capabilities can be provisioned quickly, flexibly, and in some cases automatically, scale out rapidly, be released quickly, and scale in rapidly. The capabilities available for provisioning often appear to the user to be purchasable in any amount, at any time, without limit.

[0131] Measured services: Cloud systems automatically control and optimize resource usage by leveraging measurement capabilities at an abstraction level appropriate for the type of service (e.g., storage, processing, bandwidth, and active user accounts). The amount of resource usage can be monitored, controlled, and reported, providing transparency to both the provider and the user of the services being utilized.

[0132] The service model is as follows.

[0133] SaaS (Software as a Service): The functionality provided to the user is to use the provider's applications running on the cloud infrastructure. Those applications can be accessed from various client devices via a thin-client interface such as a web browser (e.g., web-based email). The user does not manage or control the underlying cloud infrastructure, which includes the network, servers, operating systems, storage, or individual application functionality, except for limited user-specific application configuration settings.

[0134] PaaS (Platform as a Service): The capabilities provided to users are to deploy the applications created or obtained by users, which are created using the programming languages and tools supported by the provider, to the cloud infrastructure. Users do not manage or control the underlying cloud infrastructure including the network, servers, operating systems, or storage, but can control the deployed applications and, in some cases, the configuration of the application hosting environment.

[0135] IaaS (Infrastructure as a Service): The capabilities provided to users are the provisioning of processing, storage, network, and other basic computing resources, and users can deploy and run any software that can include operating systems and applications. Users do not manage or control the underlying cloud infrastructure, but can control the operating systems, storage, deployed applications, and, in some cases, can limitedly control the selected network components (such as host firewalls).

[0136] The deployment model is as follows.

[0137] Private cloud: This cloud infrastructure is operated only for an organization. It may be managed by the organization or a third party and may exist on-premises or off-premises.

[0138] Community Cloud: This cloud infrastructure is shared by multiple organizations and supports a specific community that shares concerns (e.g., mission, security requirements, policies, and compliance considerations). It may be managed by an organization or a third party and may exist on-premises or off-premises.

[0139] Public Cloud: The cloud infrastructure is made available to the general public or a large industry group and is owned by an organization that sells cloud services.

[0140] Hybrid Cloud: The cloud infrastructure remains a unique entity but is a composite of two or more clouds (private, community, or public) joined by standardized or proprietary technologies (e.g., cloud bursting for load balancing between clouds) that enable data and application portability.

[0141] The cloud computing environment is a service-oriented environment that emphasizes statelessness, loose coupling, modularity, and semantic interoperability. At the center of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0142] Referring now to FIG. 18, an exemplary cloud computing environment 1800 is shown. As illustrated, cloud computing environment 1800 includes one or more cloud computing nodes 1850 with which local computing devices (e.g., personal digital assistant (PDA) or cellular telephone 1854A, desktop computer 1854B, laptop computer 1854C, or automotive computer system 1854N, or a combination thereof, etc.) utilized by cloud consumers may communicate. The nodes 1850 can communicate with one another. These nodes may be physically or logically grouped (not shown) in one or more networks such as the private cloud, community cloud, public cloud, or hybrid cloud, or a combination thereof, etc. Thus, cloud computing environment 1800 can provide infrastructure, platform, software, or a combination thereof as services such that cloud consumers need not maintain resources on local computing devices. The types of computing devices 1854A - N shown in FIG. 18 are intended only as examples, and it is understood that cloud computing nodes 1850 and cloud computing environment 1800 can communicate with any type of computerized device via any type of network or network addressable connection or both (e.g., using a web browser).

[0143] Referring now to FIG. 19, a set of functional abstractions provided by cloud computing environment 1800 (FIG. 18) is shown. It should be understood in advance that the components, layers, and functions shown in FIG. 19 are only exemplary and embodiments of the present invention are not limited thereto. As illustrated, the following layers and corresponding functions are provided.

[0144] Hardware and software layer 1960 includes hardware components and software components. Examples of hardware components include mainframe 1961, RISC (Reduced Instruction Set Computer) architecture-based server 1962, server 1963, blade server 1964, storage device 1965, and network and networking components 1966. In some embodiments, software components include network application server software 1967 and database software 1968.

[0145] Virtualization layer 1970 provides an abstraction layer that can provide examples of virtual entities such as virtual server 1971, virtual storage 1972, virtual network 1973 including a virtual private network, virtual applications and operating systems 1974, and virtual clients 1975.

[0146] To give an example, the management layer 1980 can provide the functions described below. Resource provisioning 1981 performs dynamic procurement of computing resources and other resources used to execute tasks within a cloud computing environment. Measurement and pricing 1982 performs cost tracking when resources are utilized within a cloud computing environment and issues bills or invoices for the use of these resources. To give an example, these resources can include application software licenses. Security performs identity verification of cloud users and tasks and protects data and other resources. The user portal 1983 provides access to the cloud computing environment to users and system administrators. Service level management 1984 allocates and manages cloud computing resources so that the required service levels are met. Service level agreement (SLA) planning and fulfillment 1985 makes advance arrangements and procures cloud computing resources for which future demands are expected according to the SLA.

[0147] The workload layer 1990 provides examples of functions that can be utilized in a cloud computing environment. Examples of workloads and functions that can be provided from this layer include mapping and navigation 1991, software development and life cycle management 1992, virtual classroom education delivery 1993, data analysis processing 1994, transaction processing 1995, and various functions 1996 for implementing control systems or quantum computing systems as discussed in this specification. Further, in some embodiments, the hardware and software layer 1960 will include various hardware systems as discussed in this specification, for example, to implement or otherwise support various workloads and functions 1996 for executing quantum computing.

[0148] The descriptions of the various embodiments of the present disclosure are presented for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, practical applications, or technological improvements found in the marketplace over the technology disclosed herein, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A variable capacitor device, comprising first and second control paths, each using first and second transistors of the same doping type in the first and second control paths to enable differential control. The variable capacitor device, wherein the first and second transistors are configured as voltage variable resistors for adjusting the capacitance of the variable capacitor device.

2. The device according to claim 1, wherein both the first and second transistors include one of an N-type field effect transistor and a P-type field effect transistor.

3. The first control path includes the first transistor and at least one capacitor connected in series between a first terminal and a second terminal of the variable capacitor device. The second control path includes the second transistor and at least one capacitor connected in series between the first terminal and the second terminal of the variable capacitor device. The variable capacitor device further includes a differential control terminal including a first control terminal and a second control terminal, wherein the first control terminal is coupled to a gate terminal of the first transistor, and the second control terminal is coupled to first and second source / drain terminals of the second transistor; a first adjustment terminal and a second adjustment terminal, wherein the first adjustment terminal is coupled to the first and second source / drain terminals of the first transistor, and the second adjustment terminal is coupled to a gate terminal of the second transistor. The device according to any one of claims 1 or 2.

4. The first control terminal is coupled to the gate terminal of the first transistor by a first resistive element. The first adjustment terminal is coupled to the first source / drain terminal of the first transistor by a second resistor element and to the second source / drain terminal of the first transistor by a third resistor element. The second adjustment terminal is coupled to the gate terminal of the second transistor by a fourth resistor element. The second control terminal is coupled to the first source / drain terminal of the second transistor by a fifth resistor element and to the second source / drain terminal of the second transistor by a sixth resistor element. The device according to claim 3, wherein the first, second, third, fourth, fifth, and sixth resistor elements include one of (i) a passive resistor device and (ii) a transistor device configured in a cut-off mode.

5. The differential control terminal is configured to receive an analog differential voltage control signal and adjust the capacitance of the variable capacitor device by changing the impedances of the first and second transistors, according to any one of claims 3 or 4.

6. The first and second adjustment terminals are configured to receive respective first and second reference voltages and adjust the capacitance-to-differential voltage transfer characteristic of the variable capacitor device, according to any one of claims 3 to 5.

7. The first and second adjustment terminals are configured to receive respective first and second reference voltages and adjust the ratio of the differential mode gain to the common mode gain of the variable capacitor device, according to any one of claims 3 to 6.

8. A first voltage variable resistor element coupled in parallel with the first transistor and configured to adjust the effective capacitance of the first control path. A second voltage variable resistor element coupled in parallel to the second transistor and configured to adjust the effective capacitance of the second control path, and a device according to any one of claims 1 to 7.

9. The first voltage variable resistor element includes a third transistor and a fourth transistor connected in series, the third transistor having a gate terminal commonly coupled to a third adjustment terminal and a first source / drain terminal commonly coupled to the first adjustment terminal. The second voltage variable resistor element includes a fifth transistor and a sixth transistor connected in series, the fifth transistor having a gate terminal commonly coupled to a fourth adjustment terminal and a first source / drain terminal commonly coupled to the second control terminal, the device according to claim 8.

10. A device, comprising an oscillator circuit including a resonant tank circuit, the resonant tank circuit comprising a variable capacitor device including first and second control paths, the first and second control paths being configured to enable differential control using first and second transistors of the same doping type in the first and second control paths respectively, the first and second transistors being configured as voltage variable resistors for adjusting the capacitance of the variable capacitor device.

11. The device according to claim 10, wherein both the first and second transistors include one of an N-type field effect transistor and a P-type field effect transistor.

12. The first control path includes the first transistor and at least one capacitor connected in series between a first terminal and a second terminal of the variable capacitor device. The second control path includes the second transistor and at least one capacitor connected in series between the first terminal and the second terminal of the variable capacitor device. the variable capacitor device being, a differential control terminal including a first control terminal and a second control terminal, the first control terminal being coupled to the gate terminal of the first transistor, and the second control terminal being coupled to the first and second source / drain terminals of the second transistor; a differential control terminal, a first adjustment terminal and a second adjustment terminal, the first adjustment terminal being coupled to the first and second source / drain terminals of the first transistor, and the second adjustment terminal being coupled to the gate terminal of the second transistor; a first adjustment terminal and a second adjustment terminal, further comprising the device according to any one of claims 10 or 11.

13. the first control terminal being coupled to the gate terminal of the first transistor by a first resistive element, the first adjustment terminal being coupled to the first source / drain terminal of the first transistor by a second resistive element and to the second source / drain terminal of the first transistor by a third resistive element, the second adjustment terminal being coupled to the gate terminal of the second transistor by a fourth resistive element, the second control terminal being coupled to the first source / drain terminal of the second transistor by a fifth resistive element and to the second source / drain terminal of the second transistor by a sixth resistive element, the first, second, third, fourth, fifth, and sixth resistive elements including one of (i) a passive resistor device and (ii) a transistor device configured in a cut-off mode; the device according to claim 12

14. an analog differential adjustment control system configured to generate an analog differential voltage control signal applied to the differential control terminal of the variable capacitor device and to adjust the capacitance of the tank circuit by changing the impedance of the first and second transistors; A calibration system configured to generate first and second reference voltages respectively applied to the first and second adjustment terminals of the variable capacitor device to adjust at least one of (i) the capacitance versus differential voltage transfer curve of the variable capacitor device and (ii) the ratio of the differential mode gain to the common mode gain of the variable capacitor device, and the device according to any one of claims 12 or 13, further comprising.

15. The oscillator circuit includes a voltage controlled oscillator circuit, The tank circuit includes an inductor element coupled in parallel to the variable capacitor device, The voltage controlled oscillator circuit includes a mutual conductance cell including at least a pair of cross-coupled transistor devices connected in parallel to the tank circuit, the device according to any one of claims 10 to 14.

16. A device, Comprising a voltage controlled oscillator circuit including a resonant tank circuit, The resonant tank circuit includes a variable capacitor circuit including a plurality of variable capacitor devices connected in parallel to the first and second tank nodes of the resonant tank circuit, Each variable capacitor device includes first and second control paths, the first and second control paths being configured to enable differential control using first and second transistors of the same doping type in the first and second control paths respectively, the first and second transistors being configured as voltage variable resistors for adjusting the capacitance of the variable capacitor device.

17. The device according to claim 16, wherein the first and second transistors of each variable capacitor device both include one of an N-type field effect transistor having a substantially identical structure and a P-type field effect transistor having a substantially identical structure.

18. For each variable capacitor device, The first control path includes the first transistor and at least one capacitor connected in series between the first terminal and the second terminal of the variable capacitor device, The second control path includes the second transistor and at least one capacitor connected in series between the first terminal and the second terminal of the variable capacitor device, The first and second terminals of the variable capacitor device are respectively coupled to the first and second tank nodes of the resonant tank circuit, Each variable capacitor device, A differential control terminal including a first control terminal and a second control terminal, wherein the first control terminal is coupled to the gate terminal of the first transistor, and the second control terminal is coupled to the first and second source / drain terminals of the second transistor, a differential control terminal, A first adjustment terminal and a second adjustment terminal, wherein the first adjustment terminal is coupled to the first and second source / drain terminals of the first transistor, and the second adjustment terminal is coupled to the gate terminal of the second transistor, the first adjustment terminal and the second adjustment terminal, further comprising the device according to any one of claims 16 or 17.

19. For each variable capacitor device, The first control terminal is coupled to the gate terminal of the first transistor by a first resistor element, The first adjustment terminal is coupled to the first source / drain terminal of the first transistor by a second resistor element and coupled to the second source / drain terminal of the first transistor by a third resistor element, The second adjustment terminal is coupled to the gate terminal of the second transistor by a fourth resistor element, The second control terminal is coupled to the first source / drain terminal of the second transistor by a fifth resistor element and coupled to the second source / drain terminal of the second transistor by a sixth resistor element, The device according to claim 18, wherein the first, second, third, fourth, fifth, and sixth resistive elements include one of (i) a passive resistor device and (ii) a transistor device having a grounded gate terminal.

20. Further comprising a calibration system configured to generate different sets of first and second reference voltages applied to the first and second adjustment terminals of two or more of the variable capacitor devices, and to adjust the capacitance differential voltage transfer characteristics of each of the two or more of the variable capacitor devices to obtain a more linearized capacitance differential voltage transfer characteristic of the variable capacitor circuit of the resonant tank circuit, the device according to any one of claims 18 or 19.

21. Each variable capacitor device A first resistive element bank including one or more first voltage variable resistive elements coupled in parallel to the first transistor and configured to adjust the effective capacitance of the first transistor in the first control path; A second resistive element bank including one or more second voltage variable resistive elements coupled in parallel to the second transistor and configured to adjust the effective capacitance of the second transistor in the second control path, the device according to any one of claims 16 to 20.

22. A system comprising: A voltage controlled oscillator; An analog differential adjustment control system including a differential charge pump and a loop filter, configured to generate a differential control voltage for adjusting the output frequency of the voltage controlled oscillator; The voltage controlled oscillator includes a resonant tank circuit; The resonant tank circuit includes a variable capacitor circuit including a plurality of variable capacitor devices connected in parallel to the first and second tank nodes of the resonant tank circuit; Each variable capacitor device includes first and second control paths, the first and second control paths being configured to enable differential control by using first and second transistors of the same doping type in the first and second control paths, respectively, the first and second transistors being configured as voltage variable resistors for adjusting the capacitance of the variable capacitor device in response to the differential control voltage. Claim 23 For each variable capacitor device, the first control path includes the first transistor and at least one capacitor connected in series between a first terminal and a second terminal of the variable capacitor device, the second control path includes the second transistor and at least one capacitor connected in series between the first terminal and the second terminal of the variable capacitor device, the first and second terminals of the variable capacitor device are coupled to the first and second tank nodes of the resonant tank circuit, respectively, each variable capacitor device includes a differential control terminal including a first control terminal and a second control terminal, the first control terminal being coupled to the gate terminal of the first transistor, and the second control terminal being coupled to the first and second source / drain terminals of the second transistor, a first adjustment terminal and a second adjustment terminal, the first adjustment terminal being coupled to the first and second source / drain terminals of the first transistor, and the second adjustment terminal being coupled to the gate terminal of the second transistor, The system of claim 22, further comprising a calibration system configured to generate different sets of first and second reference voltages applied to respective first and second adjustment terminals of two or more of the variable capacitor devices to adjust at least one of (i) the capacitance differential voltage transfer characteristics of each of the two or more of the variable capacitor devices, and (ii) the ratio of the differential mode gain of the voltage controlled oscillator to the common mode gain of the voltage controlled oscillator.

24. A system comprising: A plurality of qubits; An arbitrary waveform generator system comprising a plurality of arbitrary waveform generator channels, each arbitrary waveform generator channel being coupled to a respective qubit of the plurality of qubits and configured to generate a high frequency signal for controlling the operation of the qubit; A phase locked loop system configured to generate a local oscillator signal utilized by the modulation system of each of the arbitrary waveform generator channels; The phase locked loop system comprising: A voltage controlled oscillator; An analog differential adjustment control system comprising a differential charge pump and a loop filter, the analog differential adjustment control system being configured to generate a differential control voltage for adjusting the output frequency of the voltage controlled oscillator; The voltage controlled oscillator comprising a resonant tank circuit; The resonant tank circuit comprising a variable capacitor circuit including a plurality of variable capacitor devices connected in parallel to first and second tank nodes of the resonant tank circuit; Each variable capacitor device includes first and second control paths, the first and second control paths being configured to enable differential control by using first and second transistors of the same doping type in the first and second control paths respectively, and the first and second transistors being configured as voltage variable resistors for adjusting the capacitance of the variable capacitor device in response to the differential control voltage.

25. For each variable capacitor device, the first control path includes the first transistor and at least one capacitor connected in series between a first terminal and a second terminal of the variable capacitor device, the second control path includes the second transistor and at least one capacitor connected in series between the first terminal and the second terminal of the variable capacitor device, the first and second terminals of the variable capacitor device are coupled to the first and second tank nodes of the resonant tank circuit respectively, Each variable capacitor device includes a differential control terminal including a first control terminal and a second control terminal, the first control terminal being coupled to the gate terminal of the first transistor, and the second control terminal being coupled to the first and second source / drain terminals of the second transistor, and a first adjustment terminal and a second adjustment terminal, the first adjustment terminal being coupled to the first and second source / drain terminals of the first transistor, and the second adjustment terminal being coupled to the gate terminal of the second transistor. The system of claim 24, further comprising a calibration system configured to generate different sets of first and second reference voltages applied to respective first and second adjustment terminals of two or more of the variable capacitor devices to adjust at least one of (i) the capacitance differential voltage transfer characteristics of each of the two or more of the variable capacitor devices, and (ii) the ratio of the differential mode gain of the voltage controlled oscillator to the common mode gain of the voltage controlled oscillator.

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