High Elastic Modulus Carbon-Doped Silicon Oxide Films for Scaling Solutions of Mold Stacks in High Memory Applications

Abstract

Provide a plasma-excited chemical vapor deposition process at low temperature for forming a high elastic modulus oxide film on a substrate. The substrate temperature for deposition of the oxide film is less than about 700 °C.

Description

Technical Field

[0001] [Incorporation by Reference] The PCT application form is submitted simultaneously with this specification as part of this application. Each application identified in the PCT application form submitted simultaneously and for which this application claims benefit or priority shall be incorporated by reference in its entirety into this specification for all purposes.

Background Art

[0002] The evolution of chip design requires continuous improvement in circuit speed and reliability. This brings about the need to increase the transistor speed by packing devices more densely to increase the packing density. Nevertheless, device miniaturization is not necessarily desirable. Increasing the density to a level smaller than an atom causes RC (reactance-capacitance) delay, thereby degrading transistor performance. The solution is to use a low dielectric constant intermetal dielectric film instead of the conventional silicon oxide film.

[0003] A material that may be considered suitable for such problems is a carbon-doped silicon dioxide film. The splitting of metal wires using this material can result in a device with less propagation delay, crosstalk noise, and power loss. However, replacing the silicon dioxide film may have an adverse effect on other integration modules. One long-standing problem is the etching of carbon-doped silicon oxide films. The etching profile may deviate due to excessive carbon by-products released from the film. Furthermore, the excessive carbon generated from the film can interfere with the etching, increasing the possibility of incomplete etching by stopping the etching before reaching the desired depth. The carbon content can also cause excessive microloading (the difference in etching rate between sparse trenches and dense trenches) that is difficult to adjust. For these reasons, a high carbon content in the film is typically not desirable except for reducing its dielectric constant. Therefore, a precisely controlled carbon content in the carbon-doped silicon dioxide film is advantageous, especially in 3D NAND technology where memory stacks are vertically stacked within a layer.

[0004] The background description provided herein is for the purpose of generally presenting the content of the present disclosure. Research by the present inventors, as currently named, within the scope described in this background art section, as well as aspects of the description that cannot be separately regarded as prior art at the time of filing, are not admitted as prior art against the present disclosure, whether explicitly or implicitly.

Summary of the Invention

[0005] Provided herein are methods and apparatuses for processing semiconductor substrates and semiconductor devices. The various described methods and apparatuses relate to thin films produced by plasma-enhanced chemical vapor deposition at lower temperatures and may be useful in a wide range of gap-filling applications, such as the formation of advanced 3D NAND devices. The thin films improve mechanical properties without sacrificing electrical properties or other properties that facilitate integration.

[0006] Accordingly, in a first aspect, the present invention encompasses a method of plasma-enhanced chemical vapor deposition of a thin film. In some embodiments, the method includes providing a substrate in a deposition chamber at a substrate temperature of less than about 700 °C, generating a plasma of at least one process gas comprising at least one reactant, contacting the substrate with the plasma in the deposition chamber, and depositing a thin film on the substrate. The thin film has a Young's modulus of at least 70 GPa.

[0007] In some embodiments, the reactant is a silicon-containing gas source, an aluminum-containing gas source, or a boron-containing gas source.

[0008] In some embodiments, the thin film is silicon monoxide, silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, boron carbide, or boron nitride.

[0009] In some embodiments, the thin film is a doped thin film.

[0010] In some embodiments, the doped thin film is silicon oxide doped with carbon, nitrogen, boron, phosphorus, or a combination thereof.

[0011] In some embodiments, the doped thin film has a modulus of elasticity of at least 90 GPa.

[0012] In some embodiments, the doped thin film is boron carbide doped with silicon, nitrogen, germanium, magnesium, nickel, or a combination thereof.

[0013] In some embodiments, the doped thin film is boron nitride doped with bismuth, zinc, copper, or a combination thereof.

[0014] In some embodiments, the doped thin film is silicon nitride doped with aluminum, phosphorus, carbon, oxygen, or a combination thereof.

[0015] In some embodiments, the doped thin film is aluminum oxide doped with erbium, titanium, chromium, or a combination thereof.

[0016] In some embodiments, the plasma is generated in situ or remotely.

[0017] In some embodiments, the thin film has a thickness of less than 300 angstroms.

[0018] In some embodiments, the thin film has a dielectric constant of about 4 to about 4.5.

[0019] In a second aspect, the present invention encompasses a plasma-enhanced chemical vapor deposition method of a carbon-doped silicon oxide film on a substrate. In some embodiments, the method includes providing a substrate in a deposition chamber at a substrate temperature of less than about 700 °C, generating a plasma of a process gas including a silicon-containing gas source and a carrier gas and a carbon-containing gas source, contacting the substrate with the plasma in the deposition chamber, and depositing a thin film of carbon-doped silicon dioxide on the substrate. The thin film has a Young's modulus of at least 70 GPa.

[0020] In some embodiments, the silicon-containing gas source is SiH n R 1 4-n (I), SiH n (OR 2 ) 4-n (II), O(Si(R 3 3))2 (III), or a gas of a compound of the formula of a combination thereof. Here, each of R 1 , R 2 , and R 3 is independently an optionally substituted aliphatic, optionally substituted alkyl, optionally substituted heteroalkyl, optionally substituted aryl, optionally substituted heteroaryl, optionally substituted cyclil, or optionally substituted heterocyclil, and n is an integer from 0 to 4.

[0021] In some embodiments, the silicon-containing gas source is a gas such as silane, tetramethylsilane, tetramethoxysilane, tetraethoxysilane, hexamethyldisilazane, hexamethyldisiloxane, and combinations thereof.

[0022] In some embodiments, the silicon-containing gas source contains tetramethylsilane and silane.

[0023] In some embodiments, the carbon-containing gas source is a gas such as carbon dioxide, carbon monoxide, methane, ethane, and combinations thereof.

[0024] In some embodiments, the carbon-containing gas source also includes a carrier gas such as argon, helium, hydrogen, nitrous oxide, nitrogen, and combinations thereof.

[0025] In some embodiments, the carbon-doped silicon oxide film has a Young's modulus of at least 90 GPa.

[0026] In some embodiments, the carbon-doped silicon oxide film has a carbon content of about 5% (atomic) or less.

[0027] In some embodiments, the pressure in the deposition chamber is maintained at about 1 to about 8 Torr.

[0028] In some embodiments, the substrate temperature is higher than about 400 °C and lower than about 650 °C.

[0029] In some embodiments, the ratio of the carbon-containing gas source to the silicon-containing gas source is from about 150:1 to about 10:1.

[0030] In some embodiments, the plasma is generated in situ or remotely.

[0031] In some embodiments, the thin film has a thickness of less than 300 angstroms.

[0032] In some embodiments, the thin film has a dielectric constant of about 4 to about 4.5.

[0033] In a third aspect, the present disclosure includes a composition. In some embodiments, the composition is a carbon-doped silicon oxide film having a thickness of less than 300 angstroms, a Young's modulus of at least 90 GPa, a dielectric constant of about 4 to about 4.5, and a carbon content of about 5% (atomic) or less.

[0034] In a fourth aspect, the present disclosure includes an apparatus for substrate processing. In some embodiments, the apparatus includes a reaction chamber, a substrate support configured to support a substrate within the reaction chamber, one or more inlets for introducing reactants into the reaction chamber, one or more outlets for removing materials from the reaction chamber, and a controller having at least one processor and a memory. The at least one processor and the memory are communicatively connected to each other, and the memory stores computer-executable instructions for controlling the at least one processor. The computer-executable instructions cause the at least one processor to provide a substrate within a deposition chamber at a substrate temperature of less than about 700 °C, generate a plasma of at least one process gas including at least one reactant, contact the substrate with the plasma within the deposition chamber, and deposit a thin film on the substrate. The thin film has a Young's modulus of at least 70 GPa.

[0035] In some embodiments, the thin film has a thickness of less than 300 angstroms.

[0036] In some embodiments, the thin film has a dielectric constant of from about 4 to about 4.5.

[0037] In a fifth aspect, the present disclosure includes an apparatus for forming a carbon-doped silicon oxide film on a substrate. In some embodiments, the apparatus includes a reaction chamber, a substrate support configured to support a substrate within the reaction chamber, one or more inlets for introducing reactants into the reaction chamber, one or more outlets for removing material from the reaction chamber, a plasma generator configured to deliver plasma to the reaction chamber, and a controller having at least one processor and a memory. The at least one processor and the memory are communicatively connected to each other, and the memory stores computer-executable instructions for controlling the at least one processor. The computer-executable instructions control the at least one processor to (i) receive a substrate within the reaction chamber, (ii) flow a process gas containing a silicon-containing source into the reaction chamber, and (iii) generate plasma from a carbon-containing gas source and deliver it to the reaction chamber to form a carbon-doped silicon oxide film on the substrate. The carbon-doped silicon oxide film has a Young's modulus of about 90 GPa or more and a dielectric constant of about 4 to about 4.5.

[0038] In some embodiments, the carbon-doped silicon oxide film has a thickness of less than 300 angstroms.

[0039] In some embodiments, the carbon-doped silicon oxide film has a carbon content of about 5% (atomic) or less.

[0040] These and other aspects are further described below with reference to the drawings.

Brief Description of the Drawings

[0041]

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[0045] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. The disclosed embodiments are described in conjunction with specific embodiments, but it will be understood that the disclosed embodiments are not intended to be limited to the specific embodiments. Definitions

[0046] As used herein, the term "about," unless otherwise specified, means + / - 10% of any recited value. As used herein, this term changes any recited value, range of values, or one or more endpoints.

[0047] As used herein, the terms "top," "bottom," "upper," "lower," "above," and "below" are used to provide a relative relationship between structures. The use of these terms does not indicate or require that a particular structure must be located in a particular position within the device.

[0048] As used herein, the phrase "at least one of A, B, and C" should be construed to mean a logical OR (A OR B OR C) using non-exclusive disjunction, and should not be construed to mean "at least one of A, at least one of B, and at least one of C".

[0049] "Aliphatic" means a hydrocarbon group having at least 1 to 50 carbon atoms (C 1-25 ), such as 1 to 25 carbon atoms (C 1-10 ), or 1 to 10 carbon atoms (C 1-50 ), and includes alkanes (or alkyls), alkenes (or alkenyls), alkynes (or alkynyls), their cyclic versions, and further includes straight-chain and branched-chain arrangements, as well as all stereoisomers and positional isomers. The aliphatic group is unsubstituted or substituted, for example, by a functional group described herein. For example, an aliphatic group can be substituted with one or more substituents as described herein for alkyl.

[0050] "Aryl" means at least 5 to 15 carbon atoms (C 5-10 ), such as 5 to 10 carbon atoms (C 5-15It means an aromatic carbocyclic group containing and having a monocyclic or multiple condensed rings, and the condensed rings can be aromatic or non-aromatic. However, the connection point to the remaining part of the compound disclosed in this specification is through the atoms of the aromatic carbocyclic group. The aryl group may be substituted by one or more groups other than hydrogen, such as aliphatic, heteroaliphatic, aromatic, other functional groups, or any combination thereof. Examples of aryl groups include, but are not limited to, benzyl, naphthalene, phenyl, biphenyl, phenoxybenzene, etc. The term aryl also includes heteroaryl, which is defined as a group containing an aromatic group having at least one heteroatom incorporated within the ring of the aromatic group. Examples of heteroatoms include, but are not limited to, nitrogen, oxygen, sulfur, and phosphorus. Similarly, the term non-heteroaryl further included in the term aryl defines a group containing an aromatic group that does not contain a heteroatom. The aryl group can be substituted or unsubstituted. The aryl group can be substituted by 1, 2, 3, 4, or 5 substituents. The substituents are independently selected from the group consisting of the following (1) to (47). That is, (1) C 1-6 Alkanoyl (for example, -C(O)-R, where R is C 1-6 Alkyl), (2) C 1-6 Alkyl, (3) C 1-6 Alkoxy (for example, -O-R, where R is C 1-6 Alkyl), (4) C 1-6 Alkoxy-C 1-6 Alkyl (for example, -L-O-R, where each of L and R is independently C 1-6 Alkyl), (5) C 1-6 Alkylsulfinyl (for example, -S(O)-R, where R is C 1-6 Alkyl), (6) C 1-6 Alkylsulfinyl-C 1-6 Alkyl (for example, -L-S(O)-R, where each of L and R is independently C 1-6 Alkyl), (7) C 1-6 Alkylsulfonyl (for example, -SO2-R, where R is C 1-6which is alkyl), (8) C 1-6 alkylsulfonyl-C 1-6 alkyl (e.g., -L-SO2-R, where each of L and R is independently selected from hydrogen, aliphatic, heteroaliphatic, haloaliphatic, haloheteroaliphatic, aromatic, or any combination thereof as defined herein, or L and R together with the nitrogen atom to which each is attached can form a heterocyclyl group as defined herein), (9) aryl, (10) amino (e.g., -NR 1-6 R 1 R 2 wherein R 1 and R 2 are each independently selected from hydrogen, aliphatic, heteroaliphatic, haloaliphatic, haloheteroaliphatic, aromatic, or any combination thereof as defined herein, or R 1 and R 2 together with the nitrogen atom to which each is attached can form a heterocyclyl group as defined herein), (11) C 1-6 aminoalkyl (e.g., -L 1 -NR 1 R 2 or -L 2 -C(NR 1 R 2 )(R 3 )-R 4 wherein L 1 is C 1-6 alkyl, L 2 is a covalent bond or C 1-6 alkyl, and each of R 1 and R 2 is independently selected from hydrogen, aliphatic, heteroaliphatic, haloaliphatic, haloheteroaliphatic, aromatic, or any combination thereof as defined herein, or R 1 and R 2 together with the nitrogen atom to which each is attached can form a heterocyclyl group as defined herein, and each of R 3 and R 4 is independently H or C 1-6 alkyl), (12) heteroaryl, (13) C 4-18 aryl-C 1-6 alkyl (e.g., -L-R, where L is C 1-6 alkyl and R is C 4-18Aryl), (14) Aroyl (e.g., -C(O)-R where R is aryl), (15) Azide (e.g., -N3), (16) Cyano (e.g., -CN), (17) C 1-6 Azidoalkyl (e.g., -L-N3 where L is C 1-6 Alkyl), (18) Aldehyde (e.g., -C(O)H), (19) Aldehyde-C 1-6 Alkyl (e.g., -L-C(O)H where L is C 1-6 Alkyl), (20) C 3-8 Cycloalkyl, (21) C 3-8 Cycloalkyl-C 1-6 Alkyl (e.g., -L-R where L is C 1-6 Alkyl and R is C 3-8 Cycloalkyl), (22) Halo, (23) C 1-6 Haloalkyl (e.g., -L 1 -X or -L 2 -C(X)(R 1 )-R 2 where L 1 is C 1-6 Alkyl, L 2 is a covalent bond or C 1-6 Alkyl, X is fluoro, bromo, chloro, or iodo, and each of R 1 and R 2 is independently H or C 1-6 Alkyl), (24) Heterocyclyl (e.g., a 5-, 6-, or 7-membered ring containing 1, 2, 3, or 4 non-carbon heteroatoms as defined herein), (25) Heterocyclyloxy (e.g., -O-R where R is heterocyclyl as defined herein), (26) Heterocyclyloyl (e.g., -C(O)-R where R is heterocyclyl as defined herein), (27) Hydroxyl (-OH), (28) C 1-6 Hydroxyalkyl (e.g., -L 1 -OH or -L 2 -C(OH)(R 1 )-R 2 where L 1 is C 1-6is alkyl, L 2 is a covalent bond or alkyl, R 1 and R 2 each is, independently, H or C as defined herein 1-6 alkyl), (29) nitro, (30) C 1-6 nitroalkyl (e.g., -L 1 -NO or -L 2 -C(NO)(R 1 )-R 2 wherein L 1 is C 1-6 alkyl, L 2 is a covalent bond or alkyl, R 1 and R 2 each is, independently, H or C as defined herein 1-6 alkyl), (31) N-protected amino, (32) N-protected amino-C 1-6 alkyl, (33) oxo (e.g., =O), (34) C 1-6 thioalkoxy (e.g., -S-R where R is C 1-6 alkyl), (35) thio-C 1-6 alkoxy-C 1-6 alkyl (e.g., -L-S-R where each of L and R is, independently, C 1-6 alkyl), (36)-(CH2) r CO2R 1 where r is an integer from 0 to 4 and R 1 is selected from the group consisting of (a) hydrogen, (b) C 1-6 alkyl, (c) C 4-18 aryl, and (d) C 4-18 aryl-C 1-6 alkyl (e.g., -L-R where L is C 1-6 alkyl and R is C 4-18 aryl), (37)-(CH2) r CONR 1 R 2 where r is an integer from 0 to 4 and R 1 and R 2 are each, independently, (a) hydrogen, (b) C 1-6 alkyl, (c) C4-18 Aryl, and (d) C 4-18 Aryl-C 1-6 Alkyl (e.g., -L-R, where L is C 1-6 Alkyl and R is C 4-18 Aryl) selected from the group consisting of, (38)-(CH2) r SO2R 1 where r is an integer from 0 to 4, and R 1 is (a) C 1-6 Alkyl, (b) C 4-18 Aryl, and (c) C 4-18 Aryl-C 1-6 Alkyl (e.g., -L-R, where L is C 1-6 Alkyl and R is C 4-18 Aryl) selected from the group consisting of, (39)-(CH2) r SO2NR 1 R 2 where r is an integer from 0 to 4, and R 1 and R 2 each are independently (a) hydrogen, (b) C 1-6 Alkyl, (c) C 4-18 Aryl, and (d) C 4-18 Aryl-C 1-6 Alkyl (e.g., -L-R, where L is C 1-6 Alkyl and R is C 4-18 Aryl) selected from the group consisting of, (40)-(CH2) r NR 1 R 2 where r is an integer from 0 to 4, and R 1 and R 2 each are independently (a) hydrogen, (b) N-protecting group, (c) C 1-6 Alkyl, (d) C 2-6 Alkenyl, (e) C 2-6 Alkynyl, (f) C 4-18 Aryl, and (g) C 4-18 Aryl-C 1-6 Alkyl (e.g., -L-R, where L is C 1-6 Alkyl and R is C 4-18 Aryl), (h) C 3-8Cycloalkyl, and (i) C 3-8 Cycloalkyl-C 1-6 Alkyl (e.g., -L-R where L is C 1-6 Alkyl and R is C 3-8 Cycloalkyl), selected from the group consisting of, and in one embodiment, no two groups are bonded to the nitrogen atom via a carbonyl or sulfonyl group, (41) Thiol (e.g., -SH), (42) Perfluoroalkyl (e.g., -(CF2) n CF3 where n is an integer from 0 to 10), (43) Perfluoroalkoxy (e.g., -O-(CF2) n CF3 where n is an integer from 0 to 10), (44) Aryloxy (e.g., -O-R where R is aryl), (45) Cycloalkoxy (e.g., -O-R where R is cycloalkyl), (46) Cycloalkylalkoxy (e.g., -O-L-R where L is alkyl and R is cycloalkyl), and (47) Arylalkoxy (e.g., -O-L-R where L is alkyl and R is aryl). In certain embodiments, the unsubstituted aryl group is a C 4-18 C 4-14 C 4-12 C 4-10 C 6-18 C 6-14 C 6-12 or C 6-10 aryl group.

[0051] "Deposition" or "vapor deposition" means, for example, in the case of a deposited metal layer containing one or more metal-containing compounds, a process of forming a layer (e.g., a metal) on one or more surfaces of a substrate from a vaporized precursor composition(s). The precursor composition is vaporized and directed toward and / or in contact with one or more surfaces of a substrate (i.e., a semiconductor substrate or semiconductor assembly) disposed within a deposition chamber. Typically, the substrate is heated. These precursor compositions form a non-volatile, thin, uniform layer on the surface(s) of the substrate. One operation of this method is one cycle, and in the process, the number of cycles necessary to obtain a desired layer thickness can be repeated.

[0052] "Heteroatom" means an atom other than carbon, such as oxygen, nitrogen, sulfur, silicon, boron, selenium, or phosphorus. In specific disclosed embodiments, such as when not permitted by valence constraints, the heteroatom does not include halogen atoms.

[0053] "Heterocyclyl", unless otherwise specified, means a 5-, 6-, or 7-membered ring containing 1, 2, 3, or 4 non-carbon heteroatoms (e.g., independently selected from the group consisting of nitrogen, oxygen, phosphorus, sulfur, or halogen). The 5-membered ring has 0 to 2 double bonds, and the 6-membered and 7-membered rings have 0 to 3 double bonds. The term "heterocyclyl" also includes bicyclic, tricyclic, and tetracyclic groups in which any of the above heterocycles is fused with 1, 2, or 3 rings independently selected from the group consisting of aryl rings, cyclohexane rings, cyclohexene rings, cyclopentane rings, cyclopentene rings, and other monocyclic heterocycles such as indolyl, quinolyl, isoquinolyl, tetrahydroquinolyl, benzofuryl, benzothienyl, etc. Heterocycles include thianyl, thietanyl, tetrahydrothienyl, thianyl, thiepanyl, aziridinyl, azetidinyl, pyrrolidinyl, piperidinyl, azepanyl, pyrrolyl, pyrrolinyl, pyrazolyl, pyrazolinyl, pyrazolidinyl, imidazolyl, imidazolinyl, imidazolidinyl, pyridyl, homopiperidinyl, pyrazinyl, piperazinyl, pyrimidinyl, pyridazinyl, oxazolyl, oxazolidinyl, oxazolidonyl, isoxazolyl, isoxazolidinyl, morpholinyl, thiomorpholinyl, thiazolyl, thiazolidinyl, isothiazolyl, isothiazolidinyl, indolyl, quinolinyl, isoquinolinyl, benzimidazolyl, benzothiazolyl, benzoxazolyl, furyl, thienyl, thiazolidinyl, isothiazolyl, isoindazolyl, triazolyl, tetrazolyl, oxadiazolyl, uracil, thiadiazolyl, pyrimidyl, tetrahydrofuranyl, dihydrofuranyl, dihydrothienyl, dihydroindolyl, tetrahydroquinolyl, tetrahydroisoquinolyl, pyranyl, dihydropyranyl, tetrahydropyranyl, dithiazolyl, dioxanyl, dioxinyl, dithianyl, trithianyl, oxazinyl, thiazinyl, oxothiolanyl, triazinyl, benzofuryl, benzothienyl, etc.

[0054] "Heterocyclilooxy" means a heterocyclyl group linked to a parent molecular group through an oxygen atom as defined herein. In some embodiments, the heterocyclilooxy group is -O-R, where R is a heterocyclyl group as defined herein.

[0055] "Heterocycliloyl" means a heterocyclyl group linked to a parent molecular group through a carbonyl group as defined herein. In some embodiments, the heterocycliloyl group is -C(O)-R, where R is a heterocyclyl group as defined herein.

[0056] For the purposes of this disclosure, "metal" as used in this context is to be understood to mean a conductor with a maximum resistance of 500 microohm cm, including metals and conductive metal salts, specifically conductive metal nitrides such as TiN.

[0057] In the present disclosure, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "partially fabricated integrated circuit" are used interchangeably. One of ordinary skill in the art will understand that the term "partially fabricated integrated circuit" can refer to a silicon wafer at any of many stages of integrated circuit fabrication. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the present disclosure is implemented on a wafer. However, the present disclosure is not so limited. The workpiece can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces on which the present disclosure can be utilized include various articles such as printed circuit boards. As used herein, the term "semiconductor substrate" or "substrate" refers to a substrate at any stage of semiconductor device fabrication that includes semiconductor material anywhere within its structure. It is understood that the semiconductor material within the semiconductor substrate need not be exposed. A semiconductor wafer having multiple layers of other materials (e.g., dielectrics) covering the semiconductor material is an example of a semiconductor substrate. The following detailed description assumes that the disclosed implementations are implemented on a semiconductor wafer, such as on a 200 mm, 300 mm, or 450 mm semiconductor wafer. However, the disclosed implementations are not so limited. The workpiece can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces on which the disclosed implementations can be utilized include various articles such as printed circuit boards.

[0058] "Silicon oxide" is referred to herein as including compounds containing silicon atoms and oxygen atoms, and includes all stoichiometric possibilities for Si x O y including integer and non-integer values of x and y. For example, "silicon oxide" includes compounds having the formula SiO n where 1 ≦ n ≦ 2 and n can be an integer or non-integer value. "Silicon oxide" is SiO 1.8may include stoichiometric compounds such as. "Silicon oxide" also includes silicon dioxide (SiO2) and silicon monoxide (SiO). "Silicon oxide" also includes both natural and synthetic variations and includes any crystal and molecular structure that includes the tetrahedral coordination of oxygen atoms surrounding a central silicon atom. "Silicon oxide" also includes amorphous silicon oxide and silicates.

[0059] "Silyl" means -SiR 1 R 2 R 3 or -SiR 1 R 2 - group. In some embodiments, R 1 , R 2 , and R 3 each independently is H, optionally substituted aliphatic, optionally substituted heteroaliphatic, optionally substituted aromatic, optionally substituted heteroaromatic, or optionally substituted amino. In certain embodiments, R 1 , R 2 , and R 3 each independently is H, optionally substituted alkyl, optionally substituted alkoxy, optionally substituted aryl, optionally substituted aryloxy, optionally substituted alkyl-aryl, optionally substituted aryl-alkyl, or optionally substituted amino. In other embodiments, the silyl group is -Si(R) a (OR) b (NR2) c where each R is independently H, optionally substituted aliphatic, optionally substituted heteroaliphatic, optionally substituted aromatic, or optionally substituted heteroaromatic, and each of a, b, and c is 0 or more and a + b + c = 3. In certain embodiments, each R is independently H, optionally substituted alkyl, optionally substituted aryl, optionally substituted alkyl-aryl, or optionally substituted aryl-alkyl.

[0060] "Silyloxy" means -OR, where R is an optionally substituted silyl group as described herein. In some embodiments, the silyloxy group is -O-SiR 1 R 2 R 3 wherein R 1 R 2 and R 3 each independently is H, an optionally substituted aliphatic, an optionally substituted heteroaliphatic, an optionally substituted aromatic, an optionally substituted heteroaromatic, or an optionally substituted amino. In certain embodiments, R 1 R 2 and R 3 each independently is H, an optionally substituted alkyl, an optionally substituted alkoxy, an optionally substituted aryl, an optionally substituted aryloxy, an optionally substituted alkyl-aryl, an optionally substituted aryl-alkyl, or an optionally substituted amino. In other embodiments, the silyloxy group is -O-Si(R) a (OR) b (NR2) c where each R is independently H, an optionally substituted aliphatic, an optionally substituted heteroaliphatic, an optionally substituted aromatic, or an optionally substituted heteroaromatic, and each of a, b, and c is 0 or more, and a + b + c = 3. In certain embodiments, each R is independently H, an optionally substituted alkyl, an optionally substituted aryl, an optionally substituted alkyl-aryl, or an optionally substituted aryl-alkyl.

[0061] "Substituted" means having one or more substituent moieties whose presence does not prevent the desired function or reactivity. Examples of substituents include alkyl, alkenyl, alkynyl, cycloalkyl (non-aromatic ring), Si(alkyl)3, Si(alkoxy)3, alkoxy, amino, alkylamino, alkenylamino, amide, amidine, guanidine, hydroxyl, thioether, alkylcarbonyl, alkylcarbonyloxy, alkoxycarbonyloxy, carbonate, alkoxycarbonyl, aminocarbonyl, alkylthiocarbonyl, phosphate, phosphate ester, phosphonate, cyano, halo, acylamino, imino, sulfhydryl, alkylthio, thiocarboxylic acid, dithiocarboxylic acid, sulfate, sulfato, sulfonate, sulfamoyl, sulfonamide, nitro, nitrile, azide, heterocyclyl, ether, ester, silicon-containing moiety, thioester, or combinations thereof. The substituents themselves may be substituted. For example, an amino substituent may itself be mono- or independently di-substituted by further substituents as defined above such as alkyl, alkenyl, alkynyl, and cycloalkyl (non-aromatic ring).

[0062] "Unsubstituted" means any open valence of an atom occupied by hydrogen. Also, when nothing is specified as occupying the open valence position on an atom, it is hydrogen.

[0063] One of ordinary skill in the art will understand that the above definitions are not intended to include unacceptable substitution patterns (e.g., methyl substituted with five different groups, etc.). Such unacceptable substitution patterns will be readily understood by one of ordinary skill in the art. Any functional group disclosed herein and / or defined above may be substituted or unsubstituted unless otherwise indicated herein.

[0064] Recent advancements in semiconductor fabrication technology have enabled increased density of elements on a substrate, such as memory cells within a memory device. For example, in 3D NAND technology, tall structures are designed to improve device density scaling. The increase in size of these structures presents new challenges. As described herein, new materials and processing techniques, including wide area gap filling, have been developed to address these challenges.

[0065] In an integrated flow for 3D NAND fabrication, alternating oxide and nitride layers or polysilicon layers are deposited within a staircase pattern. After the staircase is formed, the staircase is filled with an oxide layer. The oxide layer is then annealed, polished, and etched to pattern contacts. Conventional oxide films shrink after thermal annealing, causing displacement, deformation, and tilt in adjacent features and patterned vias, resulting in device defects. Insufficient thermal stability may also cause cracks in the film and structure at various locations in the device. Thermal stability becomes even more challenging at advanced nodes with a high aspect ratio and a significantly large volume of oxide material.

[0066] In typical current 3D NAND manufacturing, a "mold stack" containing 24 to 64 pairs of oxide and nitride layers (e.g., silicon dioxide (SiO2) / silicon nitride (Si3N4) layers) is typically deposited within a plasma-enhanced chemical vapor deposition (PECVD) dielectric deposition tool. The SiO2 and Si3N4 layers are sequentially deposited on each station (also referred to as a pedestal) without the wafer moving until all or most of the stack is deposited. Thereafter, vertical channels are etched downward through the oxide and nitride layers in the mold stack by high aspect ratio etching, and contacts are formed by filling with metal. Thereafter, a thick photoresist layer is applied and patterned, one set of oxide / nitride pairs is etched, and the photoresist pattern is shrunk and the next pair of oxide / nitride layers is etched. By repeating this sequence, a staircase structure is formed at the edge of the array. After a thick oxide layer is deposited and planarized, a word line slot mask is applied and slots are etched downward through all pairs of oxide / nitride layers. Thereafter, the nitride layer is etched away through the word line slots. Thereafter, a gate stack of silicon dioxide, silicon nitride, aluminum oxide, tungsten, tantalum nitride is deposited and etched back, and finally the slots are filled with oxide and tungsten.

[0067] The challenges of wide-area gap filling are faced in the fabrication of taller structures involving the deposition of thicker high-quality films. In 3D NAND, for example, thick silicon oxide films are used for isolation purposes. Conventional oxide films have the problem of high stress that causes wafer bow and pattern distortion when the film is made thicker, resulting in wafer handling challenges such as excessive lithography overlay and insufficient focus, as well as integration problems. Regarding conventional silicon oxide films, reduction of film stress leads to high moisture absorption, which can cause oxidation and high resistance in metal contacts. Also, these films are accompanied by high stress shift and film shrinkage during heat treatment, which amplifies the problem of pattern distortion. In addition, demanding even thicker films would further extend the chemical mechanical polishing (CMP) time for device planarization. Therefore, it is necessary to increase the CMP rate to reduce the overall device processing cost.

[0068] Low-stress films of sufficient thickness having high thermal stability, low moisture absorption, and excellent dielectric properties (e.g., low dielectric constant and high breakdown voltage) are desirable for wide-area gap filling and other applications in current and developing semiconductor processing technologies. For wide-area gap filling and other applications, such films should enable low-cost processing and avoid problems associated with agglomerating thicknesses greater than 5 μm, such as up to 10 micrometers (microns (μm)) or up to 20 μm or greater by deposition. Thick films can be deposited up to a thickness of over 20 μm by single-pass deposition.

[0069] A potential candidate with suitable physical properties is a doped oxide film. However, the common industry method used for depositing such films is sub-atmospheric chemical vapor deposition (SACVD). SACVD can produce films with high CMP rate and low stress after annealing, but the deposition rate is very slow, increasing the cost. In addition, the films absorb moisture, shrink unacceptably, and tend to crack when deposited to a thickness of several micrometers.

[0070] Conventional oxide films have a nominal elastic modulus within the range of 75 GPa, which is suitable for high aspect ratio memory OPOP (oxide / polycrystalline silicon) and ONON (oxide / nitride) applications. However, they cause line bending and collapse when thinner layers are applied. However, a high elastic modulus thin film deposited in accordance with certain disclosed embodiments enables thinning of the oxide layer for the tallest stack integrated layers. Such a thin film may have one or more of the following characteristics. The characteristics are an appropriate dielectric constant, high density, equal or exceeding wet etching rate, and maintenance of high power quality. Any of these characteristics is advantageous for good integration of future memory technology nodes and is also useful when the number of ONON pairs in the mold stack is increased in response to the requirements of advanced technology nodes.

[0071] FIG. 1 schematically illustrates a non-limiting process for thin film deposition. Process 10 represents a method for plasma-enhanced chemical vapor deposition of a thin film. In operation 20, a substrate is provided in a deposition chamber at a substrate temperature of less than about 700° C., for example, 650° C. or less. In the implementations disclosed below, the deposition of materials onto a substrate such as a wafer, substrate, or other workpiece is described. The workpiece can be of various shapes, sizes, and materials. In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art will understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer at any of many stages of integrated circuit fabrication. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. Unless otherwise indicated, the details of the processes described herein (e.g., flow rates, power levels, etc.) relate to the processing of a 300 mm diameter substrate, or a chamber configured to process a 300 mm diameter substrate, and can be adjusted to be appropriate for other sized substrates or chambers. In addition to semiconductor wafers, other workpieces that can be used in the implementations disclosed herein include various articles such as printed circuit boards. The processes and apparatus can be used in the fabrication of semiconductor devices, displays, LEDs, solar power panels, etc.

[0072] In various embodiments, the substrate is a semiconductor substrate. The substrate can be a silicon wafer (e.g., a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer), and includes a wafer having one or more material layers on which materials such as dielectric, conductive, or semiconductive materials are deposited. In some embodiments, the substrate temperature is from about 400° C. to less than about 650° C. In some embodiments, the substrate temperature is from about 350° C. to about 500° C. In some embodiments, the substrate temperature is from about 525° C. to about 575° C.

[0073] In some embodiments, the pressure in the deposition chamber is maintained at about 1 to about 20 Torr, for example, about 1 to about 8 Torr. In some embodiments, the pressure in the deposition chamber is maintained at about 2 to about 5 Torr. In some embodiments, the plasma power is 150 to 800 watts / station. In some embodiments, the plasma power is 200 to 500 watts / station.

[0074] In some embodiments, in operation 30, plasma is generated. The plasma may be generated in situ (inside the deposition chamber, also referred to as direct plasma) or remotely (inside a separate device outside the deposition chamber). In some embodiments, a plasma of reactive species is formed. Plasma species can include electrons, positive ions, neutral species, radicals, and other plasma species. In some embodiments, the plasma is formed from at least one process gas containing at least one reactant. In addition to the reactant, the process gas may also include a carrier gas. In some embodiments, the carrier gas is a noble gas such as argon, neon, krypton, xenon, or helium. In some examples, the plasma may include other species, such as nitrogen atoms, nitrogen radicals, nitrogen plasma, or combinations thereof.

[0075] The choice of reactant used as the process gas depends on the desired thin film. In some embodiments, when the thin film is silicon oxide, silicon dioxide, silicon nitride, or silicon oxynitride, the reactant is a silicon-containing gas source.

[0076] Suitable silicon-containing precursors for use according to the disclosed embodiments include polysilanes (H3Si-(SiH2) nExamples of silanes include (—SiH3), where n ≧ 0. Examples of silanes include silane (SiH4), disilane (Si2H6), and organosilanes such as methylsilane, ethylsilane, isopropylsilane, t-butylsilane, dimethylsilane, diethylsilane, di-t-butylsilane, allylsilane, sec-butylsilane, texylsilane, isoamylsilane, t-butyldisilane, di-t-butyldisilane, and the like.

[0077] Halosilanes contain at least one halogen group and may or may not contain hydrogen and / or carbon groups. Examples of halosilanes include iodosilanes, bromosilanes, chlorosilanes, and fluorosilanes. Halosilanes, particularly fluorosilanes, can form reactive halide species capable of etching silicon materials when plasma is applied. However, in some embodiments, the halosilane may not be introduced into the chamber when plasma is applied, and thus the formation of reactive halide species derived from the halosilane can be mitigated. Specific chlorosilanes include tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, t-butylchlorosilane, di-t-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, t-butyldimethylchlorosilane, texyldimethylchlorosilane, and the like.

[0078] Aminosilanes contain at least one nitrogen atom bonded to a silicon atom and may also include hydrogens, oxygens, halogens, and carbons. Examples of aminosilanes include mono-aminosilane, di-aminosilane, tri-aminosilane, and tetra-aminosilane (H3Si(NH2), H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively), as well as substituted mono-aminosilanes, di-aminosilanes, tri-aminosilanes, and tetra-aminosilanes, such as t-butylaminosilane, methylaminosilane, diisopropylaminosilane (DIPAS), di-sec-butylaminosilane, tert-butylsilanamine, bi(tert-butylamino)silane (SiH2(NHC(CH3)3)2 (BTBAS), tert-butylsilylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3, and the like. Further examples of aminosilanes include trisilylamine (N(SiH3)).

[0079] The silicon-containing gas source may be a gas of a compound of formula (I) of SiH n R 1 4-n of formula (II) of SiH n (OR 2 ) 4-n of formula (III) of O(Si(R 3 3))2, or a combination thereof, where each of R 1 , R 2 and R 3 is independently an optionally substituted aliphatic, optionally substituted alkyl, optionally substituted heteroalkyl, optionally substituted aryl, optionally substituted heteroaryl, optionally substituted cyclil, or optionally substituted heterocyclil, and n is an integer from 0 to 4.

[0080] Suitable silicon-containing reactants include dimethylaminotrimethylsilane, diethylaminotrimethylsilane, di-isopropylaminotrimethylsilane, piperidinotrimethylsilane, 2,6-dimethylpiperidinotrimethylsilane, di-sec-butylaminotrimethylsilane, isopropyl-sec-butylaminotrimethylsilane, tert-butylaminotrimethylsilane, isopropylaminotrimethylsilane, tert-pentylaminotrimethylsilane, diethylaminodimethylsilane, dimethylaminodimethylsilane, di-isopropylaminodimethylsilane, piperidino-dimethylsilane, 2,6-dimethylpiperidino-dimethylsilane, di-sec-butylaminodimethylsilane, isopropyl-sec-butylaminodimethylsilane, tert-butylaminodimethylsilane, isopropylaminodimethylsilane, tert-pentylaminodimethylamine silane, dimethylaminomethylsilane, diethylaminodimethylsilane, di-isopropylaminomethylsilane, isopropyl-sec-butylaminomethylsilane, 2,6-dimethylpiperidinomethylsilane, di-sec-butylaminomethylsilane, bis(dimethylamino)methylsilane, bis(diethylamino)methylsilane, bis(di-isopropylamino)methylsilane, bis(isopropyl-sec-butylamino)methylsilane, bis(2,6-dimethylpiperidino)methylsilane, bis(piperidino)methylsilane, bis(isopropylamino)methylsilane, bis(tert-butylamino)methylsilane, bis(sec-butylamino)methylsilane, bis(tert-pentylamino)methylsilane, bis(isobutylamino)methylsilane, bis(cyclohexylamino)methylsilane, bis(isopropylamino)dimethylsilane, bis(isobutylamino)dimethylsilane, bis(sec-butylamino)dimethylsilane, bis(tert-butylamino)dimethylsilane, bis(tert-pentylamino)dimethylsilane, bis(cyclohexylamino)dimethylsilane, and combinations thereof.

[0081] In some embodiments, the silicon-containing gas source is a gas such as silane, tetramethylsilane, tetramethoxysilane, tetraethoxysilane, hexamethyldisilazane, hexamethyldisiloxane, and combinations thereof.

[0082] In some embodiments, the silicon-containing gas source contains tetramethylsilane and silane.

[0083] In some embodiments, the thin film is aluminum oxide and the reactant is an aluminum-containing gas source. In some embodiments, the reactant is trimethylaluminum, aluminum tris-isopropoxide, aluminum trichloride, or aluminum acetylacetonate.

[0084] In some embodiments, the thin film is boron carbide or boron nitride and the reactant is a boron-containing gas source. In some embodiments, the reactant is trimethylboron, boron trichloride, or triethylboron.

[0085] In some embodiments, the thin film formed by the plasma-excited chemical vapor deposition method of the present disclosure is a doped thin film. In some embodiments, the thin film is silicon dioxide doped with carbon, nitrogen, boron, phosphorus, or combinations thereof. In some embodiments, the boron dopant source is triethyl borate (TEB). In some embodiments, the phosphorus dopant source is triethyl phosphate (TEPO). In some embodiments, the carbon dopant is carbon dioxide, carbon monoxide, methane, ethane, or combinations thereof. In some embodiments, the carbon-containing gas source (dopant) also includes a carrier gas such as argon, helium, hydrogen, nitrous oxide, nitrogen, and combinations thereof. In some embodiments, the flow rate ratio of the carrier gas to the carbon-containing gas source is up to 3:1.

[0086] In some embodiments, the film is boron carbide doped with silicon, nitrogen, germanium, magnesium, nickel, or combinations thereof. In some embodiments, the film is boron nitride doped with bismuth, zinc, copper, or combinations thereof. In some embodiments, the thin film is silicon nitride doped with aluminum, phosphorus, carbon, oxygen, or combinations thereof. In some embodiments, the thin film is aluminum oxide doped with erbium, titanium, chromium, or combinations thereof. In some embodiments, the thin film is a carbon material doped with silicon. In some embodiments, the thin film is silicon carbide doped with oxygen, nitrogen, or combinations thereof.

[0087] In some embodiments, the thin film formed by the plasma-excited chemical vapor deposition method of the present disclosure is a silicon oxide thin film doped with carbon. The carbon-containing gas source dopant may be a gas such as carbon dioxide, carbon monoxide, methane, ethane, or combinations thereof. The ratio of the carbon-containing gas source (dopant) to the silicon-containing gas source (reactant) is from about 150:1 to about 10:1.

[0088] Returning to FIG. 1, in operation 40, the substrate is contacted with a plasma of a process gas. The process gas contains at least one reactant. In some embodiments, the process gas also includes a carrier gas. In some embodiments, the process optionally includes one or more dopants.

[0089] In operation 50, the thin film is deposited on the substrate. The deposited thin film may have a thickness of less than 300 angstroms, a Young's modulus of at least 70 GPa, and a dielectric constant of about 4 to about 4.5. In some embodiments, the thin film is a carbon-doped silicon dioxide thin film having a Young's modulus of at least 90 GPa, a thickness of less than 300 angstroms, a carbon content of about 5% (atomic) or less, and a dielectric constant of about 4 to about 4.5. In some embodiments, the carbon-doped thin film may not have a detectable carbon content. In some embodiments, the thin film maintains the electrical properties and dielectric constant of conventional silicon oxide with a high Young's modulus (e.g., at least 70 GPa such as 90 GPa or more) and thus greater mechanical strength, as well as a lower Young's modulus (e.g., less than 70 GPa). In some embodiments, the thin film has a Young's modulus of 100 or more. In some embodiments, the thin film is equivalent to or exceeds the wet etching rate and / or density of conventional silicon oxide. Conventional oxide films formed by plasma-enhanced chemical vapor deposition of tetraethyl orthosilicate (TEOS) as a silicon-containing gas source or undoped silicate glass (USG) have Young's modulus values in the range of 70 to 80 GPa. In such conventional oxide films, adverse line bending or line collapse may be expected at pitch lengths of 40 nm or less (when thinner oxide layers are utilized).

[0090] In some embodiments, the plasma-enhanced chemical vapor deposition of the carbon-doped silicon oxide thin film is carried out according to the process shown in FIG. 1, with a substrate temperature of about 400 to about 600 °C, a deposition chamber pressure of about 1 to about 7 Torr, a ratio of CO2 to the silicon-containing compound of about 40:1, and a plasma power of about 250 to 750 W / station. In some embodiments, the flow rate of the silicon-containing gas source may be about 50 to about 100 sccm / station, and the flow rate of CO2 may be about 1000 to about 5000 sccm / station.

[0091] Figure 2 schematically shows a non-limiting process for plasma-enhanced chemical vapor deposition of a thin film. Process 60 shows a method of depositing and optionally annealing a doped silicon oxide film configured to expand upon annealing. In some embodiments, the annealing may be performed at about 500 to about 1000 °C for about 10 to about 60 minutes in the presence of nitrogen gas. At 70, a patterned semiconductor substrate is provided in a process chamber of a chemical deposition tool or the like. In some embodiments, the pattern is a staircase pattern of alternating oxide and nitride layers formed on the substrate. An exemplary substrate 100 is provided as a schematic in FIG. 3.

[0092] The method includes, at 80, depositing a thin film (such as a doped silicon oxide film) on the patterned semiconductor substrate. The thin film may have a thickness of, for example, at least 5 μm, for example, a maximum of 10 μm or a maximum of 20 μm or greater. The thin film may be deposited at a fast rate of at least 1 μm per minute, for example, about 1.25 μm / min or faster. In some embodiments, prior to deposition of the thin film, an undoped silicon oxide liner having, for example, about 200 - 2000 Å may be deposited.

[0093] Thereafter, at 90, the doped silicon oxide film is optionally annealed at a temperature higher than the film glass transition temperature. At the glass transition temperature, the film begins to expand and relax, and the film stress decreases. In some embodiments, annealing of the doped silicon oxide film may cause reflow of the film.

[0094] Post-deposition annealing may be performed on the substrate in the same process chamber or a different process chamber. In some examples, post-annealing can be performed in a process chamber at a temperature in the range of 500 °C to 950 °C for a period in the range of 20 to 60 minutes. In some examples, annealing can be performed using nitrogen (N2) or another inert gas. In some examples, annealing is performed in N2 at 750 °C for 30 minutes.

[0095] In various embodiments, the deposited oxide layer is a silicon oxide layer. In various embodiments, the deposited nitride layer is a silicon nitride layer. In some embodiments, each of the oxide layer and the nitride layer is deposited to an approximately the same thickness, for example, from about 10 nm to about 100 nm, or up to about 350 Å. The oxide layer may be deposited, for example, at a deposition temperature of approximately room temperature to about 600 °C.

[0096] The oxide layer and the nitride layer for forming the alternating oxide and nitride film stack may be deposited using any suitable technique, for example, atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or sputtering. In various embodiments, the oxide layer and the nitride layer are deposited by PECVD.

[0097] The film stack may include 48 to 512 layers of alternating oxide and nitride layers, with each oxide layer or nitride layer constituting one layer. A film stack including alternating oxide and nitride layers may also be referred to as an ONON stack.

[0098] FIG. 4 shows an exemplary schematic view of a substrate 100 having alternating oxide (101) and nitride (102) films deposited thereon. In the structure shown in FIG. 4, the oxide is deposited first, followed by nitride, oxide, nitride, etc., but the nitride may be deposited first, followed by oxide, nitride, oxide, etc.

[0099] Following the deposition of the ONON stack, a channel (not shown in FIG. 4) may be etched into the substrate. Thereafter, a staircase pattern is formed on the substrate. As used herein, a "staircase pattern" includes two or more steps, each step including an oxide layer and a nitride layer. It will be understood that the upper layer in each set of oxide and nitride layers may be either an oxide or a nitride to form a step within the staircase. In various embodiments, the staircase pattern includes, for example, from 24 to 256 steps. The staircase pattern may be formed using various patterning techniques. For example, one technique may include depositing a sacrificial layer on the substrate to mask regions of the substrate and etching each set of oxide and nitride layers to thereby form the staircase.

[0100] FIG. 5 provides an example of a substrate 100 including a staircase pattern of an oxide (111) layer and a nitride (112) layer having a hard mask 110 on the top nitride layer. In FIG. 5, four steps of the staircase pattern are shown, but it will be understood that the staircase pattern typically has more steps, for example, from 24 to 256 steps. Each step includes a nitride layer and an oxide layer and has a spacing of between about 150 nm and about 1000 nm, such as about 500 nm, as indicated by "d" in FIG. 5. This region extending from the edge of the step above it in each step may be referred to as a "pad".

[0101] For purposes of discussion, the following discussion, and subsequent schematic illustrations of the substrate, include a side view 199 as shown in FIG. 6.

[0102] The oxide film is deposited on a staircase pattern on a substrate. In the context of 3D NAND, the doped film to be deposited may expand upon annealing by being adjusted, and may exhibit post-annealing stress and stress shift that are substantially zero immediately after deposition. FIG. 7 shows an exemplary substrate 100 including an ONON staircase, a hard mask 110, and a doped oxide film 122 deposited on the staircase and configured to expand upon annealing 122.

[0103] Returning to FIG. 2, in operation 90, the doped silicon oxide film is then annealed at a temperature higher than the film glass transition temperature as described above. In some embodiments, reflow of the film may occur.

[0104] Referring to FIG. 8, in some embodiments, after deposition and annealing of the doped oxide film, a vertical slit 130 may be etched into the substrate. FIG. 8 shows a side view of the substrate 100 after the vertical slit 130 has been etched.

[0105] In some embodiments, the nitride layer within the ONON stack is etched with respect to the oxide on the substrate. The etching may be performed using a selective etching process, in which the nitride layer is etched at a faster rate than the oxide. Suitable selective etching processes may be dry or wet. For example, suitable dry selective nitride layer etching may be performed by exposing the substrate to any one or more of the following gases. The gases are chlorine (CL2), oxygen (O2), nitrous oxide (N2O), tetrafluoromethane (CF4), sulfur tetrafluoride (SF4), carbon dioxide (CO2), fluoromethane (CH3F), nitrogen trifluoride (NF3), nitrogen (N2), hydrogen (H2), ammonia (NH3), methane (CH4), sulfur hexafluoride (SF6), argon (Ar), carbonyl sulfide (COS), carbon disulfide (CS2), hydrogen sulfide (H2S), and nitric oxide (NO). In this operation, the nitride layer may be removed from the ONON stack by flowing the etching species into the vertical slit 130 and selectively etching the nitride laterally. Alternatively, the nitride layer within the ONON stack may be etched using a wet etching process. The wet etching process is performed by exposing the substrate to phosphoric acid (H3PO4) and / or dilute hydrofluoric acid ("DHF"), or a mixture of these solutions. FIG. 9 shows an exemplary schematic view of a substrate 100 having a horizontal gap 132 formed by etching the nitride.

[0106] In some embodiments, a conductor, typically tungsten, is deposited within the gap of the substrate to form a word line. The tungsten may be deposited by any suitable technique such as ALD, CVD, PEALD, and / or PECVD. In some embodiments, a barrier layer and / or a tungsten nucleation layer are deposited prior to the deposition of the bulk tungsten. FIG. 10 shows an example of a substrate including a tungsten word line 140 deposited in a location where the nitride 112 was previously located.

[0107] In other embodiments, it should also be understood that instead of the ONON stack, there may be a stack of deposited alternating dielectric and conductive layers. One example of this is a stack consisting of alternating oxides and polycrystalline silicon layers, which may also be referred to as an OPOP stack. Such an OPOP stack can be etched according to known techniques to form a staircase pattern, and as described above, it can avoid the need to replace nitrides with tungsten in the ONON technology.

[0108] Referring to FIG. 11, in some embodiments, the doped oxide film 122 is etched vertically to form a via 137. The doped oxide film 122 may be etched by dry etching using exposure to one or more of the following gases. The gases are O2, Ar, C4F6, C4F8, SF6, CHF3, and CF4. FIG. 11 shows an exemplary substrate 100 including an oxide / conductor stack within a staircase pattern, with a via 137 etched into the doped oxide 122.

[0109] Referring to FIG. 12, in some embodiments, a conductor (e.g., tungsten) may be deposited within the via 137 to form an interconnect 142 to the word line, thereby completing the 3D NAND structure.

[0110] Accordingly, another aspect includes a method of performing wide area gap fill in the fabrication of a 3D NAND structure. The method includes providing a patterned semiconductor substrate including a 3D NAND structure having alternating oxide and nitride layers or polycrystalline silicon layers within a staircase pattern, depositing a doped silicon oxide film configured to expand upon annealing at a temperature higher than the glass transition temperature of the film on the patterned semiconductor substrate over the staircase pattern, and annealing the doped silicon oxide film to a temperature higher than the glass transition temperature of the film. The doped silicon oxide film is deposited by a chemical vapor deposition (CVD) process using a silicon oxide, a B dopant, and optionally a precursor for a P dopant. The silicon oxide precursor may be tetraethyl orthosilicate (TEOS), and suitable dopant precursors are triethyl borate (TEB) and triethyl phosphate (TEPO) for the B dopant and P dopant, respectively, although others may be used. Other potential features, including the composition, dimensions, and properties of the materials, are described hereinabove.

[0111] Accordingly, another aspect includes a semiconductor device including a 3D NAND structure having alternating oxide and nitride layers or polycrystalline silicon layers within a staircase pattern and a doped silicon oxide film disposed over the staircase pattern and annealed. The doped silicon oxide film disposed over the staircase pattern and annealed exhibits post-anneal expansion and substantially zero deposition-induced stress and stress shift. Other potential features of such a device, including the composition, dimensions, and properties of the materials, are described hereinabove with reference to the fabrication method. Device

[0112] Another aspect includes an apparatus for processing a semiconductor substrate by depositing a doped silicon oxide film on a patterned semiconductor substrate. The apparatus includes a reaction chamber containing the substrate, a plasma source coupled to the reaction chamber and configured to generate plasma outside the reaction chamber, one or more first gas inlets coupled to the reaction chamber, a second gas inlet coupled to the reaction chamber, and a controller including instructions for performing the following operations. The operations include depositing a doped silicon oxide film configured to expand during annealing at a temperature higher than the glass transition temperature of the film on the patterned semiconductor substrate disposed within the chamber, and annealing the doped silicon oxide film to a temperature higher than the film glass transition temperature. The instructions may further include that the doped silicon oxide film is deposited by a chemical vapor deposition (CVD)-based process using reactants for silicon oxide and carbon dopants. The CVD process may be a plasma-enhanced CVD (PECVD) process. The composition and processing conditions of the doped silicon oxide film may be adapted such that the film exhibits a post-anneal with substantially zero deposition stress and substantially zero stress shift. The following description provides some details of an apparatus, semiconductor chamber, and tool suitable for implementing the methods described herein and fabricating the described devices.

[0113] FIG. 13 schematically shows an embodiment of a deposition process chamber 1300 suitable for film deposition and processing as described herein. The chamber may function as a chemical vapor deposition (CVD) chamber, particularly a plasma-enhanced CVD (PECVD) chamber. Chamber 1300 has a process chamber body 1302 for maintaining a low-pressure environment. A plurality of process stations 1300 may be included in a common low-pressure process tool environment. For example, FIG. 14 shows an embodiment of a multi-station process tool 1400.

[0114] Referring again to FIG. 13, process station 1300 is in fluid communication with a reactant delivery system 1301 for delivering process gas to a distribution showerhead 1306. The reactant delivery system 1301 includes a mixing vessel 1304 for formulating and / or regulating the process gas for delivery to the showerhead 1306. The process gas can be, for example, a silicon oxide precursor gas (e.g., TEOS) or a second reactant gas (e.g., a dopant reactant). One or more mixing vessel inlet valves 1320 may control the introduction of the process gas into the mixing vessel 1304. Plasma may also be delivered to the showerhead 1306 or generated within the process station 1300. The reactant delivery system 1301 may be configured to deliver process gas for depositing a doped oxide film on a substrate provided within the process station 1300.

[0115] As an example, the embodiment of FIG. 13 includes a vaporization point 1303 for vaporizing a liquid reactant supplied to the mixing vessel 1304. In some embodiments, the vaporization point 1303 may be a heated vaporizer. The saturated reactant vapor produced by such a vaporizer may condense within the downstream delivery piping. Small particles can be generated by exposing the reactants to non-compatible gases that aggregate. These small particles can, for example, clog the piping, interfere with the operation of the valves, or contaminate the substrate. Some approaches to address these issues include removing residual reactants by purging and / or evacuating the delivery piping. However, purging the delivery piping can extend the process station cycle time and degrade the process station throughput. Thus, in some embodiments, the delivery piping downstream of the vaporization point 1303 may be heat traced. In some examples, the mixing vessel 1304 may also be heat traced. In one non-limiting example, the piping downstream of the vaporization point 1303 has a rising temperature profile ranging from approximately 100° C. to approximately 150° C. in the mixing vessel 1304.

[0116] In some embodiments, the liquid precursor or liquid reactant may be vaporized by a liquid injector. For example, the liquid injector may inject pulses of the liquid reactant into the carrier gas stream upstream of the mixing vessel. In one embodiment, the liquid injector may vaporize the reactant by flowing the liquid from a higher pressure to a lower pressure. In another example, the liquid injector may atomize the liquid into spray droplets and then vaporize it in a heated delivery pipe. Smaller droplets vaporize faster than larger droplets and can reduce the delay between injection of the liquid and complete vaporization. Faster vaporization can shorten the length of the pipe downstream of the vaporization point 1303. In one scenario, the liquid injector may be directly attached to the mixing vessel 1304. In another scenario, the liquid injector may be directly attached to the showerhead 1306.

[0117] In some examples, a liquid flow controller (LFC) upstream of the vaporization point 1303 may be provided to control the mass flow rate of the liquid for vaporization and delivery to the process station 1300. For example, the LFC may include a thermal mass flow meter (MFM) located downstream thereof. And the plunger valve of the LFC may be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller that is in electrical communication with the MFM. However, it may take more than one second to stabilize the liquid flow using feedback control. This may extend the time for introducing the liquid reactant. Thus, in some embodiments, the LFC may be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, this may be done by disabling the sensing tube and the PID controller of the LFC.

[0118] The showerhead 1306 distributes the process gas toward the substrate 1312. In the embodiment shown in FIG. 13, the substrate 1312 is shown positioned under the showerhead 1306 and placed on the pedestal 1308. The showerhead 1306 may have any suitable shape and may have any suitable number and arrangement of ports for distributing the process gas to the substrate 1312.

[0119] In some embodiments, pedestal 1308 may be raised and lowered to expose substrate 1312 to the volume between substrate 1312 and showerhead 1306. It will be appreciated that in some embodiments, the height of the pedestal may be programmatically adjusted by a suitable computer controller 1350.

[0120] In another scenario, adjusting the height of pedestal 1308 may allow for changing the plasma density during the plasma activation cycle in the process in embodiments where the plasma is ignited. At the end of the process step, removing substrate 1312 from pedestal 1308 may be enabled by lowering pedestal 1308 during the step of transporting another substrate.

[0121] In some embodiments, pedestal 1308 may be temperature controlled via heater 1310. In some embodiments, pedestal 1308 may be heated to a temperature of at least about 400 °C during deposition of a silicon nitride film as described in the disclosed embodiments, or in some embodiments, may be heated to less than about 300 °C, such as about 250 °C. In some embodiments, the pedestal is set to a temperature of about 400 °C to about 600 °C for doped oxide film deposition. In some embodiments, the pedestal is set to a temperature of about 500 °C to about 950 °C for annealing of the doped oxide film as described herein.

[0122] Further, in some embodiments, pressure control for process station 1300 may be provided by butterfly valve 1318. As shown in the embodiment of FIG. 13, butterfly valve 1318 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of process station 1300 may be adjusted by changing the flow rate of one or more gases introduced into process station 1300.

[0123] In some embodiments, the volume between the substrate 1312 and the showerhead 1306 may be varied by adjusting the position of the showerhead 1306 relative to the pedestal 1308. Further, it will be understood that the vertical position of the pedestal 1308 and / or the showerhead 1306 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 1308 may include a rotation axis for rotating the orientation of the substrate 1312. In some embodiments, it will be understood that one or more of these adjustment examples may be programmatically executed by one or more suitable computer controllers 1350.

[0124] In some embodiments where plasma can be used as described above, the showerhead 1306 and the pedestal 1308 are in electrical communication with a radio frequency (RF) power source 1314 and a matching network 1316 to supply power to the plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 1314 and the matching network 1316 may operate at any suitable power to generate a plasma having a desired composition of radical species. Suitable powers include those described above. Similarly, the RF power source 1314 may provide RF power at any suitable frequency. In some embodiments, the RF power source 1314 may be configured to control a high-frequency RF power source and a low-frequency RF power source independently of each other. Examples of low-frequency RF frequencies may include, but are not limited to, frequencies in the range of 0 kHz to 500 kHz. Examples of high-frequency RF frequencies may include, but are not limited to, frequencies of 1.8 MHz to 2.45 GHz, or higher than about 13.56 MHz, or higher than 27 MHz, or higher than 180 MHz, or higher than 60 MHz. It will be understood that plasma energy for surface reactions may be provided by discretely or continuously adjusting any suitable parameters.

[0125] In some embodiments, the plasma may be monitored in situ by one or more plasma monitors. In one scenario, the plasma power may be monitored by one or more voltage and current sensors (e.g., VI probes). In another scenario, the plasma density and / or the process gas concentration may be measured by one or more optical emission spectroscopy (OES) sensors. In some embodiments, one or more plasma parameters may be programmatically adjusted based on measurements from such in situ plasma monitors. For example, an OES sensor may be used in a feedback loop to provide programmatic control of the plasma power. It will be understood that in some embodiments, other monitors may be used to monitor the plasma and other process characteristics. Such monitors may include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.

[0126] In some embodiments, one or more hardware parameters of the process station 1300, including those discussed in detail below, may be programmatically adjusted by one or more computer controllers 1350.

[0127] In some embodiments, instructions for the controller 1350 may be provided via input / output control (IOC) sequence instructions. In one example, instructions for setting conditions for a process step may be included in the corresponding recipe step of a process recipe. Optionally, the process recipe steps may be sequentially arranged such that all instructions for a process step are executed simultaneously with that process step. In some embodiments, instructions for setting one or more reactor parameters may be included in the recipe steps. It will be understood that these recipe steps may be further subdivided and / or repeated in any suitable manner within the scope of the disclosed embodiments.

[0128] As described above, one or more process chambers may be included as stations within a multi-station process tool. FIG. 14 shows a schematic diagram of an embodiment of a multi-station process tool 1400. The multi-station process tool 1400 includes a process chamber 1414 having a plurality of process stations in a low-pressure environment. The process chamber 1414 may be configured to be maintained in a low-pressure environment such that a substrate can move between process stations without undergoing vacuum breakage and / or air exposure.

[0129] The tool 1400 further includes a load lock 1402 for loading and an unload lock 1404 for unloading. Either or both of the load lock 1402 for loading and the unload lock 1404 for unloading may include a remote plasma source. An atmospheric pressure robot 1406 is configured to move a wafer from a cassette loaded through a pod 1408 into the load lock 1402 via an atmospheric port 1410. The wafer is placed on a pedestal 1412 within the load lock 1402 by the robot 1406, the atmospheric port 1410 is closed, and the load lock is pumped down. If the load lock 1402 includes a remote plasma source, the wafer may be subjected to remote plasma treatment within the load lock prior to introduction into the process chamber 1414. Further, the wafer may also be heated within the load lock 1402, for example, thereby removing moisture and adsorbed gases. Next, a chamber transfer port 1416 to the process chamber 1414 is opened, and a wafer is placed on a pedestal of a first station shown in the processing reactor within the reactor by another robot (not shown). Although the embodiment shown in FIG. 14 includes load locks, it will be understood that in some embodiments, direct loading of wafers into the process stations may be provided.

[0130] In the embodiment shown in FIG. 14, the illustrated process chamber 1414 includes four process stations, numbered 1 to 4. Each process station may be configured to deposit TEOS-based silicon dioxide and silane-based silicon nitride. Each process station may be supplied by a common mixing vessel (e.g., 1304 of FIG. 13) for formulating and / or conditioning the process gas prior to delivery to each process station. Each process station shown in FIG. 14 includes a process station substrate holder (shown as 1418 for station 1) and a process gas delivery line inlet. In some embodiments, one or more process station substrate holders 1418 may be heated.

[0131] In some embodiments, each process station may have different purposes, or multiple purposes. For example, the process station may be switchable between an ultra-smooth PECVD process mode and a conventional PECVD mode or CVD mode. Additionally or alternatively, in some embodiments, the process chamber 1414 may include one or more pairs in which an ultra-smooth PECVD station and a conventional PECVD station are combined (e.g., a pair including an ultra-smooth PECVD SiO2 station and a conventional PECVD SiN station). In another example, the process station may be switchable between two or more types of films, whereby stacks of different types of films may be deposited within the same process chamber. Although the illustrated process chamber 1414 includes four stations, it will be understood that the process chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the process chamber may have five or more stations, while in other embodiments, the process chamber may have three or fewer stations.

[0132] FIG. 14 also shows an embodiment of a substrate handling system 1490 for transporting substrates within the process chamber 1414. In some embodiments, the substrate handling system 1490 may be configured to transport substrates between various process stations and / or between a process station and a load lock. It will be understood that any suitable substrate handling system may be employed. Non-limiting examples include substrate carousels and substrate handling robots.

[0133] The multi-station process tool 1400 also includes an embodiment of a system controller 1450 employed to control the process conditions and hardware state of the process tool 1400. For example, in some embodiments, the system controller 1450 may control the characteristics of the deposited film by controlling one or more process parameters during the PECVD film deposition stage. Characteristics of the deposited film may include its composition, thickness, and the like.

[0134] The system controller 1450 may include one or more memory devices 1456, one or more mass storage devices 1454, and one or more processors 1452. The processor 1452 may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, and the like.

[0135] In some embodiments, the system controller 1450 controls all of the operations of the process tool 1400. The system controller 1450 executes machine-readable system control software 1458 that is stored in the mass storage device 1454, loaded into the memory device 1456, and executed on the processor 1452. The system control software 1458 may include instructions for controlling the timing of a particular process performed by the process tool 1400, the gas mixture, the chamber and / or station pressure, the chamber and / or station temperature, the substrate temperature, the target power level, the RF power level, the position of the substrate pedestal, the chuck, and / or the susceptor, and other parameters. The system control software 1458 may be configured in any suitable manner. For example, the operation of process tool components for performing various process tool processes may be controlled by describing subroutines or control objects of the various process tool components. The system control software 1458 may be coded in any suitable computer-readable programming language.

[0136] In some embodiments, the system control software 1458 may include input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of a PECVD process may include one or more instructions executed by the system controller 1450. Instructions for setting process conditions for a PECVD process stage may be included in the corresponding PECVD recipe stage, and examples include the deposition of a thick doped silicon oxide film as described herein. In some embodiments, the PECVD recipe stages may be sequentially arranged such that all instructions for a PECVD process stage may be executed simultaneously with that process stage.

[0137] In some embodiments, other computer software and / or programs stored in the mass storage device 1454 and / or memory device 1456 associated with the system controller 1450 may be employed. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0138] The substrate positioning program may include program code for loading the substrate onto the process station substrate holder 1418 and for controlling the spacing between the substrate and other parts of the process tool 1400 for process tool components.

[0139] The process gas control program may include code for controlling the composition and flow rate of the gas and, optionally, for flowing the gas into one or more process stations prior to deposition to stabilize the pressure within the process station. The pressure control program may include code for controlling the pressure within the process station, for example, by adjusting a throttle valve in the exhaust system of the process station, the gas flow into the process station, and the like.

[0140] The heater control program may include code for controlling the current to a heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) to the substrate.

[0141] The plasma control program may include code for setting the RF power level applied to the process electrodes within one or more process stations.

[0142] In some embodiments, there may be a user interface associated with the system controller 1550. The user interface may include a display screen, a graphical software display of device and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0143] In some embodiments, the parameters adjusted by the system controller 1450 may be related to process conditions. Non-limiting examples include the composition and flow rate of process gases, temperature, pressure, plasma conditions (such as RF bias power level), pressure, temperature, etc. These parameters may be provided to the user in the form of a recipe and may be input using the user interface.

[0144] Signals for monitoring the process may be provided from various process tool sensors through the analog and / or digital input connections of the system controller 1450. Signals for controlling the process may be output on the analog and digital output connections of the process tool 1400. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. The process conditions may be maintained by using appropriately programmed feedback and control algorithms with the data from these sensors.

[0145] The system controller 1450 may provide program instructions for performing the deposition process described above. The program instructions may control various process parameters such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control the parameters for operating the in situ deposition of the film stack according to various embodiments described herein.

[0146] In some implementations, system controller 1450 is part of a system, and the system may be part of the above examples. Such a system may include semiconductor processing equipment including one or more process tools, one or more chambers, one or more processing platforms, and / or certain processing components (such as wafer pedestals, gas flow systems, etc.). These systems may be integrated with the electronic equipment to control the operation of the electronic equipment before, during, and after the processing of semiconductor wafers or substrates. The electronic equipment may be referred to as a "controller" that can control various components or sub-parts of one or more systems. System controller 1450 may be programmed to control any of the processes disclosed herein, depending on the processing conditions and / or the type of system. Such processes include, for example, delivery of process gases, temperature setting (e.g., heating and / or cooling), pressure setting, vacuum setting, power setting, radio frequency (RF) generator setting, RF matching circuit setting, frequency setting, flow rate setting, fluid delivery setting, position and motion setting, loading and unloading of wafers to and from the tool, and loading and unloading of wafers to and from other transfer tools and / or load locks connected or coupled to a particular system.

[0147] Generally, system controller 1450 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that, for example, receive commands, issue commands, control operations, enable cleaning operations, and enable endpoint measurements. The integrated circuits may include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions transmitted to system controller 1450 in the form of various individual settings (or program files), defining operating parameters for performing a particular process on a semiconductor wafer or for a semiconductor wafer, or for the system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to achieve one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0148] In some implementations, system controller 1450 may be part of a computer integrated with the system, coupled to the system, or otherwise network-connected to the system, or may be coupled to such a computer, or may be a combination thereof. For example, system controller 1450 may be within a “cloud” or may be all or part of a fab host computer system, thereby enabling remote access to wafer processing. By enabling remote access to the system, the computer can monitor the current progress of fabrication operations, verify the history of past fabrication operations, verify trends or performance criteria from multiple fabrication operations, change the parameters of the current process, set the process steps following the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide a process recipe to the system through a network that may include a local network or the Internet. The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, system controller 1450 receives instructions in the form of data that specify the parameters of each process step executed during one or more operations. It should be understood that the parameters may be specific to the type of process being executed and the type of tools configured to be coupled or controlled by system controller 1450. Thus, as described above, system controller 1450 may be distributed, such as by including one or more separate controllers network-connected to each other and working towards a common purpose such as the processes and controls described herein. Examples of controllers distributed for such a purpose include one or more integrated circuits on a chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) to collaboratively control the process on the chamber.

[0149] Exemplary systems include, but are not limited to, chemical vapor deposition (CVD / PECVD) chambers or modules, plasma etching chambers or modules, track chambers or modules, and any other semiconductor processing systems that may be associated with or used in the fabrication and / or manufacture of semiconductor wafers. The etching operations described herein, for example, for etching nitrides or oxides, may be performed in any suitable process chamber. In some embodiments, the substrate may be etched in a capacitively coupled confinement RF plasma reactor with adjustable gap used to perform the etching operations described herein.

[0150] As described above, depending on one or more process steps performed by the tool, the system controller 1450 may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, main computers, other controllers, or tools used for material transport that move the wafer container into and out of the tool position and / or load port within a semiconductor manufacturing factory.

[0151] In some embodiments, it will be appreciated that a low-pressure transfer chamber may be included within a multi-station process tool to facilitate transfer between multiple process chambers. For example, FIG. 15 schematically illustrates another embodiment of a multi-station process tool 1500. In the embodiment shown in FIG. 15, the multi-station process tool 1500 includes a plurality of process chambers 1514 including a plurality of process stations (numbered 1-4). The process chamber 1514 is coupled to a low-pressure transfer chamber 1504 that includes a robot 1506 configured to transfer substrates between the process chamber 1514 and the load lock 1519. An atmospheric substrate transfer module 1510 including an atmospheric robot 1512 is configured to facilitate transfer of substrates between the load lock 1519 and the pod 1508. Although not shown in FIG. 15, an embodiment of the multi-station process tool 1500 may include a suitable system controller, such as the embodiment of the system controller 1450 shown in and described with reference to FIG. 14. Conclusion

[0152] While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be made within the scope of the appended claims. Note that there are many alternative ways to implement the processes, systems, and apparatuses of this embodiment. Accordingly, this embodiment should be regarded as illustrative and not restrictive, and should not be limited to the details provided herein.

Claims

1. A plasma-excited chemical vapor deposition method of a carbon-doped silicon oxide film on a substrate, comprising: providing the substrate in a deposition chamber at a substrate temperature of less than about 700°C; generating a plasma of a process gas containing a silicon-containing gas source and a carrier gas and a carbon-containing gas source; bringing the substrate into contact with the plasma in the deposition chamber; depositing a thin film of carbon-doped silicon dioxide on the substrate; and the thin film having a Young's modulus of at least 70 GPa.

2. The method according to claim 1, wherein the silicon-containing gas source is SiH n R 1 4-n (I), SiH n (OR 2 ) 4-n (II), O(Si(R 3 3 )) 2 (III), or a gas of a compound having a composition formula of a combination thereof, each of R 1 , R 2 , and R 3 is independently an optionally substituted aliphatic, optionally substituted alkyl, optionally substituted heteroalkyl, optionally substituted aryl, optionally substituted heteroaryl, optionally substituted cyclil, or optionally substituted heterocyclil, and n is an integer from 0 to 4.

3. The method according to claim 1, wherein the silicon-containing gas source includes silane, tetramethylsilane, tetramethoxysilane, tetraethoxysilane, hexamethyldisilazane, hexamethyldisiloxane, or a combination thereof.

4. The method according to claim 3, wherein the silicon-containing gas source includes tetramethylsilane and silane.

5. The method according to claim 1, wherein the carbon-containing gas source includes carbon dioxide, carbon monoxide, methane, ethane, or a combination thereof.

6. The method according to claim 5, wherein the carbon-containing gas source further includes a carrier gas of argon, helium, hydrogen, nitrous oxide, nitrogen, or a combination thereof.

7. The method according to claim 1, wherein the carbon-doped silicon oxide film has a modulus of elasticity of at least 90 GPa.

8. The method according to claim 1, wherein the carbon-doped silicon oxide film has a carbon content of about 5% (atomic) or less.

9. The method according to claim 1, wherein the pressure in the deposition chamber is maintained at about 1 to about 8 Torr.

10. The method according to claim 1, wherein the substrate temperature is higher than about 400 °C and lower than about 650 °C.

11. The method according to claim 1, wherein the ratio of the carbon-containing gas source to the silicon-containing gas source is about 150:1 to about 10:

1.

12. The method according to claim 1, wherein the plasma is generated in situ or remotely.

13. The method according to claim 12, The method wherein the thin film has a thickness of less than 300 angstroms.

14. The method according to claim 12, wherein the thin film has a dielectric constant of about 4 to about 4.

5.

15. An apparatus for forming a carbon-doped silicon oxide film on a substrate, the apparatus comprising: a reaction chamber, a substrate support configured to support the substrate within the reaction chamber, one or more inlets for introducing reactants into the reaction chamber, one or more outlets for removing material from the reaction chamber, a plasma generator configured to send plasma into the reaction chamber, a controller having at least one processor and a memory, wherein the at least one processor and the memory are communicatively connected to each other, and the memory stores computer-executable instructions for controlling the at least one processor, the computer-executable instructions cause the at least one processor to (i) receive the substrate within the reaction chamber, (ii) flow a process gas containing a silicon-containing source into the reaction chamber, and (iii) generate the plasma from a carbon-containing gas source and send it into the reaction chamber to form the carbon-doped silicon oxide film on the substrate, wherein the carbon-doped silicon oxide film has (1) a Young's modulus of about 90 GPa or more, and (2) a dielectric constant of about 4 to about 4.

5.

16. The apparatus according to claim 15, wherein the carbon-doped silicon oxide film has a thickness of less than 300 angstroms. Claim 17 The apparatus according to claim 15, wherein the carbon-doped silicon oxide film has a carbon content of about 5% (atomic) or less.

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