Wiring Substrate and Method for Manufacturing the Same, Light-Emitting Substrate, and Display Device

Abstract

A wiring substrate, a method for manufacturing the same, a light-emitting substrate, and a display device. The wiring substrate (100) includes a base (101), a first conductive layer (102) located on the base and at least within a functional region (E), a second conductive layer (103) located on the first conductive layer and at least within a bonding region (B) and electrically connected to the first conductive layer, and a first insulating layer (105) located on a side of the second conductive layer away from the base and including a main body portion (1051) and an opening (1052). At least one of the first conductive layer and the second conductive layer includes a plurality of electrodes (1033) located within the bonding region and extending along a first direction (D1). The electrodes include a first end (P) adjacent to the functional region in the first direction. A projection of the main body portion of the first insulating layer onto the base at least partially overlaps a projection of the first end of each electrode onto the base.

Description

Technical Field

[0001] The present disclosure relates to the technical field of displays, and particularly to a wiring substrate, a light-emitting substrate including the wiring substrate, a display device, and a method for manufacturing the wiring substrate.

Background Art

[0002] Display devices are generally classified into two types: liquid crystal display devices and organic light-emitting diode display devices. Liquid crystal display devices are widely applied because they are thin, light, have excellent impact resistance, a wide viewing angle, and high contrast. A liquid crystal display device generally includes a display panel and a backlight light source, and the backlight light source is usually disposed on the non-display side of the display panel to provide light for the display operation of the display panel. Characteristics such as the contrast, brightness uniformity, and stability of a liquid crystal display device are related to the structure and performance of the backlight light source. In recent years, mini light-emitting diodes (Mini-LEDs) have attracted wide attention due to their excellent performance and are increasingly applied to backlight light sources.

Summary of the Invention

Means for Solving the Problems

[0003] According to one aspect of the present disclosure, a wiring substrate is provided. The wiring substrate includes a base including a functional region and a bonding region, a first conductive layer located on the base and at least within the functional region, a second conductive layer located on a side of the first conductive layer away from the base and at least within the functional region and electrically connected to the first conductive layer, and a first insulating layer located on a side of the second conductive layer away from the base and including a main body portion and an opening. At least one of the first conductive layer and the second conductive layer includes a plurality of electrodes located within the bonding region and extending along a first direction. Each of the plurality of electrodes includes a first end adjacent to the functional region in the first direction, and a positive projection of the main body portion of the first insulating layer on the base at least partially overlaps a positive projection of the first end of each electrode on the base.

[0004] In some embodiments, the wiring substrate further includes a second insulating layer located between the first conductive layer and the second conductive layer, and the second conductive layer contacts the first conductive layer through via holes in the second insulating layer.

[0005] In some embodiments, the second conductive layer includes a first portion and a second portion, the first portion is located within the functional region, the second portion is located within the bonding region, the second portion includes a plurality of first electrodes extending along the first direction, and each of the plurality of first electrodes includes the first end.

[0006] In some embodiments, the second conductive layer includes a first surface departing from the base, the distance between the portion of the first surface located at the first portion and the base is greater than the distance between the portion of the first surface located at the second portion and the base, and the orthographic projection of the opening of the first insulating layer on the base at least partially overlaps with the orthographic projection of the second portion on the base.

[0007] In some embodiments, the opening of the first insulating layer exposes the remaining portions of each first electrode except the first end.

[0008] In some embodiments, in the bonding region, the orthographic projection of the opening of the first insulating layer on the base does not overlap with the orthographic projection of the second insulating layer on the base.

[0009] In some embodiments, the first conductive layer is only located within the functional region, and the orthographic projection of the first conductive layer on the base partially overlaps with the orthographic projection of the first portion of the second conductive layer on the base.

[0010] In some embodiments, within the functional region, the first conductive layer includes a second surface facing the second conductive layer and a side surface connected to the second surface and facing the bonding region, and the second conductive layer directly contacts the side surface of the first conductive layer.

[0011] In some embodiments, the first conductive layer includes a third portion located within the bonding region. The third portion includes a plurality of second electrodes extending along the first direction. The plurality of first electrodes correspond one-to-one to the plurality of second electrodes, and the orthographic projection of each of the plurality of first electrodes on the base overlaps at least partially with the orthographic projection of a corresponding one of the plurality of second electrodes on the base. Each first electrode and the second electrode corresponding to the first electrode are electrically connected to form an electrode, and both the electrically connected first electrode and second electrode include the first end.

[0012] In some embodiments, the orthographic projection of the first ends of the first electrode and the second electrode on the base is within the orthographic projection of the main body portion of the first insulating layer on the base.

[0013] In some embodiments, the opening of the first insulating layer exposes the remaining portion of each first electrode except the first end.

[0014] In some embodiments, each second electrode includes a plurality of tooth-like structures extending along the first direction and arranged along a second direction, and the second direction intersects the first direction.

[0015] In some embodiments, each of the plurality of tooth-like structures includes a second surface facing the second conductive layer and a side surface connected to the second surface, and the first electrode is in direct contact with the side surface of the tooth-like structure.

[0016] In some embodiments, the bonding region includes a plurality of openings in the first insulating layer. The plurality of openings correspond one-to-one to the plurality of electrodes, and the orthographic projection of each of the plurality of openings on the base is within the orthographic projection of the first electrode of the electrode corresponding to the opening on the base. The electrode further includes a second end opposite to the first end, and the orthographic projection of the second end of the electrode on the base is within the orthographic projection of the main body portion of the first insulating layer on the base.

[0017] In some embodiments, in the bonding region, the first insulating layer includes a plurality of openings, the plurality of openings correspond one-to-one to the plurality of electrodes, and the orthographic projection of each of the plurality of openings on the base overlaps partially with the orthographic projection of the electrode corresponding to the opening on the base. The electrode further includes a second end on the side opposite to the first end, and a part of the second end is exposed by the opening corresponding to the electrode.

[0018] In some embodiments, the orthographic projection of the second insulating layer on the base does not overlap with the orthographic projections of the first electrode and the second electrode on the base, and the first electrode of each electrode is in direct contact with the second electrode.

[0019] In some embodiments, in the bonding region, the first insulating layer includes a plurality of openings, the plurality of openings correspond one-to-one to the plurality of electrodes, the orthographic projection of each of the plurality of openings on the base is within the orthographic projection of the first electrode of the electrode corresponding to the opening on the base, the electrode further includes a second end on the side opposite to the first end, and the orthographic projection of the second end of the electrode on the base is within the orthographic projection of the main body portion of the first insulating layer on the base.

[0020] In some embodiments, for each electrode, the orthographic projection of the first electrode on the base is within the orthographic projection of the second electrode on the base.

[0021] In some embodiments, the main body portion of the first insulating layer includes a plurality of sub-insulating portions that extend along the first direction and are spaced apart from each other in a second direction intersecting the first direction. The orthographic projections of two adjacent sub-insulating portions among the plurality of sub-insulating portions on the base overlap partially with the orthographic projection of the electrode on the base, and the orthographic projections of the first ends of the first electrode and the second electrode on the base overlap partially with the orthographic projections of the two adjacent sub-insulating portions on the base.

[0022] In some embodiments, the second conductive layer is disposed only within the functional region, and the first conductive layer includes a third portion disposed within the bonding region. The third portion includes a plurality of second electrodes extending along the first direction, and each of the plurality of second electrodes includes the first end.

[0023] In some embodiments, the second insulating layer includes a plurality of via holes. The plurality of via holes correspond one-to-one to the plurality of second electrodes, and the orthographic projection of each of the plurality of via holes on the base is within the orthographic projection of the second electrode corresponding to the via hole on the base.

[0024] In some embodiments, the main body of the first insulating layer includes a plurality of sub-insulating portions extending along the first direction and spaced apart from each other in a second direction intersecting the first direction. The orthographic projections of two adjacent sub-insulating portions among the plurality of sub-insulating portions on the base partially overlap with the orthographic projection of the second electrode on the base, respectively, and the orthographic projection of the first end of the second electrode on the base partially overlaps with the orthographic projections of the two adjacent sub-insulating portions on the base.

[0025] According to another aspect of the present disclosure, a light-emitting substrate is provided. The light-emitting substrate includes the wiring substrate according to any of the above embodiments, a plurality of light-emitting elements provided within the functional region, and a circuit board provided within the bonding region.

[0026] According to still another aspect of the present disclosure, a display device is provided. The display device includes the wiring substrate according to any of the above embodiments or the light-emitting substrate according to any of the above embodiments.

[0027] According to a further aspect of the present disclosure, there is provided a method for manufacturing a wiring substrate, the manufacturing method including the steps of: providing a base including a functional region and a bonding region; applying a first conductive film onto the base and patterning the first conductive film through a first mask to form a first conductive layer located at least within the functional region; applying a second conductive film on a side of the first conductive layer away from the base and patterning the second conductive film through a second mask to form a second conductive layer located at least within the functional region and electrically connected to the first conductive layer; applying a first insulating film on a side of the second conductive layer away from the base and patterning the first insulating film through a third mask to form a first insulating layer including a main body portion and an opening; wherein at least one of the first conductive layer and the second conductive layer includes a plurality of electrodes located within the bonding region and extending along a first direction, each of the plurality of electrodes includes a first end adjacent to the functional region in the first direction, and a positive projection of the main body portion of the first insulating layer on the base at least partially overlaps with a positive projection of the first end of each electrode on the base.

[0028] In some embodiments, after the step of forming the first conductive layer on the base, the method further includes the steps of: applying a second insulating film on a side of the first conductive layer away from the base and patterning the second insulating film through a fourth mask to form a second insulating layer; and forming the second conductive layer on a side of the second insulating layer away from the base.

[0029] To more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required to be used in the embodiments are briefly introduced below. Apparently, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings based on these drawings without creative efforts.

Brief Description of the Drawings

[0030]

Figure 1

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Mode for Carrying Out the Invention

[0031] Hereinafter, while combining the drawings in the embodiments of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the present disclosure.

[0032] FIG. 1 shows a wiring board 10 in the related art. The wiring board 10 includes structures such as a base 11, a first conductive layer 12, a first sub-insulating layer 141, a second sub-insulating layer 142, a second conductive layer 13, and an insulating layer 15. It is necessary to perform an antioxidant treatment on the surface of the region where the second conductive layer 13 is exposed away from the base 11. For example, it is processed by an electro-less nickel / immersion gold method to grow a desired nickel-gold layer 17 on the surface, thereby enhancing the oxidation resistance and / or connection reliability of the second conductive layer 13. Specifically, in the electro-less nickel / immersion gold process, first, pickling is performed on the wiring board 10, and then the wiring board 10 is placed in an activation solution containing Pd 2+ At this time, the metal (for example, Cu) in the region where the surface of the second conductive layer 13 is exposed reacts with Pd in the activation solution 2+ by a substitution reaction, and Cu 2+and Pd (palladium) are generated, and Pd adheres to the surface separated from the base 11 of the second conductive layer 13 to form a palladium layer. Then, the wiring board 10 is placed in a solution mainly composed of nickel sulfate, sodium hypophosphite (a reducing agent for reducing nickel ions to metallic nickel), and a complexing agent to generate a layer of nickel-phosphorus alloy layer on the surface of the pad. Since the nickel-phosphorus alloy layer is still oxidized and it is difficult and unreliable to weld with the oxidized nickel-phosphorus alloy layer and solder, finally, it is necessary to immerse the wiring board 10 in a gold ion-containing solution to form an immersion gold layer on the surface of the nickel-phosphorus alloy layer. The gold particles in the immersion gold layer can fill the gaps of the electroless nickel / immersion gold layer, and the oxidation probability of the nickel-phosphorus alloy layer can be reduced, thereby reducing the degree of oxidation of the exposed area of the second conductive layer 13. Thereby, the surface of the exposed area of the second conductive layer 13 has a nickel-gold layer 17 (including the above nickel-phosphorus alloy layer and immersion gold layer).

[0033] When the first sub-insulating layer 141 and the second sub-insulating layer 142 are continuous film layers without via holes within the region I surrounded by the dotted rectangular frame in FIG. 1, they can cover the surface of the first conductive layer 12 to prevent oxidation. In order to provide a good interface for forming the nickel-gold layer 17 on the surface of the second conductive layer 13, the insulating layer 15 is etched to form via holes 16 to expose the second conductive layer 13, and it is necessary to perform a certain degree of etching on the surface of the second conductive layer 13 away from the base 11. Since it is necessary to further etch the surface of the second conductive layer 13 away from the base 11, the etching time increases compared to the case where only the insulating layer 15 is etched. Although the thicknesses of the first sub-insulating layer 141 and the second sub-insulating layer 142 are usually thin, when the etching time increases, the first sub-insulating layer 141 and the second sub-insulating layer 142 are inevitably over-etched, thereby forming unnecessary via holes 19 in the first sub-insulating layer 141 and the second sub-insulating layer 142. Due to the via holes 16 in the insulating layer 15 and the unnecessary via holes 19 in the first sub-insulating layer 141 and the second sub-insulating layer 142, the surface of the first conductive layer 12 away from the base 11 is partially exposed, and the nickel-gold layer 18 grows abnormally at the position where the surface of the first conductive layer 12 is exposed. The abnormally grown nickel-gold layer 18 causes problems such as short circuits between film layers and damage to the surface flatness of the insulating layer 15, thereby significantly affecting the reliability of the wiring substrate 10.

[0034] Some embodiments of the present disclosure provide an improved wiring substrate that can solve the problem of abnormal growth of the nickel-gold layer, at least within the bonding region.

[0035] FIG. 2A shows a schematic plan view of a partial region of the wiring board 100, and FIG. 2B shows a cross-sectional view taken along the line AA' of FIG. 2A. As shown in FIGS. 2A and 2B, the wiring board 100 includes a base 101 including a functional region E and a bonding region B, a first conductive layer 102 located on the base 101 and at least within the functional region E, a second conductive layer 103 located on the side of the first conductive layer 102 away from the base 101 and at least within the functional region E and electrically connected to the first conductive layer 102, and a first insulating layer 105 located on the side of the second conductive layer 103 away from the base 101 and including a main body portion 1051 and an opening 1052. A plurality of electrodes 150 are arranged in the bonding region B. The plurality of electrodes 150 each extend along a first direction D1 and are provided at intervals along a second direction D2 intersecting the first direction D1. At least one of the first conductive layer 102 and the second conductive layer 103 includes the plurality of electrodes 150. Each of the plurality of electrodes 150 includes a first end P adjacent to the functional region E in the first direction D1. The orthographic projection of the main body portion 1051 of the first insulating layer 105 on the base 101 at least partially overlaps the orthographic projection of the first end P of each electrode 150 on the base 101. The region where the surface of the electrode 150 is exposed functions as a bonding electrode 107. It should be noted that the relative positional relationship of the first conductive layer 102, the second conductive layer 103, and the first insulating layer 105 described is applicable not only to the wiring board 100 but also to each wiring board described in other embodiments of the present disclosure, which will be described in detail later.

[0036] It should be noted that in this specification, the term "main body portion 1051 of the first insulating layer 105" refers to the physical part of the first insulating layer 105, which is composed of a suitable insulating material, and the term "opening portion 1052 of the first insulating layer 105" refers to the hollow via hole of the first insulating layer 105, and the first insulating layer 105 has no arbitrary physical material at the opening portion 1052. The main body portion 1051 and the opening portion 1052 constitute the first insulating layer 105. Also, the term "functional region" refers to the region for arranging the functional components (such as light-emitting elements) of the base 101, and the term "bonding region" refers to the region for arranging the electrodes 150 of the base 101. The bonding region is used for coupling to a circuit board. When the circuit board has a gold finger structure, the widths of the electrodes 150 in the bonding region in the second direction of each electrode are basically the same, for example, slightly larger than the width of the gold finger structure in the second direction.

[0037] The inventor of the present application has discovered that abnormal growth of electroless nickel / immersion gold is likely to occur at the first end P of the electrode 150 in the bonding region B. Therefore, in the embodiment of the present application, by at least partially overlapping the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the base 101 with the orthographic projection of the first end P of each electrode 150 on the base 101, the main body portion 1051 of the first insulating layer 105 can cover at least a part of the first end P of the electrode 150. In this way, even when the first insulating layer 105 is etched to form the opening portion 1052, the main body portion 1051 of the first insulating layer 105 has a shielding and protecting effect on the first end P of the electrode 150, so that the surface of the first end P of the electrode 150 is not exposed, thereby reducing and even avoiding the occurrence of abnormal growth of electroless nickel / immersion gold at the first end P of the electrode 150.

[0038] Specifically, referring to FIGS. 2A and 2B, the first conductive layer 102 of the wiring substrate 100 is disposed only within the functional region E rather than within the bonding region B. The second conductive layer 103 includes a first portion 1031 disposed within the functional region E and a second portion 1032 disposed within the bonding region B. The second portion 1032 of the second conductive layer 103 includes a plurality of first electrodes 1033 extending along the first direction D1, and the region where the surface of each first electrode 1033 is exposed functions as a bonding electrode 107. The first electrode 1033 includes a first end P. The orthographic projection of the base 101 of the first conductive layer 102 does not overlap with the orthographic projection of the base 101 of the first electrode 1033. In some embodiments, the length L1 of the first end P of the first electrode 1033 along the first direction D1 is 30 to 60 microns, and the length L2 of the first electrode 1033 along the first direction D1 is 1050 to 1100 microns. In some embodiments, the ratio of the length L1 to the length L2 is between 2% and 6%.

[0039] FIG. 2C shows a simplified schematic diagram of region II in FIG. 2A, showing only the relative positional relationship between the first conductive layer 102 and the second conductive layer 103. The first conductive layer 102 includes a drive voltage signal line VLED, a common voltage signal line 111 (shown in FIG. 4), and several other signal lines. The drive voltage signal line VLED and / or the common voltage signal line 111 extends substantially along the first direction D1. One end of the drive voltage signal line VLED and / or the common voltage signal line 111 extends to an arbitrary position away from the bonding region B of the functional region E of the wiring substrate 100, and the other end is connected to a plurality of first electrodes 1033 extending from the bonding region B toward the functional region E. The first conductive layer 102 shown in FIG. 2C can represent the drive voltage signal line VLED or the common voltage signal line 111, directly contacts the first portion 1031 of the second conductive layer 103 within the functional region E, and since the line width of the drive voltage signal line VLED or the common voltage signal line 111 is much larger than the line width of the first electrode 1033, the other end of the drive voltage signal line VLED or the common voltage signal line 111 may be electrically connected corresponding to the plurality of first electrodes 1033.

[0040] The inventor of the present application has found that in the related art, since the surface of the bonding electrode 107 is exposed within the bonding region B and there is a step between the position where the signal line in the first conductive layer 102 is connected to the electrode and the bonding electrode 107, the abnormal growth phenomenon of electroless nickel / immersion gold is likely to occur. However, in the embodiment of the present disclosure, since the first conductive layer 102 is disposed only within the functional region E rather than within the bonding region B, the abnormal growth of electroless nickel / immersion gold within the bonding region B is avoided on the driving voltage signal line VLED and the common voltage signal line 111 formed by the first conductive layer 102. As can be seen from FIGS. 2A to 2C, the orthographic projection of the base 101 of the first conductive layer 102 partially overlaps with the orthographic projection of the base 101 of the first portion 1031 of the second conductive layer 103, and the orthographic projection of the base 101 of the first conductive layer 102 does not overlap with the orthographic projection of the base 101 of the first electrode 1033 of the second portion 1032 of the second conductive layer 103. By disposing the first conductive layer 102 only within the functional region E rather than within the bonding region B, when the first insulating layer 105 is etched to form the opening 1052 located within the bonding region B, the occurrence of the abnormal growth phenomenon of the above-mentioned electroless nickel / immersion gold can be avoided regardless of whether the etching time increases.

[0041] In some embodiments, the wiring substrate 100 may further include a second insulating layer 104 located between the first conductive layer 102 and the second conductive layer 103. The first portion 1031 of the second conductive layer 103 is electrically connected to the first conductive layer 102 through a via hole 1043 in the second insulating layer 104. Since the second insulating layer 104 is disposed only in the functional region E rather than in the bonding region B, the orthographic projection of the base 101 of the second insulating layer 104 does not overlap with the orthographic projection of the base 101 of the first electrode 1033. When a plurality of stacked insulating layers are disposed in the bonding region B, the adhesion between the plurality of insulating layers is usually low, so that the film layer peeling phenomenon of the insulating layer is likely to occur. When the stacked thickness of the plurality of insulating layers exceeds a certain threshold value (for example, 6000 Å), the occurrence probability of such a peeling phenomenon will increase significantly. In order to avoid the occurrence of the film layer peeling problem in the bonding region B, in the light-emitting substrate 100, as shown in FIG. 2A, in the region between any two adjacent first electrodes 1033 among the plurality of first electrodes 1033, since the main body portion 1044 of the second insulating layer 104 is not provided, in the region between any two adjacent first electrodes 1033 among the plurality of first electrodes 1033, the orthographic projection of the base 101 of the main body portion 1051 of the first insulating layer 105 does not overlap with the orthographic projection of the base 101 of the main body portion 1044 of the second insulating layer 104. Thus, the overlap of the main body portion 1051 of the first insulating layer 105 and the main body portion 1044 of the second insulating layer 104 in the bonding region B can be reduced, thereby reducing and even avoiding the occurrence of the peeling phenomenon in the bonding region B between the first insulating layer 105 and the second insulating layer 104.

[0042] As shown in FIG. 2B, the second conductive layer 103 includes a first portion 1031 located within the functional region E and a second portion 1032 located within the bonding region B. The second conductive layer 103 includes a first surface that is separated from the base 101, and the first surface is stepped. Specifically, the portion of the first surface located at the first portion 1031 can be denoted as surface S11, the portion of the first surface located at the second portion 1032 can be denoted as surface S13, and the portion of the first surface located between surface S11 and surface S13 and connecting surface S11 and surface S13 can be denoted as surface S12. Since the surface S12 is an inclined surface, the distance d1 between the portion S11 located at the first portion 1031 of the first surface and the base 101 is greater than the distance d2 between the portion S13 located at the second portion 1032 of the first surface and the base 101. The main body portion 1051 of the first insulating layer 105 is attached to at least the portion located within the first ends P of the surfaces S11, S12, and the surfaces S13 of the respective first electrodes 1033, and can play a role of better covering and protecting the first portion 1031 of the second conductive layer 103 and the first ends P of the first electrodes 1033. The orthographic projection of the opening 1052 of the first insulating layer 105 on the base 101 at least partially overlaps the orthographic projection of the second portion 1032 on the base 101. In some embodiments, the orthographic projection of the opening 1052 of the first insulating layer 105 on the base 101 does not overlap the orthographic projection of the second insulating layer 104 on the base 101. The flexible printed circuit board may be bonded to the region excluding the first ends P of the first electrodes 1033, that is, the flexible printed circuit board is bonded and connected to the bonding electrodes.

[0043] In some embodiments, the first conductive layer 102 includes a second surface S21 facing the second conductive layer 103 and a side surface S22 connected to the second surface S21 and facing the bonding region B. The second insulating layer 104 covers a part of the second surface S21 of the first conductive layer 102 but does not cover the side surface S22 of the first conductive layer 102. The second conductive layer 103 is in direct contact with the side surface S22 of the first conductive layer 102 through a via hole 1043 in the second insulating layer 104. The second insulating layer 104 may be a single film layer or a laminate including a plurality of film layers. In one example, the second insulating layer 104 includes a first sub-insulating layer 1041 and a second sub-insulating layer 1042. In a direction perpendicular to the base 101, the thickness of the second insulating layer 104 is usually thinner than the thickness of the first conductive layer 102 (in one example, the thickness of the first conductive layer 102 in a direction perpendicular to the base 101 is 1.8 μm, the thickness of the first sub-insulating layer 1041 in a direction perpendicular to the base 101 is 0.24 μm, and the thickness of the second sub-insulating layer 1042 in a direction perpendicular to the base 101 is 0.15 μm). In the related art, the second insulating layer 104 needs to cover the side surface S22 of the first conductive layer 102, and there is a large step between the second surface S21 of the first conductive layer 102 and the surface of the underlying film layer. Therefore, the second insulating layer 104 is likely to be broken from the second surface S21 of the first conductive layer 102 to the position connected to the side surface S22. As a result, the second insulating layer 104 cannot completely cover and protect the first conductive layer 102. Also, after the second insulating layer 104 is broken, the subsequently formed second conductive layer 103 cannot be realized to be in good contact with the underlying film layer at the break position, and furthermore, the problem of the second conductive layer 103 falling off is caused. Further, after the second insulating layer 104 is broken, the surface of a partial region of the first conductive layer 102 is exposed, thereby oxidizing to generate an irregularly shaped metal oxide, reducing the consistency and flatness of the film layer of the first conductive layer 102. When the second conductive layer 103 is in direct contact with the region where the irregularly shaped oxide of the first conductive layer 102 is generated, the second conductive layer 103 is likely to bulge at this location, and furthermore, the problem of the second conductive layer 103 falling off is likely to be caused. Therefore, when the second insulating layer 104 is disposed on the side surface S22 of the first conductive layer 102, the phenomenon of the second conductive layer 103 falling off is likely to be caused.In FIG. 3A, it is shown that the second conductive layer 103 and the second insulating layer (PVX1-2) in the related art fall off the side surface of the first conductive layer (Cu1), and the second conductive layer (Cu2) and the first conductive layer (Cu1) fall off the side surface of the first conductive layer (Cu1). In FIG. 3B, in the related art, since there is a step in the first conductive layer 12, the first sub-insulating layer 141 or the second sub-insulating layer 142 is broken (Crack), and further, the first conductive layer 12 is oxidized at the corresponding position to generate an irregularly shaped (Tip) oxide, and finally, it is shown that the second conductive layer 13 bulges.

[0044] In the wiring board 100 provided by the embodiment of the present disclosure, the second insulating layer 104 does not cover the side surface S22 of the first conductive layer 102, and the second conductive layer 103 is in direct contact with the side surface S22 of the first conductive layer 102 through the via hole 1043 in the second insulating layer 104. In this way, the second insulating layer 104 is not broken, and thereby, the first electrode 1033 of the second conductive layer 103 does not cause film layer peeling from the second insulating layer 104 due to contact with the broken second insulating layer 104. Further, since the second insulating layer 104 is not broken, the side surface S22 of the first conductive layer 102 is not oxidized due to surface exposure to have an irregular surface shape, thereby the second conductive layer 103 does not bulge, and further, no film layer peeling problem occurs between the first electrode 1033 of the second conductive layer 103 and the first conductive layer 102.

[0045] In some embodiments, the first conductive layer 102 may be a laminate of MoNb / Cu / MoNb. In an alternative embodiment, the first conductive layer 102 may be a laminate of Mo / Cu / Mo. In some embodiments, the second conductive layer 103 may be a laminate of MoNb(300 Å) / Cu(6000 - 9000 Å) / MoNb(300 Å). In an alternative embodiment, the second conductive layer 103 may be a laminate of Mo(300 Å) / Cu(6000 - 9000 Å) / Mo(17 - 30 Å). The thickness of the first conductive layer 102 is usually greater than the thickness of the second conductive layer 103.

[0046] As shown in FIG. 2B, in some embodiments, the wiring substrate 100 may further include a buffer layer 106 located between the base 101 and the first conductive layer 102. The buffer layer 106 has a planarizing effect and can improve the adhesion between the first conductive layer 102 and the base 101.

[0047] In FIGS. 2A to 2C, the arrangement method in the bonding region B of the wiring substrate 100 is mainly shown. In order to enable the reader to more clearly understand the overall arrangement of the wiring substrate 100, in FIG. 4, the arrangement method in the functional region E of the wiring substrate 100 is shown as an example.

[0048] In the functional area of the wiring board 100, a group of pads to be bonded and connected to tens of thousands of electronic components is provided. Referring to FIG. 4, in the functional area E of the wiring board 100, it is located on the base 101 and includes a power supply pad Pwr and an output pad Out. Optionally, a first pad group 102 coupled to the micro drive chip 002, a power signal line 103 located on the same side of the base 101 as the first pad group 102 and coupled to the power supply pad Pwr, and a second pad group 104 located on the same side of the base 101 as the first pad group 102 and optionally coupled to each electronic component 003 respectively. The area of the second conductive layer 103 located in the functional area E and having its surface exposed constitutes the above-mentioned first pad group 102 and second pad group 104. Specifically, the first insulating layer 105 includes an opening 1052 in the functional area E, and the opening 1052 exposes a part of the area of the second conductive layer 103 to function as a pad. The first pad group 102 can realize the connection with the micro drive chip 002 by the reflow soldering process with the assistance of solder, and the second pad group 104 can realize the connection with the light-emitting element 003 by the reflow soldering process with the assistance of solder. The part of the second conductive layer 103 exposed by the opening 1052 in the bonding area B functions as a bonding electrode (for example, the part except the first end P of the first electrode 1033), and the bonding electrode realizes the bonding connection with the gold finger structure of the circuit board (for example, FPC) by the hot press process with the assistance of anisotropic conductive adhesive. In some embodiments, the base 101 includes a plurality of pad areas P, and each pad area P includes a plurality of cascaded first pad groups 102 and a plurality of second pad groups 104 respectively coupled to each first pad group 102. Optionally, within one pad area P, the plurality of cascaded first pad groups 102 are arranged in an array along the first direction D1 and / or the second direction D2, but are not limited thereto here. In FIG. 4, the case where the plurality of cascaded first pad groups 102 within one pad area P are arranged in a row is schematically illustrated as an example.In some embodiments, the power signal line 103 may be coupled to the power supply pads Pwr of a plurality of first pad groups 102 arranged along the first direction D1 in the pad region P and cascade-connected. In this way, the winding design of the power signal line 103 can be reduced, thereby reducing the resistance of the power signal line 103 and further reducing the loss of the pulse width modulation signal in the power signal line 103. In some embodiments, the wiring substrate 100 may further include a first connection lead 106. The power signal line 103 includes a plurality of sub-segments 103'. Two adjacent sub-segments 103' in the first direction D1 may be interconnected via the first connection lead 106 such that the same power signal line 103 supplies power to the power supply pads Pwr of a plurality of first pad groups 102 arranged along the first direction D1 and cascade-connected within the same pad region P. Optionally, the first connection lead 106 and the sub-segment 103' are of an integral structure. In some embodiments, the first pad group 102 further includes an address pad Di and a ground pad Gnd. The address pad Di and the power supply pad Pwr belonging to the same first pad group 102 are provided at intervals in the second direction D2, and are provided at intervals from the output pad Out in the first direction D1. The ground pad Gnd and the power supply pad Pwr are provided at intervals in the first direction D1 and are provided at intervals from the output pad Out in the second direction D2. Exemplarily, the output pad Out is located at the upper left corner of the first pad group 102, the address pad Di is located at the lower left corner of the first pad group 102, the ground pad Gnd is located at the upper right corner of the first pad group 102, and the power supply pad Pwr is located at the lower right corner of the first pad group 102. Each first pad group 102 may be coupled to a micro drive chip 002, and each second pad group 104 is coupled to a plurality of electronic components 003. In some embodiments, the address pad Di can receive an address signal to strobe the micro drive chip 002 of the corresponding address. The power supply pad Pwr can provide a first operating voltage and communication data to the micro drive chip 002, and the communication data can be used to control the emission luminance of the corresponding light-emitting element.The output pad Out can output a relay signal and a drive signal within different periods respectively. The relay signal is an address signal provided to the address pad Di in the next-stage first pad group 102, and the drive signal is a drive current, which is used to drive the light-emitting element coupled to the first pad group 102 where the output pad Out is located to emit light. The ground pad Gnd receives a common voltage signal. In some embodiments, in each first pad group 102, the arrangement of the power supply pad Pwr, the output pad Out, the ground pad Gnd, and the address pad Di is the same, so that the wiring path between the first pad groups 102 cascaded with each other within the same pad region P is simplified, and the occurrence of many windings is avoided.

[0049] In some embodiments, the wiring substrate 100 may further include an address signal line 108, and the address signal line 108 may be coupled to the address pads Di of the first pad group 102 in the first stage within the pad region P, whereby within each pad region P, the address signal provided by the address signal line 107 is received by the address pads Di of the first pad group 102 in the first stage. In some embodiments, the wiring substrate 100 may further include a cascade connection line 109, and the cascade connection line 109 is arranged to connect the output pad Out of the first pad group 102 in the n-th stage belonging to the same pad region P and the address pad Di of the first pad group 102 in the (n + 1)-th stage, where n is a positive integer, and the relay signal output by the output pad Out of the first pad group 102 in the n-th stage is provided to the address pad Di of the first pad group 102 in the (n + 1)-th stage via the cascade connection line 109. In some embodiments, the wiring substrate 100 may further include a feedback signal line 110, and the feedback signal line 110 is coupled to the output pad Out of the first pad group 102 in the final stage within the pad region P to form a circuit for transporting an address signal within the pad region P. In some embodiments, the wiring substrate 100 may further include a common voltage signal line 111, and the common voltage signal line 111 is coupled to the ground pads Gnd of all the first pad group 102 within the pad region P. In some embodiments, the wiring substrate 100 may further include a drive voltage signal line VLED for coupling to the electronic component 003.

[0050] Taking FIG. 4 as an example, within the functional region E of the wiring substrate, the first conductive layer 102 is arranged to implement the power supply signal line 103, the first connection lead line 106, the second connection lead line 107, the address signal line 108, the cascade connection line 109, the feedback signal line 110, the common voltage signal line 111, the drive voltage signal line VLED, the connection line connecting the first pad group and the second pad group, and the connection line (not shown) connecting the second pad group and the second pad group. In the manufacturing process, the same mask plate is used, and the first conductive layer 102 is patterned by a single patterning process to form these signal lines.

[0051] For better understanding, in some other embodiments, within the functional region E of the wiring substrate, the first conductive layer 102 is only arranged to realize the power signal line 103, the address signal line 108, the feedback signal line 110, the common voltage signal line 111, and the drive voltage signal line VLED, and the second conductive layer 103 is arranged to realize the first connection lead 106, the second connection lead 107, the cascade connection line 109, the connection line connecting the first pad group and the second pad group, and the connection line connecting the second pad group and the second pad group.

[0052] FIG. 5A shows a planar schematic diagram of a partial structure in the bonding region B and the functional region E of the wiring substrate 200, and FIG. 5B shows a cross-sectional view taken along the line BB' of FIG. 5A. For the sake of brevity, the description of the common points between the wiring substrate 200 and the wiring substrate 100 is omitted, and hereinafter, only the differences between the wiring substrate 200 and the wiring substrate 100 will be described.

[0053] The wiring board 200 shown in FIG. 5A includes structures such as a base 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, and a second insulating layer 104. Different from the wiring board 100, the first conductive layer 102 of the wiring board 200 is disposed within the functional region E and the bonding region B, and the first conductive layer 102 includes a third portion 1022 located within the bonding region B. The third portion 1022 includes a plurality of second electrodes 1023 that extend along the first direction D1 and are spaced apart along the second direction D2. The second conductive layer 103 includes a first portion 1031 located within the functional region E and a second portion 1032 located within the bonding region B. The second portion 1032 includes a plurality of first electrodes 1033 that extend along the first direction D1. The plurality of first electrodes 1033 correspond one-to-one with the plurality of second electrodes 1023. The orthographic projection of each first electrode 1033 on the base 101 is within the orthographic projection of the corresponding second electrode 1023 on the base 101. Each first electrode 1033 and the second electrode 1023 corresponding to the first electrode 1033 are electrically connected to form an electrode. The region where the surface of the electrode is exposed constitutes a bonding electrode 107. Both the first electrode 1033 and the second electrode 1023 include a first end P that approaches the functional region E. The orthographic projection of the first end P of the first electrode 1033 and the second electrode 1023 on the base 101 is within the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the base 101. In some embodiments, the opening 1052 of the first insulating layer 105 exposes the remaining region except for the first end P of each first electrode 1033.

[0054] The driving voltage signal line VLED and the common voltage signal line 111, which belong to the first conductive layer 102 and are located in the functional region E, are bonded and connected to the electrode at the first end P of the electrode. As described above, in the related art, since the surfaces of the driving voltage signal line VLED and the common voltage signal line 111 are exposed at the first end P, abnormal growth of electroless nickel / immersion gold is likely to occur. In the wiring board 200 provided by the embodiment of the present disclosure, the electrode includes a second electrode 1023 and a first electrode 1033 located on the side away from the base 101 of the second electrode 1023. The orthographic projection of the first end P of the electrode on the base 101 is within the orthographic projection of the main body 1051 of the first insulating layer 105 on the base 101, that is, at least the first electrode 1033 is separated between the main body 1051 of the first insulating layer 105 and the second electrode 1023. With such an arrangement method, when etching the first insulating layer 105, even if the etching time increases, at most the surface separated from the base 101 of the first electrode 1033 may be over-etched, but the first electrode 1033 having a large thickness (compared with the thickness of the second insulating layer 104) shields and protects the second electrode 1023, so that the first end P of the second electrode 1023 is not etched, and thereby the surface of the first end P of the second electrode 1023 is not exposed. Correspondingly, that is, the first ends of the second electrodes 1023 of each signal line are not exposed, and thereby abnormal growth of electroless nickel / immersion gold does not occur.

[0055] In some embodiments, the length L1 along the first direction D1 of the first end P of the first electrode 1033 is 30 to 60 microns, the length L2 along the first direction D1 of the first electrode 1033 is 1050 to 1100 microns, and the length L3 along the first direction D1 of the second electrode 1023 is 1066 to 1116 microns. In some embodiments, the ratio of the length L1 to the length L2 is between 2% and 6%, and the ratio of the length L1 to the length L3 is between 2% and 6%.

[0056] In some embodiments, the second insulating layer 104 includes a plurality of via holes 1043 within the bonding region B, the plurality of via holes 1043 corresponding one-to-one to the plurality of electrodes, and the orthographic projection of the base 101 of each via hole 1043 being within the orthographic projection of the base 101 of the corresponding first electrode 1033 of the electrode. As shown in FIG. 5B, in one example, the second insulating layer 104 extends along the first direction D1 to cover a part of the surface of the second electrode 1023 located in the bonding region B of the first conductive layer 102, and can cover and protect, for example, a part of the surface of the first end P approaching the functional region E of the second electrode 1023. For example, W1 is about 22 μm.

[0057] It should be noted that in FIG. 5A, only the structural schematic diagram of a partial region of the wiring substrate 200 is shown, and in this schematic diagram, the electrical connection relationship between the third part 1022 and various signal lines located in the functional region E is not shown. In fact, in the wiring substrate 200, the third part 1022 is electrically connected to various signal lines (such as a power signal line 103, an address signal line 108, a feedback signal line 110, a common voltage signal line 111, and a drive voltage signal line VLED) located in the first conductive layer 102.

[0058] FIG. 6A shows a plan schematic diagram of a partial structure in the bonding region B and the functional region E of the wiring substrate 300, and FIG. 6B shows a cross-sectional view taken along the line CC' of FIG. 6A. For the sake of brevity, the description of the common points between the wiring substrate 300 and the wiring substrate 100 is omitted, and hereinafter, only the differences between the wiring substrate 300 and the wiring substrate 100 will be described.

[0059] The wiring board 300 shown in FIG. 6A includes structures such as a base 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, and a second insulating layer 104. Different from the wiring board 100, the first conductive layer 102 of the wiring board 200 is disposed within the functional region E and the bonding region B. The first conductive layer 102 includes a third portion 1022 located within the bonding region B. The third portion 1022 includes a plurality of second electrodes 1023 extending along the first direction D1. The second conductive layer 103 includes a first portion 1031 located within the functional region E and a second portion 1032 located within the bonding region B. The second portion 1032 includes a plurality of first electrodes 1033 extending along the first direction D1. The plurality of first electrodes 1033 correspond one-to-one with the plurality of second electrodes 1023. The orthographic projection of each second electrode 1023 on the base 101 is within the orthographic projection of the corresponding first electrode 1033 on the base 101. Each first electrode 1033 and the second electrode 1023 corresponding to the first electrode 1033 are electrically connected to form an electrode. The region where the surface of the electrode is exposed constitutes a bonding electrode. Both the first electrode 1033 and the second electrode 1023 include a first end P approaching the functional region E. The orthographic projection of the first end P of the first electrode 1033 on the base 101 is within the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the base 101. With such an arrangement method, when etching the first insulating layer 105, even if the etching time increases, at most, only the surface separating from the base 101 of the first electrode 1033 may be over-etched. However, the first electrode 1033 has a greater thickness than the second insulating layer 104, and the first electrode 1033 can shield and protect the second electrode 1023 during the etching process. Therefore, the side surface S32 of the first end P of the second electrode 1023 is not etched, and thus the side surface S32 is not exposed. That is, the first end of each signal line's second electrode 1023 is not exposed, thereby preventing abnormal growth of electroless nickel / immersion gold.

[0060] As shown in FIG. 6A, each second electrode 1023 includes a plurality of tooth-shaped structures 1023A that extend along a first direction D1 and are arranged along a second direction D2 that intersects the first direction D1. Each second electrode 1023 further includes a connection structure 1023B arranged along the second direction D2, and the plurality of tooth-shaped structures 1023A belonging to the same signal line are interconnected via the connection structure 1023B, and the connection structure 1023B may have the same line width as the portion disposed within the functional region E of the signal line. Assuming that two metal layers have the same surface area, the surface roughness of the thicker one is also larger. When two metal layers are in direct contact, a lateral sliding shear force is likely to occur on the contact surface, and the adhesion between them becomes low, thereby causing a film layer peeling problem. In the wiring substrate 300 provided by the embodiments of the present disclosure, by designing the shape of the region in the thick second electrode 1023 that is in direct contact with the first electrode 1033 to be comb-shaped, the contact area between the second electrode 1023 and the first electrode 1033 can be increased, thereby reducing the sliding shear force between them, increasing the adhesion between the second electrode 1023 and the first electrode 1033, and avoiding the occurrence of a film layer peeling problem between the second electrode 1023 and the first electrode 1033.

[0061] Each tooth-shaped structure 1023A includes a second surface S31 facing the second conductive layer 103 and a side surface S32 connected to the second surface S31. The via hole 1043 of the second insulating layer 104 exposes at least the side surface S32 of each tooth-shaped structure 1023A. As a result, the first electrode 1033 is in direct contact with the side surface S32 of the tooth-shaped structure 1023A through the via hole 1043 in the second insulating layer 104. In other words, the second insulating layer 104 does not cover the side surface S32 of the tooth-shaped structure 1023A. With such an arrangement method, the second insulating layer 104 is not broken at the side surface S32 of the tooth-shaped structure 1023A. Thereby, the first electrode 1033 does not cause film layer peeling from the second insulating layer 104 due to contact with the broken second insulating layer 104. Furthermore, since the second insulating layer 104 is not broken at the side surface S32 of the tooth-shaped structure 1023A, the side surface S32 of the tooth-shaped structure 1023A is not exposed and oxidized to generate an oxide, whereby the first electrode 1033 does not bulge at this location, and furthermore, no film layer peeling problem occurs between the first electrode 1033 and the second electrode 1023.

[0062] As shown in FIGS. 6A and 6B, within the bonding region B, the first insulating layer 105 includes a plurality of openings 1052. The plurality of openings 1052 correspond one-to-one to the plurality of first electrodes 1033. The orthographic projection of the base 101 of each opening 1052 is within the orthographic projection of the base 101 of the first electrode 1033 corresponding to the opening 1052. Each first electrode 1033 further includes a second end Q opposite to the first end P. The orthographic projections of the first end P and the second end Q of each first electrode 1033 on the base 101 are both within the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the base 101. By making the area of the opening 1052 smaller than the area of the first electrode 1033, both the first end P and the second end Q of the first electrode 1033 are covered by the main body portion 1051 of the first insulating layer 105, thereby enhancing the corrosion resistance of the bonding electrode 107.

[0063] It should be noted that in FIG. 6A, only a structural schematic diagram of a partial region of the wiring substrate 300 is shown, and in this schematic diagram, the electrical connection relationship between the third part 1022 and various signal lines located in the functional region E is not shown. Actually, in the wiring substrate 300, the third part 1022 is electrically connected to various signal lines (such as a power supply signal line 103, an address signal line 108, a feedback signal line 110, a common voltage signal line 111, and a drive voltage signal line VLED) located in the first conductive layer 102.

[0064] FIG. 7A shows a planar schematic diagram of a partial structure in the bonding region B and the functional region E of the wiring substrate 400, and FIG. 7B shows a cross-sectional view taken along the line DD' of FIG. 7A. Except that the opening 1052 of the first insulating layer 105 is different from that of the wiring substrate 300, the structure of the wiring substrate 400 is basically the same as that of the wiring substrate 300. For the sake of brevity, hereinafter, only the differences between the wiring substrate 400 and the wiring substrate 300 will be described.

[0065] As shown in FIGS. 7A and 7B, within the bonding region B, the first insulating layer 105 includes a plurality of openings 1052, and the plurality of openings 1052 correspond one-to-one to a plurality of first electrodes 1033. The orthographic projection of the base 101 of each opening 1052 partially overlaps with the orthographic projection of the base 101 of the first electrode 1033 corresponding to the opening 1052. Each first electrode 1033 further includes a second end Q opposite to the first end P. The orthographic projection of the first end P of each first electrode 1033 on the base 101 is within the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the base 101, and the second end Q of each first electrode 1033 is exposed by the opening 1052. By such an arrangement method, the main body portion 1051 of the first insulating layer 105 does not have to be provided at the second end Q of the first electrode 1033, thereby effectively reducing the problem of film layer peeling due to the presence of the first insulating layer 105.

[0066] It should be noted that in FIG. 7A, only a structural schematic diagram of a partial region of the wiring substrate 400 is shown, and in this schematic diagram, the electrical connection relationship between the third part 1022 and various signal lines located in the functional region E is not shown. Actually, in the wiring substrate 400, the third part 1022 is electrically connected to various signal lines (for example, a power supply signal line 103, an address signal line 108, a feedback signal line 110, a common voltage signal line 111, and a drive voltage signal line VLED) located in the first conductive layer 102.

[0067] FIG. 8A shows a plan schematic diagram of a partial structure in the bonding region B and the functional region E of the wiring substrate 500, and FIG. 8B shows a cross-sectional view taken along the line EE' of FIG. 8A. For the sake of brevity, the description of the common points between the wiring substrate 500 and the wiring substrate 100 is omitted, and hereinafter, only the differences between the wiring substrate 500 and the wiring substrate 100 will be described.

[0068] The wiring board 500 shown in FIG. 8A includes structures such as a base 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, and a second insulating layer 104. Different from the wiring board 100, the first conductive layer 102 of the wiring board 500 is disposed within the functional region E and the bonding region B, and the first conductive layer 102 includes a third portion 1022 located within the bonding region B. The third portion 1022 includes a plurality of second electrodes 1023 extending along the first direction D1. The second conductive layer 103 includes a first portion 1031 located within the functional region E and a second portion 1032 located within the bonding region B. The second portion 1032 includes a plurality of first electrodes 1033 extending along the first direction D1. The plurality of first electrodes 1033 correspond one-to-one with the plurality of second electrodes 1023. The orthographic projection of each first electrode 1033 on the base 101 is within the orthographic projection of the corresponding second electrode 1023 on the base 101. Each first electrode 1033 and the second electrode 1023 corresponding to the first electrode 1033 constitute an electrode, and the region where the surface of the electrode is exposed constitutes a bonding electrode 107. The electrode includes a first end P approaching the functional region E. The orthographic projection of the first end P of the electrode on the base 101 is within the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the base 101. With such an arrangement method, when etching the first insulating layer 105, even if the etching time increases, at most, only the surface separating from the base 101 of the first electrode 1033 may be over-etched. However, the thickness of the first electrode 1033 is greater than the thickness of the second insulating layer 104, and the first electrode 1033 has the effect of shielding and protecting the second electrode 1023. Therefore, the first end P of the second electrode 1023 is not etched, and thereby the first end P of the second electrode 1023 is not exposed. That is, the first ends of the second electrodes 1023 of each signal line are not exposed, and thereby abnormal growth of electroless nickel / immersion gold does not occur.

[0069] It should be noted that in FIG. 8A, only a structural schematic diagram of a partial region of the wiring substrate 500 is shown, and in this schematic diagram, the electrical connection relationship between the third part 1022 and various signal lines located in the functional region E is not shown. Actually, in the wiring substrate 500, the third part 1022 is electrically connected to various signal lines (such as the power supply signal line 103, the address signal line 108, the feedback signal line 110, the common voltage signal line 111, and the drive voltage signal line VLED) located in the first conductive layer 102. Also, since the second insulating layer 104 is disposed only within the functional region E rather than within the bonding region B, the orthographic projection of the base 101 of the second insulating layer 104 does not overlap with the orthographic projections of the bases 101 of the first electrode 1033 and the second electrode 1023, and the first electrode 1033 and the second electrode 1023 that constitute each electrode are in direct contact. By not providing the second insulating layer 104 within the bonding region B, the problem of film layer peeling due to the superposition of a plurality of insulating layers within the bonding region B can be effectively reduced.

[0070] Within the bonding region B, the first insulating layer 105 includes a plurality of openings 1052, the plurality of openings 1052 correspond one-to-one to a plurality of electrodes, and the orthographic projection of the base 101 of each opening 1052 is within the orthographic projection of the base 101 of the electrode corresponding to the opening 1052. The electrode composed of each first electrode 1033 and the second electrode 1023 corresponding to the first electrode 1033 further includes a second end Q on the side opposite to the first end P, and the orthographic projections of the first end P and the second end Q of each electrode on the base 101 are both within the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the base 101. As shown in FIG. 8B, in one example, the overlapping width W2 along the second direction D2 between the main body portion 1051 of the first insulating layer 105 and the first electrode 1033 is about 30 μm. By making the area of the opening 1052 smaller than the area of the first electrode 1033, both the first end P and the second end Q of the electrode are covered by the main body portion 1051 of the first insulating layer 105, thereby enhancing the corrosion resistance of the electrode.

[0071] FIG. 9A shows a schematic plan view of a partial structure in the bonding region B and the functional region E of the wiring substrate 600, and FIG. 9B shows a cross-sectional view taken along the line FF' of FIG. 9A. For the sake of brevity, the description of the common points between the wiring substrate 600 and the wiring substrate 100 is omitted, and hereinafter, only the differences between the wiring substrate 600 and the wiring substrate 100 will be described.

[0072] The wiring substrate 600 shown in FIG. 9A includes structures such as a base 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, and a second insulating layer 104. Different from the wiring substrate 100, the first conductive layer 102 of the wiring substrate 600 is disposed within the functional region E and the bonding region B, and the first conductive layer 102 includes a third portion 1022 located within the bonding region B. The third portion 1022 includes a plurality of second electrodes 1023 extending along the first direction D1. It should be noted that in FIG. 9A, only a schematic structural view of a partial region of the wiring substrate 600 is shown, and in this schematic view, the electrical connection relationship between the third portion 1022 and various signal lines located in the functional region E is not shown. In fact, in the wiring substrate 600, the third portion 1022 is electrically connected to various signal lines (such as a power supply signal line 103, an address signal line 108, a feedback signal line 110, a common voltage signal line 111, and a drive voltage signal line VLED) located in the first conductive layer 102.

[0073] The second conductive layer 103 includes a first portion 1031 located within the functional region E and a second portion 1032 located within the bonding region B. The second portion 1032 includes a plurality of first electrodes 1033 extending along the first direction D1. The plurality of first electrodes 1033 correspond one-to-one to the plurality of second electrodes 1023. The orthographic projection of each first electrode 1033 on the base 101 is within the orthographic projection of the corresponding second electrode 1023 on the base 101. Each first electrode 1033 and the second electrode 1023 corresponding to the first electrode 1033 constitute an electrode, and the region where the surface of the electrode is exposed constitutes a bonding electrode 107. The electrode includes a first end P approaching the functional region E.

[0074] As shown in FIG. 9A, the main body portion 1051 of the first insulating layer 105 includes a plurality of sub-insulating portions 1054 that extend along the first direction D1 and are spaced apart from each other in the second direction D2. The orthographic projections of the bases 101 of two adjacent sub-insulating portions 1054 among the plurality of sub-insulating portions 1054 partially overlap with the orthographic projection of the base 101 of the electrode respectively. Each electrode is provided with a space between each other in the second direction D2, and each sub-insulating portion 1054 is also provided with a space between each other in the second direction D2. Since each electrode corresponds to two sub-insulating portions 1054, there is inevitably no sub-insulating portion 1054 in a part of the interval region between two adjacent electrodes. As shown in the region W in FIG. 9A, there is no sub-insulating portion 1054 in the region W. By not disposing the first insulating layer 105 in the region W, the laminated thickness of the insulating layer in the region W can be reduced, thereby reducing the problem of film layer peeling due to the laminated thickness of the insulating layer being too large.

[0075] As shown in FIG. 9A, the orthographic projection of the base 101 of the first end P of the electrode formed by each first electrode 1033 and the second electrode 1023 corresponding to the first electrode 1033 partially overlaps with the orthographic projection of the bases 101 of the two adjacent sub-insulating portions 1054. Therefore, the two adjacent sub-insulating portions 1054 can protect the first end P of the electrode to a certain extent. When etching the first insulating layer 105, even if the etching time increases, at most, only the surface separated from the base 101 of the first electrode 1033 may be over-etched. However, the thickness of the electrode is larger than the thickness of the second insulating layer 104, and the first electrode 1033 can shield and protect the second electrode 1023 at least partially. Therefore, the first end P of the second electrode 1023 is basically not etched, and thereby the surface of the first end P of the second electrode 1023 is basically not exposed. That is, the first end P of the second electrode 1023 of each signal line is basically not exposed, and thereby the abnormal growth of electroless nickel / immersion gold basically does not occur.

[0076] As shown in FIG. 9B, in one example, the overlapping width W3 along the second direction D2 between the sub-insulating portion 1054 of the first insulating layer 105 and the first electrode 1033 is about 15 μm, thereby protecting the two side edges extending along the first direction D1 of the first electrode 1033. The overlapping width W4 along the second direction D2 between the second insulating layer 104 and the second electrode 1023 is about 22 μm, thereby protecting the two side edges extending along the first direction D1 of the second electrode 1023.

[0077] FIG. 10A shows a plan schematic view of a partial structure in the wiring substrate 700 bonding region B and the functional region E, and FIG. 10B shows a cross-sectional view taken along the line GG' of FIG. 10A. For the sake of brevity, the description of the common points between the wiring substrate 700 and the wiring substrate 100 is omitted, and hereinafter, only the differences between the wiring substrate 700 and the wiring substrate 100 will be described.

[0078] The wiring board 700 shown in FIG. 10A includes structures such as a base 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, and a second insulating layer 104. Different from the wiring board 100, the first conductive layer 102 of the wiring board 700 is disposed within the functional region E and the bonding region B. The first conductive layer 102 includes a third portion 1022 located within the bonding region B. The third portion 1022 includes a plurality of second electrodes 1023 extending along the first direction D1. The region where the surface of the second electrode 1023 is exposed constitutes the bonding electrode 107. The second electrode 1023 includes a first end P approaching the functional region E. In some embodiments, the second conductive layer 103 of the wiring board 700 is disposed only within the functional region E and not within the bonding region B. In an alternative embodiment, the second conductive layer 103 is not provided within either the functional region E or the bonding region B, that is, the wiring board 700 includes only the first conductive layer 102 and does not include the second conductive layer 103. It should be noted that in FIG. 10A, only a structural schematic diagram of a partial region of the wiring board 700 is shown, and the electrical connection relationship between the third portion 1022 and various signal lines located in the functional region E is not shown in the schematic diagram. In actuality, in the wiring board 700, the third portion 1022 is electrically connected to various signal lines (such as a power supply signal line 103, an address signal line 108, a feedback signal line 110, a common voltage signal line 111, and a drive voltage signal line VLED) located in the first conductive layer 102.

[0079] The second insulating layer 104 includes a plurality of via holes 1043. The plurality of via holes 1043 correspond one-to-one to the plurality of second electrodes 1023. The orthographic projection of each of the plurality of via holes 1043 on the base 101 is within the orthographic projection of the second electrode 1023 corresponding to the via hole 1043 on the base 101.

[0080] As shown in FIG. 10A, the main body portion 1051 of the first insulating layer 105 includes a plurality of sub-insulating portions 1054 that extend along the first direction D1 and are spaced apart from each other in the second direction D2. The orthographic projections of the bases 101 of two adjacent sub-insulating portions 1054 among the plurality of sub-insulating portions 1054 partially overlap with the orthographic projection of the base 101 of the second electrode 1023 respectively, and the orthographic projection of the first end P of the second electrode 1023 on the base 101 partially overlaps with the orthographic projections of the bases 101 of two adjacent sub-insulating portions 1054. Each second electrode 1023 is provided at intervals in the second direction D2, and each sub-insulating portion 1054 is also provided at intervals in the second direction D2. Since each second electrode 1023 corresponds to two sub-insulating portions 1054, there is inevitably no sub-insulating portion 1054 in a part of the interval region between two adjacent second electrodes 1023. As shown in the region W in FIG. 10A, there is no sub-insulating portion 1054 in the region W. By not disposing the first insulating layer 105 in the region W, the laminated thickness of the insulating layer in the region W can be reduced, thereby reducing the problem of film layer peeling due to the laminated thickness of the insulating layer being too large.

[0081] In one example, the overlapping width along the second direction D2 between the sub-insulating portion 1054 of the first insulating layer 105 and the second electrode 1023 is about 22 μm, thereby protecting two side edges of the second electrode 1023 extending along the first direction D1. The overlapping width along the second direction D2 between the second insulating layer 104 and the second electrode 1023 is about 15 - 20 μm, thereby protecting two side edges of the second electrode 1023 extending along the first direction D1.

[0082] FIG. 11A shows a plan schematic view of the bonding region B of the wiring substrate 800, and FIG. 11B shows a cross-sectional view taken along the line HH' of FIG. 11A. For the sake of brevity, the description of the common points between the wiring substrate 800 and the wiring substrate 100 is omitted, and hereinafter, only the differences between the wiring substrate 800 and the wiring substrate 100 will be described.

[0083] The wiring board 800 shown in FIG. 11A includes structures such as a base 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, and a second insulating layer 104. Different from the wiring board 100, the first insulating layer 105 and the second insulating layer 104 of the wiring board 800 are disposed only within the functional region E rather than within the bonding region B, and the first conductive layer 102 is disposed within both the functional region E and the bonding region B. The first conductive layer 102 includes a third portion 1022 located within the bonding region B, and the third portion 1022 includes a plurality of second electrodes 1023 extending along the first direction D1, and the second electrodes 1023 constitute the bonding electrodes 107. In some embodiments, the second conductive layer 103 of the wiring board 800 is disposed only within the functional region E rather than within the bonding region B. In an alternative embodiment, the second conductive layer 103 is not provided within either the functional region E or the bonding region B, that is, the wiring board 800 includes only the first conductive layer 102 and does not include the second conductive layer 103. It should be noted that in FIG. 11A, only a structural schematic diagram of a partial region of the wiring board 800 is shown, and in this schematic diagram, the electrical connection relationship between the third portion 1022 and various signal lines located within the functional region E is not shown. In reality, in the wiring board 800, the third portion 1022 is electrically connected to various signal lines (such as a power signal line 103, an address signal line 108, a feedback signal line 110, a common voltage signal line 111, and a drive voltage signal line VLED) located within the first conductive layer 102.

[0084] By etching and removing all portions of the first insulating layer 105 and the second insulating layer 104 located within the bonding region B, the lamination situation within the bonding region B of the plurality of insulating layers can be avoided, thereby preventing the problem of film layer peeling due to the lamination of the plurality of insulating layers.

[0085] It should be noted that, for the wiring boards 200 shown in FIGS. 5A to 5B, the wiring boards 300 shown in FIGS. 6A to 6B, the wiring boards 400 shown in FIGS. 7A to 7B, the wiring boards 500 shown in FIGS. 8A to 8B, the wiring boards 600 shown in FIGS. 9A to 9B, the wiring boards 700 shown in FIGS. 10A to 10B, and the wiring boards 800 shown in FIGS. 11A to 11B, the first conductive layer 102 of these wiring boards includes a plurality of types of signal lines located in the functional region E, such as power signal lines 103, address signal lines 108, feedback signal lines 110, common voltage signal lines 111, and drive voltage signal lines VLED. These signal lines usually have different line widths along the second direction D2. For example, the line widths of the common voltage signal line 111 and the drive voltage signal line VLED along the second direction D2 are usually larger than the line width of any of the power signal line 103, the address signal line 108, and the feedback signal line 110 along the second direction D2. For signal lines with different line widths, the number of the second electrodes 1023 included in each third portion 1022 is different. For example, when the line width of a certain signal line (such as the power signal line 103, the address signal line 108, or the feedback signal line 110) in the functional region E along the second direction D2 is equal to the line width of the electrode 150 in the bonding region along the second direction D2, the third portion 1022 of the signal line in the bonding region B includes only one second electrode 1023. When the line width of a certain signal line (such as the drive voltage signal line VLED and the common voltage signal line 111) in the functional region E along the second direction D2 is much larger than the line width of the electrode 150 in the bonding region along the second direction D2, the third portion 1022 of the signal line in the bonding region B includes a plurality of second electrodes 1023. In some embodiments, a plurality of second electrodes 1023 belonging to the same signal line are connected to each other at the first end.

[0086] According to another aspect of the present disclosure, a light-emitting substrate is provided. FIG. 12 shows a block diagram of the light-emitting substrate 900, which includes the wiring substrate described in any of the above embodiments, a plurality of light-emitting elements provided in the functional region E, and a circuit board provided in the bonding region B. In some embodiments, each light-emitting element may be a light-emitting diode (LED), a mini light-emitting diode (Mini LED), or a micro light-emitting diode (Micro LED). By using Mini LED as the light-emitting element, high-dynamic range (HDR) display can be realized. When such a light-emitting substrate is applied to a display device, the contrast of the display device can be significantly improved. The circuit board may be, for example, a flexible printed circuit (FPC). One end of the FPC is connected to a printed circuit board assembly (PCBA), and the other end of the FPC is connected to the bonding electrode 107 of the light-emitting substrate 900, for example, via a chip on film (COF). The control signal of the IC of the PCBA is transmitted to the bonding electrode 107 via the FPC. One end of a plurality of signal lines of the light-emitting substrate 900 is bonded to the bonding electrode 107, and the other end is electrically connected to the light-emitting element. Therefore, the control signal can be transmitted to the light-emitting element via the signal line to control the light-emitting element to emit light.

[0087] The light-emitting substrate 900 provided by the embodiments of the present disclosure can have basically the same technical effects as the wiring substrate described in the above embodiments. Therefore, for the sake of brevity, the technical effects of the light-emitting substrate 900 will not be repeatedly described here.

[0088] According to yet another aspect of the present disclosure, a display device is provided. FIG. 13 shows a block diagram of the display device 1000, and the display device 1000 includes the wiring substrate or the light-emitting substrate described in any of the above embodiments. In some embodiments, the display device 1000 may be a liquid crystal display device, including a liquid crystal panel and a backlight light source provided on the non-display side of the liquid crystal panel. The backlight light source includes the wiring substrate described in any of the above embodiments and may be used, for example, to achieve HDR dimming for display operations. The liquid crystal display device can have more uniform backlight luminance and better display contrast. The display device 1000 may be any suitable display device and includes, but is not limited to, any product or component having a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and an e-book.

[0089] Since the display device 1000 can have basically the same technical effects as the wiring substrate described in each of the above embodiments, for the sake of brevity, the technical effects of the display device 1000 will not be repeatedly described here.

[0090] According to a further aspect of the present disclosure, a method for manufacturing a wiring substrate is provided. FIG. 14 shows a flowchart of the method 1100, and the method 1100 can be applied to the wiring substrate described in any of the above embodiments. The method 1100 may include the following steps S1101 to S1104.

[0091] S1101: Provide a base 101 including a functional region E and a bonding region B.

[0092] The base 101 may be a flexible or rigid material, specifically, it may be a PEN resin, a silica gel resin, a polyimide, glass, quartz, plastic, etc., and the embodiments of the present disclosure do not limit the material of the base 101.

[0093] S1102. Apply a first conductive film on the base 101, pattern the first conductive film through a first mask to form a first conductive layer 102, and the first conductive layer 102 is located at least within the functional region E.

[0094] Apply the first conductive film on the base 101 by magnetron sputtering method or electroplating method, and form the first conductive layer 102 by patterning the first conductive film using the first mask. The first conductive layer 102 may include the above drive voltage signal line, address selection signal line, power signal line, data drive signal line, common voltage signal line, feedback signal line, and a selectable second electrode 1023. In one example, the first conductive layer 102 may be a laminate of MoNb / Cu / MoNb. In an alternative embodiment, the first conductive layer 102 may be a laminate of Mo / Cu / Mo.

[0095] S1103. Apply a second conductive film on the side of the first conductive layer 102 away from the base 101, pattern the second conductive film through a second mask to form a second conductive layer 103, and the second conductive layer 103 is located at least within the functional region B and is electrically connected to the first conductive layer 102.

[0096] A second conductive film is applied to the side of the base 101 of the first conductive layer 102 away from the base 101 by a magnetron sputtering method or an electroplating method, and the second conductive layer 103 is formed by patterning the second conductive film using a second mask. The second conductive layer 103 may include the first pad group 102, the second pad group 104, and a selectable first electrode 1033. The first pad group 102 may be used for attaching the micro drive chip 002, and the second pad group 104 may be used for attaching the electronic component 003. In one example, the second conductive layer 103 may be formed by a process of first forming a MoNb layer with a thickness of about 300 Å on the side of the base 101 of the first conductive layer 102 away from the base 101, then forming a Cu layer with a thickness of about 6000 - 9000 Å on the MoNb layer, and finally forming a MoNb layer with a thickness of about 300 Å on the Cu layer. In an alternative example, the second conductive layer 103 may be formed by a process of first forming a Mo layer with a thickness of about 300 Å on the side of the base 101 of the first conductive layer 102 away from the base 101, then forming a Cu layer with a thickness of about 6000 - 9000 Å on the Mo layer, and finally forming a Mo layer with a thickness of about 17 - 30 Å on the Cu layer.

[0097] S1104. A first insulating film is applied to the side of the base 101 of the second conductive layer 103 away from the base 101, and the first insulating film is patterned through a third mask to form a first insulating layer 105 including a main body portion 1051 and an opening portion 1052. At least one of the first conductive layer 102 and the second conductive layer 103 includes a plurality of electrodes located within the bonding region B and extending along the first direction D1. Each of the plurality of electrodes includes a first end P adjacent to the functional region E in the first direction D1. The orthographic projection of the main body portion 1051 of the first insulating layer 105 on the base 101 at least partially overlaps with the orthographic projection of the first end P of each electrode on the base 101.

[0098] The first insulating layer 105 can be formed on the side of the base 101 of the second conductive layer 103 away from the base 101 by a magnetron sputtering method. By at least partially overlapping the orthographic projection of the main body 1051 of the first insulating layer 105 on the base 101 with the orthographic projection of the first end P of each electrode on the base 101, abnormal growth of the electro-less nickel / immersion gold on the signal line of the first end P can be prevented. The material of the first insulating layer 105 may be an organic material, an inorganic material, or a combination of an organic material and an inorganic material. The first insulating layer 105 may be a single film layer or may include a plurality of film layers.

[0099] In some embodiments, after the step of forming the first conductive layer 102 and before the step of forming the second conductive layer 103, a second insulating film may be coated on the side of the first conductive layer 102 away from the base 101 by a magnetron sputtering method, and the step of patterning the second insulating film through a fourth mask to form the second insulating layer 104 may be further included. The material of the second insulating layer 104 may be an organic material, an inorganic material, or a combination of an organic material and an inorganic material. The second insulating layer 104 may be a single film layer or may include a plurality of film layers. In one example, the second insulating layer 104 includes a first sub-insulating layer 1041 and a second sub-insulating layer 1042.

[0100] In an embodiment where the second insulating layer 104 includes a first sub-insulating layer 1041 and a second sub-insulating layer 1042, an OC (Over Coating) layer can also be formed between the first sub-insulating layer 1041 and the second sub-insulating layer 1042 through a fifth mask, and the OC layer may be a negative photoresist made of an organic material. The thickness of the OC layer is greater than the thicknesses of the first insulating layer 105 and the second insulating layer 104 and is usually disposed only in the functional region E. In one example, the thickness of the OC layer is 3 to 4 microns. The thick OC layer can enclose the particles between the first conductive layer 102 and the second conductive layer 103 and prevent the particles from piercing the first conductive layer 102 and the second conductive layer 103 to cause a short circuit between the two. Also, the OC layer can act as a planarization layer.

[0101] In some embodiments, before the step of forming the first conductive layer 102, the method may further include a step of forming a buffer layer 106 on the base 101, for example, by a magnetron sputtering method. The buffer layer 106 may be used to reduce the stress on the base 101 when manufacturing the subsequent first conductive layer 102 and second conductive layer 103, thereby avoiding the bending deformation of the base 101. The buffer layer 106 can also avoid the adverse effects of impurities in the base 101 on the conductive performance of the subsequently formed first conductive layer 102 and second conductive layer 103. The buffer layer 112 may be any suitable material, for example, SiN, SiO, or SiON.

[0102] The method 1100 can manufacture a wiring board using fewer mask plates (for example, five mask plates). Compared with the related art which requires at least seven mask plates to manufacture a wiring board, the method 1100 provided by the embodiments of the present disclosure can reduce the number of required mask plates, simplify the process, and reduce the production cost. Other technical effects achieved by the method 1100 can be referred to the technical effects of the wiring board described in each of the above embodiments. For the sake of brevity, they will not be described repeatedly here.

[0103] As can be understood, terms such as first, second, and third can be used in this specification to describe various elements, members, regions, layers, and / or parts. However, these elements, members, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, member, region, layer, or part from another region, layer, or part. Therefore, the above-mentioned first element, member, region, layer, or part may be referred to as the second element, member, region, layer, or part without departing from the teachings of the present disclosure.

[0104] Spatial relative terms such as "row", "column", "below...", "above...", "left", and "right" may be used in this specification to facilitate the description of the relationship between one element or feature and another (some) element or feature as shown in the figures. As understood, these spatial relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. For example, if the device in the figure is turned over, an element described as "below another element or feature" will be oriented "above the other element or feature". Thus, the exemplary term "below..." can encompass both the above and below orientations of.... The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used in this specification are interpreted accordingly. Also, as further understood, when a layer is described as "between two layers", it may be the only layer between the two layers, or one or more intermediate layers may exist.

[0105] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used in this specification, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further understood, the terms "comprising" and / or "including", when used in this specification, specify the presence of the said features, wholes, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items. In the description of this specification, the descriptions of reference terms such as "one embodiment" and "another embodiment" mean that the specific features, structures, materials or characteristics described in combination with the embodiments are included in at least one embodiment of the disclosure. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. And the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. Also, where not conflicting, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples.

[0106] As will be understood, when an element or layer is described as being "on another element or layer", "connected to another element or layer", "coupled to another element or layer", or "adjacent to another element or layer", it may be directly on another element or layer, directly connected to another element or layer, directly coupled to another element or layer, or directly adjacent to another element or layer, or intervening elements or layers may be present. Conversely, when an element is described as being "directly on another element or layer", "directly connected to another element or layer", "directly coupled to another element or layer", "directly adjacent to another element or layer", there are no intervening elements or layers. However, in any case, "on..." or "directly on..." should not be construed as requiring that one layer completely cover the underlying layer.

[0107] In this specification, embodiments of the present disclosure are described with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As a result, for example, variations from the illustrated shapes should be expected as a result of manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be construed as being limited to the specific shapes of the regions illustrated herein, but should include, for example, shape deviations resulting from manufacturing. Accordingly, the regions shown in the figures are essentially schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the present disclosure.

[0108] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Further, as will be understood, those terms as defined in commonly used dictionaries should be construed to have a meaning consistent with the meaning in the context of the relevant art and / or this specification, and should not be construed in an idealized or overly formal sense unless expressly so defined herein.

[0109] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in the present disclosure should be included within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the described patent claims.

Claims

1. A wiring board, including a base including a functional region and a bonding region, a first conductive layer located on the base and at least within the functional region, a second conductive layer located on a side of the first conductive layer away from the base and at least within the functional region, and electrically connected to the first conductive layer, and a first insulating layer located on a side of the second conductive layer away from the base and including a main body portion and an opening, at least one of the first conductive layer and the second conductive layer includes a plurality of electrodes located within the bonding region and extending along a first direction, each of the plurality of electrodes includes a first end adjacent to the functional region in the first direction, and a normal projection of the main body portion of the first insulating layer on the base at least partially overlaps a normal projection of the first end of each electrode on the base. The wiring board.

2. Further including a second insulating layer located between the first conductive layer and the second conductive layer, and the second conductive layer contacts the first conductive layer through a via hole in the second insulating layer. The wiring board according to claim 1.

3. The second conductive layer includes a first portion and a second portion. The first portion is located within the functional region, the second portion is located within the bonding region, the second portion includes a plurality of first electrodes extending along the first direction, and each of the plurality of first electrodes includes the first end. The wiring board according to claim 2.

4. The second conductive layer includes a first surface away from the base, a distance between a portion of the first surface located in the first portion and the base is greater than a distance between a portion of the first surface located in the second portion and the base, and a normal projection of the opening of the first insulating layer on the base at least partially overlaps a normal projection of the second portion on the base. The wiring board according to claim 3.

5. The opening of the first insulating layer exposes the remaining portions of the first ends of the respective first electrodes, the wiring substrate according to claim 4.

6. In the bonding region, a front projection of the opening of the first insulating layer on the base does not overlap with a front projection of the second insulating layer on the base, the wiring substrate according to claim 5.

7. The first conductive layer is located only within the functional region, and a front projection of the first conductive layer on the base partially overlaps with a front projection of the first portion of the second conductive layer on the base, the wiring substrate according to any one of claims 3 to 6.

8. In the functional region, the first conductive layer includes a second surface facing the second conductive layer and a side surface connected to the second surface and facing the bonding region, and the second conductive layer is in direct contact with the side surface of the first conductive layer, the wiring substrate according to claim 7.

9. The first conductive layer includes a third portion located within the bonding region, the third portion includes a plurality of second electrodes extending along the first direction, the plurality of first electrodes correspond to the plurality of second electrodes one-to-one, and a front projection of each of the plurality of first electrodes on the base at least partially overlaps with a front projection of a corresponding one of the plurality of second electrodes on the base, Each first electrode and the second electrode corresponding to the first electrode are electrically connected to form the electrode, and both the electrically connected first electrode and second electrode include the first end, the wiring substrate according to claim 3.

10. A front projection of the first ends of the first electrode and the second electrode on the base is within a front projection of the main body portion of the first insulating layer on the base, the wiring substrate according to claim 9.

11. The opening of the first insulating layer exposes the remaining portions of the first ends of the respective first electrodes, the wiring substrate according to claim 10.

12. Each second electrode includes a plurality of tooth-shaped structures extending along the first direction and arranged along the second direction, and the second direction intersects the first direction. The wiring substrate according to claim 10.

13. Each of the plurality of tooth-shaped structures includes a second surface facing the second conductive layer and a side surface connected to the second surface, and the first electrode is in direct contact with the side surface of the tooth-shaped structure. The wiring substrate according to claim 12.

14. In the bonding region, the first insulating layer includes a plurality of openings, the plurality of openings correspond to the plurality of electrodes one-to-one, and the orthographic projection of each of the plurality of openings on the base is within the orthographic projection of the first electrode corresponding to the opening on the base. The electrode further includes a second end opposite to the first end, and the orthographic projection of the second end of the electrode on the base is within the orthographic projection of the main body of the first insulating layer on the base. The wiring substrate according to claim 12 or 13.

15. In the bonding region, the first insulating layer includes a plurality of openings, the plurality of openings correspond to the plurality of electrodes one-to-one, and the orthographic projection of each of the plurality of openings on the base partially overlaps the orthographic projection of the electrode corresponding to the opening on the base. The electrode further includes a second end opposite to the first end, and a part of the second end is exposed by the opening corresponding to the electrode. The wiring substrate according to claim 12 or 13.

16. The orthographic projection of the second insulating layer on the base does not overlap the orthographic projections of the first electrode and the second electrode on the base, and the first electrode of each electrode is in direct contact with the second electrode. The wiring substrate according to claim 10.

17. In the bonding region, the first insulating layer includes a plurality of openings, the plurality of openings correspond to the plurality of electrodes one-to-one, and the orthographic projection of each of the plurality of openings on the base is within the orthographic projection of the first electrode corresponding to the opening on the base. The electrode further includes a second end on a side opposite to the first end, and a positive projection of the second end of the electrode on the base is within a positive projection of the main body portion of the first insulating layer on the base. The wiring substrate according to claim 16.

18. For each electrode, a positive projection of the first electrode on the base is within a positive projection of the second electrode on the base. The wiring substrate according to claim 9.

19. The main body portion of the first insulating layer includes a plurality of sub-insulating portions that extend along the first direction and are spaced apart from each other in a second direction intersecting the first direction. Positive projections of two adjacent sub-insulating portions among the plurality of sub-insulating portions on the base partially overlap with a positive projection of the electrode on the base, respectively. Positive projections of the first ends of the first electrode and the second electrode on the base partially overlap with positive projections of the two adjacent sub-insulating portions on the base. The wiring substrate according to claim 18.

20. The second conductive layer is disposed only within the functional region, and the first conductive layer includes a third portion disposed within the bonding region. The third portion includes a plurality of second electrodes extending along the first direction, and each of the plurality of second electrodes includes the first end. The wiring substrate according to claim 2.

21. The second insulating layer includes a plurality of via holes. The plurality of via holes correspond one-to-one to the plurality of second electrodes, and a positive projection of each of the plurality of via holes on the base is within a positive projection of the second electrode corresponding to the via hole on the base. The wiring substrate according to claim 20.

22. The main body of the first insulating layer includes a plurality of sub-insulating portions that extend along the first direction and are spaced apart from each other in a second direction intersecting the first direction. The orthographic projections of two adjacent sub-insulating portions among the plurality of sub-insulating portions on the base partially overlap the orthographic projection of the second electrode on the base, respectively. The orthographic projection of the first end of the second electrode on the base partially overlaps the orthographic projections of the two adjacent sub-insulating portions on the base. The wiring board according to claim 21.

23. A light-emitting substrate, comprising the wiring board according to any one of claims 1 to 22, a plurality of light-emitting elements provided in the functional region, and a circuit board provided in the bonding region.

24. A display device, comprising the wiring board according to any one of claims 1 to 22 or the light-emitting substrate according to claim 23.

25. A method for manufacturing a wiring board, providing a base including a functional region and a bonding region; applying a first conductive film on the base and patterning the first conductive film through a first mask to form a first conductive layer located at least within the functional region; applying a second conductive film on a side of the first conductive layer away from the base and patterning the second conductive film through a second mask to form a second conductive layer located at least within the functional region and electrically connected to the first conductive layer; applying a first insulating film on a side of the second conductive layer away from the base and patterning the first insulating film through a third mask to form a first insulating layer including a main body portion and an opening. At least one of the first conductive layer and the second conductive layer includes a plurality of electrodes located within the bonding region and extending along a first direction, each of the plurality of electrodes includes a first end adjacent to the functional region in the first direction, and a front projection of the main body portion of the first insulating layer on the base at least partially overlaps with a front projection of the first end of each electrode, a method for manufacturing a wiring substrate.

26. After the step of forming the first conductive layer on the base, applying a second insulating film on a side of the first conductive layer away from the base, and patterning the second insulating film through a fourth mask to form a second insulating layer; and forming the second conductive layer on a side of the second insulating layer away from the base, the method according to claim 25, further comprising.

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