One-Time Programmable (ROTP) NVM

Abstract

In one embodiment, the method comprises receiving a plurality of redundant bit addresses and a first program bit address associated with a first transistor-based memory cell, wherein each of the plurality of redundant bit addresses is associated with a respective transistor-based memory cell; providing a programming pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell; reading redundant bit values from transistor-based memory cells associated with the plurality of redundant bit addresses; determining a majority bit value based on the first bit value and the redundant bit values when one of the first bit value and the redundant bit values does not match the first write value; and asserting a flag signal when the majority bit value does not match the first write value.

Description

Technical Field

[0001] This application claims the benefit of U.S. Patent Application No. 17 / 937,012, filed Sep. 30, 2022, which claims the benefit of U.S. Provisional Application No. 63 / 349,227, titled "Fuse Replacement by Real One Time Programing (ROTP) NVM," filed Jun. 6, 2022, and these applications are incorporated herein by reference.

[0002] The present disclosure generally relates to electronic systems and methods, and in particular embodiments, to one-time programmable (OTP) non-volatile memory (NVM).

Background Art

[0003] One-time programmable (OTP) memory is commonly used in integrated circuits (ICs) to store immutable data. OTP memory is a type of memory that is writable but not erasable. OTP memory may be implemented as OTP by decision or as OTP by design.

[0004] OTP memory implemented as OTP by decision can perform an erase operation by design, but the erase operation is prevented by software. Thus, OTP memory implemented as OTP by decision may be programmed and erased during testing, and the erase operation may be disabled during normal operation.

[0005] OTP memory implemented as OTP by design (also referred to as real OTP or ROTP) is OTP memory that cannot perform an erase operation by design. An example of ROTP is a fuse array.

[0006] Secure systems, such as secure microcontrollers, typically require a ROTP array, for example, to store confidential data. A conventional method for implementing such a ROTP array is to use a fuse array. For example, a secure system may include an OTP array that includes a fuse array, and each fuse of the fuse array corresponds to a bit of the OTP array.

[0007] A common fuse for implementing a fuse array is a so-called polyfuse. Polyfuses are typically manufactured using a conductive trace across two terminals. The programming operation is performed by injecting a high current into the polyfuse, which causes the conductive trace to melt and the two terminals to become non-conductive. By checking whether the polyfuse is conductive or non-conductive, it is possible to determine whether the bit stored in the polyfuse is a logical 1 (e.g., short) or a logical 0 (e.g., open).

[0008] Once the polyfuse becomes non-conductive, the operation cannot be reversed (the non-conductive trace cannot be converted to a conductive trace). Therefore, after programming the polyfuse, an erase operation is not possible. Summary of the Invention Means for Solving the Problems

[0009] According to one embodiment, a method of operating a memory includes receiving a first program bit address, where the first program bit address is associated with a first plurality of redundant bit addresses, the first program bit address is associated with a first transistor-based memory cell, and each of the first plurality of redundant bit addresses is associated with a respective transistor-based memory cell; providing a programming pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell via a first bit line; reading redundant bit values from transistor-based memory cells associated with the first plurality of redundant bit addresses via respective bit lines; determining a majority bit value based on the first bit value and one of the redundant bit values when one of the first bit value and the redundant bit values does not match the first write value; and asserting a flag signal indicating a failure in programming the first program bit address to the first write value when the majority bit value does not match the first write value.According to one embodiment, a circuit includes a plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell including first and second bit line terminals coupled to associated bit lines of a plurality of bit lines, and a gate terminal coupled to an associated word line of a plurality of word lines, each word line of the plurality of word lines being coupled to the gate terminals of the transistor-based memory cells of an associated row; a controller configured to: provide a programming pulse to a first word line coupled to a first transistor-based memory cell among the plurality of transistor-based memory cells to write a first write value to the first transistor-based memory cell; cause the first bit value to be read from the first transistor-based memory cell via a first bit line; cause a redundant bit value to be read from a redundant transistor-based memory cell among the plurality of transistor-based memory cells, the redundant transistor-based memory cell storing the same value as the first transistor-based memory cell; determine a majority bit value based on the first bit value and the redundant bit value read from the redundant transistor-based memory cell when one of the first bit value and the redundant bit value does not match the first write value; and assert a flag signal indicating a failure in programming the first transistor-based memory cell to the first write value when the majority bit value does not match the first write value.

[0010] According to one embodiment, the non-volatile memory is a one-time programmable (OTP) sector including a first plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell of the first plurality of transistor-based memory cells including first and second bit line terminals coupled to associated bit lines of a first plurality of bit lines and a gate terminal coupled to an associated word line of a first plurality of word lines; and a non-OTP sector including a second plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell of the second plurality of transistor-based memory cells including first and second bit line terminals coupled to associated bit lines of a second plurality of bit lines and a gate terminal coupled to an associated word line of a second plurality of word lines, wherein the second plurality of word lines are configured to receive a first positive voltage during a read mode, a second positive voltage during a write mode, and a first negative voltage during an erase mode, the first plurality of word lines are configured to receive a third positive voltage during a read mode and a fourth positive voltage during a write mode, the first plurality of word lines are designed not to receive a negative voltage in any mode, and the transistor-based memory cells of the OTP sector and the transistor-based memory cells of the non-OTP sector are of the same type.

[0011] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0012]

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DETAILED DESCRIPTION OF THE INVENTION

[0013] Corresponding numerals and symbols in different figures generally refer to corresponding parts, unless otherwise indicated. The drawings are drawn to clearly show relevant aspects of the preferred embodiments and are not necessarily drawn to scale.

[0014] The configuration and usage of the disclosed embodiments will be described in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific situations. The specific embodiments described are merely illustrative of specific ways to construct and use the present invention and do not limit the scope of the present invention.

[0015] The following description sets forth various specific details in order to provide a thorough understanding of some illustrative embodiments by way of explanation. Embodiments may be obtained without one or more of the specific details, or by using other methods, components, materials, and the like. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure different aspects of the embodiments. References herein to "an embodiment" indicate that a particular configuration, structure, or feature described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" and the like that may appear in different places in this specification are not necessarily all referring to the same embodiment. Furthermore, the particular configurations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0016] Embodiments of the present invention are described in the context of a large NVM including non-OTP bits, for example, as part of a secure system such as a secure microcontroller or a secure stand-alone memory (including, for example, an OTP portion and a non-OTP portion), such as a secure SoC, implemented in an OTP array based on NOR-based multi-bit memory cells. Embodiments of the present invention may be implemented in other types of transistor-based memory cells, such as NAND-based memory cells and / or single-bit memory cells. Some embodiments may be implemented as a stand-alone OTP memory. Some embodiments may be implemented in a non-secure IC.

[0017] The physical size of the fuse, such as a polyfuse, is relatively large (e.g., about 10 μm 2) Some manufacturing node technologies may not include the fuse cell design.

[0018] In one embodiment of the present invention, the OTP array is implemented with transistor-based memory cells, such as NOR memory cells. Data immutability is achieved in the OTP array by preventing (e.g., by design) the application of an erase pulse (e.g., physically preventing the application of a negative voltage to the gate of the memory cell). Implementing the OTP array using transistor-based memory cells may advantageously result in a small OTP implementation (e.g., more than 1000 times smaller than a fuse array of similar size), and may advantageously enable manufacturing node technologies that lack a design for a fuse cell to implement the OTP array.

[0019] FIG. 1 shows a portion of a transistor-based (non-OTP) memory cell array 100 according to one embodiment of the present invention. The memory cell array 100 includes a plurality of non-volatile memory cells 102 arranged in rows and columns. As shown in FIG. 1, each memory cell 102 has two conductive terminals each coupled to a respective bit line BL and a control terminal coupled to a word line WL. In some embodiments, such as embodiments where the memory cell 102 is implemented as a multi-bit memory cell, the two bit lines (e.g., BL i and BL i+1 ) coupled to the terminals of the memory cell 102 may operate as a drain line and a source line, respectively, during a read operation and as a source line and a drain line, respectively, during a program operation. Thus, in some embodiments, each bit line BL may function as a source line or a drain line depending on the operating mode, as well as depending on which cell 102 and, in some embodiments, which bit within the cell 102 is being read / written (e.g., to the left or right of the bit line BL). In other embodiments, such as some embodiments where the memory cell 102 is implemented as a single-bit memory cell, the two bit lines (e.g., BL i and BL i+1may operate as a source line and a drain line, respectively, regardless of the operation mode (e.g., during reading or writing).

[0020] The following description refers to cell 102 having a control terminal coupled to word line WL j a left terminal coupled to bit line BL i and a right terminal coupled to bit line BL i+1 i、j During a read operation, the gate of memory cell 102 may be biased at a positive voltage (e.g., 5V) (e.g., using the associated word line WL

[0021] ), the bit line BL of memory cell 102 j may be biased at a small positive voltage (e.g., 1.5V), and the bit line BL i+1 may be biased at a low voltage such as ground. In another embodiment, during a read operation, the bias voltages of bit lines BL i may be reversed. To determine the value stored in memory cell 102, a sense amplifier (not shown) coupled to each bit line BL compares, in a known manner, the current flowing through each bit line BL with a current threshold, and a current lower than the threshold corresponds to a first state or a programmed state (e.g., the assigned logic 0), and a current higher than the threshold corresponds to a second state or an erased state (e.g., the assigned logic 1). In an alternative embodiment, the assigned logic values ("0" and "1") may be reversed. i and BL i+1

[0022] In some embodiments, for example, to mitigate aging resulting from multiple programming of memory cell 102, the current threshold is adaptively changed to track changes in aging.

[0023] During a program (write) operation, the gate of memory cell 102 is at a high positive voltage (e.g., 9V) (e.g., using the associated word line WL jmay be biased (using), and bit line BL i may be biased at a high positive voltage (e.g., 5V), and bit line BL i+1 may be at a low voltage (e.g., between 0V and 2V). Under such conditions, memory cell 102 is programmed to a first state (e.g., logic 0). In another embodiment, bit lines BL i and BL i+1 may have their voltage biases reversed to program memory cell 102 to the first state.

[0024] During the erase operation, the gate of memory cell 102 may be biased at a negative voltage (e.g., -7V) (using, for example, the associated word line WL j ), and bit line BL i may be biased at a positive voltage (e.g., 5V), and bit line BL i+1 may be left floating or biased at a weak positive voltage (e.g., less than 5V). Under such conditions, memory cell 102 is erased to a second state (e.g., logic 1). In another embodiment, the voltage biases of bit lines BL i and BL i+1 may be reversed to erase memory cell 102 to the second state.

[0025] In some embodiments, the voltages applied to the gate, drain, and source of memory cell 102 for reading, programming, and erasing memory cell 102 may vary according to a particular manufacturing node and design.

[0026] In some embodiments, each memory cell 102 includes a charge trap material 104 for storing one or more bits. For example, in some embodiments, the charge trap material 104 includes a non-conductive material such as silicon nitride and can store 2 bits per memory cell 102. An example of such a multi-bit memory cell is the MirrorBit™ memory device / array manufactured by Infineon Technologies. In some embodiments, each memory cell 102 stores a single bit. Other implementations are possible.

[0027] Although FIG. 1 shows only nine memory cells 102, it is understood that the memory cell array 100 may include more than nine memory cells 102, such as hundreds, thousands, or millions (or more) of memory cells 102.

[0028] FIG. 2 shows a flowchart of an embodiment of a method 200 for testing a memory cell array 100 according to an embodiment of the present invention. The method 200 may be performed for each memory cell 102 of the memory cell array 100.

[0029] During step 202, the memory cell 102 is programmed to a first state (e.g., logic 0). For example, in some embodiments, a program pulse is provided during step 204 (e.g., a gate voltage of 9V), the voltage of bit line BL i is set to a high positive voltage (e.g., 3V to 5V), and the voltage of bit line BL i+1 is set to a low voltage (e.g., 0V to 2V). The program verification voltage V PV is used as the gate voltage to perform a read operation during step 206, and the voltage V PV is greater in magnitude than the operating read voltage V read applied to the gate of the memory cell 102 during the read operation, as preferably shown in FIG. 3. If the program verification fails, the bit line BL iThe voltage is set to the voltage of the next pulse (e.g., an increased voltage or the same voltage), and new programming pulses are provided until it is verified that the memory cell 102 has been successfully programmed (or until the maximum number of attempts is reached and the memory cell 102 is labeled as non-operational).

[0030] After performing step 202, during step 212, the memory cell 102 is erased to a second state (e.g., logic 1). For example, in some embodiments, during step 214, an erase pulse is provided (e.g., a gate voltage of -7V, a voltage on the BL i at 5V, and a floating BL or a biased BL i+1 at a voltage lower than 5V i+1 ). The erase - verification voltage V EV is used as the gate voltage to perform a read operation during step 216, and the voltage V EV is smaller in magnitude than the operational read voltage V read as preferably shown in FIG. 3. If the erase verification fails, the voltage of the bit line BL i is set to the next pulse (e.g., increasing or remaining the same), and new erase pulses are provided until it is verified that the memory cell 102 has been successfully erased (or until the maximum number of attempts is reached and the memory cell 102 is labeled as non - operational).

[0031] In other embodiments, the voltage biases of BL1 and BL i+1 may be reversed during the program, erase, and verify read operations in method 200.

[0032] In some embodiments, step 202 may be performed to program data into the memory cell 102 during normal operation. Similarly, in some embodiments, step 212 may be performed to erase data from the memory cell 102 during normal operation.

[0033] FIG. 3 shows, according to an embodiment of the present invention, the voltages V EV , V read and VPV shows the distribution of the memory cell 102 in the first state (304) and the second state (302).

[0034] In some embodiments, the original distribution of the memory cell 102 (from the semiconductor manufacturing facility) is represented by the curve 302. As can be seen from the curve 302 (having a significant number of memory cells 102 exceeding the original voltage V EV ), for example, even if a significant number of memory cells 102 initially fail the first read - verification operation (step 216), such memory cells 102 will be normally erased during step 212 after several repetitions of steps 214 and 216.

[0035] As also shown in FIG. 3, during the read operation, the gate voltage V applied to the memory cell 102 read is between the erase verification voltage V EV and the program verification voltage V PV thereby presenting a safety margin to prevent incorrect reads.

[0036] As shown in FIGS. 1 and 2, the memory cell array 100 can be erased and thus is not an OTP memory cell array. FIG. 4 shows a transistor-based OTP memory cell array 400 according to an embodiment of the present invention. The memory cell array 400 includes a plurality of non-volatile memory cells 102 arranged in rows and columns. As can be seen from FIGS. 1 and 4, the OTP memory cell array 400 may be implemented in a manner similar to the memory cell array 100 and may operate in a manner similar to the memory cell array 100. However, since the OTP memory cell array 400 cannot receive a negative voltage on the word line WL, it cannot be erased (step 212 cannot be performed). Therefore, the memory cell array 400 is a ROTP. As a result, (when all of the memory cells 102 of the OTP memory cell array 400 are programmed for testing purposes, the memory cells 102 of the OTP memory cell array 400 cannot be erased and thus cannot be used to store other data), method 200 cannot be applied to the OTP memory cell array 400.

[0037] In one embodiment of the present invention, during the read operation of the memory cell 102 of the OTP memory cell array 400, the OTP read voltage V read_OTP is applied to the gate of the memory cell 102, and the OTP read voltage V read_OTP is higher than the read voltage V read applied to the gate of the memory cell 102 of the memory cell array 100 during the read operation. By using a read voltage V read_OTP higher than the read voltage used for the memory cell array 100 for the OTP memory cell array 400, some embodiments normally use the original distribution of the memory cells 102 during normal operation (without erasing the memory cells 102 during testing).

[0038] In some embodiments, to program the memory cell 102 of the OTP memory cell array 400, step 202 uses the program verification voltage V used to program the memory cell 102 of the memory cell array 100PV A higher OTP program verification voltage V PV_OTP may be used.

[0039] FIG. 5 shows voltage V according to an embodiment of the present invention read_OTP and V PV_OTP as well as the distributions of the memory cell 102 in the first state (304) and the second state (302). As shown in FIG. 5, voltage V read_OTP is higher than voltage V read and may be equidistant from voltage V 1_OTP (representing the upper limit of the original distribution 302) and voltage V PV_OTP , thereby advantageously providing a safety margin to prevent incorrect reading.

[0040] In some embodiments, a portion of the OTP array is programmed during testing. By sacrificing a (e.g., relatively small) portion of the OTP array, some embodiments advantageously test the programmability of the OTP array and access to the OTP array. For example, in some embodiments, a portion of the OTP memory cell array 400 is programmed (e.g., to the first state) to test access to all word lines and bit lines. By sacrificing a portion of the OTP memory cell array 400, some embodiments advantageously verify that all bit lines and word lines of the OTP memory cell array 400 have proper connectivity and can carry the desired current / voltage.

[0041] FIG. 6 shows a simplified top view of the layout of the OTP memory cell array 400 according to an embodiment of the present invention.

[0042] As shown in FIG. 6, the OTP memory cell array 400 has P bit lines BL and Q word lines WL. In some embodiments, P may be 1024 or less, and Q may be between 128 and 512. Other values may be used.

[0043] During the test of the OTP memory cell array 400, all memory cells 102 associated with one word line (e.g., WL1) and one bit line (e.g., BL1) or cache line (e.g., CL1) are programmed (e.g., using step 202, e.g., instead of V read and V PV using V read_OTP and V PV_OTP ). If all the sacrificed memory cells are programmed successfully, the test of the OTP memory cell array 400 is considered successful because the connectivity paths to all word lines WL and all bit lines BL are verified.

[0044] In some embodiments, sacrificing one row and one column of the OTP memory cell array 400 advantageously represents a small portion of the total capacity of the OTP memory cell array 400 in exchange for an indication that the connectivity paths to all word lines WL and bit lines BL are appropriate. For example, in an embodiment where P equals 128 and Q equals 1024, 1,151 out of 131,072 memory cells of the OTP memory cell array 400 are sacrificed during the test of the OTP memory cell array 400.

[0045] In some embodiments, multiple columns and / or multiple rows of the memory cells 102 are sacrificed during the test of the OTP memory cell array 400.

[0046] In some embodiments, the outlier memory cells 102 of the OTP memory array 400 can have a Vt voltage associated with a second state higher than V 1_OTP . Thus, some memory cells 102 of the OTP memory array 400 can read as logic 0 (the first state) when read at the OTP read voltage V read_OTP , even though they have never been programmed.

[0047] In some embodiments, the outlier memory cell 102 may be likely to be found around the position 402 that represents the position of the via connecting the metal bit line to the embedded bit line. In some embodiments, the memory cells 102 near (e.g., directly adjacent to) the position 402 (e.g., coupled to the word line WL that is physically closest to the position 402) are not used (sacrificed, such as not being programmed and / or not being read during normal operation), which may advantageously increase the reliability of the OTP memory cell array 400. In some embodiments, a plurality of positions 402 having, for example, physical periodicity are found on each bit line BL (i.e., many positions 402 for each bit line BL).

[0048] In some embodiments, the prevention of the read operation for the sacrificial memory cell 102 may be implemented by software, such as by making the sacrificial memory cell 102 unaddressable.

[0049] In one embodiment of the present invention, data is stored in the OTP memory cell array 400 having redundancy, and majority voting is used while reading the OTP memory cell array 400 to determine the data stored in the OTP memory cell array 400. By using redundancy and majority voting, some embodiments advantageously enable the OTP memory cell array 400 having some defective or outlier memory cells 102 (e.g., related to manufacturing process defects) to be reliably used without implementing the method 200 to test the memory cells 102 of the OTP memory cell array 400.

[0050] In some embodiments, triple redundancy is used for each bit of the data stored in the OTP memory cell array 400. For example, in some embodiments, the same bit is stored in three different memory cells 102. In some embodiments, for example, to enhance immunity against cluster defects, the same bit is stored in three physically separated memory cells 102 (e.g., associated with different word lines WL and different bit lines BL that are physically separated). For example, in some embodiments, each of the bits is stored at a position associated with word lines and bit lines that are not physically adjacent. For example, in some embodiments, the three redundant bits associated with a single-bit of data are stored in the memory cells 102 associated with WL = 1, BL = 1, WL = 3, BL = 3, and WL = 5, BL = 5, respectively.

[0051] In some embodiments, reading a bit from the OTP memory cell array 400 includes using a majority vote. FIG. 7 shows a flowchart of an exemplary method 700 for reading a bit from the OTP memory cell array 400 using a majority vote, according to one embodiment of the present invention.

[0052] During step 702, an address associated with the bit to be read is received.

[0053] During step 704, values from all redundant positions are read. For example, in embodiments using triple redundancy, the values from each of the three redundant memory cells 102. In some embodiments, reading the value of each bit includes using a read voltage V read_OTP and comparing the current obtained from the associated bit line BL with a current threshold. A current that exceeds the current threshold is interpreted as, for example, a logic 0, and a current that is below the current threshold is interpreted as, for example, a logic 1.

[0054] In some embodiments, since the memory cells 102 of the OTP memory cell array 400 do not undergo multiple programming cycles, the current threshold used during step 704 is fixed and does not change over time (e.g., does not track aging).

[0055] During step 706, the reporting of bit reads is performed according to a majority vote. For example, in some embodiments, the reading of bits from the OTP memory cell array 400 includes reading from three redundant positions (during step 704) and reporting the state that receives the most votes as the read bit (during step 706). For example, if all three bits are read as logic 0, the read bit is reported as logic 0. If two bits are read as logic 0 and one bit is read as logic 1, the read bit is reported as logic 0. If two bits are read as logic 1 and one bit is read as logic 0, the read bit is reported as logic 1. If all three bits are read as logic 1, the read bit is reported as logic 1.

[0056] In some embodiments, an error correcting code (ECC) is used to detect and correct errors. For example, in some embodiments, the ECC used can correct one or more errors in the read values (e.g., in a cluster of read values such as 128 bits). In some such embodiments, step 706 may be performed before performing the ECC step. In some embodiments, step 706 may be performed after performing the ECC step.

[0057] FIG. 8 shows a flowchart of an exemplary method 800 for programming data into the OTP memory cell array 400 according to an embodiment of the present invention. In some embodiments, the method 800 may be implemented, for example, on-site.

[0058] During step 802, the addresses of the bits to be programmed to the first state (e.g., logic 0) are received. In some embodiments, during step 802 (since the associated memory cell 102 is expected to already be in the second state from the semiconductor manufacturing facility), only the addresses of the bits expected to be in the first state (e.g., logic 0) are received, and the address bits expected to be in the second state (e.g., logic 1) are not received.

[0059] During step 804, the write buffer is filled with all the bits to be programmed to the first state. In some embodiments, the write buffer includes all the redundant bit addresses associated with the bits to be programmed. In some embodiments, the write buffer includes additional bit addresses (e.g., the respective redundant bit addresses of other bits to be programmed).

[0060] As shown by steps 806, 808, 810, 812, 814, 816 and step 818, an attempt is made to program each of the bits stored in the write buffer until all the bits are programmed (''yes'' from step 806) or until a bit fails to be programmed (''no'' from step 818). For the purposes of this description, assume that the write buffer contains M bits.

[0061] During step 808, a programming pulse is provided to the OTP memory cell array 400 in an attempt to program the k-th bit of the write buffer (where k is a number between 1 and M). In some embodiments, step 202 is PV Instead, it is implemented as part of the OTP programming verification voltage V PV_OTP of step 808.

[0062] In some embodiments, during step 808, multiple bits (e.g., from a write buffer) are programmed simultaneously with the same programming pulse. For example, in some embodiments, all redundant bits associated with the k-th bit are programmed during the same programming pulse during step 808.

[0063] During step 810, it is determined whether the programming of the k-th bit was successful. For example, during step 810, the k-th bit is read out (e.g., using a read voltage V read_OTP . If the bit read out during step 808 matches the bit written to the k-th bit, step 810 results in "yes". Otherwise, step 810 results in "no".

[0064] If step 810 is "yes", step 806 is performed. Otherwise, if step 810 is "no" and the number of attempts to program the k-th bit is lower than the maximum number of attempts (determined during step 812), the drain voltage of the memory cell 102 associated with the k-th bit is set during step 814 for the next programming pulse. For example, in some embodiments, the drain voltage V d is increased (e.g., by a predetermined amount) if it has not reached the maximum drain voltage, or is maintained the same during step 814 if it has reached the maximum drain voltage. After step 814, a new programming pulse is provided during step 808.

[0065] Otherwise, if the maximum number of programming attempts for the k-th bit has been reached (a "yes" from step 812), no further attempts are made to program the k-th bit and step 816 is performed.

[0066] During step 816, multiple reads are performed (e.g., using method 700). Step 816 is performed if an attempt is made to program all redundant bits associated with a particular bit address received during step 802. If the result from the multiple reads matches the written value (e.g., logic 0), step 806 is performed. Otherwise (a "no" from step 818), the programming fails. In some embodiments, when the programming fails, a signal is asserted, for example, to indicate that the programming has failed. In some embodiments, such a signal is provided to an external controller, for example.

[0067] In some embodiments, bit redundancy and majority voting may advantageously increase the reliability of transistor-based OTP and may advantageously enable the reliable use of an OTP array having process-defective memory cells 102.

[0068] In some embodiments, steps 816 and 818 (i.e., when step 812 is "yes", the programming fails) are omitted, and instead of V PV_OTP and V read_OTP memory cell array 100 may be programmed (e.g., during step 202) using method 800 that uses V PV and V read instead.

[0069] FIG. 9 shows a schematic diagram of a fixed IC 900 according to an embodiment of the present invention. IC 900 includes a positive voltage generator 902, a negative voltage generator 904, a controller 908, and an internal memory 906. The internal memory 906 includes a plurality of memory sectors. Some of the memory sectors may be implemented with respective memory cell arrays 100, and other memory sectors may be implemented with OTP memory cell arrays 400.

[0070] As shown in FIG. 9, each of the memory sectors implemented in the memory cell array 100 can receive a positive voltage and a negative voltage from a positive voltage generator 902 and a negative voltage generator 904 to be provided to the word line WL, respectively, for example, during write, erase, and read operations.

[0071] As also shown in FIG. 9, none of the memory sectors implemented in the OTP memory cell array 400 can receive a negative voltage from the negative voltage generator 904. As a result, the OTP memory cell array 400 does not receive a bipolar supply and cannot physically (by design) perform an erase operation.

[0072] In some embodiments, the read operation of one of the non-OTP sectors implemented in the memory array 100 is performed using a read voltage V read (e.g., provided by the positive voltage generator 902) and using a current threshold, is adaptive, and varies to track the aging of the memory cell, while determining the state (e.g., logic 0 or logic 1) of the associated memory cell 102, while the read operation of one of the OTP sectors implemented in the memory array 400 is performed using a read voltage V read_OTP (e.g., provided by the positive voltage generator 902 and higher than V read ) and using a current threshold, is fixed, and does not change over time, to determine the state (e.g., logic 0 or logic 1) of the associated memory cell 102.

[0073] In some embodiments, the write operation of one of the non-OTP sectors implemented in the memory array 100 is performed using a voltage V PV (e.g., provided by the positive voltage generator 902), while the write operation of one of the OTP sectors implemented in the memory array 400 is performed using a voltage V PV_OTP (e.g., provided by the positive voltage generator 902 and higher than V PV ).

[0074] In some embodiments, voltage generators 902 and 904 may be implemented in any manner known in the art.

[0075] In some embodiments, internal memory 906 includes one or more OTP sectors (each implemented by an OTP memory cell array 400) and one or more non-OTP NVMs (each implemented by a memory cell array 100). In some embodiments, internal memory 906 includes one or more OTP sectors and no non-OTP NVM sectors.

[0076] In some embodiments, each of the memory cells 102 of the OTP sectors and non-OTP sectors is implemented as a single-bit memory cell.

[0077] In some embodiments, each of the memory cells 102 of the OTP sectors and non-OTP sectors is implemented as a multi-bit memory cell. For example, in some embodiments, each of the memory cells 102 of the OTP sectors and non-OTP sectors is implemented as a 2-bit memory cell, such as MirrorBit™, and the read operation of the first or second bit of the 2-bit memory cell is performed by swapping the drain and source of the memory cell 102 in a known manner.

[0078] In some embodiments implementing the memory cells 102 of an OTP sector with multi-bit memory cells (e.g., MirrorBit™ type), all bits of the multi-bit cell are programmed (or not programmed) to have the same value, which may advantageously increase the reliability of the OTP memory cell because the currents associated with logic 0 and logic 1 may be further apart compared to when mixed values (e.g., one logic 0 and one logic 1) are stored in the same multi-bit memory cell. In some such embodiments, each bit of the memory cells 102 of the non-OTP sectors may be treated as an independent bit and thus may have different values.

[0079] In some embodiments implementing the memory cell 102 of the OTP sector having a multi-bit memory cell (e.g., MirrorBit (trademark) type), each bit of the multi-bit memory cell is treated as an independent bit, and thus may have a value different from other bits of the same multi-bit memory cell, which may advantageously result in an increase in the memory capacity of the OTP sector.

[0080] In some embodiments, the controller 908 is configured to perform or cause to perform programming, erasing, and reading operations on the non-OTP memory sectors of the IC 900, as well as programming and reading operations on the OTP memory sectors of the IC 900. In some embodiments, the controller 908 receives instructions to perform programming and / or reading operations on the OTP memory sectors of the IC 900 from another controller (not shown), such as another controller external to the IC 900, via, for example, a communication interface.

[0081] In some embodiments, the controller 908 is implemented as a general-purpose or custom controller or processor configured to execute instructions from memory. In some embodiments, the controller 908 includes a finite state machine (FSM). Other implementations are possible.

[0082] In some embodiments, the secure IC 900 is a stand-alone memory. In some embodiments, the secure IC 900 is a secure SoC, such as a secure microcontroller.

[0083] In some embodiments, the secure IC 900 advantageously provides an OTP function without using a polyfuse array.

[0084] Figure 10 shows a schematic diagram of the secure IC 1000 according to an embodiment of the present invention. The IC 1000 operates in the same manner as the IC 900 and includes a positive voltage generator 902, a negative voltage generator 904, and an internal memory 906. However, the IC 1000 has a similar or identical layout for all memory sectors (including the memory sector implemented by the OTP memory cell array 400 and the memory sector implemented by the memory cell array 100). Thus, as shown in FIG. 10, the memory sector implemented by the OTP memory cell array 400 is coupled to the negative voltage generator 904 in a manner similar to the memory sector implemented by the memory cell array 100.

[0085] The IC 1000 also includes a controller 1008 instead of the controller 908. In some embodiments, the controller 1008 is implemented and operates in the same manner as the controller 908. However, when the OTP memory cell array 400 is accessed (e.g., for either a read or write operation), the controller 1008 prevents the erasure of the memory cells 102 located within the memory sector implemented by the OTP memory cell array 400 by forcing the voltage at the output of the negative voltage generator 904 from a negative voltage to 0V. For example, FIG. 11 shows a flowchart of an embodiment method 1100 for preventing the erasure of the OTP memory cell array 400 according to an embodiment of the present invention. In some embodiments, the controller 1008 may implement the method 1100.

[0086] During step 1102, a memory address to be accessed (e.g., of internal memory 906) is received (e.g., by controller 1008) (e.g., for reading or writing). During step 1104, if it is determined that the received memory address is associated with the OTP memory cell array 400 (the "yes" of step 1104), the output of the negative voltage generator (e.g., 904) is set (during step 1108) to a non-erasure voltage (i.e., a voltage that does not cause erasure of the memory cell 102, e.g., 0V). Otherwise, if the received memory address is associated with a non-OTP memory cell (e.g., 100), the output of the negative voltage generator 904 is set (during step 1106) to a target voltage such as -7V.

[0087] In some embodiments, the controller 1008 implements the method 1100 by design (i.e., cannot be changed by software) such that the OTP memory cell array 400 is a ROTP.

[0088] Exemplary embodiments of the present invention are summarized herein. Other embodiments can also be understood from the entire specification and the claims filed herein.

[0089] Exemplary embodiments of the present disclosure are summarized herein. Other embodiments can also be understood from the entire specification and the claims filed herein.

[0090] Example 1. Receiving a first program bit address, where the first program bit address is associated with a first plurality of redundant bit addresses, the first program bit address is associated with a first transistor-based memory cell, and each of the first plurality of redundant bit addresses is associated with a respective transistor-based memory cell; providing a programming pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell via a first bit line; reading redundant bit values from transistor-based memory cells associated with the first plurality of redundant bit addresses via respective bit lines; determining a majority bit value based on the first bit value and one of the redundant bit values when one of the first bit value and the redundant bit values does not match the first write value; and asserting a flag signal indicating a failure in programming the first program bit address to the first write value when the majority bit value does not match the first write value.

[0091] Example 2. The method of Example 1, wherein providing a programming pulse to the first word line includes providing a first positive voltage to the first word line, and the first word line cannot receive a negative voltage.

[0092] Example 3. Each of the transistor-based memory cells associated with the redundant bit addresses is coupled to a respective word line, and the method further includes providing an additional programming pulse to the word line associated with one of the first bit value and the redundant bit values when one of the first bit value and the redundant bit values does not match the first write value, and determining the majority bit value includes determining the majority bit value after providing the additional programming pulse, the method of Example 1 or 2.

[0093] Example 4. The method according to any one of Examples 1 to 3, wherein a first transistor-based memory cell and a transistor-based memory cell associated with a first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array, and the method further includes testing the OTP memory array by programming a first row and a first column of the OTP memory array with a first write value.

[0094] Example 5. The method according to Examples 1 and 4, further including preventing a read operation for a first row and a first column of the OTP memory array.

[0095] Example 6. The method according to any one of Examples 1 to 5, wherein a first transistor-based memory cell and a transistor-based memory cell associated with a first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory further includes a non-OTP memory array sector, and the method further includes reading a second bit value from a transistor-based memory cell of the non-OTP memory array sector by comparing a current from a related bit line of the non-OTP memory array sector with an adaptive current threshold, and reading a first bit value from the first transistor-based memory cell via a first bit line includes comparing a current from the first bit line with a fixed current threshold.

[0096] Example 7. The first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory further comprising a non-OTP memory array sector, the method further comprising programming a second bit value into a second transistor-based memory cell of the non-OTP memory array sector by providing a first programming voltage to a second word line associated with the second transistor-based memory cell, providing a programming pulse to the first word line including providing a second programming voltage higher than the first programming voltage, the method of Examples 1 to 6.

[0097] Example 8. The first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory further comprising a non-OTP memory array sector, the method further comprising reading a second bit value from a second transistor-based memory cell of the non-OTP memory array sector by providing a first read voltage to a second word line associated with the second transistor-based memory cell, reading a first bit value from the first transistor-based memory cell including providing a second read voltage higher than the first read voltage to the first transistor-based memory cell, the method of Examples 1 to 7.

[0098] Example 9. Each of the first program bit address and the transistor-based memory cells associated with the first plurality of redundant bit addresses is a multi-bit memory cell, the method of Examples 1 to 8.

[0099] Example 10. Receiving a plurality of additional program bit addresses, each of the plurality of additional program bit addresses being associated with a respective multi-bit transistor-based memory cell; programming each of the multi-bit transistor-based memory cells associated with the plurality of additional program bit addresses to a first write value, such that after programming each of the multi-bit transistor-based memory cells, each bit of each of the multi-bit transistor-based memory cells is programmed to the first write value; and further including the method of Examples 1 to 9.

[0100] Example 11. The method of Examples 1 to 10, wherein the first write value corresponds to a logical 0.

[0101] Example 12. The first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory further comprising a non-OTP memory array sector, the method further comprising receiving a memory address; setting an output of a negative voltage generator to a target negative voltage when the memory address corresponds to a memory cell of the OTP memory array; and setting the output of the negative voltage generator to an erase-free voltage different from the target negative voltage when the memory address corresponds to a memory cell of the OTP memory array; and further including the method of Examples 1 to 11.

[0102] Example 13. The method of Examples 1 to 11, wherein the erase-free voltage is equal to 0V.

[0103] Example 14. The circuit is a plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell having first and second bit line terminals coupled to associated bit lines of a plurality of bit lines, and a gate terminal coupled to an associated word line of a plurality of word lines, each word line of the plurality of word lines being coupled to the gate terminals of the transistor-based memory cells of the associated row, the plurality of transistor-based memory cells, to write a first write value to the first transistor-based memory cell, providing a programming pulse to a first word line coupled to the first transistor-based memory cell among the plurality of transistor-based memory cells, reading a first bit value from the first transistor-based memory cell via a first bit line, reading a redundant bit value from a redundant transistor-based memory cell among the plurality of transistor-based memory cells, the redundant transistor-based memory cell storing the same value as the first transistor-based memory cell, determining a majority bit value based on the first bit value and the redundant bit value read from the redundant transistor-based memory cell when one of the first bit value and the redundant bit value does not match the first write value, and asserting a flag signal indicating a failure in programming the first write value to the first transistor-based memory cell when the majority bit value does not match the first write value, a controller configured to perform the above.

[0104] Example 15. The circuit of Example 14, wherein each transistor-based memory cell of the plurality of transistor-based memory cells includes a charge trap material including a non-conductive material.

[0105] Example 16. The circuit of Examples 14 to 15, wherein the non-conductive material includes silicon nitride.

[0106] Example 17. The circuit of Examples 14 to 16, wherein each transistor-based memory cell of the plurality of transistor-based memory cells is configured to store single-bit data.

[0107] Example 18. The circuit of Examples 14 to 17, wherein each transistor-based memory cell of the plurality of transistor-based memory cells is configured to store data of a plurality of bits.

[0108] Example 19. The circuit of Examples 14 and 17 to 18, wherein each of the plurality of bits of the first transistor-based memory cell matches a first write value.

[0109] Example 20. The circuit of Examples 14 to 19, wherein the rows of the transistor-based memory cells and the columns of the transistor-based memory cells are programmed with a first write value.

[0110] Example 21. The circuit of Examples 14 to 20, wherein each of the first transistor-based memory cell and the redundant transistor-based memory cell is coupled to a separate word line and a separate bit line.

[0111] Example 22. A one-time programmable (OTP) sector in which the non-volatile memory comprises a first plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell of the first plurality of transistor-based memory cells comprising first and second bit line terminals coupled to a respective bit line of a first plurality of bit lines and a gate terminal coupled to a respective word line of a first plurality of word lines; a non-OTP sector in which the non-volatile memory comprises a second plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell of the second plurality of transistor-based memory cells comprising first and second bit line terminals coupled to a respective bit line of a second plurality of bit lines and a gate terminal coupled to a respective word line of a second plurality of word lines; wherein the second plurality of word lines are configured to receive a first positive voltage during a read mode, a second positive voltage during a write mode, and a first negative voltage during an erase mode, and the first plurality of word lines are configured to receive a third positive voltage during a read mode and a fourth positive voltage during a write mode, and the first plurality of word lines are designed not to receive a negative voltage in any mode, and the transistor-based memory cells of the OTP sector and the transistor-based memory cells of the non-OTP sector are of the same type.

[0112] Example 23. The non-volatile memory of Example 22, in which the non-volatile memory lacks a polyfuse array.

[0113] Example 24. The non-volatile memory of Examples 22 to 23, in which the third positive voltage is higher than the first positive voltage and the fourth positive voltage is higher than the second positive voltage.

[0114] The present invention has been described with reference to exemplary embodiments, but this description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present invention, will be apparent to those skilled in the art upon reference to the description. Accordingly, the appended claims are intended to embrace such modifications or embodiments.

Claims

1. A step of receiving a first program bit address, wherein the first program bit address is associated with a first plurality of redundant bit addresses, the first program bit address is associated with a first transistor-based memory cell, and each of the first plurality of redundant bit addresses is associated with its respective transistor-based memory cell. The steps include providing a programming pulse to a first word line coupled to the first transistor-based memory cell in order to write a first write value to the first transistor-based memory cell, The steps include reading a first bit value from the first transistor-based memory cell via a first bit line, The steps include reading redundant bit values ​​from transistor-based memory cells associated with the first plurality of redundant bit addresses via each bit line, When either the first bit value or the redundant bit value does not match the first write value, the steps include determining a majority bit value based on the first bit value and the redundant bit value read from the transistor-based memory cell associated with the first plurality of redundant bit addresses, When the aforementioned number of bit values ​​does not match the first write value, the step of asserting a flag signal indicating a failure in programming the first program bit address to the first write value, A method that includes this.

2. The step of providing the programming pulse to the first word line includes the step of providing a first positive voltage to the first word line, wherein the first word line cannot receive a negative voltage. The method according to claim 1.

3. Each of the transistor-based memory cells associated with the redundant bit address is coupled to its respective word line, and the method further includes the step of providing an additional programming pulse to the word line associated with the first bit value and the redundant bit value when one of the first bit value and the redundant bit value does not match the first write value, and the step of determining the majority bit value includes the step of determining the majority bit value after the step of providing the additional programming pulse. The method according to claim 1.

4. The first transistor-based memory cell and the transistor-based memory cell associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array, and the method further includes the step of testing the OTP memory array by programming the first row and first column of the OTP memory array to the first write values. The method according to claim 1.

5. The method further includes the step of preventing read operations on the first row and first column of the OTP memory array. The method according to claim 4.

6. The first transistor-based memory cell and the transistor-based memory cell associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of the memory, the memory further comprises a non-OTP memory array sector, and the method further includes the step of reading a second bit value from a transistor-based memory cell of the non-OTP memory array sector by comparing the current from an associated bit line of the non-OTP memory array sector with an adaptive current threshold, the step of reading the first bit value from the first transistor-based memory cell via the first bit line includes the step of comparing the current from the first bit line with a fixed current threshold. The method according to claim 1.

7. The first transistor-based memory cell and the transistor-based memory cell associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of the memory, the memory further comprises a non-OTP memory array sector, and the method further includes the step of programming a second bit value into the second transistor-based memory cell by providing a first programming voltage to a second word line associated with a second transistor-based memory cell in the non-OTP memory array sector, wherein the step of providing the programming pulse to the first word line includes the step of providing a second programming voltage that is higher than the first programming voltage. The method according to claim 1.

8. The first transistor-based memory cell and the transistor-based memory cell associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of the memory, the memory further comprises a non-OTP memory array sector, and the method further includes the step of reading a second bit value from the second transistor-based memory cell by providing a first read voltage to a second word line associated with a second transistor-based memory cell of the non-OTP memory array sector, the step of reading the first bit value from the first transistor-based memory cell includes the step of providing the first transistor-based memory cell with a second read voltage higher than the first read voltage. The method according to claim 1.

9. Each of the transistor-based memory cells associated with the first program bit address and the first plurality of redundant bit addresses is a multibit memory cell. The method according to claim 1.

10. The aforementioned method, A step of receiving a plurality of additional program bit addresses, wherein each of the plurality of additional program bit addresses is associated with a respective multibit transistor-based memory cell, A step of programming each of the multibit transistor-based memory cells associated with the plurality of additional program bit addresses to the first write value, wherein, after the step of programming each of the multibit transistor-based memory cells, each bit of each of the multibit transistor-based memory cells is programmed to the first write value, Further including, The method according to claim 1.

11. The first written value corresponds to logical 0, The method according to claim 1.

12. The first transistor-based memory cell and the transistor-based memory cell associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of the memory, the memory further comprises a non-OTP memory array sector, and the method is The step of receiving a memory address, When the memory address corresponds to a memory cell of the non-OTP memory array sector, the step is to set the output of the negative voltage generator to a target negative voltage. When the memory address corresponds to a memory cell of the OTP memory array sector, the step of setting the output of the negative voltage generator to a non-erasable voltage different from the target negative voltage, Further including, The method according to claim 1.

13. The voltage without erasure is equal to 0V. The method according to claim 12.

14. Multiple transistor-based memory cells arranged in rows and columns, Controller and A circuit comprising, Each transistor-based memory cell comprises first and second bit line terminals coupled to related bit lines of a plurality of bit lines, and gate terminals coupled to related word lines of a plurality of word lines, wherein each word line of the plurality of word lines is coupled to the gate terminal of the transistor-based memory cell of the related row. The aforementioned controller, To write a first write value to a first transistor-based memory cell, a programming pulse is provided to a first word line coupled to the first transistor-based memory cell among the plurality of transistor-based memory cells, To read a first bit value from the first transistor-based memory cell via the first bit line among a plurality of bit lines, The method involves reading a redundant bit value from a redundant transistor-based memory cell among the plurality of transistor-based memory cells, wherein the redundant transistor-based memory cell is configured to store the same value as the first transistor-based memory cell. When either the first bit value or the redundant bit value does not match the first written value, the majority bit value is determined based on the first bit value and the redundant bit value read from the redundant transistor-based memory cell. When the aforementioned multi-bit value does not match the first write value, a flag signal indicating a failure to program the first transistor-based memory cell to the first write value is asserted. It is configured to implement, circuit.

15. Each of the plurality of transistor-based memory cells includes a charge trapping material which includes a non-conductive material. The circuit according to claim 14.

16. The aforementioned nonconductive material contains silicon nitride, The circuit according to claim 15.

17. Each of the plurality of transistor-based memory cells is configured to store single-bit data. The circuit according to claim 14.

18. Each of the plurality of transistor-based memory cells is configured to store a plurality of bits of data. The circuit according to claim 14.

19. Each of the plurality of bits of the first transistor-based memory cell matches the first written value. The circuit according to claim 18.

20. The rows and columns of the transistor-based memory cells are programmed with the first write value. The circuit according to claim 14.

21. Each of the first transistor-based memory cell and the redundant transistor-based memory cell is coupled to a separate word line and a separate bit line. The circuit according to claim 14.

22. A one-time programmable (OTP) memory sector comprising a first plurality of transistor-based memory cells arranged in rows and columns, wherein each transistor-based memory cell of the first plurality of transistor-based memory cells comprises first and second bit-line terminals coupled to related bit lines of a plurality of bit lines, and gate terminals coupled to related word lines of a plurality of word lines, and each word line of the plurality of word lines is coupled to the gate terminal of the transistor-based memory cell of the related row, Controller and A non-volatile memory comprising, The aforementioned controller, To write a first write value to a first transistor-based memory cell among the first plurality of transistor-based memory cells, a programming pulse is provided to a first word line coupled to the first transistor-based memory cell, To read a first bit value from the first transistor-based memory cell via the first bit line among the plurality of bit lines, The method involves reading a redundant bit value from a redundant transistor-based memory cell among the first plurality of transistor-based memory cells, wherein the redundant transistor-based memory cell is configured to store the same value as the first transistor-based memory cell. When either the first bit value or the redundant bit value does not match the first written value, the majority bit value is determined based on the first bit value and the redundant bit value read from the redundant transistor-based memory cell. When the aforementioned multi-bit value does not match the first write value, a flag signal indicating a failure to program the first transistor-based memory cell to the first write value is asserted. It is configured to implement, Non-volatile memory.

23. The non-volatile memory further comprises a non-OTP memory sector having a second plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell of the second plurality of transistor-based memory cells having first and second bit line terminals coupled to related bit lines of the second plurality of bit lines, and gate terminals coupled to related word lines of the second plurality of word lines, the controller, Reading a second bit value from a second transistor-based memory cell in a non-OTP memory sector by providing a first read voltage to the word lines of the second plurality of word lines associated with the second transistor-based memory cell in the second plurality of transistor-based memory cells, wherein reading the first bit value from the first transistor-based memory cell includes providing the first transistor-based memory cell with a second read voltage higher than the first read voltage, Further configured to implement, The non-volatile memory according to claim 22.

24. Each transistor-based memory cell of the plurality of transistor-based memory cells includes a charge trapping material which includes a non-conductive material. The non-volatile memory according to claim 22.

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