System and method for manufacturing the system

Abstract

The present invention relates to a system (110) comprising at least one semiconductor chip (40). The analog electrical circuit comprises at least one input (20) and at least one output (26). The analog artificial neural network (10) electrically connects the input (20) to the output (26). The semiconductor chip (40) is recursively coupled to a second digital artificial neural network (50). The output of the semiconductor chip (40) is provided to at least one hidden layer of the second digital artificial neural network (50). The input (20) of the semiconductor chip (40) and the input layer of the second digital artificial neural network (50) are electrically connected to the input projection.

Description

Technical Field

[0001] The present invention relates to a system including a semiconductor chip and a method for manufacturing the system.

Background Art

[0002] Artificial intelligence may be used to recognize patterns in technical applications such as, for example, image recognition or monitoring of machine parameters. An artificial neural network that mimics the function of biological neurons can provide artificial intelligence. These neural networks can be trained using training data, and through training, the neural network adapts and its ability to perform tasks is improved.

[0003] To distribute the tasks to be executed into subtasks, different artificial neural networks may be combined. For example, when the task is image recognition, the first subtask may be a rough classification of image elements, and the second subtask may be the recognition of image elements. For example, in the human brain, the first part of the brain roughly classifies image elements, for example, into dangerous elements and harmless elements, and the second part of the brain recognizes the image elements for the same image. For example, the first part of the brain may affect the second part of the brain to accelerate the recognition of dangerous image elements.

[0004] This structure is formed by a first and a second artificial neural network, and the first artificial neural network is recursively coupled to the second artificial neural network. Both artificial neural networks receive the same input based on the same data. The first artificial neural network may affect the result of the second artificial neural network, but the second artificial neural network does not affect the first artificial neural network. Such a structure is known from International Publication No. WO 2020 / 233850 A1.

[0005] The first artificial neural network needs to provide an output before the second artificial neural network in order to affect the second artificial neural network. If the first artificial neural network is not more complex than the second artificial neural network, or if the input data of the first artificial neural network is subsampled, or if the second artificial neural network is started after the first artificial neural network generates an output that affects the second artificial neural network, the first artificial neural network can provide an output before the second artificial neural network.

Summary of the Invention

Problems to be Solved by the Invention

[0006] There is a need to provide an artificial neural network for high-speed processing, which has the same complexity and uses the same sampling of input data as another artificial neural network and can complete its operation during the operation of the other artificial neural network.

[0007] The object of the present invention is solved by the matters defined in the independent claims. Further embodiments are incorporated in the dependent claims and the following description.

Means for Solving the Problems

[0008] According to the present invention, there is provided a system including an input projection layer, at least one second digital artificial neural network, and at least one semiconductor chip obtained by at least the following steps: the steps include providing a trained first digital artificial neural network; determining a state of the trained first digital artificial neural network, the state including at least information regarding digital nodes of the trained first digital artificial neural network and information regarding a digital connection architecture between the digital nodes of the trained first digital artificial neural network; manufacturing the semiconductor chip, including an analog electrical circuit having an analog artificial neural network designed according to the state of the trained first digital artificial neural network, the analog electrical circuit including at least one input configured to receive at least one input signal and at least one output configured to provide at least one analog output signal, the analog artificial neural network electrically connecting the input to the output, and the semiconductor chip, particularly the analog artificial neural network, being recursively coupled to the second digital artificial neural network, an output of the semiconductor chip being provided to at least one hidden layer of the second digital artificial neural network, and the input of the semiconductor chip and an input layer of the second digital artificial neural network being electrically connected to the input projection layer.

[0009] As used herein, the term "digital artificial neural network" includes software-based artificial neural networks that are executed on an information technology (IT) platform or within a microprocessor. Thus, a digital artificial neural network exists only on a platform of digital electronic circuits such as, for example, random access memory. Accordingly, the nodes and the connections between the nodes exist only virtually and may be deleted. Due to the architecture of the software-based artificial neural network, the IT platform or the microprocessor processes each node of the digital artificial neural network in sequence.

[0010] As used herein, the term "analog artificial neural network" includes artificial neural networks formed on analog hardware, such as on a microchip connected as hardware. The analog artificial neural network physically exists as an analog electrical circuit. The analog electrical wires and the components of the semiconductor chip itself form the analog artificial neural network. Accordingly, the nodes of the analog artificial neural network and the connections between the nodes cannot be completely deleted. The nodes of each layer of the analog artificial neural network process the input data simultaneously.

[0011] These steps provide a semiconductor chip including an analog electrical circuit. These analog electrical circuits are non-programmable and form an analog artificial neural network. The analog artificial neural network operates analogously such that an electrical signal of an input layer of the analog artificial neural network propagates simultaneously to all nodes in one layer of the artificial neural network. Thus, the number of layers determines the processing speed of the electrical signal. In a digital artificial neural network, multiple nodes in one layer process the signal one after another. Thus, the number of nodes determines the processing speed of the electrical signal within the digital artificial neural network. Usually, since the number of nodes is larger than the number of layers, the digital artificial neural network is slower than an analog artificial neural network with the same complexity. As a result, when the number of nodes and the number of layers of the analog artificial neural network are the same as those of the digital artificial neural network, the analog artificial neural network on the semiconductor chip is faster than the corresponding digital artificial neural network executed on an IT platform or a microprocessor. Both artificial neural networks may have the same input data sampling and the same complexity.

[0012] To manufacture a semiconductor chip, as is generally known, a first digital artificial neural network is trained. The trained first digital artificial neural network is also referred to as a digital master artificial neural network. Next, the state of the trained first digital artificial neural network is determined. The state can be read from a program that executes the trained first digital artificial neural network. The state includes information regarding at least the digital nodes of the trained first digital artificial neural network and the digital connections between the digital nodes, the so-called digital connection architecture. The information regarding at least the digital nodes may include, for example, bias, weight, transfer function, and activation function. The first digital artificial neural network is completely determined by the information regarding the digital nodes and the digital connection architecture. An analog artificial neural network is designed based on the information. The designed analog artificial neural network is provided as an analog electrical circuit on a semiconductor chip. Of course, the semiconductor chip manufactured by this method can include a plurality of analog artificial neural networks. Each of the plurality of analog artificial neural networks may be based on a different trained digital artificial neural network. Some of the plurality of analog artificial neural networks may be based on the same trained digital artificial neural network.

[0013] Accordingly, the semiconductor chip includes an analog electrical circuit having an analog artificial neural network designed according to the state of the trained first digital artificial neural network. As described above, the analog artificial neural network operates much faster than the trained first digital artificial neural network. Therefore, the present invention provides a high-speed processing artificial neural network that has the same complexity as other artificial neural networks, uses the same sampling of input data as other artificial neural networks, and can complete operations during the operation of other artificial neural networks.

[0014] The input can include, for example, an electrical connector configured to receive a signal. The signal can be an electrical signal, an optical signal, an acoustic signal, an olfactory signal, etc. Also, the output can include, for example, an electrical connector configured to supply an electrical signal. The input may be electrically connected to the input layer of an analog artificial neural network. Alternatively, the input may be the input layer of an analog artificial neural network. The output may be electrically connected to the output layer of an analog artificial neural network. Alternatively, the output may be the output layer of an analog artificial neural network.

[0015] The semiconductor chip is recursively coupled to a second digital artificial neural network having the same complexity and using the same sampling for the input data. The coupling can be performed, for example, via an analog-digital interface. And the analog artificial neural network may output an electrical signal to affect the operation of the second digital artificial neural network while the second digital artificial neural network is operating.

[0016] The analog artificial neural network and the second digital artificial neural network operate using the same input data of the input projection layer. The input projection layer simultaneously provides the input data to the input layer of the analog artificial neural network, and the digital nodes of the input layer of the second digital artificial neural network can receive the input data in sequence. Thus, both the analog artificial neural network and the second digital artificial neural network receive the input data with the same sampling. Further, the analog artificial neural network operates faster than the second digital artificial neural network. Thus, the analog artificial neural network provides an output that affects the operation of the second digital artificial neural network before the second digital artificial neural network provides an output.

[0017] Since the analog artificial neural network is implemented on an analog electronic circuit connected as hardware, all the basic moral and ethical rules regarding artificial intelligence can be permanently implemented in the analog artificial neural network. These rules can be changed only within known limits, or may not be changeable.

[0018] Furthermore, since the analog artificial neural network runs on a semiconductor chip that does not require an external access connection, it is impossible to hack the analog artificial neural network.

[0019] In one example, the analog artificial neural network includes analog electronic nodes and an analog connection architecture between the analog electronic nodes. In the step of manufacturing the semiconductor chip, the analog electronic nodes and the analog connection architecture are manufactured to correspond to the digital nodes and the digital connection architecture of a learned first digital artificial neural network.

[0020] Analog electrical components may form analog electronic nodes and an analog connection architecture between the analog electronic nodes. The bias, weight, transfer function, and activation function of the analog electronic nodes correspond to the bias, weight, transfer function, and activation function of the digital nodes of a learned first digital artificial neural network. Furthermore, the electrical wires between the analog electronic nodes forming the analog connection architecture correspond to the digital connections between the digital nodes.

[0021] In one example, the analog artificial neural network of the semiconductor chip includes analog electronic nodes and an analog connection architecture between the analog electronic nodes, and the analog electronic nodes and the analog connection architecture respectively correspond to the digital nodes and the digital connection architecture of a learned first digital artificial neural network.

[0022] In a further example, the analog artificial neural network may include at least one analog electronic switch and / or at least one analog electronic node.

[0023] The analog electronic switch may be configured to interrupt or establish an electrical connection between analog nodes of different layers of the analog artificial neural network. For example, a switch array may be disposed between the input layer and the first hidden layer of the analog artificial neural network. That is, the electrical connection between each node of the input layer and each node of the first hidden layer is composed of analog electronic switches. And the switch array can control the propagation of electrical signals through the analog artificial neural network. The analog artificial neural network processes electrical signals only when the switch array does not interrupt the electrical connection between the input layer and the first hidden layer. Therefore, the switch array can control the start of the operation of the analog artificial neural network. Of course, the electrical connection of the analog artificial neural network may include an analog electronic switch that controls the propagation of electrical signals.

[0024] The analog electronic switch may include, for example, a transistor and / or a field effect transistor. Further, the analog electronic switch can be controlled by a controller that provides a control signal. The semiconductor chip can include, for example, the controller. Or, the controller and the semiconductor chip may be separate components.

[0025] Furthermore, for example, the input can include a sensor array configured to simultaneously provide sensor data signals from respective sensors to the analog artificial neural network.

[0026] All sensors of the sensor array can provide corresponding sensor signals simultaneously. For example, the sensor array may include a pixel array. The pixel array can include, for example, active pixel sensors. Further, the sensors of the sensor array can, for example, sequentially and additionally provide corresponding sensor signals. And the sensor array functions simultaneously as an input to an analog artificial neural network and a second digital artificial neural network. In another example, the sensor array can include an olfactory sensor array, a pressure sensor array, an ultrasonic sensor array, a temperature sensor array, and / or an acoustic sensor array.

[0027] In another example, the analog electrical circuit may be composed only of electronic components with fixed characteristics, and the analog artificial neural network may not be trained.

[0028] In this example, the analog artificial neural network is fixed and may not be trained. In this example, a semiconductor chip that is easy to manufacture and cost-effective is provided together with the analog artificial neural network, whereby the analog artificial neural network can be trained.

[0029] In a further example, the analog electrical circuit can include at least one electronic component with changeable characteristics.

[0030] In this example, the analog artificial neural network can be trained by changing the characteristics of the at least one electronic component. The at least one electronic component having changeable characteristics may be, for example, an adjustable resistor or an analog electronic switch. The adjustable resistor can, for example, electrically connect two nodes and adjust the weight of the electrical connection between those nodes. The analog electronic switch can, for example, switch the on / off of the electrical connection between two nodes. The fewer the electronic components having changeable characteristics present in the analog artificial neural network, the lower the training ability of the analog artificial neural network.

[0031] According to a third aspect of the present invention, there is provided a device including at least one semiconductor chip and at least one controller as described above, the controller being configured to provide at least one control signal to the semiconductor chip, the control signal preferably being a start signal of a sensor array of the semiconductor chip, the controller preferably including at least one of a group of an analog electrical control circuit, a digital electrical control circuit, a control program, and a processor, the semiconductor chip further preferably including a control input configured to receive the start signal, and more preferably, the sensor array is configured to further provide a sensor data signal when receiving the start signal.

[0032] In one example, the controller may be further configured to provide a reset signal for resetting the analog electrical circuit. In one example, the system may further include at least one interface configured to control and transfer data and configured to recursively couple the semiconductor chip to a second digital artificial neural network, the interface preferably being configured to provide at least one analog control signal to the analog artificial neural network, the interface preferably further being configured to receive an analog output signal from the semiconductor chip, and by generating a digital control signal from the analog output signal and providing at least one digital control signal to at least one digital node in at least one hidden layer of the second digital artificial neural network, the interface recursively couples the semiconductor chip to the second digital artificial neural network.

[0033] The interface can convert the analog output signal of the analog artificial neural network into a digital control signal. At least one digital node in the hidden layer of the second trained artificial neural network receives the digital control signal. The digital signals affect the operation of those digital nodes and as a result affect the output of those digital nodes. Thus, the analog artificial neural network affects the operation of the second trained artificial neural network.

[0034] The advantages, effects, and further developments of the system result from the advantages, effects, and further developments of the semiconductor chip and device described above. Reference is made to the above description in this regard. In a further example, the input projection layer can include at least one of a group of a pixel array, an olfactory sensor array, a pressure sensor array, an ultrasonic sensor array, a temperature sensor array, and an acoustic sensor array.

[0035] According to another aspect of the present invention, there is provided a method of manufacturing a system according to the above description, the manufacturing method including at least: a step of separately training a second digital artificial neural network without providing the output from the analog artificial neural network to the second digital artificial neural network; a step of providing a semiconductor chip having an analog artificial neural network separately trained, wherein the training of the analog artificial neural network is performed without providing the output of the analog artificial neural network to the second digital artificial neural network; a step of recursively connecting the semiconductor chip to the separately trained second digital artificial neural network so that the output of the analog artificial neural network is provided to at least one hidden layer of the second digital artificial neural network; and a step of jointly training the analog artificial neural network recursively connected to the semiconductor chip and the separately trained second digital artificial neural network.

[0036] The recursive connection between the semiconductor chip and the separately trained second digital artificial neural network includes the recursive connection between the analog artificial neural network and the separately trained second digital artificial neural network.

[0037] In the step of jointly training an analog artificial neural network recursively connected to a semiconductor chip and a second digital artificial neural network trained individually, the analog artificial neural network may remain fixed. Then, the training consists of the training of the second digital artificial neural network trained individually, while the analog artificial neural network affects the second digital artificial neural network trained individually. Alternatively, the analog artificial neural network may be trainable such that the training also includes the training of the analog artificial neural network. The advantages, effects, and further developments of the method for manufacturing the system result from the advantages, effects, and further developments of the semiconductor chip, device, system, and method for manufacturing the semiconductor chip described above. Reference is made to the foregoing description in this regard.

[0038] In one example, the step of providing a semiconductor chip with an analog artificial neural network trained individually may include at least the following sub-steps, namely, the step of training the first digital artificial neural network individually.

[0039] Therefore, before the manufacturing of the analog artificial neural network, the first digital artificial neural network is trained. Next, a semiconductor chip is manufactured using the trained first digital artificial neural network according to the above-described method for manufacturing the semiconductor. Next, a semiconductor chip is manufactured using the trained first digital artificial neural network according to the above-described method for manufacturing the semiconductor.

[0040] Alternatively or additionally, the analog artificial neural network may be trained in an analog electrical circuit including analog electronic components having adjustable characteristics.

[0041] Furthermore, for example, an individually trained analog artificial neural network can be provided to a semiconductor chip using a first training dataset. Preferably, the second digital artificial neural network is trained using a second training dataset, and more preferably, a third training dataset is used to train together the analog artificial neural network and the individually trained second digital artificial neural network.

[0042] The first training dataset can be adapted for training the analog artificial neural network. The second training dataset can be adapted for training the second digital artificial neural network. The third training dataset can be adapted to train together the analog artificial neural network and the second digital artificial neural network. Thus, the training is performed more efficiently. Hereinafter, exemplary embodiments will be used to describe the present invention with reference to the accompanying drawings.

Brief Description of the Drawings

[0043]

Fig. 1a-1b

Fig. 1c

Fig. 2a-2b

Fig. 3a

Fig. 3b

Fig. 4

Fig. 5

Fig. 6a-6h

Fig. 7a-7g

Fig. 8

Fig. 9a-9b

Fig. 10

Fig. 11

Fig. 12

DETAILED DESCRIPTION OF THE INVENTION

[0044] Figure 1a shows a schematic diagram of an analog artificial neural network 10. The analog artificial neural network 10 is implemented as an analog electrical circuit on a semiconductor chip 40, as shown in Figure 1c. This means that the analog artificial neural network 10 cannot be reprogrammed by modifying software. The physical structure of the analog artificial neural network 10 is fixed. The analog electrical circuit is connected as hardware, and the analog artificial neural network 10 is also connected as hardware.

[0045] The analog electrical circuit includes an input 20 and an output 26, and the analog artificial neural network 10 electrically connects the input 20 to the output 26.

[0046] As shown in FIG. 1a, the analog artificial neural network 10 may include an input layer 11, at least one hidden layer 12, and an output layer 13. All layers may include at least one analog electronic node constructed from analog electrical components. The analog electronic node includes a node input and a node output.

[0047] FIG. 1a shows an analog electronic node within the hidden layer 12 as an example of an analog electrical component. This does not limit the analog electronic nodes to those analog electrical components.

[0048] Furthermore, this example shows two hidden layers 12. Of course, the analog artificial neural network may be composed of only one hidden layer 12 or may be composed of two or more hidden layers 12.

[0049] The node input of the input layer 11 may be electrically connected to the input 20. According to the example shown in FIG. 1a, the input 20 may be the input layer 11. The electrical signal from the input 20 may propagate to the node input of the input layer 11.

[0050] The input 20 may be a sensor array, for example, a two-dimensional pixel array that collects light emitted or reflected from the object 31. In this example, the object 31 is an image.

[0051] The node output of the output layer 13 may be electrically connected to the output 26. The electrical signal from the node output of the output layer 13 may propagate to the output 26.

[0052] The nodes of at least one hidden layer 12 are electrically connected to the nodes of the input layer 11 and / or the nodes of the output layer 13. The electrical lines 18, 19 can provide an electrical connection between the node output and the node input.

[0053] The electrical wire 18 connects a node output close to the input 20 to a node input close to the output 26. Therefore, an electrical signal propagates along the electrical wire 18 in the forward direction from the input 20 towards the output 26.

[0054] The electrical wire 19 connects a node output close to the output 26 to a node input close to the input 20. In this example, the electrical wire 19 only connects the nodes of the hidden layer 12. Therefore, the electrical wire 19 can connect a node output to a node input of the same node or a node input of a node closer to the input 20. Therefore, an electrical signal propagates along the electrical wire 19 in the reverse direction from the output 26 towards the input 20.

[0055] Between the input layer 11 and the first hidden layer 12 shown on the lower side in FIG. 1a, the analog artificial neural network 10 may include a switching layer 33. The switching layer 33 can have at least two switching states. In the first switching state, the switching layer 33 can interrupt the electrical connection between the nodes of the input layer 11 and the remaining nodes of the analog artificial neural network 10. In the second switching state, the switching layer 33 can establish an electrical connection between the nodes of the input layer 11 and the remaining nodes of the analog artificial neural network 10, for example, the nodes of the first hidden layer 12. Thereby, it becomes possible to start and stop the processing of the input signal by the analog artificial neural network 10. The switching layer 33 can simultaneously switch all the electrical connections between the input layer 11 and the remaining layers.

[0056] As shown in FIG. 1b, the switching layer 33 can include at least one analog electronic switch 34. The analog electronic switch 34 can include, for example, a field effect transistor with a control signal input. The control signal at the gate of the field effect transistor can switch the on / off of the analog electronic switch 34. For example, when the control signal has a negative voltage UB, the analog electronic switch 34 can be turned off, and the electrical connection between the drain and the source can be interrupted. For example, when the control signal has a positive voltage UB, the analog electronic switch 34 can be turned on, and the electrical connection between the drain and the source is established.

[0057] The controller 35 can provide a control signal via the control input 36. The controller 35 may be a component of the semiconductor chip 40. Alternatively, the controller 35 and the semiconductor chip 40 may be separate components of the device (not shown).

[0058] Furthermore, the controller 35 can supply an output control signal to the output layer 13 via the control signal line 84. The controller 35 may further include an analog electrical control circuit for controlling the analog artificial neural network 10. Furthermore, the controller 35 may include a digital electrical control circuit for controlling the second digital artificial neural network 50. Additionally, the controller 35 includes a control program and a processor, and the control program executed on the processor can control the control circuit.

[0059] By analog signal processing, the analog artificial neural network 10 is much faster than a digital artificial neural network with the same network structure and the same training level.

[0060] FIG. 2a shows a schematic diagram of a trained first digital artificial neural network 17 that functioned as a master for the manufacture of the analog artificial neural network 10 shown in FIG. 2b.

[0061] The vertical arrow 14 indicates a digital input signal. Arrow 15 indicates the processing order of the digital nodes of the trained first digital artificial neural network 17. This indicates that the digital input signals are input one after another in sequence. Furthermore, the digital nodes are processed one after another in sequence, and the processing speed is determined by the number of nodes.

[0062] The vertical arrow 16 in FIG. 2b indicates the processing order of the analog nodes of the analog artificial neural network 10. All the nodes in one layer operate simultaneously. Therefore, the processing speed is determined by the number of layers. Usually, since the number of nodes is larger than the number of layers, the analog artificial neural network 10 processes signals much faster than the trained first digital artificial neural network 17. As a result, the analog artificial neural network 10 provides output data earlier than the trained first digital artificial neural network 17.

[0063] FIGS. 3a and 3b show an example of a sensor array of inputs 20 that can provide input signals to each node of the input layer 11 of the analog artificial neural network 10 simultaneously. In order to collect the signals from the inputs 20 simultaneously, the inputs 20 may not operate as charge-coupled devices.

[0064] FIG. 3a shows a schematic diagram of a pixel line of a two-dimensional array of photodiodes 21. Each photodiode 21 is connected to the base of a transistor 22. FIG. 3b shows a schematic diagram of a pixel line of a two-dimensional array of phototransistors 23. In either example, each pixel includes transistors 22, 23 for amplifying the resulting signal. These components can be active pixel sensors known from the prior art. Such a pixel architecture allows all the pixels of one array to be read simultaneously. Furthermore, with that pixel architecture, pixel signals can also be provided sequentially.

[0065] By designing the analog artificial neural network 10 such that the input layer 11 directly processes the signals of the sensor array of the input 20, it becomes unnecessary to normalize the signals of the sensor array. Therefore, the analog nodes of the input layer 11 may be the sensors of the sensor array. This may further accelerate the processing speed of the analog artificial neural network 10.

[0066] It is obvious that the sensor array can include sensors of any type and number, such as olfactory sensors, pressure sensors, ultrasonic sensors, temperature sensors, and / or acoustic sensors.

[0067] FIG. 4 shows an example of a controllable sensor 21 of the input 20. The sensor is a photodiode 21 connected to the base of a first field-effect transistor 43. The first field-effect transistor 43 amplifies the signal of the photodiode 21. The second field-effect transistor 42 can reset the signal of the photodiode 21 when a reset control signal is applied. The third field-effect transistor 44 can turn on the amplification of the first field-effect transistor 43 when receiving a read control signal.

[0068] The reset control signal and the read control signal are provided by the controller 35 via the control input 36 shown in FIG. 1a.

[0069] Passive electrical components such as resistors and capacitors are omitted in FIG. 4 for clarity. However, the dimensions of passive electrical components in such electronic circuits are known in the prior art.

[0070] The following discussion refers to the design process of the analog nodes of the hidden layer 12 of the analog artificial neural network 10. Analog electronic nodes mimic the functions of biological neurons and implement basic mathematical operations such as AND, NOR, OR, NAND, etc. Therefore, in the design process of the analog electrical circuit representing the analog electronic node, all node parameters need to be adaptable.

[0071] Figure 5 shows the basic mathematical definition of a node for programming a digital artificial neural network. The node links a plurality of input signals x1, …, xn from a plurality of previous nodes, and each input signal is weighted with weights w1j…wnj. The weights can be positive, negative, or zero, and zero means that the connection to the corresponding previous node is off.

[0072] The transfer function Σ links the input signals, for example, by summing the input signals. However, the transfer function can also perform multiplication, Boolean operations, differentiation, integration, or other logical operations.

[0073] The activation function Φ determines the output signal O of the node J . The output signal can be a Gaussian bell function, a jump function, a rectangular signal, a cylindrical function, a sigmoid, etc. A threshold or bias θ J may affect the activation function.

[0074] When converting digital nodes to analog circuit technology, the design can be based on basic circuit variations of the passive four-terminal theory of electrical engineering and analog circuits of operational amplifiers.

[0075] The examples shown in FIGS. 3a to 5 have a clear transfer function and show examples of "reasonable" known electronic circuits for use. Such circuits map neurons, for example. However, it is also conceivable to use electronic circuits that are "unreasonable" in the electronic sense. For example, an electronic circuit having passive and active components that do not reproduce neurons as basic elements. These basic elements only have defined inputs and outputs, and the connections between different basic elements are non-temporary, for example, they cannot be destroyed but can be changed. The circuits established between these basic elements may be such that technically defined objects are not solved. For example, these basic elements may not mimic neurons. However, even such circuits can provide the function of an artificial neural network.

[0076] Figures 6a to 6h show examples of basic analog electrical circuits that can implement the characteristics described in FIG. 5. Some or all of the examples can be arbitrarily combined to provide an analog electronic node. FIGS. 6a and 6b show passive electronic components, and FIGS. 6c to 6h show active electronic components, for example, operational amplifiers.

[0077] FIG. 6a shows a voltage divider for weighting an input signal. FIG. 6b shows a circuit that shifts any function around the zero line to implement a bias or threshold. FIG. 6c shows a circuit including an operational amplifier for adding two inputs U e1 and U e2 . FIG. 6e shows a circuit including an operational amplifier for subtracting inputs V1 and V2. The circuit of FIG. 6d represents a combination of mixing, adding, and amplifying different signals. FIG. 6f is a circuit including an operational amplifier for differentiating an input signal. FIG. 6g shows an integrator. FIG. 6h shows a non-inverting comparator that enables adjacent conversion of a function curve.

[0078] FIG. 7a shows yet another example of a circuit with an operational amplifier. In this example, an offset can be introduced into the signal as an implementation of bias. Further, by adding resistors and / or capacitors and linking them together with the operational amplifier, any function can be implemented. Examples of these functions are shown in FIGS. 7b to 7h. FIG. 7b shows a one-dimensional Gaussian bell. FIG. 7c shows a conical function. FIG. 7d shows a cylindrical function. FIG. 7e shows a Mexican hat function. FIG. 7f shows a hyperbolic tangent function. FIG. 7g shows a Fermi function with a temperature parameter.

[0079] The nodes of the hidden layer 12 may be implemented according to the state of the trained first digital artificial neural network 17. The state includes at least information regarding the digital nodes of the trained first digital artificial neural network 17 and information regarding the digital connection architecture between the digital nodes of the trained first digital artificial neural network 17. The state of each digital node of the trained first digital artificial neural network 17 is determined.

[0080] The information may include information regarding biases, transfer functions, activation functions, and / or weights. The information regarding the digital connection architecture may include information regarding the connections between nodes.

[0081] The information regarding the digital nodes of the trained first digital artificial neural network is used, for example, to design analog electronic nodes using an analog electrical circuit such as the circuit described above. The information regarding the digital connection architecture is used to design the electrical wires between nodes, and an analog connection architecture is generated.

[0082] The analog electronic nodes and the analog connection architecture are implemented as an analog electrical circuit on the semiconductor chip 40.

[0083] The analog electronic nodes and / or the analog connection architecture may include non-adaptable electronic components with fixed characteristics. In this case, the analog artificial neural network 10 cannot learn.

[0084] To provide a learnable analog artificial neural network 10, the analog electrical circuit can include adaptable electronic components. Those electronic components may have changing characteristics.

[0085] Since the analog artificial neural network 10 is based on a trained digital artificial neural network, only a very small part of the analog electronic nodes and / or analog connection architecture requires such electronic components with changeable characteristics.

[0086] Some of these analog electronic nodes and / or parts of the analog connection architecture can be connected to electronic components with variable characteristics, such as digital potentiometers and varactor diodes. The controller can control those electronic components during the training of the analog artificial neural network 10.

[0087] Figure 8 shows an example of using a field-effect transistor to bypass resistors R L1 ~R L3 to create a variable resistor R L . The controller can individually control each field-effect transistor using the control signal of the corresponding gate. When the field-effect transistor is turned on, the corresponding resistor is bypassed.

[0088] Similarly, as shown in Figure 9a, the electrical connections 102, 103 between nodes 101 can be established or interrupted. Circuit 104 shows a field-effect transistor in electrical wire 103. When the field-effect transistor is off, the field-effect transistor blocks electrical wire 103.

[0089] Figure 9b shows wire 103 having circuit 104. Further, wire 103 includes a voltage divider 105. The voltage divider 105 functions as the weight of the signal propagating along wire 103. Therefore, to implement the weights of digital nodes in an analog electronic circuit, it may be sufficient to implement those weights in the analog connection architecture. This simplifies the implementation of the analog artificial neural network 10.

[0090] Line 103 can include, for example, a plurality of different voltage dividers that are switched by corresponding field effect transistors. Next, the weight of line 103 may be changed according to the number of different voltage dividers that are active. This can be an exemplary method for training the analog artificial neural network 10.

[0091] To train the analog artificial neural network 10, the controller 35 may include a training algorithm that can be implemented as known in digital artificial neural networks. Thereby, the controller 35 may be able to control electronic components having changeable characteristics to execute the training process. In the final training state, the controller 35 can provide a corresponding switching signal to the semiconductor chip 40 when the analog artificial neural network 10 processes a signal.

[0092] FIG. 10 shows a system 110 including an input projection layer 111, a semiconductor chip 40, and a second digital artificial neural network 50. The second digital artificial neural network 50 may be a trained digital neural network. Further, the system 110 may include a controller 35 and an analog-digital interface 112. The interface 112 receives the analog output signal of the semiconductor chip 40, that is, the analog artificial neural network 10. The interface 112 converts the analog output signal into a digital signal and transfers it to the digital nodes of the second digital artificial neural network 50. The digital nodes may be arranged in the hidden layer of the second digital artificial neural network 50.

[0093] Thereby, the analog artificial neural network 10 and the second digital artificial neural network 50 are recursively coupled.

[0094] For example, the analog artificial neural network 10 can provide an output signal that roughly classifies the elements of the image 31 into, for example, dangerous elements and harmless elements. The second digital artificial neural network 50 can identify, for example, the image elements of the image 31. The category of the image elements provided by the analog artificial neural network may affect the identification of the image elements by the second digital artificial neural network.

[0095] The input projection layer 111 can supply input signals to both neural networks 10 and 50. The input projection layer 111 may be the input layer 11 of the analog artificial neural network 10. The analog artificial neural network 10 receives the input signals of all the nodes in the input layer 11 simultaneously. The second digital artificial neural network 50 receives the input signals sequentially.

[0096] The controller 35 can synchronize the operation of the analog artificial neural network 10 with that of the second digital artificial neural network 50. For example, the controller 35 can provide a start signal to the analog artificial neural network 10 when the second digital artificial neural network 50 starts operating. Due to the start signal, the switching layer 33 can establish a connection between the input layer 11 and the first hidden layer 12 of the analog artificial neural network. Furthermore, the controller 35 may reset the analog artificial neural network 10 after the operation of the system 110.

[0097] FIG. 11 shows a flowchart of a method 120 for manufacturing a semiconductor chip. In a first step 121, a trained first digital artificial neural network is provided. The trained first digital artificial neural network performs a specific task with sufficient accuracy. The trained first digital artificial neural network is a software-based artificial neural network executed on an IT platform. The training of the trained first digital artificial neural network can be performed using training data as known in the prior art.

[0098] Then, in the next step 122, the state of the trained first digital artificial neural network is determined. This state includes information regarding the digital nodes and digital connection architecture of the trained first digital artificial neural network.

[0099] The state completely characterizes the trained first digital artificial neural network, such as weights, transfer functions, activation functions, biases of nodes, etc. Further, the state characterizes the connections between the digital nodes of the trained first digital artificial neural network, i.e., the digital connection architecture.

[0100] In a further step 123, a semiconductor chip is manufactured. In the manufacturing process, an analog electrical circuit forming an analog artificial neural network is designed. The state of the trained first digital artificial neural network is implemented in the design of the analog artificial neural network.

[0101] For example, an analog artificial neural network may include analog electronic nodes and an analog connection architecture between the analog electronic nodes. The analog electronic nodes are designed according to the digital nodes of a trained first digital artificial neural network. If the trained first digital artificial neural network is composed of a hidden layer with 10 digital nodes, the analog artificial neural network is implemented with a hidden layer having 10 analog nodes including the same weights, transfer functions, activation functions, and biases as the first trained artificial neural network.

[0102] Thereby, the analog connection architecture is designed according to the digital connection architecture. Therefore, if a specific digital node is further connected to a series of digital nodes, the corresponding analog electronic node is connected to a set of corresponding analog electronic nodes.

[0103] By the manufacturing method 120, a semiconductor chip as described above is obtained. FIG. 12 shows a flowchart of a manufacturing method 130 of a system in which an analog artificial neural network is recursively connected to a second digital artificial neural network.

[0104] In step 131, the second digital artificial neural network is trained individually. In the next step 132, a semiconductor chip with an individually trained analog artificial neural network is provided. The semiconductor chip can include any number of individually trained analog artificial neural networks.

[0105] Step 132 may be executed simultaneously with Step 131. Alternatively, Step 131 and Step 132 may be executed in any order. An analog artificial neural network can be trained to provide a semiconductor chip including an analog artificial neural network trained separately. Alternatively or additionally, a trained first digital artificial neural network may be trained before manufacturing the semiconductor chip.

[0106] In another step 133, the semiconductor chip is recursively coupled to a separately trained second digital artificial neural network. The above-described interface may be used for the recursive coupling.

[0107] After step 133, in step 134, the analog artificial neural network and the separately trained second digital artificial neural network are trained together. In that training, the separately trained second digital artificial neural network receives an input from the analog artificial neural network.

[0108] In the individual training of the analog artificial neural network and / or the first digital artificial neural network underlying the analog artificial neural network, a first training data set may be used.

[0109] The individual training of the second digital artificial neural network may be performed by a separate second training data set. In the joint training of the analog artificial neural network and the second digital artificial neural network, a third training data set may be used.

[0110] Each training data set can be optimized according to a specific training purpose. That is, the first training data set can be optimized to provide an output signal that may affect the operation of the second digital artificial neural network.

Claims

1. A system comprising an input projection layer (111), at least one second digital artificial neural network (50), and at least one semiconductor chip (40) obtained by at least the following steps: Said steps are: Step (121) of providing a trained first digital artificial neural network (17); A step of determining the state of the trained first digital artificial neural network (17), said state including at least information regarding the digital nodes of the trained first digital artificial neural network (17) and information regarding the digital connection architecture between the digital nodes of the trained first digital artificial neural network (17), step (122); A step of manufacturing the semiconductor chip (40), including an analog electrical circuit having an analog artificial neural network (10) designed according to the state of the trained first digital artificial neural network (17), step (123), Said analog electrical circuit comprises at least one input (20) configured to receive at least one input signal and at least one output (26) configured to provide at least one analog output signal; Said analog artificial neural network (10) electrically connects the input (20) to the output (26); Said semiconductor chip (40), in particular said analog artificial neural network (10), is recursively coupled to the second digital artificial neural network (50); The output of the semiconductor chip (40) is provided to at least one hidden layer of the second digital artificial neural network (50); A system wherein the input (20) of the semiconductor chip (40) and the input layer of the second digital artificial neural network (50) are electrically connected to the input projection layer (111).

2. The system according to claim 1, wherein the analog artificial neural network (10) comprises analog electronic nodes and an analog connection architecture between the analog electronic nodes. In the step of manufacturing the semiconductor chip (40), the analog electronic node and the analog connection architecture are manufactured to correspond to the digital nodes and the digital connection architecture of the learned first digital artificial neural network (17).

3. The system according to claim 1 or 2, wherein the analog artificial neural network (10) includes at least one analog electronic switch (34) and / or at least one analog electronic node.

4. The system according to any one of claims 1 to 3, wherein the input (20) includes a sensor array configured to simultaneously provide sensor data signals from each sensor (21, 23) to the analog artificial neural network (10).

5. The system according to any one of claims 1 to 4, wherein the analog electrical circuit includes only electronic components having fixed characteristics so that the analog artificial neural network (10) cannot be trained.

6. The system according to any one of claims 1 to 5, wherein the analog electrical circuit includes at least one electronic component having changeable characteristics so that the analog artificial neural network (10) can be trained.

7. The system according to any one of claims 1 to 6, comprising at least one controller (35), wherein the controller (35) is configured to provide at least one control signal to the semiconductor chip (40), the control signal is a start signal for the sensor array of the semiconductor chip (40), the controller (35) includes at least one of a group consisting of an analog electrical control circuit, a digital electrical control circuit, a control program, and a processor, the semiconductor chip (40) further includes a control input (36) configured to receive the start signal, and the sensor array is further configured to provide a sensor data signal when the start signal is received.

8. The system according to any one of claims 1 to 7, The system (110) further includes at least one interface (112) configured to recursively couple the semiconductor chip (40) to the second digital artificial neural network (50) for controlling and transferring data, The interface (112) provides at least one analog control signal to the analog artificial neural network (10), The interface (112) is, Receives an analog output signal from the semiconductor chip (40), generates a digital control signal from the analog output signal, Provides at least one digital control signal to at least one digital node in at least one hidden layer of the second digital artificial neural network (50), A system in which the interface (112) is configured to recursively couple the semiconductor chip (40) to the second digital artificial neural network (50).

9. A system according to any one of claims 1 to 8, The input projection layer (111) includes at least one of a group of a pixel array, an olfactory sensor array, a pressure sensor array, an ultrasonic sensor array, a temperature sensor array, and an acoustic sensor array. A system.

10. A method of manufacturing a system according to any one of claims 1 to 9, The manufacturing method (130) includes at least, A step (131) of separately training the second digital artificial neural network without providing the output from the analog artificial neural network to the second digital artificial neural network, A step of providing the semiconductor chip provided with the analog artificial neural network trained separately, wherein the training of the analog artificial neural network is performed without providing the output of the analog artificial neural network to the second digital artificial neural network. Step (132), A step of recursively connecting the semiconductor chip to the second digital artificial neural network trained separately, such that the output of the analog artificial neural network is provided to at least one hidden layer of the second digital artificial neural network. Step (133), A method of manufacturing a system, comprising: a step (134) of jointly training the analog artificial neural network recursively connected to the semiconductor chip and the second digital artificial neural network individually trained.

11. A method of manufacturing a system according to claim 10, wherein the step (132) of providing the semiconductor chip with the analog artificial neural network individually trained includes, as a sub-step, at least a step (135) of individually training the first digital artificial neural network.

12. A method of manufacturing a system according to claim 10 or 11, wherein a first training data set is used to provide the semiconductor chip with the analog artificial neural network individually trained, the second digital artificial neural network is trained with a second training data set, and a third training data set is used to jointly train the analog artificial neural network and the second digital artificial neural network individually trained.

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