Spike Interconnect On-Chip Single Packet Multicast

Abstract

A method for routing spikes in a neuromorphic processor, the neuromorphic processor comprising a plurality of neuromorphic array cores each having an associated router. The method comprises generating spike data representing spikes (plural) generated by neurons (plural) in a source neuromorphic array core. A spike data packet is generated that includes the spike data, a destination vector, and source core identification information. The spike data packet is transmitted to one or more of the routers. Based on the destination vector, it is determined whether the receiving neuromorphic array core is the destination. If so, the spike data is sent to the receiving neuromorphic array core. Further, it is determined whether there are additional destinations. If so, the destination vector is updated. Further, one or more next destinations are determined, and the spike data packet or a copy of the spike data packet is sent to one or more output ports of the router.

Description

Technical Field

[0001]

[0001] This disclosure generally relates to neuromorphic processors, and more particularly, to a neuromorphic array that forms a Spike Interconnect on Chip, and a routing method used to communicate between different cores of the neuromorphic array.

Background Art

[0002]

[0002] Neuromorphic computing is an approach to computing inspired by the structure and function of the human brain. In a biological neural network model, each individual neuron communicates asynchronously and through sparse events, or spikes. In such an event-based spiking neural network (SNN), only the neurons that change state generate spikes, which can trigger signal processing in subsequent layers, thus saving computing resources.

[0003]

[0003] An SNN encodes information not as integer or real-valued vectors, but in the form of one or more precisely time-stamped (voltage) spikes. Computation for inference (i.e., inferring the presence of a particular feature in an input signal) is effectively performed in the analog and time domains. For this reason, SNNs are typically implemented in hardware as full-custom mixed-signal integrated circuits. This allows them to perform inference functions with several orders of magnitude lower energy consumption than their artificial neural network counterparts.

[0004]

[0004] Therefore, a neuromorphic processor generally comprises an array of spiking neurons and synapses. Thus, a spiking neuron receives inputs from one or more synapses and generates a spike when the input reaches a certain predetermined threshold. The exact timing at which a spike occurs depends on the intensity and sequence of the input stimulus.

[0005]

[0005] An SNN consists of a network of spiking neurons interconnected by synapses that determine the strength of the connections between the spiking neurons. This strength is represented as a weight, which moderates the effect of the output of the presynaptic neuron on the input to the postsynaptic neuron. Typically, these weights are set in a training process that involves exposing the network to a large amount of labeled input data and gradually adjusting the synaptic weights until the desired network output is achieved.

[0006]

[0006] An SNN can be directly applied to pattern recognition and sensor data fusion based on the principle that the features in the input signal in the amplitude domain, time domain, and frequency domain can be encoded into a unique spatially and temporally encoded spike sequence.

[0007]

[0007] The generation of these sequences relies on the use of one or more ensembles of spiking neurons, where an ensemble is a collaborative group of neurons. Each ensemble performs a specific signal processing function, such as feature encoding, conditioning, filtering, data fusion, classification. Each ensemble is composed of one or more interconnected layers of spiking neurons, with the connectivity within and between layers following a certain topology. The size (number of neurons), their connectivity (synaptic topology and number), and their configuration (number of layers and weights) of each ensemble depend on the characteristics of the input signal, such as the dynamic range, bandwidth, time scale, or complexity of the features in the input signal.

[0008]

[0008] Generally, as the complexity of the features to be recognized in the input signal increases, the size of the ensemble required to process them also increases. Spiking neural network hardware can utilize an array of configurable spiking neurons and synapses, connected using a programmable interconnect structure that facilitates the implementation of any arbitrary connection topology. However, to implement a large ensemble, the underlying SNN hardware needs to have at least the required number of neurons and synapses.

[0009]

[0009] The need for a network-on-chip architecture arises from the communication throughput efficiency being evaluated according to certain criteria such as the channel capacity, latency, temporal dispersion (i.e., latency distribution), and channel integrity (i.e., the success rate of spike delivery to the correct destination) of the communication channels between arrays of neurons, which is independent of the implementation and thus valid for both analog or digital / discrete implementations of those arrays.

[0010]

[0010] In PCT / EP2019 / 081662, it was proposed to partition an SNN into a plurality of sub-networks. Each sub-network comprises a subset of spiking neurons connected to receive synaptic output signals from a subset of synaptic elements. Further, each sub-network is adapted to generate a sub-network output pattern signal in response to a sub-network input pattern signal applied to the sub-network. Further, each sub-network forms part of one or more cores in an array of cores, each core comprising a programmable network of spiking neurons implemented in hardware or a combination of hardware and software, and the communication between cores within the core array is arranged through a programmable interconnect structure.

[0011]

[0011] The resulting neuromorphic processor may form a neuromorphic array that may include a plurality of interconnected neuromorphic array (NMA) cores. Such interconnects may form a network of cores, which may be on a single chip and may form a network on chip (NoC).

[0012]

[0012] By partitioning a large spiking neural network into smaller sub-networks and implementing each sub-network on one or more cores, the amount of neurons in each core can be reduced, and these cores can communicate with each other via the NoC.

[0013]

[0013] An ensemble of neurons forming a sub-network, or a collaborative group, may form, for example, a classifier, an ensemble of classifiers, a group of neurons, etc., that handle only data conversion, feature encoding, or classification.

[0014]

[0014] In such a regime, a large network of the ensemble is partitioned and mapped onto an array of cores, each of which includes a programmable network of spiking neurons. As a result, each core may implement a single ensemble (related to the number of neurons and synapses in the core), multiple small ensembles, or, in the case of a large ensemble, only a part of a single ensemble, with other parts being implemented on other cores of the array. The modality of how the ensemble is partitioned and mapped to the cores is determined by the mapping technique.

[0015]

[0015] The mapping method may include constraint-driven partitioning, but other mapping methods are also possible. The constraints can be performance metrics linked to the functions of each respective subnetwork. The performance metrics can depend on the number of hops for a packet to move between cores, the minimum distance between cores, power-area limitations, memory structure, memory access, time constants, biases, technology limitations, resilience, the level of allowed mismatch, and / or the network or physical artifacts.

[0016]

[0016] The periphery of the array includes a column of synapse circuits that mimic the action of the cell bodies and axon hillocks of biological neurons. Further, each neurosynaptic core in the array has a local router that communicates with the routers of other cores within a dedicated real-time reconfigurable network-on-chip.

[0017]

[0017] The local routers and their connections form a programmable interconnect structure between the cores of the core array. These cores can be connected through a switchable matrix. Different cores of the core array are thus connected via the programmable interconnect structure. In particular, different parts of a spiking neural network implemented on different cores of the core array are interconnected through the programmable interconnect structure. In this way, quantum effects and external noise act only individually on each core and not on the network as a whole. Thus, these effects can be mitigated if relevant.

[0018]

[0018] A spiking neural network implemented on a core array can have high modularity in the sense that the spiking neural network has dense connections between neurons within a core but sparse connections between different cores. In this way, noise and quantum effects are further reduced between cores, while still allowing sub-networks to increase classification accuracy, for example, by enabling high complexity.

[0019]

[0019] Communication between neurons in a neuromorphic array involves spike events. Spike events can be encoded simply as the identifier of the neuron in which the spike occurred, or additionally as a relative timestamp (e.g., for the previous spike that occurred) at which the event was generated, and the magnitude of the spiking response generated by the neuron. Across all modalities, every time a spike occurs, the spike needs to be communicated to all synapses to which the spiking neuron is connected. Spike events are relayed to other cores in a data packet called a spike packet.

[0020]

[0020] A spike packet is a communication unit between NMA cores that generates spikes and also consumes different spikes.

[0021]

[0021] A programmable interconnect structure can form a packet-switched network between cores in a core array. These connections can form a digital network. Data can be, for example, an output of one of the sub-networks of a spiking neural network implemented on one or more cores of the core array.

[0022]

[0022] Routing these spike packets involves charting a path with several spike routers and physical links through which the spike packets are forwarded according to a routing algorithm to reach the destination node from the source node. The spike routers present at all nodes may have multiple input and output ports. Each spike router has an ID, and the spike packet may include a destination spike router ID for an intermediate spike router(s) to route the spike packet towards the required destination according to the router algorithm.

[0023]

[0023] Some known examples of routing techniques are shown below.

[0024]

[0024] The first example is deterministic routing where the path between the source and destination is determined beforehand. This technique preserves packet order and can avoid deadlocks. This approach does not utilize all the ports of the routers and other connections (paths) of the interconnect to balance the network.

[0025]

[0025] The second example of a routing technique is dimension - order routing, which calculates the shortest deterministic path between the source and destination in the three topologies described above. Packets are first routed along a specific direction and then routed in other directions until it reaches the desired destination. For example, in a 2D mesh, according to the XY - dimension routing algorithm, the packet is routed in the X - dimension until it reaches the X - coordinate of the destination router, and then it is routed along the Y - dimension until it reaches the Y - coordinate of the destination router, which is the final destination router.

[0026]

[0026] The neural networks mapped on a multi-core NMA chip can be of several different natures, which can be fully connected networks, partially connected, recurrently connected, skip layer connected, etc. Therefore, it may be necessary for spikes to be sent from one core to multiple cores. The mapping of neural network neurons onto the NMA determines the flow of spike packets in the interconnect. The one-to-many nature of the neural network requires that spike packets be multicast to different NMA cores.

[0027]

[0027] Sending spike packets from one core to multiple cores is called multicast communication, which can be unicast-based. In this approach, the multicast operation is performed by replicating the payload for all destinations or a subset of destinations. These packets contain the same payload but have different destination IDs. This approach sends N packets when there are N destinations. This approach has significant network latency and high power consumption.

[0028]

[0028] The state-of-the-art for multicast communication is unicast-based, which is shown in more detail in Figure 3 and described below. This approach can create a large number of packets in the interconnect and can lead to congestion. Furthermore, generating unnecessary extra spike packets can be a burden on the source node. Therefore, new routing techniques are needed.

Summary of the Invention

[0029]

[0029] In one aspect, the present invention provides a method for routing spikes in a neuromorphic processor. The neuromorphic processor includes a plurality of neuromorphic array cores, each having an associated router. Each neuromorphic array core may include a spiking neural network including a plurality of neurons connected via synapses. The method includes generating spike data representing one or more spikes generated by one or more neurons in a source neuromorphic array core among the plurality of neuromorphic array cores, generating a spike data packet including the spike data, a destination vector indicating one or more destinations for the spike data packet, and source identification information indicating the source neuromorphic array core, transmitting the spike data packet to one or more of the routers of the neuromorphic processor, receiving the spike data packet at the router of a receiving-side neuromorphic array core among the plurality of neuromorphic array cores, reading the destination vector of the received spike data packet, determining based on the destination vector whether the receiving-side neuromorphic array core is a destination for the spike data packet, and if so, sending the spike data to the receiving-side neuromorphic array core, determining based on the destination vector whether there is one or more additional destinations for the spike data packet other than the receiving-side neuromorphic array core, and if so, (a) updating the destination vector to remove the receiving-side neuromorphic array core as a destination for the spike data packet if it is indicated as a destination in the destination vector, (b) determining one or more next destinations for the spike data packet based on the destination vector and the routing algorithm of the router, and (c) sending the spike data packet or a copy of the spike data packet to one or more output ports of the router based on the determined one or more next destinations.

[0030]

[0030] This provides a multicast routing method that reduces the burden on the source neuromorphic array core to generate multiple packets and facilitates packet modification in each router when the neuromorphic array core associated with the router is one of the destination nodes. The proposed approach enables intermediate routers to forward packets using simple router logic without a routing table in the router and reducing latency in spike transmission.

[0031]

[0031] A method for routing may comprise determining only one next destination for a spike data packet based on a destination vector and sending the spike data packet or a copy of the spike data packet to one output port based on the determined next destination. When the destination vector is updated, the updated destination vector may be included in the spike data packet or the copy of the spike data packet sent to the output port. This method may be described as a single-packet multicast method, where a single spike data packet is transmitted through the neuromorphic processor without replicating the packet. This reduces congestion in the neuromorphic processor since there are no multiple packets with the same payload and different destinations. This approach also preserves the order of spiking data when received at the destination neuromorphic array core and uses simple router logic for low-latency transmission.

[0032]

[0032] Alternatively, a method for routing may further comprise deriving a plurality of new destination vectors from a destination vector when more than one next destination for a spike data packet is determined, where these destinations indicated in the destination vector are divided among the plurality of new destination vectors and each of the spike data packets sent to the output port includes one of the new destination vectors. This approach further reduces the latency for packet delivery due to the presence of a plurality of spike data packets having the same payload of spike data and different destination vectors created on-the-fly by the router. The order of spiking data reception may also be preserved using a deterministic routing algorithm such as the X-Y routing algorithm.

[0033]

[0033] The spike data included in a spike data packet may indicate which neurons in the source neuromorphic array core generated spikes within a certain time period. The spike data may comprise encoded data such as binary encoded data, where each bit of the binary encoded data indicates whether a spike was generated by the corresponding neuron during the time period. Additionally, each of the spike data packets may comprise timing data indicating the time period during which the spike occurred. The timing data may indicate a time such as a timestamp when one or more spikes were generated by one or more neurons and may be relative time.

[0034]

[0034] The destination vector can be a destination bit vector comprising a plurality of bits, each bit indicating whether a corresponding one of the neuromorphic array cores of the neuromorphic processor is the destination of the spike data packet. The position of each bit of the destination bit vector can be assigned to indicate whether the corresponding neuromorphic array core is the destination for the spiking data packet. For example, a bit at a particular bit position can be set to "1" to indicate that the corresponding neuromorphic array core is the destination for the spiking data packet. The number of bits in the destination bit vector can be equal to the number of neuromorphic array cores in the neuromorphic processor.

[0035]

[0035] A method for routing can further comprise transmitting at least a portion of the spike data to one or more neurons in the receiving neuromorphic array core based on the source identification information when the destination vector indicates that the receiving neuromorphic array core is the destination for the spike data packet. Sending the spike data to the neuromorphic array core can comprise sending the spike data packet or a copy of the spike data packet to a local output port of the router. The method can further comprise generating one or more spikes based on the spike data packet and transmitting the one or more spikes to one or more neurons in the neuromorphic array core.

[0036]

[0036] The next destination for the spiking data packet can be determined using an X-Y dimensional routing algorithm, a cost function-based selection algorithm, or a fixed priority-based selection algorithm. Each of the spiking data packets can comprise data regarding the next destination of the spiking data packet in addition to the destination bit vector. This enables the router to forward the packet to a preferred destination.

[0037]

[0037] In another aspect, the present invention provides a router for routing spikes in a neuromorphic processor, the neuromorphic processor comprising a plurality of neuromorphic array cores each having an associated router. The router can be used in the methods described herein. The router receives a spike data packet that includes spike data representing one or more spikes generated by one or more neurons in a source neuromorphic array core among the plurality of neuromorphic array cores, a destination vector indicating one or more destinations for the spike data packet, and source identification information indicating the source neuromorphic array core, reads the destination vector of the received spike data packet, determines, based on the destination vector, whether the neuromorphic array core associated with the router is a destination for the spike data packet, and if so, sends the spike data to the neuromorphic array core, determines, based on the destination vector, whether there are one or more additional destinations for the spike data packet other than this neuromorphic array core, and if so, (a) updates the destination vector to remove the neuromorphic array core as a destination for the spike data packet if it is indicated as a destination in the destination vector, (b) determines one or more next destinations for the spike data packet based on the destination vector and the routing algorithm of the router, and (c) sends the spike data packet or a copy of the spike data packet to one or more output ports of the router based on the one or more determined next destinations.

[0038]

[0038] The router may be configured to determine only one next destination for the spike data packet based on the destination vector, and to send the spike data packet or a copy of the spike data packet to one output port based on the determined next destination. When the destination vector is updated, the updated destination vector may be included in the spike data packet or the copy of the spike data packet sent to the output port.

[0039]

[0039] Alternatively, the router may be configured to derive a plurality of new destination vectors from the destination vector when more than one next destination for the spike data packet is determined, where these destinations indicated in the destination vector are divided among the plurality of new destination vectors, and each of the spike data packets sent to the output port includes one of the new destination vectors.

[0040]

[0040] In a further aspect of the present invention, an interconnect is provided for multicasting spikes in a neuromorphic processor, where the interconnect comprises a plurality of routers as described herein and a plurality of communication links connecting these routers. The routers are arranged in a two-dimensional mesh.

[0041]

[0041] In yet a further aspect of the present invention, a neuromorphic processor comprises a plurality of neuromorphic array cores, each of the neuromorphic array cores comprises a spiking neural network and has an associated router, and the neuromorphic processor further comprises an interconnect and routers as described herein. The neuromorphic processor may be implemented as a single integrated circuit.

[0042]

[0042] Next, embodiments will be described by way of example only with reference to the accompanying schematic drawings, where corresponding reference numerals indicate corresponding parts.

Brief Description of the Drawings

[0043]

Figure 1

[0043] Figure 1 is a schematic diagram of a neuromorphic processor having a mesh topology, where each neuromorphic array core includes a router.

Figure 2

[0044] Figure 2 is a schematic diagram of a router according to the present invention and its connection to a neuromorphic array core to which it is assigned or to another router of the neuromorphic array.

Figure 3

[0045] Figure 3 is a schematic overview of a routing technique, particularly unicast-based multicast communication known in the art.

Figure 4

[0046] Figure 4 is a schematic overview of a routing technique, particularly single-packet multicast communication.

Figure 5

[0047] Figure 5 is a schematic diagram of a spike routing concept for a router for single-packet multicast communication.

Figure 6

[0048] Figure 6 is a flowchart illustrating a single-packet multicast communication method.

Figure 7

[0049] Figure 7 is a flowchart illustrating an address modifier method.

Figure 8

[0050] Figure 8 is a schematic overview of a routing technique, particularly multi-packet chain reaction multicast communication.

Figure 9

[0051] Figure 9 is a schematic diagram of a spike routing concept for a router for multi-packet multicast communication.

Figure 10

[0052] Figure 10 is a schematic diagram of a flowchart illustrating a multi-packet multicast communication method.

Figure 11

[0053] FIG. 11 is a schematic diagram of a flowchart for explaining a destination vector splitting algorithm. **DETAILED DESCRIPTION OF THE INVENTION**

[0044]

[0054] Hereinafter, certain specific embodiments will be described in more detail. However, it should be understood that these embodiments should not be construed as limiting the scope of protection of the present disclosure.

[0045]

[0055] FIG. 1 is a schematic diagram of a neuromorphic processor comprising a neuromorphic array divided into a plurality of neuromorphic array cores interconnected in a 2D mesh topology, where each neuromorphic array core 4 has a router 1. Other topologies may also be used and are within the scope of the present invention. The router 1 and the core 4 together form nodes of the neuromorphic array. Each core may comprise a programmable network of spiking neurons and synapses. Each router 1 may be used for inter-node communication.

[0046]

[0056] An ensemble is a sub-network of neurons that form a collaborative group, which may form, for example, a classifier, an ensemble of classifiers, a group of neurons, etc., that handle only data conversion, feature encoding, or classification.

[0047]

[0057] The network of the ensemble can be partitioned and mapped onto an array of cores. As a result, each core may implement a single ensemble (related to the number of neurons and synapses in the core), implement multiple small ensembles, or, in the case of a large ensemble, implement only a part of a single ensemble, with other parts being implemented on other cores of the array. The modality of how the ensemble is partitioned and mapped to the cores can be determined by a mapping technique outside the scope of the present invention.

[0048]

[0058] Accordingly, each core comprises at least a part of a spiking neural network comprising one or more neurons and one or more synapses (also referred to as synaptic elements). The neurons and synapses are implemented at least partly, or fully, in hardware. Neuron 1 and synaptic element 2 can be implemented in hardware, for example, using analog circuit elements or digital hard-wired logic circuits. They can also be implemented partly in hardware and partly in software. Implementation in hardware or at least partly in hardware is preferred, i.e., instead of using a large processor that executes software emulating individual neurons, hardware circuits or elements are used to execute the functions of individual neurons. These (partial) hardware implementations achieve faster processing and enable, for example, much faster pattern recognition and event-driven processing where blocks of neurons and synaptic elements are activated only when needed.

[0049]

[0059] A typical router 1 can have, for example, five input ports and five output ports. The ports can be local, i.e., between router 1 at node 4 and different hardware structures within that node 4 (e.g., those directed to a spiking neural network formed in the core of the node), or the ports can be non-local, i.e., between router 1 of different nodes 4. The number of input ports and output ports can be the same or different.

[0050]

[0060] In this embodiment, for each node, one local input port (L_in) and one local output port (L_out) are shown. Further, the four non-local input ports shown are the north, south, west, and east input ports N_in, S_in, W_in, and E_in. The name of each input port is the input signal (11 N、S、W、E) indicates the direction to the nodes within the mesh where it arrives from there. The four non-local output ports shown are the north, south, west, and east output ports, denoted as N_out, S_out, W_out, and E_out respectively. Also, for the output ports, the name of each output port is the output signal (12 N、S、W、E ) indicates the direction to the nodes within the mesh where it is sent there.

[0051]

[0061] The mesh in this embodiment has a total of 16 nodes, although more or fewer nodes can also be assumed. The routers at the edges of the mesh can have less than 4 non-local input and output ports in use. For example, a router located at a node in the southeast corner of the mesh may only require input / output to both the north and west. The exemplary mesh shown is a 2D mesh, although 1D or 3D meshes linked in a similar way can also be assumed. The exemplary mesh shown only shows the connections between adjacent nodes, although it is also assumed that the routers can be connected to nodes adjacent diagonally or to certain nodes that are not directly adjacent.

[0052]

[0062] FIG. 2 is a schematic diagram of a router according to the present invention, its input ports from different routers within the mesh, and its output ports to different routers. This provides a more detailed overview of one or more of the routers 1 shown in FIG. 1, for example.

[0053]

[0063] Local input port 22 L and local output port 21 L are shown. As described above, these are configured for communication between the router and other parts of the node to which the router is assigned. Non-local input port 21 N、S、W、E and non-local output port 22 N、S、W、E constitute communication to and from other routers within the mesh.

[0054]

[0064] The signal arriving at the router can pass through buffer 25. The buffer is a block of memory that can process data, such as spike packets, during the network routing process. As data flows through different nodes of the network, different rates of transmission occur between routers, which can cause network congestion. Buffer 25 temporarily stores (for example, spike) packets to compensate for speed variations and handle large bursts during data transmission. Next, the arriving signal can pass through control logic point 23. Control logic point 23 can read the data in the spike packet and determine whether the spike packet needs to be sent onwards or absorbed by the node. The control logic point can also include a routing algorithm module that applies a routing algorithm for determining whether the spike packet is to be sent to a local port and / or a non-local port and calculates the next destination. The control logic point can also modify the information in the spike packet, for example, as described below with respect to the destination vector. The control logic point can also control the flow from the buffer to the crossbar. For example, multiple spike packets can be held in the router's buffer until they are sent onwards. Next, the arriving signal (which can be adapted) reaches crossbar 24, and crossbar 24 redirects input 21 to output 22, which can be a local output or a non-local output. Crossbar 24 configures the connection between the input port and the output port to establish the desired path for each packet.

[0055]

[0065] Figure 3 is a schematic overview of known unicast-based multicast communication. Nodes (cores) are arranged in a mesh topology. Each square box in Figure 3 represents a neuromorphic array core (node) with a router. When sending spike packets from source node S to four destinations (A, B, C, and D), this approach requires four independent spike packets to be sent, one for each destination. These spike packets are visualized by four different arrow types. Each spike packet comprises spike data and the address of the destination node (A, B, C, or D) to which the spike packet (SP) is directed, and has the general form SP = [<spike_data>, <destination_node_address>], resulting in the following spike packets: 1) SP1 = [<spike_data>, <destination_node_address(A)>]; 2) SP2 = [<spike_data>, <destination_node_address(B)>]; 3) SP3 = [<spike_data>, <destination_node_address(C)>]; 4) SP4 = [<spike_data>, <destination_node_address(D)>].

[0056]

[0066] In Figure 3, each arrow from source node S is a spike packet, and each packet can be sent either sequentially or in parallel through the E_out port according to the XY - dimensional routing algorithm. In this approach, multicast is implemented with multiple unicast packets. This approach creates a large number of packets in the interconnect and can lead to congestion. Further, the spike data is the same for all of the spike packets SP1 - SP4, which can lead to an unnecessary amount of copying of the same data. The drawbacks of the multi - packet unicast method are overcome in the present invention by the use of single - packet multicast communication, which is detailed below.

[0057]

[0067] Other forms of multicast communication other than unicast-based communication are path-based and tree-based multicast communication.

[0058]

[0068] In path-based communication, spike packets are sequentially transferred to each destination by following one path determined by a routing algorithm. In tree-based communication, the source node is regarded as the root of the tree, packets are sent down the tree, and spike packets can be replicated at branches for a single set of destination nodes as needed. The method of the present invention is path-based and tree-based multicast communication. These will be described below.

[0059]

[0069] Figure 4 is a schematic overview of single-packet multicast communication. In this proposed method, a destination bit vector (DBV) is used to send the same spike data to four different destination nodes. The destination bit vector can be a vector of a length equal to the number of nodes in the network. In this example, the number of nodes is 16, and thus the DBV has a width of 16 bits. Each bit position in the DBV represents a node / router ID. The node identified by the letter S is the source node in this example, while A, B, C, and D indicate the destination nodes. In this approach, only one SP is sent: Spike Packet (SP) = [<spike_data>, <destination_bit_vector>, <next_destination>]. Note that the next destination field is optional and may be required for a particular routing algorithm.

[0060]

[0070] In this specific example, the source node S sets the destination bit vector as [1000010001000010] and sets the next destination as node A. Packets composed of spike data and the destination bit vector are routed in all routers according to the XY - dimensional routing algorithm and take the following path. First, the packet proceeds to node A, where the spike data is copied and absorbed, and the destination bit vector and the next destination field are changed. Next, the packet is sent to the next router according to the XY - dimensional routing algorithm. This procedure is followed at all the listed destination nodes. When the packet reaches the last node, in this case node D, the packet is routed to the local port and is not sent to the next router anymore.

[0061]

[0071] When a specific bit position is set to 1 in the DBV, it indicates that the node ID equal to that bit position is one of the destinations of the packet. In this example, the node / router ID of node A is 1, which is one of the destinations of the spike data. When the packet reaches node A, bit position 1 is cleared, i.e., it is set to 0 after the packet is replicated and the original is absorbed. This approach is followed by all the destination nodes until the final destination node D where the packet is not replicated but simply absorbed.

[0062]

[0072] This method enables spikes to be replicated by intermediate destination nodes, thus reducing the burden on the source node to generate multiple packets. This method also facilitates the modification of packets at each input port when the current node is one of the destination nodes. The proposed approach enables intermediate nodes to forward packets without a routing table within the router. This also reduces congestion within the network as there are no multiple packets with the same payload but different destination IDs. This approach not only preserves the spike ordering at the destination node, but also enables us to create simple router logic. The latter reduces the latency in the transmission of spikes. To implement such a spike multicast technique, a spike routing concept as shown in FIG. 5 can be used.

[0063]

[0073] FIG. 5 is a schematic diagram of a spike routing concept for a router for single packet multicast communication. The network interface block 512 of the neuromorphic array 511 is responsible for determining the destination address / ID for the packet. The address modifier block 54 is responsible for modifying the destination bit vector.

[0064]

[0074] Packets are received from one of the N_in, S_in, W_in, and E_in non-local input ports (51 N、S、W、E ) that are connected to other routers within the mesh. Packets can pass through buffer 53, which can temporarily store incoming packets, especially in case of congestion or other reasons. After passing through buffer 53, the packets can reach the address modifier block 54. The address modifier block has sub-blocks 54 N、S、W、E for each of these ports 51 N、S、W、Emay have, and these sub - blocks act on the packets received through their corresponding ports. There can also be a single address modifier block that acts on the packets received through all input ports. The address modifier block checks whether the final destination node of the packet is the current node. If so, the packet can be absorbed and no copy of the packet is created. If the node is not the final destination but is one of the destinations, a copy of the packet can be created, and the destination bit vector of the copied packet is changed by clearing the bit position corresponding to the current node address / ID. The original packet is absorbed and the copy is sent to the next router according to the routing algorithm.

[0065]

[0075] This is shown in Figure 4, where the input spike packet to Node A has a destination bit vector equal to [1000010001000010]. The spike packet is replicated by the router at Node A, and the address modifier block of the router at Node A changes the destination bit vector to [1000010001000000]. That is, the destination bit vector is changed so that Node A is no longer indicated as the destination of the spike packet by the destination bit vector. The original packet payload can be routed to the local port of the router at Node A.

[0066]

[0076] If the current node is not the destination, the packet can be sent forward to the next node according to the routing algorithm without changing the destination bit vector of the spike packet.

[0067]

[0077] Absorption of the original packet can be done through the following steps. First, the signal from the address modifier block of each of the ports (54 N、S、W、E ) goes to the individual buffer 55 N、S、W、Ecan pass through to reach arbiter 56. Arbiter 56 can generate one single output from all of these inputs, or the spike data from all inputs can be held separately. The output of the arbiter is the local output 52 L which is called. The local output serves as the network interface local input 51 NI_L and enters the network interface block 512 of the neuromorphic array 511. Then, the network interface local input 51 NI_L can arrive at the neuromorphic array 511 and can be used as spike inputs to the neuromorphic array.

[0068]

[0078] The network interface local input 51 NI_L can indicate, for example, according to the spike data, which one or more synapses of the neuromorphic array the spike represented by the spike data needs to reach. For example, the spike data can indicate from which one or more neurons in the source node S, for example, the spike represented by the spike data occurred. The spike data can, additionally or alternatively, indicate one or more target synapses or neurons in the neuromorphic array 511 that one or more spikes represented by the spike data need to affect.

[0069]

[0079] The neuromorphic array core 511 can have neurons that create spatio-temporal spike trains where spike data (at least a part of it) needs to be sent to neurons or synapses at different nodes. This can result from the spikes represented by the network interface local input 51 NI_L but can also have other causes. Thus, the neuromorphic array outputs a spike or spike data, whereby the network interface block 512 receives the network interface local output 52 L as the local input 51 and enters the router NI_Lcan be generated. This local input 51 L includes information regarding the destination address / ID for the data packet, which can be generated by the neuromorphic array or can be generated by the network interface.

[0070]

[0080] The next destination field in the spike packet can be calculated using different methods. The first method can be cost function-based destination selection. In this method, the total number of hops for each of the destination nodes is calculated, and the next destination can be determined by using one of several methods, for example, (a) selecting the destination corresponding to the minimum number of hops as the next destination, or (b) selecting the destination corresponding to the maximum number of hops as the next destination. The second method can be fixed priority-based destination selection. A priority can be given to each destination bit vector bit position. If the bit position in the destination bit vector is set to 1, this can imply that the node having the ID / address corresponding to that BIT position is one of the destinations. Among these destinations, the next destination can be selected based on the priority.

[0071]

[0081] input 51 L and 54 N、S、W、E The outputs from can all be temporarily stored in their respective buffers 57 L、N、S、W、E The routing algorithm 58 uses the information in buffer 57 to determine the next hop on the path that the data packet should take to reach its destination.

[0072]

[0082] The routing decision is then communicated to the switch allocator 59, which schedules the packet for transmission on a specific output port (52 N、S、W、E ) considering the available resources. The switch allocator relays this information to the crossbar 510. The crossbar 510 establishes the desired path for the packet using buffer 57 N、S、W、E and output port 52 N、S、W、EConfigure an appropriate connection with. Then, the packet is transferred through the output port 52 N、S、W、E to the crossbar, where it can be transferred to the next router. The crossbar can also be used, alternatively, to send spike data to the neuromorphic array via the local input port.

[0073]

[0083] Figure 6 is a schematic diagram of a flowchart according to one way of implementing a single packet multicast communication method. The flowchart starts at start 60. In step 61, one or more spike packets can be collected from one or more input ports at one or more nodes. In step 62, the node address / ID of the node where the spike packet was collected and the destination bit vector of the spike packet collected at the node are obtained.

[0074]

[0084] In step 63, it is then determined whether the node address / ID exists in the destination bit vector. For example, whether the bit in the destination bit vector associated with the node is set to a specific value.

[0075]

[0085] If the node address / ID does not exist in the destination bit vector, follow path 63 b to proceed to step 68, where the spike packet is routed according to the routing algorithm without the need to absorb spike data at the node. Then, in step 69, the flowchart for this iteration of the single packet multicast communication method ends.

[0076]

[0086] On the other hand, if the node address / ID exists in the destination bit vector, follow path 63 a to proceed to step 64, where it is checked whether this node is the final destination node.

[0077]

[0087] If the node is the final destination node (node D in Figure 4), follow path 64 aFollowing, the spike packet / payload is absorbed through the local port in step 65 and in 69, the flowchart ends.

[0078]

[0088] If the node is not the final destination node, path 64 b is followed to proceed to step 66 where a copy of the spike packet is created. Either the original or the copy of the spike packet is then absorbed through the local port. In step 67, then, either the copy or the original of the spike packet is taken in respectively and then the next destination of this spike packet is determined according to the preferred destination using the destination selection method described above.

[0079]

[0089] As a result, the packet is routed in 68 according to the routing algorithm. Also, it is possible that after the payload is absorbed / ejected through the local port, for example, at the network interface, a copy of the spike packet is made.

[0080]

[0090] Figure 7 is a schematic diagram of a flowchart according to one way of implementing the address changer method. After start 70, the method requires that in step 71, the node address / ID of the node where the spike packet arrives and the destination bit vector for that spike packet are obtained.

[0081]

[0091] In step 72, it is checked whether the current node address / ID position in the destination bit vector is set to a specific value, for example 1.

[0082]

[0092] If the current node address / ID position in the destination bit vector is not set to a specific value, this means that the node is not the destination of the spike packet and path 72 b is followed to proceed to step 77 where the packet is routed according to the routing algorithm.

[0083]

[0093] However, if the current node address / ID position in the destination bit vector is set to a specific value, path 72 a is followed to proceed to step 73. In step 73, the payload is replicated to obtain two payloads, namely, the original and the replica. Either the original or the replica payload follows path 73 a to proceed to step 74, where the payload is absorbed through the local port. The replica or the original payload each follows path 73 b to proceed to step 75, where the current node ID position in the destination bit vector is set to 0. Then, in step 76, the next destination field value is determined according to the next preferred destination using the destination selection method. Thereafter, in step 77, the packet is routed according to the routing algorithm.

[0084]

[0094] FIG. 8 is a schematic overview of multi-packet chain reaction multicast communication. In the proposed method, to send a packet to M destinations, an intermediate node duplicates the packet during routing and creates up to (M-1) new packets, each with a different destination bit vector and next destination field value. For a network of N nodes, for example, a destination bit vector with a length equal to the number of nodes in the network is used. In this case, for example, each bit position in the destination bit vector represents a node or router address / ID. In this particular embodiment, there are M=4 destinations and N=16. To send spike data to four destinations, the source node sends one packet, and if appropriate, an intermediate node splits the destination vector into two vectors. The intermediate node may duplicate the packet and create one or more new packets with different destination bit vectors and next destination field values. In this example, at node A, only one duplicate of the original packet is created, so that two spike packets with at least the original spike data are finally sent from node A.

[0085]

[0095] Figure 8 shows the proposed method with node S as the source node and A, B, C, and D as destination nodes. In this approach, only one spike packet is sent from the source node: spike packet (SP) = [<spike_data> ,<destination_bit_vector> ,<next_destination> ]. As before, the following destination fields are optional.

[0086]

[0096] The source node S creates a spike packet with the destination bit vector as [1000010001000010], and therefore SP=[<spike_data> , <1000010>001000010>, <Node A>. Next, the spike packet is routed, for example, according to the XY-routing algorithm and can take the following path. When the packet reaches Node A, since Node A is the destination node of the spike packet, the spike data included in the spike_data field is absorbed. The absorption can be performed according to the above description. Next, according to the destination vector splitting (DVS) method (further disclosed with respect to FIG. 11), the packet can be replicated, the destination bit vector is changed, and the packet is passed according to the XY-routing algorithm. Note that the packet can be replicated before or after being absorbed at the node. Thus, at Node A, two packets are created / changed with different destination bit vectors, one packet (p1) is designated for Node B, and the other packet (p2) is designated for C and D.

[0087]

[0097] Spike packet p1 is routed to Node B according to the XY algorithm. At Node number 2, since there is only one destination in the destination bit vector, there is no need to replicate the packet. Further, at Node 2, since it is not the destination node, the packet does not need to be absorbed.

[0088]

[0098] Spike packet p2 is routed to Node number 5 according to the XY algorithm. At this Node 5, the packet is replicated and the destination bit vector is changed according to the destination vector splitting method. The new packet p2_1 is routed to Node C, and the other new packet p2_2 is routed to destination D. At Node numbers 6 and 9, since there is only one destination in the DVB, the spike packet is not replicated. When each packet reaches its final destination, the packet is absorbed and not replicated further.

[0089]

[0099] Figure 8 shows the node or router ID / address of all nodes / routers having numbers from 0 to 15. The bit position in the destination bit vector may indicate the router ID. In the destination bit vector, if the value of a specific bit position is set to "1", it indicates that the node ID equal to that bit position is one of the destinations of the packet.

[0090]

[0100] In this example, the node or router ID / address of node A is 1, which is one of the destinations. When the packet reaches node A, before or after the packet is replicated into two copies, bit position 1 is cleared, i.e., set to 0, and the original is absorbed. The next destination in each of the new spike packets is set according to one of the destination selection methods (DSM). This approach is followed by all intermediate destination nodes until the final destination node of each spike packet, where the packet is not replicated and is only routed through the local input port and is not transferred further.

[0091]

[0101] As described above, spike packets can also be replicated into two or more copies. Whether a spike packet needs to be replicated and whether the destination bit vector is split among destinations may depend on the routing algorithm used. For example, in a specific XY-routing algorithm, splitting can be done if multiple destinations are in the same column. Other methods for determining whether splitting needs to be done are also within the scope of the present invention. Depending on whether the node is a destination node, the original is either absorbed or not.

[0092]

[0102] The proposed method enables spike packets to be replicated by intermediate nodes, thus reducing the burden of generating multiple packets by the source node. Further, this method also facilitates the modification of packets at each input port when the current node is one of the intermediate nodes and the destination bit vector has, for example, more than one destination bit set.

[0093]

[0103] The proposed method further enables intermediate nodes to forward packets without a routing table in the router. This approach reduces the latency of packet delivery in the network due to the presence of multiple packets in the network having the same payload and different destination IDs created on-the-fly. This approach preserves the ordering of spikes (which form the basis for spike packets) at the destination node according to a deterministic routing algorithm such as the X-Y algorithm.

[0094]

[0104] Also, the destination bit vector enables the creation of simple router logic and thus reduces the latency in the transmission of spikes. The next destination field enables the router to forward the packet to the preferred next destination.

[0095]

[0105] FIG. 9 is a schematic diagram of the spike routing concept for a router for multi-packet multicast communication. The embodiment of FIG. 9 is similar to the embodiment of FIG. 5, and similar parts are not explicitly mentioned. The main difference between the embodiments is that the embodiment of FIG. 9 includes a destination vector split (DVS) block 94 that serves to change the destination bit vector.

[0096]

[0106] Packets are received from N_in, S_in, W_in and E_in non-local input ports (91 N、S、W、E ) connected to other routers in the mesh. The spike packet can then pass through buffer 93, which can temporarily store incoming packets, especially in case of congestion or other reasons. Each port can have its own dedicated buffer. After passing through buffer 93, the packet can reach DVS block 94. DVS block 94 can be a single functional module or a block for each of the non-local input ports (94 N、S、W、E) can be subdivided. The DVS block 94 can check whether the final destination node of the packet is the current node. If so, the packet is absorbed and no copy of the packet is created.

[0097]

[0107] If the node is not the final destination but one of the intermediate destination nodes, more than two copies of the packet are created, and the destination bit vectors and the next destination fields of these replicated packets are changed by clearing the bit positions corresponding to the current node ID / address and setting the next destination using an appropriate destination selection method (DSM) as appropriate. The original packet is absorbed and the replicas are sent to the next router according to the routing algorithm.

[0098]

[0108] The absorption of the original packet and the transmission of the replicas according to the routing algorithm are performed in a manner similar to that in FIG. 5. The absorption and transmission are also visualized in FIG. 8, where the input packet to node A has a destination bit vector equal to [0010010001000010], and two new packets, namely p1 and p2, have destination bit vectors [0000000001000000] and [0010010000000000] respectively, and the original packet payload is routed to the local input port of the router at node A. If the current node is the final destination, the packet is not sent further; otherwise, the packet is sent according to the routing algorithm. This procedure is repeated for all intermediate nodes of the spike packet.

[0099]

[0109] Figure 10 is a schematic diagram of a flowchart for explaining a multi-packet multicast communication method. After start 101, in step 102, spike packets can be collected from an input port at a specific node, and in 103, a node address / ID and a destination bit vector are obtained for the spike packets at the node. Next, in step 104, a comparison is made as to whether the node address / ID exists in the destination bit vector, for example, by the indicated value of "1" in the destination bit vector.

[0100]

[0110] If the node address / ID does not exist in the destination bit vector, path 104 b is followed to proceed to step 107, where one or more copies of the packet can be created using different destination bit vectors according to the destination vector split (DVS) algorithm as needed. In step 108, the next destination can be determined according to a preferred destination using a destination selection method. As a result, the spike packet can be routed in 109 according to a routing algorithm. In step 110, the method ends.

[0101]

[0111] If the node address / ID exists in the destination bit vector, path 104 a is followed to proceed to step 105, where it is checked whether a specific node is the final destination node. If the node is the final destination node, path 105 a can be followed, and the packet / payload is absorbed / emitted through a local port in step 106a, and in 110, the method ends. If the node is not the final destination node, path 105 bProceed to step 107 following it, where one or more copies of the packet can be created using different destination bit vectors according to the destination vector splitting (DVS) algorithm. Next, in step 106b, the (original) packet / payload can be absorbed / emitted through the local port. Next, in step 108, the next destination of the copy can be determined according to the preferred destination using the destination selection method. As a result, the copied spike packet can be routed according to the routing algorithm 109, and in step 110, the method ends. Also, it is possible to make a copy of the packet after the payload is absorbed / emitted through the local port, which means that in the method, 106a / 106b comes before 105.

[0102]

[0112] Figure 11 is a schematic diagram of a flowchart illustrating the destination vector splitting algorithm. The flowchart starts from the top at start 111. In step 112, all input packets having an N-bit destination bit vector are obtained. In step 113, it is checked whether the processing of the previous spike packet is completed.

[0103]

[0113] If the processing of the previous spike packet is not completed, follow path 113a and proceed to step 114, where the method waits until the processing is completed.

[0104]

[0114] However, if the routing is complete, it follows path 113b and proceeds to step 115, where a new spike packet is processed. After processing the destination bit vector of the packet, which is N bits long, the packet is split in step 116 into two DBVs, namely A and B, at the center of the original DBV, such that DBV A = DBV[N / 2:0] and DBV B = DBV[N-1:(N / 2)+1]. An example of this split is provided in FIG. 8 for DBV[0010010001000010] with N = 16. This DBV is split into DBV A, which includes the first half of the digits ([8:0]), DBV A = [00100100], and DBV B, which includes the second half of the digits ([15:9]), DBV B = [01000000]. Note that the node at which the split occurs is node A, and thus, when this split occurs, the bit position corresponding to node A has been cleared, i.e., set to 0, since the spike packet has already arrived at destination A in FIG. 8.

[0105]

[0115] In step 117, it is checked whether both DBV A and DBV B are not equal to zero. If they are not equal to zero, it follows path 117a and proceeds to 118, where two replicated spike packets are created with A and B as the destination bit vectors, where A and B can be vectors with zeros added, such that these destination bit vectors will again have the original length equal to, for example, the amount of nodes in the mesh. Thus, in the case of FIG. 8, DBV A = [0010010000000000] and DBV B = [0000000001000000], and the splitting of the packet is completed at 1115.

[0106]

[0116] If either DBV A or DBV B is equal to zero, proceed to step 119 by following path 117b. At step 119, it is checked whether DBV A is equal to zero. If DBV A contains only zero, proceed to step 1110a by following path 119a, where it is checked whether N is equal to 1. If N is not equal to 1, proceed to step 1112 by following path 1110aa, where the destination bit vector is set to DBV B, N is set to N / 2 (since this is the length of DVB B), and then the flowchart starts again from step 116, but is walked through using DVB B instead of the original destination bit vector. If N is equal to 1, no further division can be done, and proceed to step 1111 by following path 1110ab, where a replicated spike packet with the new DBV B is sent, with zeros added if necessary.

[0107]

[0117] If DBV A does not contain only zero, this means that DVB B contains only zero. Then, proceed to step 1110b by following path 119b, where it is checked whether N is equal to 1. If N is not equal to 1, proceed to step 1113 by following path 1110bb, where the destination bit vector is set to DBV A, and N is set to N / 2 (since this is the length of DVB A). Then, the flowchart starts again from step 116, but is walked through using DVB A instead of the original destination bit vector. If N is equal to 1, no further division can be done, and proceed to step 1114 by following path 1110ba, where a replicated spike packet with the new DBV A is sent (with zeros added if necessary).

[0108]

[0118] In all of the above examples, note that as long as the time difference is less than the decay period of the neuron (at least a certain percentage thereof), the destination neuron within the destination node can be agnostic of spike ordering and the time difference between different spike arrivals. Since the decay period of a neuron is generally programmable, the amount by which the destination neuron is independent of spike ordering can be adjusted to some extent.

[0109]

[0119] In all of the above examples, note that at each source node, optionally, the spike can be encoded into a binary format (e.g., a bit vector indicating which of the neurons in the source node spiked), along with the timestamp of the spike / set of spikes at the moment the spike occurred. This can be, for example, the time relative to the previous spike. This can be input into the spike data field of the spike packet. Thus, a spike packet can contain information about a single spike of a single neuron within the source node, but it can also contain information about the spikes of a group of neurons or all neurons within the source node.

[0110]

[0120] This can be implemented by detecting a spike or spikes at the source node, optionally taking a snapshot of the timer value, and then restarting the timer. The detected spike can then be encoded in a binary representation as described above, where a representation, e.g., a bit vector, indicates whether a neuron fired for each bit position. This encoded data can then be placed in the spike packet as spike data, optionally along with a timestamp. The spike data can also include other information about the spike that occurred.

[0111]

[0121] Spike packets in all embodiments can also include the source node or source router address / ID, along with the spike data. Further, a destination bit vector encoding the destination node address / ID can be included, as described above.

[0112]

[0122] In the foregoing, a destination bit vector was used. More generally, the disclosed method may utilize a destination vector, which conveys information regarding the intended recipient of a spike packet, e.g., an intended router, node, or neuron(s). The destination vector may encode the destination node in bits by setting a "0" to "1" in the bit positions corresponding to the address / ID of a particular node or router in the destination bit vector. However, other ways of encoding such information are envisioned. For example, the destination vector may be a list of addresses or IDs of nodes or routers. The destination vector may also indicate a particular destination neuron, and a router may check whether such a destination neuron exists in a neuromorphic array core to which the router is connected. The destination vector may also indicate a source neuron, and each router may check whether there is a neuron in the neuromorphic array core connected to that router that should receive corresponding spike data as a result of such a source neuron firing.

[0113]

[0123] Optionally, in addition to spike data, source node ID, and destination vector, a spike packet may further include the following destination field, although this is not required. The following destination field value may be required depending on a particular routing algorithm. For example, static or dynamic routing may be used, and depending on the routing algorithm, the following destination field value may be required. The above embodiments showed a spike packet having the following destination field; thus, this value is not essential for practicing the present invention and is merely optional.

[0114]

[0124] Generally, dynamic routing may be used to take into account data traffic between cores in a mesh and route packets through less busy routers. The routing algorithm then takes into account the data load on each router and updates the following destination field, for example, after each hop between routers in the mesh.

[0115]

[0125] In all of the described embodiments, a source ID decoder may be present within the destination node. The source ID decoder decodes the source node ID information present in the spike packet. Based on the decoded source ID, the destination node may determine which presynapse or set of presynapses will receive the incoming spike / spikes. A lookup table may be used to match the decoded source ID with the intended destination presynapse or presynapses.

[0116]

[0126] It is possible to decode at all presynaptic levels, but this will result in a larger lookup table that consumes more on-chip area. In a preferred embodiment, the decoded source ID is matched to a particular group of presynapses. For example, each node comprises 32 neurons and 128 presynapses connecting to the 32 neurons. Information regarding which of the 32 neurons spiked is encoded in the spike data encapsulated in the spike packet, and after routing the spike packet to the destination node, by matching the decoded source node ID via a lookup table, a destination group of, for example, 32 presynapses may be selected. In this example, the destination node has four groups of 32 presynapses that can be matched to the decoded source node ID via a lookup table. Any number of presynapses, neurons, groups of presynapses may be used. Further, multiple layers of neurons and synapses may be used within the same core.

[0117]

[0127] Generally, for all incoming packets, the encoded spike data in the packet can be decoded, and the presynaptic data can be formed based on the decoded spike data. This presynaptic data can then be sent to the presynaptic in parallel (i.e., simultaneously). The incoming spikes can be digital pulses (e.g., edge detector circuits). The presented network-on-chip design is independent of whether the neuromorphic array is an analog array or a digital array. In the case of a digital array, the spikes can be represented as bit values, and then the standard multiplier accumulator module in the presynaptic applies weights to the spikes.

[0118]

[0128] Accordingly, the present invention discloses a mesh of neuromorphic array nodes each having its own router. The present invention focuses on the routing techniques used between these routers. The idea of the inventors' invention was generally to use spike packets. These spike packets generally comprise spike data and a destination vector. The spike packet can indicate the source node ID from which the spike data originated. The spike data conveys spike information regarding either a single neuron within the source node or a group of neurons within the source node. Either the destination router has information for mapping the spike data to the correct part of the neuromorphic array contained within their associated neuromorphic array core, or the spike packet comprises this information.

[0119]

[0129] Any of the embodiments disclosed above can be combined in any suitable way.

Claims

1. A method for routing spikes in a neuromorphic processor, wherein the neuromorphic processor comprises a plurality of neuromorphic array cores, each having an associated router, and the method is To generate spike data representing one or more spikes generated by one or more neurons in the source neuromorphic array core among the plurality of neuromorphic array cores, Generating the spike data packet, which includes the spike data, a destination vector indicating one or more destinations for the spike data packet, and source identification information indicating the source neuromorphic array core; The spike data packets are transmitted to one or more of the routers of the neuromorphic processor. In the router of the receiving neuromorphic array core among the plurality of neuromorphic array cores, the spike data packets are received, Reading the destination vector of the received spike data packet, Based on the destination vector, determine whether the receiving neuromorphic array core is the destination for the spike data packet, and if so, send the spike data to the receiving neuromorphic array core. Based on the destination vector, determine whether there are one or more additional destinations for the spike data packet other than the receiving neuromorphic array core, and if so, (a) Updating the destination vector to remove the receiving neuromorphic array core as the destination for the spike data packet if it is indicated as a destination in the destination vector, (b) Determining one or more next destinations for the spike data packet based on the destination vector and the router's routing algorithm, (c) Sending the spike data packet or a copy of the spike data packet to one or more output ports of the router based on one or more of the following determined destinations: A method for providing this.

2. Only one next destination for the spike data packet is determined based on the destination vector, and the spike data packet or the copy thereof is sent to one output port based on the determined next destination. Preferably, the method according to claim 1, wherein if the destination vector is updated, the updated destination vector is included in the spike data packet or the copy of the spike data packet sent to the output port.

3. The method according to claim 1, further comprising deriving a plurality of new destination vectors from the destination vector when one or more next destinations are determined for the spike data packet, wherein the destination indicated in the destination vector is divided among the plurality of new destination vectors, and each of the spike data packets sent to the output port includes one of the new destination vectors.

4. The spike data contained in the spike data packet indicates which neuron in the source neuromorphic array core generated the spike within a certain time period, and / or Each of the spike data packets comprises timing data indicating the time period during which the spike occurred, and / or The method according to any one of claims 1 to 3, wherein each of the spike data packets comprises, in addition to the destination bit vector, data relating to the next destination of the spike data packet.

5. The method according to any one of claims 1 to 3, wherein the destination vector is a destination bit vector having a plurality of bits, each bit indicating whether the corresponding one of the neuromorphic array cores of the neuromorphic processor is the destination of the spike data packet.

6. The method according to any one of claims 1 to 3, further comprising transmitting at least a portion of the spike data to one or more neurons in the receiving neuromorphic array core based on the source identification information, if the destination vector indicates that the receiving neuromorphic array core is the destination for the spike data packet.

7. A router for routing spikes in a neuromorphic processor, wherein the neuromorphic processor comprises a plurality of neuromorphic array cores, each having an associated router, and the routers are Receiving a spike data packet which includes spike data representing one or more spikes generated by one or more neurons in one or more source neuromorphic array cores among the plurality of neuromorphic array cores, a destination vector indicating one or more destinations for the spike data packet, and source identification information indicating the source neuromorphic array core, Reading the destination vector of the received spike data packet, Based on the destination vector, determine whether the neuromorphic array core associated with the router is the destination for the spike data packet, and if so, send the spike data to the neuromorphic array core. Based on the destination vector, determine whether there are one or more additional destinations for the spike data packet other than the neuromorphic array core, and if so, (a) Updating the destination vector to remove the neuromorphic array core as the destination for the spike data packet if it is indicated as a destination in the destination vector, (b) Determining one or more next destinations for the spike data packet based on the destination vector and the router's routing algorithm, (c) Sending the spike data packet or a copy of the spike data packet to one or more output ports of the router based on one or more of the following determined destinations: A router configured to perform the following actions.

8. Only one next destination for the spike data packet is determined based on the destination vector, and the spike data packet or the copy thereof is sent to one output port based on the determined next destination. Preferably, the router according to claim 7, wherein if the destination vector is updated, the updated destination vector is included in the spike data packet or the copy of the spike data packet sent to the output port.

9. The router according to claim 7, further configured to derive a plurality of new destination vectors from the destination vector when more than one next destination is determined for the spike data packet, wherein the destination indicated in the destination vector is divided among the plurality of new destination vectors, and each of the spike data packets sent to the output port includes one of the new destination vectors.

10. The spike data contained in the spike data packet indicates which neuron in the source neuromorphic array core generated the spike within a certain time period, and / or Each of the spike data packets comprises timing data indicating the time period during which the spike occurred, and / or The router according to any one of claims 7 to 9, wherein each of the spike data packets comprises, in addition to the destination bit vector, data relating to the next destination of the spike data packet.

11. The router according to any one of claims 7 to 9, wherein the destination vector is a destination bit vector comprising a plurality of bits, each bit indicating whether the corresponding one of the neuromorphic array cores of the neuromorphic processor is the destination of the spike data packet.

12. The router according to any one of claims 7 to 9, further configured to transmit at least a portion of the spike data to one or more neurons in the receiving neuromorphic array core based on the source identification information, if the destination vector indicates that the receiving neuromorphic array core is the destination for the spike data packet.

13. An interconnect for multicasting spikes in a neuromorphic processor, the interconnect comprising a plurality of routers as described in any one of claims 7 to 9, and a plurality of communication links connecting the routers.

14. A neuromorphic processor comprising a plurality of neuromorphic array cores, each of which comprises a spiking neural network and associated routers, wherein the neuromorphic processor further comprises the interconnect described in claim 13, wherein the router is the router described in any one of claims 7 to 9.

Images