Efficient System-on-Chip Power Delivery Using Adaptive Voltage Headroom Control

Abstract

Systems and methods related to efficient system-on-chip (SoC) power delivery by adaptive voltage headroom control are described. A method for adaptively controlling the voltage headroom for a system includes independently limiting the operating frequency of each core clock signal in response to either detection of a headroom violation by a per-core voltage regulator headroom monitor or detection of a voltage droop by a per-core droop detector. The method further includes, in response to meeting a predetermined criterion, (1) lowering the operating frequency of each core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) changing a voltage set point associated with a motherboard voltage regulator to a second voltage set point corresponding to a higher voltage if the monitored headroom violation event or the monitored droop event continues to meet the predetermined criterion.

Description

Background Art

[0001] A power delivery device for a system-on-chip (SoC) device includes a voltage regulator (e.g., a motherboard voltage regulator) for supplying power to transistors or other semiconductor devices within the SoC device. Practical physical constraints and cost optimization requirements impose low limits on the electrical impedance between the motherboard voltage regulator and the SoC transistors. Conventional power delivery devices have attempted to guarantee sufficient voltage headroom at the transistor level for the full range of SoC load current and current transients. A conventional method for guaranteeing sufficient voltage headroom at the transistor level was to set the regulator voltage high enough so as not to violate the minimum voltage requirement for any load. Such conventional power delivery devices can guarantee sufficient voltage headroom, but setting the voltage regulator to supply a high enough voltage so as not to violate the minimum voltage requirement for any load results in avoidable power losses.

Summary of the Invention

Problems to be Solved by the Invention

[0002] Accordingly, there is a need for improvements to SoC power supply systems and methods.

Means for Solving the Problems

[0003] In one example, the present disclosure relates to a system including a system-on-chip (SoC) including a plurality of cores. The system includes a voltage regulator module (VRM), where the VRM is based on a voltage setpoint associated with the VRM and is configured to supply an input voltage to each of the per-core voltage regulators in the SoC, and each of the per-core voltage regulators is configured to supply an output voltage to a corresponding core from among the plurality of cores. The system can further include an adaptive voltage headroom control device including (1) a voltage controller for controlling the voltage setpoint associated with the VRM, (2) a per-core voltage regulator headroom monitor, (3) a per-core droop detector, and (4) a per-core frequency controller configured to control the frequency of the core clock signal of each core from among the plurality of cores.

[0004] The adaptive voltage headroom control device can be configured to independently limit the operating frequency of each core clock signal in response to either detection of a headroom violation by the per-core voltage regulator headroom monitor or detection of a voltage droop by the per-core droop detector. The adaptive voltage headroom control device can be further configured to, in response to either a headroom violation event or a droop event satisfying a predetermined criterion, (1) lower the operating frequency of each core clock signal to a reduced operating frequency, (2) monitor the headroom violation event and the droop event at the reduced operating frequency, and (3) change the voltage setpoint associated with the VRM to a second voltage setpoint corresponding to a higher voltage if the monitored headroom violation event or the monitored droop event continues to satisfy the predetermined criterion even at the reduced operating frequency.

[0005] In another example, the present disclosure relates to a method for adaptively controlling voltage headroom for a system including (1) a system-on-chip (SoC) including a plurality of cores, and (2) a voltage regulator module (VRM), where the VRM is based on a voltage set point associated with the VRM and is configured to supply an input voltage to each of the voltage regulators for each core in the SoC, and the voltage regulator for each core is configured to supply an output voltage to a corresponding core from among the plurality of cores. The method can include independently restricting the operating frequency of each core clock signal in response to either detection of headroom violation by a per-core voltage regulator headroom monitor or detection of voltage droop by a per-core droop detector.

[0006] The method can further include, in response to either a headroom violation event or a droop event satisfying a predetermined criterion, (1) reducing the operating frequency of each core clock signal to a reduced operating frequency, (2) monitoring the headroom violation event and the droop event at the reduced operating frequency, and (3) changing the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage if the monitored headroom violation event or the monitored droop event continues to satisfy the predetermined criterion even at the reduced operating frequency.

[0007] In yet another example, the present disclosure relates to a system including a system-on-chip (SoC) that includes a plurality of cores. The system includes a voltage regulator module (VRM), where the VRM is based on a voltage set point associated with the VRM and is configured to supply an input voltage to each of the low dropout (LDO) voltage regulators for each core in the SoC, and each LDO voltage regulator for each core is configured to supply an output voltage to a corresponding core from among the plurality of cores. The system can further include a voltage regulator module (VRM). The system further includes an adaptive voltage headroom control device including: (1) a voltage controller for controlling a voltage set point associated with the VRM; (2) a headroom monitor for each core's LDO voltage regulator; (3) a droop detector for each core; and (4) a frequency controller for each core configured to control the frequency of the core clock signal of each core from among the plurality of cores.

[0008] The adaptive voltage headroom control device can be configured to independently limit the operating frequency of each core clock signal in response to either detection of a headroom violation by the headroom monitor for each core's LDO voltage regulator or detection of a voltage droop by the droop detector for each core. The adaptive voltage headroom control device can be further configured to, in response to either a headroom violation event or a droop event satisfying a predetermined criterion: (1) lower the operating frequency of each core clock signal to a reduced operating frequency; (2) monitor the headroom violation event and the droop event at the reduced operating frequency; and (3) change the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage if the monitored headroom violation event or the monitored droop event continues to satisfy the predetermined criterion even at the reduced operating frequency.

[0009] This "Summary of the Invention" is provided to introduce the selection of concepts in a simplified form, and the concepts will be further described in detail in the "Detailed Description of the Invention" below. This "Summary of the Invention" is not intended to identify the important features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0010] This disclosure is shown by way of example and is not limited by the accompanying drawings in which like reference numerals indicate like elements. The elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Detailed Description of the Invention

[0012] The examples described in this disclosure relate to efficient system-on-chip (SoC) power delivery using adaptive voltage headroom control. As previously explained, conventional power delivery devices have attempted to guarantee sufficient voltage headroom at the transistor level for the full range of SoC load current and current transients. In other words, the conventional method of guaranteeing sufficient voltage headroom at the transistor level was to set the voltage regulator voltage high enough so that no load would violate the minimum voltage requirement. Such conventional power delivery devices can guarantee sufficient voltage headroom, but setting the voltage regulator to supply a high enough voltage so that no load violates the minimum voltage requirement results in avoidable power losses.

[0013] Reduction of the voltage guard band enables significant power savings, but it can also create an insufficient voltage situation when the system-on-chip (SoC) current consumption increases unpredictably and rapidly. In this case, the voltage on the SoC side may instantaneously droop below the minimum allowable level, potentially causing the SoC to malfunction. To address such potential SoC malfunctions, additional mechanisms are built to guarantee the safe operation of the SoC during such events. Exemplary mechanisms include a monitor and droop detector for each decentralized voltage regulator headroom, an adaptive clocking scheme for each core, a performance monitor for each core that records droop and headroom violation events, a warning system, and a voltage controller that closes the control loop. The decentralized adaptive clocking scheme described herein enables independent high-frequency limiting of the affected cores in response to a low dropout (LDO) regulator input voltage headroom violation event or an LDO regulator output voltage droop event. A fast detector sensitive to the rate of change of voltage triggers the frequency limit, which results in a droop reduction and prevents violation of the core frequency-voltage operating point. The detected events are recorded and reported to the motherboard voltage regulator (MBVR) voltage controller, which adjusts the set point to reduce the probability of recurrence of such events.

[0014] FIG. 1 shows a diagram 100 depicting power loss when the voltage regulator set point (VR SET POINT ) is set to a conservative VR SET POINT . The vertical axis of diagram 100 represents voltage, and the horizontal axis represents current (e.g., the current drawn by a system-on-chip (SoC)). In this example, curve 110 represents the input voltage to the regulator (e.g., a low-dropout (LDO) regulator), and curve 120 represents the output voltage of the regulator (e.g., an LDO regulator). In this example, I TDP corresponds to the current drawn by the SoC at the thermal design power point. This current corresponds to the maximum amount of current that the SoC can draw, taking into account the cooling constraints related to the heating of the SoC due to an increase in the current draw. In this example, I PEAK corresponds to the peak current that the SoC can draw. As shown in diagram 100, as the current drawn by the SoC increases, the output voltage of the regulator (represented by curve 120) drops. To ensure that the output voltage of the regulator does not drop below the minimum voltage (V PEAK ) required at the peak current (I MIN ), the regulator is configured such that curve 110 (corresponding to the input voltage of the regulator) and curve 120 (corresponding to the output voltage of the regulator) intersect at point 122 shown in diagram 100. This ensures that the headroom (the difference between the input voltage of the regulator and the output voltage of the regulator) is zero or greater (e.g., by a few millivolts) at point 122. However, ensuring the headroom according to diagram 100 results in a power loss 140 with respect to the actual computational power 150 used by the SoC. In this case, the power loss 140 is the product of the current drawn by the SoC and the difference between the voltage of the conservative VR SET POINT and the minimum voltage (V PEAK ) required at the peak current (I MIN ).

[0015] FIG. 2 shows a diagram where the voltage regulator set point (VR SET POINT ) is a lower VR SET POINT compared to a conservative VR SET POINTFIG. 200 showing the power saved when set to is shown. Similar to FIG. 100, in this FIG. 200, the vertical axis represents voltage and the horizontal axis represents current (e.g., the current drawn by a system-on-chip (SoC)). In this example, curve 210 represents the input voltage to a regulator (e.g., a low dropout (LDO) regulator), and curve 220 represents the output voltage of the regulator (e.g., an LDO regulator). In this example, similar to what was described with respect to FIG. 1, I TDP corresponds to the current drawn by the SoC at the thermal design power point. This current corresponds to the maximum amount of current that the SoC can draw, taking into account the cooling constraints associated with heating of the SoC due to an increase in the amount of current drawn. In this example, I PEAK corresponds to the peak current that the SoC can draw. As shown in FIG. 200, as the current drawn by the SoC increases, the output voltage of the regulator (represented by curve 220) drops. In this example, the voltage regulator set point does not guarantee that it will never drop below the minimum voltage (V PEAK ) required at the peak current (I MIN ).

[0016] Continuing to refer to FIG. 2, unlike the regulator configuration where curve 110 (corresponding to the input voltage of the regulator) and curve 120 (corresponding to the output voltage of the regulator) intersect at point 122, in this regulator configuration, curve 230 (corresponding to the reduced input voltage of the regulator) and curve 220 (corresponding to the output voltage of the regulator) intersect at point 222. This means that it is guaranteed that the headroom (the difference between the input voltage of the regulator and the output voltage of the regulator) is zero or more (e.g., by only a few millivolts) at point 222. However, the headroom set by FIG. 200 results in a reduced power loss 240 with respect to the actual computational power 250 used by the SoC. This advantageously results in a saved power 260. In the present disclosure, a reduced VR SET POINT compared to a careful VR SET POINT is the SoC voltage to a careful VR SET POINTIt is adjusted to dynamically decrease below (for example, the set point corresponding to the worst-case current draw condition). By monitoring the actual short-term average SoC current, a voltage regulator set point that is not so cautious as to be sufficient for the optimal performance operation of the SoC under normal operating conditions is used. Rarely, a reduced VR SET POINT (for example, the reduced VR shown in FIG. 2 SET POINT ) is insufficient, a distributed droop relaxation mechanism and an adaptive clocking mechanism are used to prevent failures due to voltage droop.

[0017] FIG. 3 shows a block diagram of a system 300 including various components for implementing adaptive voltage headroom control according to one example. The system 300 can include a motherboard voltage regulator (MBVR 302) coupled to a system on chip (SoC) 304. The MBVR 302 can be a voltage regulator configured to supply voltage to a number of voltage regulators (for example, low dropout (LDO) regulators associated with various processing units of the SoC 304). In this example, the MBVR 302 can be configured to supply LDO_VDD as an input voltage to various LDOs included as part of the SoC 304.

[0018] Continuing to refer to FIG. 3, SoC 304 can include a number of processing units (e.g., a central processing unit (CPU) or a portion thereof), such as processing units 310, 340, 350, and 360. In this example, each processing unit can include a core. As an example, processing unit 310 can include core 312. Each core can have a corresponding LDO. As an example, core 312 can have a corresponding LDO 314 configured to supply CORE_VDD as an input voltage to core 312. Each core further has a corresponding core phase-locked loop (PLL) and a frequency controller associated with the core PLL. As an example, core 312 can have a corresponding core PLL 316 and a corresponding frequency controller 318. Each core can also have a corresponding loop detector and a headroom monitor. As an example, core 312 can have a corresponding loop detector 320 and a corresponding headroom monitor 330.

[0019] Referring further to FIG. 3, the core PLL 316 may be implemented as a phase-locked loop configured to output a clock signal (e.g., the CORE_CLK signal) for the core 312. The core PLL 316 may include clock division or multiplication and may provide functions related to a PLL used in core clocking that uses a feedback loop to ensure that the output clock closely aligns with a reference clock. The frequency controller 318 may include dynamic voltage frequency (DVFS) control logic. The DVFS control logic may receive an output from a loop detector 320 indicating loop detection and may be configured to dynamically compensate for the detected loop. In one example, the DVFS control logic corresponding to the frequency controller 318 may operate according to a core voltage ID corresponding to the frequency at which the core needs to operate. Since the core can operate at different frequencies, there may be multiple core voltage IDs corresponding to different clock frequencies. The DVFS control logic may also be able to track an adaptive voltage clock ID for each core. At a given core voltage ID, the adaptive voltage clock ID corresponds to a voltage within a selected delta of the voltage specified by the core voltage ID. The delta itself may be set to be on the order of a few millivolts. The loop detector 320 may be configured to detect the difference between a voltage corresponding to a given core voltage ID and the corresponding adaptive voltage clock ID. A difference that crosses or exceeds a threshold may be attributed to a loop detection event.

[0020] Next, referring to FIG. 4, it is a block diagram of a loop detector 400 for use in the system of FIG. 3 according to one example. The loop detector 400 receives a core voltage (e.g., CORE_VDD) as a voltage reference (V REF) can be configured to compare with. The voltage reference can be related to a voltage that can be compared with the core voltage to determine the amount of droop. The voltage reference can be generated by converting a digital value to an analog value using a digital-to-analog converter (DAC). As previously explained, the voltage reference can be the voltage corresponding to the adaptive clock ID, and the core voltage can be the voltage corresponding to the core voltage ID. Comparator 420 can compare the two voltages and generate a signal that can be sampled using sampling logic 430. The sampling logic 430 may be clock-controlled, which allows for sampling of the comparator output over several clock cycles if necessary. Based on the sampled output from comparator 420, a droop detection signal is generated by droop detector 400. As previously explained, the frequency controller 318 of FIG. 3 can receive the droop detection signals and react to these signals. FIG. 4 shows the droop detector 400 as including a specific number of components arranged in a specific way, but the droop detector 400 may include additional components or fewer components arranged differently.

[0021] Referring back to FIG. 3, each core can further include a headroom monitor for each LDO. As an example, FIG. 3 shows the headroom monitor 330 of LDO 314. As described above, headroom refers to the difference between the input voltage of a regulator (e.g., LDO 314) and the output voltage of the regulator. The headroom monitor 330 can be configured to detect the difference between the input voltage (e.g., LDO_VDD) and the output voltage of an LDO (e.g., CORE_VDD). The headroom monitor 330 can be configured such that when the difference between the input voltage to the LDO and the output voltage of the LDO is equal to or below a threshold (e.g., a threshold of a few millivolts), a signal indicating a headroom event is generated. The headroom event signal can be provided to the frequency controller 318 and the MBVR voltage controller 380. The frequency controller 318 can respond to the headroom event signal regardless of loop detection by the loop detector, and vice versa. As an example, when a headroom event signal is generated, measures related to adaptive control can be taken by the frequency controller 318. In one example, any violation of headroom can result in a change in clock frequency, a change in core voltage, or another corrective measure.

[0022] FIG. 5 shows the effect of adaptive clocking according to one example. As described above, system 300 is configured to perform per-core adaptive clocking in response to either a headroom event signal or a droop detection signal, independently of each other. In one example, the fast response mode of the adaptive voltage headroom response mechanism can be implemented as a combination of frequency controller 318 and headroom monitor 330. In one example, the droop response mechanism can be implemented as a combination of frequency controller 318 and droop detector 320. In this example, the control device can reduce the core clock frequency by a specific percentage of the operating frequency by masking the alternating high phases of the core clock. This helps to stop the droop and recover the core voltage because the reduction in the effective clock frequency reduces the current draw. The control device can continue to mask the core clock, which enables the core voltage to recover. When the voltage is fully recovered, the control device can restore the core performance by raising the frequency back to its original value. The frequency recovery process is smoothly performed by gradually increasing the number of unmasked high phases, thereby avoiding subsequent droop. Additionally, the frequency drop and recovery may be performed using other mechanisms.

[0023] Continuing to refer to FIG. 5, waveform 510 shows the core clock signal without adaptive clocking (e.g., without the effect of the adaptive voltage headroom response mechanism or the droop response mechanism). Waveform 540 shows the core clock signal with adaptive clocking. Waveform 540 shows the effect of masking the core clock signal in response to the detection of a droop. Curve 512 shows the core current without adaptive clocking, and curve 514 shows the core voltage without adaptive clocking. As shown in FIG. 5, without adaptive clocking, after N core clock cycles, the core current reaches its maximum and does not increase further. In the case of a droop event (e.g., when the voltage goes from V SET to V SET- When changing to -ΔV, without adaptive clocking, the core voltage drops and does not recover until slowly. Curve 542 shows the core current due to adaptive clocking, and waveform 544 shows the core voltage due to adaptive clocking. As shown in FIG. 5, when a droop is detected (at the time of droop detection in FIG. 5), after an additional synchronization delay (the additional synchronization delay in FIG. 5), clock masking is started (at the time of clock masking start in FIG. 5). In one example, clock masking is implemented by applying a mask to the selected high phase of the core clock signal by the frequency controller 318 of FIG. 3. The application of the mask (e.g., mask 11111010101010…) results in waveform 540, which corresponds to the core clock signal due to adaptive clocking. As shown in FIG. 5, masking is used in a way that clock recovery is smooth and not abrupt. As an example, to ensure a smooth response, the mask is selected such that the core current increases gradually (e.g., as shown by curve 542 in FIG. 5). The mask ensures that initially only some of the high phases of the clock signal are unmasked and the number of high phases of the unmasked clock signal increases slowly. As an example, after N' core clock cycles, the high phase of the clock signal is unmasked in a controlled and gradual manner. This prevents additional droops that may occur when the current increases rapidly (e.g., as shown by curve 514 corresponding to a sudden increase in current as shown by curve 512).

[0024] Referring back to FIG. 3, the SoC 304 can further include an MBVR voltage controller 380. The MBVR voltage controller 380 can be configured to continuously count each of the droop events and headroom violation events within a specific time window. When the number of droop events and / or headroom violation events exceeds a set threshold (each type of event can have a different threshold), an indication that the current performance level is not sustainable by the power delivery configuration is provided to the MBVR voltage controller 380. Successive droops can negatively impact performance since each droop event will decrease the frequency by the selected percentage. The MBVR voltage controller 380 can monitor the droop events or headroom violation events, track the progress, and respond in two ways: (1) by decreasing the core clock frequency by a small amount (only 2 - 5 percent of the operating frequency) for a specific period of time, and / or (2) by increasing the on-die and / or off-die voltage regulator output voltage to raise the voltage headroom, thereby reducing the likelihood of another droop event or headroom violation event occurring.

[0025] By reducing the frequency and monitoring the droop behavior after the frequency reduction, the adaptive voltage headroom control device finds the maximum sustainable performance level without causing additional droop events that would cause a loss of performance. The adaptive voltage headroom control device can also use the knowledge to adapt its settings. By increasing the input voltage, the adaptive voltage headroom control device can provide additional voltage margin to maintain a higher rate of change of current. This reduces the performance impact due to the reduction of the clock frequency due to voltage droop. After the system has operated in this state for a set period, the adaptive voltage headroom control device attempts to restore the energy efficiency of the system by raising the frequency or lowering the headroom of the voltage regulator. FIG. 3 shows a system 300 as including a specific number of components arranged and coupled in a specific way, although system 300 may include fewer components or additional components arranged and coupled differently.

[0026] FIG. 6 shows a flowchart 600 of a method for adaptively controlling a voltage headroom according to one example. In this example, the method corresponding to flowchart 600 may be executed as part of a system including (1) a system-on-chip (SoC) including a plurality of cores, and (2) a voltage regulator module (VRM), where the voltage regulator module (VRM) is based on a voltage setpoint associated with the voltage regulator module (VRM) and is configured to supply an input voltage to each of the voltage regulators for each core in the SoC, and each voltage regulator for each core is configured to supply an output voltage to a corresponding core from among the plurality of cores. In one example, this method may be executed using various components of the system 300 of FIG. 3. The MBVR 302 of FIG. 3 can perform the function of the voltage regulator module (VRM) and supply the input voltage to the SoC. Step 610 can include independently restricting the operating frequency of each core clock signal in response to either detection of a headroom violation by a per-core voltage regulator headroom monitor or detection of a voltage droop by a per-core droop detector. As part of this step, as previously described with respect to FIGS. 3-5, a headroom monitor (e.g., the headroom monitor 330 of FIG. 3) can detect a headroom violation. Additionally, as part of this step, as previously described with respect to FIGS. 3-5, a droop detector (e.g., the droop detector 320 of FIG. 3) can detect a voltage droop. As described with respect to FIG. 3, the system 300 includes a per-core headroom monitor and a per-core droop detector.

[0027] Continuing to refer to FIG. 6, step 620 can include, in response to either a headroom violation event or a droop event meeting a predetermined criterion: (1) lowering the operating frequency of each core clock signal to a reduced operating frequency; (2) monitoring the headroom violation event and the droop event at the reduced operating frequency; and (3) changing the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage if the monitored headroom violation event or the monitored droop event continues to meet the predetermined criterion even at the reduced operating frequency. As previously explained, an adaptive headroom voltage control device including the MBVR voltage controller 380 of FIG. 3 can be configured to set the voltage set point of a voltage regulator module (e.g., MBVR 302 of FIG. 3) and execute these steps. As an example, the MBVR voltage controller 380 of FIG. 3 can continue to count each of the droop events and headroom violation events within a particular time window. If the number of droop events and / or headroom violation events exceeds a set threshold (each type of event can have a different threshold), an indication that the current performance level is not sustainable by the power delivery configuration is provided to the MBVR voltage controller 380. Further, as previously explained with respect to FIGS. 3-5, an adaptive headroom voltage control device including the MBVR voltage controller 380 can change the voltage set point associated with a voltage regulator module (e.g., MBVR 302 of FIG. 3). Although FIG. 6 shows a particular number of steps executed in a particular order, additional steps or fewer steps in a different order may be executed as part of flowchart 600.

[0028] In short, the present disclosure relates to a system including a system-on-chip (SoC) including a plurality of cores. This system includes a voltage regulator module (VRM), and the voltage regulator module (VRM) is based on a voltage set point related to the voltage regulator module (VRM) and is configured to supply an input voltage to each of the voltage regulators for each core in the SoC, and each voltage regulator for each core is configured to supply an output voltage to a corresponding core from among the plurality of cores, and may further include a voltage regulator module (VRM). This system further includes an adaptive voltage headroom control device including: (1) a voltage controller for controlling the voltage set point related to the VRM; (2) a voltage regulator headroom monitor for each core; (3) a droop detector for each core; and (4) a frequency controller for each core configured to control the frequency of the core clock signal of each core from among the plurality of cores.

[0029] The adaptive voltage headroom control device may be configured to independently limit the operating frequency of each core clock signal in response to either detection of a headroom violation by the voltage regulator headroom monitor for each core or detection of a voltage droop by the droop detector for each core. The adaptive voltage headroom control device, in response to either a headroom violation event or a droop event satisfying a predetermined criterion, is further configured to: (1) lower the operating frequency of each core clock signal to a reduced operating frequency; (2) monitor the headroom violation event and the droop event at the reduced operating frequency; and (3) change the voltage set point related to the VRM to a second voltage set point corresponding to a higher voltage if the monitored headroom violation event or the monitored droop event continues to satisfy the predetermined criterion even at the reduced operating frequency.

[0030] Each of the per-core voltage regulators can include a low dropout (LDO) regulator, and a headroom violation event can correspond to a headroom violation associated with each LDO regulator. Each of the per-core voltage regulators can include a low dropout (LDO) regulator, and a voltage droop event can correspond to a droop associated with the output voltage of each LDO regulator.

[0031] The adaptive voltage headroom control device can be configured to independently limit the frequency of each core clock signal by masking each core clock signal. The adaptive voltage headroom control device can be further configured to increase the operating frequency of one or more of the respective core clock signals after operating the system for a predetermined period after changing the voltage setpoint associated with the VRM to a second voltage setpoint associated with the VRM.

[0032] The adaptive voltage headroom control device can be further configured to lower the headroom associated with one or more of the per-core voltage regulators after operating the system for a predetermined period after changing the voltage setpoint associated with the VRM to a second voltage setpoint associated with the VRM. The per-core frequency controller can be further configured to monitor each core voltage and increase the limited operating frequency of each core clock signal to its original frequency after each core voltage has recovered from a voltage droop.

[0033] In another example, the present disclosure relates to a method for adaptively controlling voltage headroom for a system including (1) a system-on-chip (SoC) including a plurality of cores, and (2) a voltage regulator module (VRM), where the voltage regulator module (VRM) is based on a voltage setpoint associated with the voltage regulator module (VRM) and is configured to supply an input voltage to each of the voltage regulators for each core in the SoC, and each voltage regulator for each core is configured to supply an output voltage to a corresponding core from among the plurality of cores. The method can include independently restricting the operating frequency of each core clock signal in response to either detection of a headroom violation by a per-core voltage regulator headroom monitor or detection of a voltage droop by a per-core droop detector.

[0034] The method can further include, in response to either a headroom violation event or a droop event meeting a predetermined criterion, (1) reducing the operating frequency of each core clock signal to a reduced operating frequency, (2) monitoring the headroom violation event and the droop event at the reduced operating frequency, and (3) changing the voltage setpoint associated with the VRM to a second voltage setpoint corresponding to a higher voltage if the monitored headroom violation event or the monitored droop event continues to meet the predetermined criterion even at the reduced operating frequency.

[0035] Each of the voltage regulators for each core can include a low dropout (LDO) regulator, and the headroom violation event can correspond to a headroom violation associated with each LDO regulator. Each of the voltage regulators for each core can include a low dropout (LDO) regulator, and the voltage droop event can correspond to a droop associated with the output voltage of each LDO regulator.

[0036] Independently restricting the frequency of each core clock signal can include masking each core clock signal. This method can further include operating the system for a predetermined period after changing the voltage setpoint related to the VRM to a second voltage setpoint related to the VRM, and then increasing the operating frequency of one or more of each core clock signal. This method can further include operating the system for a predetermined period after changing the voltage setpoint related to the VRM to a second voltage setpoint related to the VRM, and then reducing the headroom related to the voltage regulator for each of one or more cores. This method can further include monitoring each core voltage and, after each core voltage has recovered from the voltage droop, increasing the limited operating frequency of each core clock signal to its original frequency.

[0037] In yet another example, the present disclosure relates to a system including a system-on-chip (SoC) including a plurality of cores. The system includes a voltage regulator module (VRM), where the voltage regulator module (VRM) is based on a voltage setpoint related to the voltage regulator module (VRM) and is configured to supply an input voltage to each of the low-dropout (LDO) voltage regulators for each core in the SoC, and each of the LDO voltage regulators for each core is configured to supply an output voltage to a corresponding core from among the plurality of cores. The system can further include an adaptive voltage headroom control device including (1) a voltage controller for controlling the voltage setpoint related to the VRM, (2) a headroom monitor for each LDO voltage regulator for each core, (3) a droop detector for each core, and (4) a frequency controller for each core configured to control the frequency of the core clock signal of each core from among the plurality of cores.

[0038] The adaptive voltage headroom control device can be configured to independently limit the operating frequency of each core clock signal in response to either detection of headroom violation by an LDO voltage regulator headroom monitor for each core or detection of voltage droop by a droop detector for each core. The adaptive voltage headroom control device, in response to either a headroom violation event or a droop event satisfying a predetermined criterion, (1) reduces the operating frequency of each core clock signal to a reduced operating frequency, (2) monitors the headroom violation event and the droop event at the reduced operating frequency, and (3) if the monitored headroom violation event or the monitored droop event continues to satisfy the predetermined criterion even at the reduced operating frequency, further configures to change the voltage set point related to the VRM to a second voltage set point corresponding to a higher voltage.

[0039] The headroom violation event can correspond to a headroom violation related to each LDO regulator. The voltage droop event can correspond to a droop related to the output voltage of each LDO regulator. The adaptive voltage headroom control device can be further configured to independently limit the frequency of each core clock signal by masking each core clock signal.

[0040] The adaptive voltage headroom control device can be further configured to increase the operating frequency of one or more of each core clock signal after operating the system for a predetermined period after changing the voltage set point related to the VRM to the second voltage set point related to the VRM. The adaptive voltage headroom control device can be further configured to lower the headroom related to one or more LDO voltage regulators per core after operating the system for a predetermined period after changing the voltage set point related to the VRM to the second voltage set point related to the VRM.

[0041] It should be understood that the systems, services, devices, methods, terminals, and components described in this specification are merely examples. Alternatively or in addition, the functions described in this specification may be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that may be used include FPGAs, ASICs, application-specific standard products (ASSPs), system-on-chip systems (SoCs), and complex programmable logic devices (CPLDs). Although abstract, the configurations of components that achieve the same function are effectively "associated" so that the desired function is achieved. Thus, any two components in this specification that are combined to achieve a particular function can be considered to be "associated" with each other such that the desired function is achieved regardless of structure or intermediate components. Similarly, any two components so associated can also be considered to be "operably connected" or "coupled" to each other to achieve the desired function. Just because a component is described in this specification as being coupled to another component does not necessarily mean that the components are separate components, as they could be any other implementation of a device, structure, device, system, or function. As an example, component A, which is described as being coupled to another component B, may be a sub-component of component B, component B may be a sub-component of component A, or components A and B may be combined sub-components of another component C.

[0042] The functionality associated with some of the examples described in this disclosure can further include instructions stored on a non-transitory medium. As used herein, the term "non-transitory medium" refers to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Exemplary non-transitory media include non-volatile media and / or volatile media. Non-volatile media includes, for example, hard disks, solid state drives, magnetic disks or tapes, optical disks or tapes, flash memory, EPROM, NVRAM, PRAM, or other such media, or networked versions of such media. Volatile media includes, for example, dynamic memory such as DRAM, SRAM, cache, or other such media. A non-transitory medium is different from a transmission medium, but may be used in conjunction with a transmission medium. A transmission medium is used to transfer data and / or instructions to or from a machine. Exemplary transmission media include coaxial cables, fiber optic cables, copper wire, and wireless media such as radio waves.

[0043] Furthermore, those skilled in the art will recognize that the boundaries between the functionality of the operations described above are merely illustrative. Many of the operations' functionality may be combined into a single operation and / or the functionality of a single operation may be distributed over additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments.

[0044] Although this disclosure provides specific examples, various modifications and changes may be made without departing from the scope of the disclosure as set forth in the following claims. Accordingly, this specification and the figures are to be considered in an illustrative rather than a limiting sense, and all such modifications are intended to be included within the scope of the disclosure. No benefit, advantage, or solution to any problem described herein with respect to a particular example is intended to be construed as a critical, required, or essential feature or element of any or all of the claims.

[0045] Furthermore, as used herein, the terms "a" or "an" are defined as one or more than one. Further, the use of introductory phrases such as "at least one" and "one or more" in the claims is not to be construed to mean that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to an invention having only one such element, even if the same claim contains introductory phrases such as "one or more" or "at least one" and indefinite articles such as "a" or "an". The same applies to the use of definite articles.

[0046] Unless otherwise specified, terms such as "first" and "second" are used to conveniently distinguish between elements described by such terms. Thus, these terms are not necessarily intended to indicate a temporal or other precedence of such elements.

Claims

1. A system-on-a-chip (SoC) containing multiple cores, A voltage regulator module (VRM) is configured to supply an input voltage to each of the core-level voltage regulators in the SoC based on a voltage setpoint associated with the VRM, and each of the core-level voltage regulators is configured to supply an output voltage to a corresponding core from among the plurality of cores. An adaptive voltage headroom control device comprising (1) a voltage controller for controlling the voltage setpoint associated with the VRM, (2) a per-core voltage regulator headroom monitor, (3) a per-core droop detector, and (4) a per-core frequency controller configured to control the frequency of the core clock signal of each of the multiple cores, wherein the adaptive voltage headroom control device The operating frequency of each core clock signal is independently limited in response to either the detection of a headroom violation by the voltage regulator headroom monitor for each core or the detection of droop by the droop detector for each core. Depending on whether a headroom violation event or a droop event satisfies a predetermined criterion, (1) the operating frequency of each core clock signal is reduced to a lower operating frequency; (2) the headroom violation event and droop event are monitored at the lower operating frequency; and (3) if the monitored headroom violation event or monitored droop event continues to satisfy the predetermined criterion at the lower operating frequency, the voltage setpoint associated with the VRM is changed to a second voltage setpoint corresponding to a higher voltage. An adaptive voltage headroom control device configured to perform the following: A system that includes this.

2. The system according to claim 1, wherein each of the voltage regulators for each core includes a low dropout (LDO) regulator, and the headroom breach event corresponds to a headroom breach associated with each LDO regulator.

3. The system according to claim 1, wherein each of the voltage regulators for each core includes a low dropout (LDO) regulator, and the droop event corresponds to a droop associated with the output voltage of each LDO regulator.

4. The system according to claim 1, wherein the adaptive voltage headroom control device is configured to independently limit the frequency of each of the core clock signals by masking each of the core clock signals.

5. A system according to claim 1, wherein the adaptive voltage headroom control device is further configured to operate the system for a predetermined period of time after changing the voltage setpoint associated with the VRM to the second voltage setpoint associated with the VRM, thereby increasing the operating frequency of one or more respective core clock signals.

6. A system according to claim 1, wherein the adaptive voltage headroom control device is further configured to operate the system for a predetermined period of time after changing the voltage setpoint associated with the VRM to a second voltage setpoint associated with the VRM, thereby reducing the headroom associated with one or more per-core voltage regulators.

7. The system according to claim 1, wherein the frequency controller for each core is further configured to monitor the respective core voltage and, after the respective core voltage has recovered from the droop, to raise the limited operating frequency of the respective core clock signal to its original frequency.

8. A method for adaptively controlling voltage headroom for a system, the system comprising (1) a system-on-a-chip (SoC) including a plurality of cores, and (2) a voltage regulator module (VRM), the VRM being configured to supply an input voltage to each of the per-core voltage regulators in the SoC based on a voltage setpoint associated with the VRM, and each of the per-core voltage regulators being configured to supply an output voltage to a corresponding core from among the plurality of cores, the method comprising: The steps include independently limiting the operating frequency of each core clock signal in response to either detection of a headroom violation by a per-core voltage regulator headroom monitor or detection of droop by a per-core droop detector, Depending on whether a headroom violation event or a droop event satisfies a predetermined criterion, the following steps are taken: (1) reducing the operating frequency of each core clock signal to a lower operating frequency; (2) monitoring the headroom violation event and droop event at the lower operating frequency; and (3) if the monitored headroom violation event or monitored droop event continues to satisfy the predetermined criterion at the lower operating frequency, changing the voltage setpoint associated with the VRM to a second voltage setpoint corresponding to a higher voltage. Methods that include...

9. A method according to claim 8, wherein each of the core-level voltage regulators includes a low dropout (LDO) regulator, and the headroom breach event corresponds to a headroom breach associated with the respective LDO regulator.

10. A method according to claim 8, wherein each of the voltage regulators for each core includes a low dropout (LDO) regulator, and the droop event corresponds to a droop associated with the output voltage of each LDO regulator.

11. A method according to claim 8, wherein the step of independently limiting the frequency of each of the core clock signals includes the step of masking each of the core clock signals.

12. A method according to claim 8, further comprising the step of operating the system for a predetermined period of time after changing the voltage setpoint associated with the VRM to the second voltage setpoint associated with the VRM, thereby increasing the operating frequency of one or more respective core clock signals.

13. A method according to claim 8, further comprising the step of operating the system for a predetermined period of time after changing the voltage setpoint associated with the VRM to the second voltage setpoint associated with the VRM, thereby reducing the headroom associated with one or more per-core voltage regulators.

14. A method according to claim 8, further comprising the steps of monitoring each core voltage and, after each core voltage has recovered from the droop, raising the limited operating frequency of each core clock signal to its original frequency.

15. A system-on-a-chip (SoC) containing multiple cores, A voltage regulator module (VRM) is configured to supply an input voltage to each of the core-level low-dropout (LDO) voltage regulators in the SoC based on a voltage setpoint associated with the VRM, and each of the core-level LDO voltage regulators is configured to supply an output voltage to a corresponding core from among the plurality of cores. An adaptive voltage headroom control device comprising: (1) a voltage controller for controlling the voltage setpoint related to the VRM; (2) a per-core LDO voltage regulator headroom monitor; (3) a per-core droop detector; and (4) a per-core frequency controller configured to control the frequency of the core clock signal of each of the multiple cores, wherein the adaptive voltage headroom control device The operating frequency of each core clock signal is independently limited in response to either the detection of a headroom violation by the LDO voltage regulator headroom monitor for each core or the detection of droop by the droop detector for each core. Depending on whether a headroom violation event or a droop event satisfies a predetermined criterion, (1) the operating frequency of each core clock signal is reduced to a lower operating frequency; (2) the headroom violation event and droop event are monitored at the lower operating frequency; and (3) if the monitored headroom violation event or monitored droop event continues to satisfy the predetermined criterion at the lower operating frequency, the voltage setpoint associated with the VRM is changed to a second voltage setpoint corresponding to a higher voltage. An adaptive voltage headroom control device configured to perform the following: A system that includes this.

16. The system according to claim 15, wherein the headroom violation event corresponds to a headroom violation associated with each LDO regulator.

17. The system according to claim 15, wherein the droop event corresponds to a droop associated with the output voltage of each LDO regulator.

18. The system according to claim 15, wherein the adaptive voltage headroom control device is configured to independently limit the frequency of each of the core clock signals by masking each of the core clock signals.

19. A system according to claim 15, wherein the adaptive voltage headroom control device is further configured to operate the system for a predetermined period of time after changing the voltage setpoint associated with the VRM to the second voltage setpoint associated with the VRM, thereby increasing the operating frequency of one or more respective core clock signals.

20. A system according to claim 15, wherein the adaptive voltage headroom control device is further configured to operate the system for a predetermined period of time after changing the voltage setpoint associated with the VRM to the second voltage setpoint associated with the VRM, thereby reducing the headroom associated with one or more core-level LDO voltage regulators.

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