Power estimation system

Abstract

This application relates to a power estimation system. A method for power estimation for integrated circuit design includes loading a test vector into a first sequence of flip-flops in scan mode, evaluating the test vector in scan mode and saving the results of the evaluation in a second sequence of flip-flops, reading the results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vector is received from an automatic test pattern generator.

Description

[0001] Priority

[0002] This application claims priority to U.S. Provisional Application No. 62 / 704,204, filed April 27, 2020, and incorporates that application in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to power analysis, and in particular, to power estimation based on analysis of test patterns without simulation or emulation. BACKGROUND

[0004] Test patterns are used to verify the integrity of manufactured silicon circuits. Manufactured chips are placed into a tester and the patterns are input into the device using scan chains. The test pattern input is optimized to provide maximum control and visibility into manufacturing defects.

[0005] During scan testing, test patterns are loaded into the circuit serially through a set of scan chains. During this loading process, the number of toggles inside the circuit is high and peak glitch power can overload the tester or damage the silicon.

[0006] To eliminate these power problems, the circuit with the test patterns can be simulated using standard delay format (SDF) delays, followed by a power calculation. This gate level simulation and power estimation is slow and can take a significant amount of time (e.g., weeks) to perform, even using a computing grid, due to the length of the test vectors.

[0007] Emulation cannot solve this problem because detailed delay information is needed, which is typically not supported by emulators.

[0008] Detailed and accurate power calculation using all waveforms is slow, but is needed using simulation or emulation outputs. SUMMARY

[0009] A method for power estimation of a portion of an integrated circuit design includes loading a test vector into a first sequence of flip-flops in a scan mode, evaluating the test vector in the scan mode and saving results of the evaluation in a second sequence of flip-flops, reading the results out of the second sequence of flip-flops to a scan chain, and calculating power used by the portion of the integrated circuit design based on the results. BRIEF DESCRIPTION OF DRAWINGS

[0010] The disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like references indicate similar elements and in which:

[0011] Figure 1A One embodiment of a method for power estimation for test vector stimulation is described.

[0012] Figure 1B An embodiment of an improved method for power estimation is described.

[0013] Figure 2 This is a block diagram of one embodiment of a power estimation system.

[0014] Figure 3 This is an overview flowchart of one embodiment of the power estimation process.

[0015] Figure 4 This is a flowchart of an embodiment of a power analysis system using an integrated waveform and power engine method.

[0016] Figure 5 A simplified diagram illustrating one embodiment of the components involved in the process is shown.

[0017] Figure 6 This describes one example of loading scan data.

[0018] Figure 7 This is a block diagram of one embodiment of the evaluation between sequential elements.

[0019] Figure 8 Explain the instance value of the sequence element.

[0020] Figure 9 This describes the evaluation sequence over time.

[0021] Figures 10A to 10C Explain the typical peak power type.

[0022] Figure 11A Explain the instance matrix.

[0023] Figure 11B Explanation of the processed Figure 11A The matrix.

[0024] Figure 12 Flowcharts depicting various processes used during the design and manufacture of integrated circuits according to some embodiments of the present disclosure.

[0025] Figure 13 A diagram depicting an example computer system in which embodiments of the present disclosure may operate. Detailed Implementation

[0026] This application addresses the power analysis problem of test vectors by eliminating gate-level simulation or emulation. An integrated waveform and power engine approach is used to directly compute test pattern data. In one embodiment, test pattern data is received from an automated test pattern generator that computes relevant data to simulate a specific pattern or loop of interest without serially simulating previous loops to reach the desired loop. Using initial state data generated by the automated test pattern generator enables faster and partial simulations, and also eliminates the need to decompress compressed scan chains. The test pattern comprises a series of 0 / 1 values ​​shifted into the silicon device using a serial scan chain. This pattern dataset is the value of each sequential unit in the scan chain. From the test pattern data, the system can directly identify the values ​​of all scan elements in the design for the entire test.

[0027] If the sequence values ​​are known, waveform calculation techniques are used to compute the values ​​of all combined elements. The values ​​of all sequence elements are known from the scan chain; therefore, this method efficiently computes all nodes in the design. The integrated power engine then performs a fast approximate power estimate on the gate-level netlist using the waveform values ​​of each node.

[0028] This provides fast power estimation. Because the initial state data applies to a relevant subset of the transition, the power estimator will provide data much faster. This power calculation can be performed after each test vector is generated, and it can regenerate any vector exceeding the maximum power value. This yields a set of test vectors that meet the power requirements.

[0029] In one embodiment, the scan vectors are also cascaded to form a series of scan tests. Each of these vectors overlaps with the next / previous set. A vector is read from silicon while the next vector is loaded into silicon. Power calculation is a combination of switching during vector readout and switching during next vector loading. Individually calculating the power of each vector allows the system to reorder and calculate the power of all type combinations, thereby achieving an optimal order to meet power requirements. Therefore, the power estimation system provides fast, relevant, and accurate power estimates for all type combinations, enabling the selection of the optimal type order for the power requirements of the integrated circuit.

[0030] Figure 1AThis describes one embodiment of a method for power estimation of a test vector stimulus. In one embodiment, the process includes generating a test vector at 110 using a test pattern generator. The process further includes simulating or analogizing the test vector on a gate-level netlist with an SDF delay at 120. The process further includes saving the waveform in a Fast Signal Database (FSDB) or another waveform format at 130, and performing a loop-based power analysis using a power analysis system at 140. As will be described in more detail below, the power analysis system determines the peak power and whether the test vector meets the power requirements of the circuit.

[0031] In one embodiment, a serial scan chain is used to load test vectors into the design. This allows control of any sequential triggers by loading the required data via the scan chain. Otherwise, it would be difficult or impossible to control these sequential units using design logic.

[0032] Figure 1B This describes one embodiment of the system and method used to provide power estimation. A test pattern generator 150 generates a test pattern and transmits data 160 to a power analyzer 170, which generates a peak power map 180. Figure 1A Compared to the method described in [the previous section], this method does not utilize gate level simulation. This makes it more efficient in terms of both time and computational cost.

[0033] Figure 2 This is a block diagram of one embodiment of a power estimation system. The power estimation system 200 includes an automatic test pattern generator 220 and a power analysis system 230. In one embodiment, the power estimation system 200 is implemented in a computer system. In another embodiment, different parts of the power estimation system 200 may be implemented in different systems. The power estimation system 200 is used in integrated circuit design and / or verification to ensure that power requirements are met, as will be discussed below. This system provides an improved power estimation system that offers technical improvements in the design and testing of circuits such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.

[0034] The input to the automated test pattern generator 220 is a design typically in netlist format 205. The netlist represents an integrated circuit design or a portion thereof. In one embodiment, the test target is selected by a user via user interface 210. The test target identifies a subset of cycles of interest for evaluation. In one embodiment, the test target also identifies portions of the integrated circuit of interest for evaluation. In one embodiment, the system is used to evaluate a subset of cycles that may cause power spikes or exceed capacity. In one embodiment, the user can identify such cycles. In another embodiment, other systems 215 can identify such cycles for evaluation.

[0035] The Automatic Test Pattern Generator (ATPG) 220 receives requests for the state of sequential elements in a selected shift and / or capture cycle. The ATPG 220 provides value outputs to the power analysis system. The ATPG 220 uses test pattern generation to determine the state of relevant elements in a selected pattern / cycle. Relevant elements may include one or more of scanned elements and non-scanned elements (sequential or combined). The ATPG 220 can output any combination of the initial and final states of the elements.

[0036] In one embodiment, the ATPG 220 outputs the initial states of all scanned and non-scanned elements whose values ​​can be determined. In one embodiment, this covers most of the non-scanned elements in the design. In another embodiment, the ATPG 220 provides the initial and final states of all scanned and non-scanned elements in the design. In another embodiment, the ATPG 220 provides the initial states of all scanned and non-scanned elements as well as the initial states of all combined elements. In yet another embodiment, the ATPG 220 provides the initial and final states of scanned and non-scanned elements, as well as the initial and final states of combined elements. The ATPG 220 is capable of providing the initial states of all scanned elements, the initial states of non-scanned elements, and the initial states of sequential elements for selected type / cycle selection.

[0037] In one embodiment, the power analysis system 230 receives value outputs from the ATPG 220. In one embodiment, the value outputs are uncompressed. In one embodiment, the value outputs are the initial states of some or all components in a relevant segment of the circuit. In one embodiment, the initial states of sequential scan, sequential non-scan, and combined components may be provided to the power analysis system 230. In one embodiment, the ATPG 220 provides compressed outputs to the silicon tester system 280 for manufacturing testing, diagnostics, and fault analysis after chip production. The silicon tester system 280 applies the ATPG format to the manufactured device to verify chip functionality.

[0038] Scan logic 235 scans data into scan chain 240. The data used by scan logic 235 is the initial state data provided by ATPG 220. Then, before the output is scanned by scan logic 235, the data in scan chain 240 is evaluated by waveform evaluator 245. Scan inputs and outputs can be performed in parallel, as will be discussed below. Waveform evaluator 245 can be any waveform evaluator. The waveform evaluator evaluates the design logic between sequential elements to calculate the value of the target sequential element for one or more cycles of the design evaluation clock.

[0039] The combined node calculator 250 uses a scan-chain-based evaluation to calculate the power generated as a combination of two test patterns, as described in more detail below. Matrix logic 255 identifies the order of the patterns to select the lowest power value and identifies the lowest power path. Matrix logic 255 utilizes a power matrix containing power values ​​as an NxN matrix—one row for each pattern to be run first and one column for each pattern to be run next. Matrix logic 255 analyzes the power logic to identify the order of the patterns based on the lowest combined power value.

[0040] Power estimator 260 performs tests in an identified order and uses an overlapping pattern to measure power. In one embodiment, power estimator 260 uses scan chain 240. Evaluator 265 evaluates the power results to determine if they meet power criteria. If not, regeneration trigger 270 triggers pattern regeneration. In one embodiment, power analysis system 230 can trigger automatic test pattern generator 220 via application programming interface (API) 275 to generate an updated pattern or provide subsequent data.

[0041] Figure 3 This is a flowchart of one embodiment using a power estimation system. The process begins at 310. In one embodiment, this process is part of the logic design and functional verification process of the circuit design.

[0042] At 320, the system receives a specific pattern of interest for a given shift and / or capture cycle. In one embodiment, this data may be selected by the user. In another embodiment, other systems may identify specific patterns that may cause power spikes or peaks and use those patterns.

[0043] At 330, the ATPG calculation will pass the state data to the power estimator. The state data may contain the initial states of some or all sequential scans, sequential non-scans, and combined elements of the selected shift / capture cycle. The state data may additionally or alternatively contain the final states of these elements.

[0044] At point 340, the state data is passed to the power estimator. In one embodiment, the data is passed from the ATPG in its uncompressed state. In another embodiment, a separate system can be used to decompress the data.

[0045] At 350, a scan chain is used to evaluate the power of the type of interest. Figure 4 One embodiment of this calculation is provided. Other methods can be used to calculate power based on the start and / or end states of the element.

[0046] At 360, the process determines whether the value is within range. If the value does not exceed the maximum power and is not lower than a threshold, then the value is considered to be within range. If the result is within range, then at 370, the result is output for evaluation. In one embodiment, this may include outputting a power curve to the user on the user interface. The process then ends at 380.

[0047] If the result is outside the range, it is discarded at position 390, and the regeneration of state data is triggered. In one embodiment, the system may warn the user that the result is out of range. In another embodiment, these results may also be used for evaluation and may be tagged.

[0048] Figure 4 This is a flowchart of one embodiment using a scan chain to evaluate power. In one embodiment, Figure 4 Corresponding to Figure 3 350. Return to Figure 4 The process begins at 410, where data is received from ATPG.

[0049] At position 415, the scan data is serially loaded into the trigger. The scan data represents the initial state of the element being evaluated, received from the ATPG. The scan data is the initial state data received from the ATPG.

[0050] At 420, the design is time-controlled for one or more loops in normal mode. This shifts the state forward by a certain number of loops.

[0051] At position 425, the system evaluates the loop and stores the value in the sequence unit.

[0052] At point 430, the process determines whether there is more data to be evaluated. That is, whether there is still any unevaluated data. If so, the process continues to point 435.

[0053] At 435, the result is read out and, in parallel, the value for the next evaluation is moved into the trigger. This enables parallel data processing and accelerates the evaluation. The process then returns to 420 to time the design using additional scan data.

[0054] If no further unevaluated data is found at 430, the final set of values ​​is read from the scan chain at 440. Then, the power is calculated using the saved data at 445. The process then ends at 450.

[0055] Figure 5 A simplified diagram illustrating one embodiment of the components involved in the power estimation process. Scan input data 510 is serially loaded into flip-flops 520FF_A1 to FF_A4.

[0056] This scan chain is a set of sequential elements connected and controlled by scan logic. In 'scan mode', the input of each flip-flop is driven from the previous flip-flop in the scan chain. Using this method, sequential elements can be loaded serially using the scan_enable and scan_in data pins. For a scan chain with 1000 sequential elements, 1000 clock cycles are required to serially load all data into the design.

[0057] Test pattern generators typically generate compressed pattern sets, which are then decompressed by circuitry existing on silicon. This allows for smaller test patterns, and in many cases, multiple scan chain data can be derived from a single compressed test pattern. The uncompressed pattern is then provided to this waveform and power calculation system and method.

[0058] A subset of uncompressed waveforms can be provided to this waveform and power calculation system and method. The test pattern generator can perform some kind of switching-based analysis on the uncompressed waveforms to determine which waveforms or which slices of waveforms are more likely to cause peak power events. These waveforms or slices can then be analyzed using the described process.

[0059] Next, the design is timed for one or more cycles in normal (non-scan) mode. All design logic 530 is evaluated and the new design values ​​are stored in sequence units FF_B1 to FF_B4 540. Then, the scan chain is shifted again, and in one embodiment, the same scan chain logic as the scan output data 550 is used to shift the results from the design evaluation phase out of the design. For a scan chain with 1000 sequence elements, 1000 clock cycles are used to serially read all data from the design.

[0060] The values ​​of all sequential elements are known during the scan loading phase. For example... Figure 6 As shown, as scan data is loaded into the design, each sequential element at scan chain position #N will have a value specified by scan_data[TN].

[0061] During the evaluation phase of the design, all sequential elements are known. A waveform evaluator can evaluate the design logic between sequential elements to calculate the value of the target sequential element, such as... Figure 7 As explained in [the document]. This can be used for a single cycle, or for any number of design evaluation clocks.

[0062] During the scan-read phase, a scan chain is used to read sequential values ​​from the design. The value of each sequential element flows through the scan chain, and these values ​​are known from the previous step. Each sequential element at position T has scan_data[T+N], as shown below. Figure 8 As explained in the text.

[0063] In one embodiment, the scan loading and scan reading phases occur in parallel. When the data value of vector M is read from the design, the scan chain value of vector M+1 is loaded into the design. A combination of these two methods is used to calculate power. Figure 9 This illustrates a simplified example of this sequence over time. In this example, data is shifted in for four cycles, and then evaluated for one cycle. In this way, the data is evaluated over time.

[0064] To calculate the power of the gate-level design during the scan-load / read phase, the value of each sequential element is used. Then, waveform evaluation techniques are applied to calculate the value of each combination node in the circuit without performing sequential simulation of the design.

[0065] In one embodiment, two methods are used to calculate the value of each sequential unit.

[0066] • As data is scanned into the design, test vector data flows through the scan chain. All sequential element values ​​can be determined from the test vector data, for example, sequential element value [N] = scan_vector[TN].

[0067] • As data is read from the design, values ​​from the evaluation phase are shifted through the scan chain. All sequential component values ​​can be determined from the design evaluation data, for example, sequential component value [N] = design_evaluation_value [T+N].

[0068] The values ​​of all sequential units can be determined using the methods described above. Since the sequential values ​​are now known for the full test vector loading / storage phase, the values ​​of all combined nodes can be calculated. This can be achieved by running a simulation method to evaluate all nodes at times t1, t2, and t3, or by using a waveform evaluation method.

[0069] If waveform evaluation is used in one embodiment, then each gate in the circuit can be evaluated once. The input pin values ​​are known, and the unit can be evaluated once for all output pin values. This has the advantage of eliminating contention and allowing efficient scheduling of the design on multi-threaded or multi-host computing environments. Since there is no cycle-by-cycle communication between computing threads, dynamic task scheduling is simplified.

[0070] Next, design evaluation occurs when the design is brought into normal mode and evaluated for one or more clock cycles. In this case, the design logic is evaluated and the value of each flip-flop is driven, except for the design logic (excluding test / scan logic). In one embodiment, the design evaluation occurs using the same technique as the scan load / read phase.

[0071] Since the waveform is now known to all sequential and combined units in the design, it can be used in different types of power estimation methods. These methods can be more accurate but more complex and slower, or less accurate but less complex and faster. This will yield average and peak power results for the test configuration.

[0072] In one embodiment, the power calculation can be initiated by a test pattern generator to calculate the power. If the power exceeds the maximum value, the test pattern can be discarded and regenerated using a sequence of different values. This yields a set of test patterns that meet the power target.

[0073] The power generated during test pattern execution is a combination of two test patterns. As the results are read from the first test pattern, the next test pattern is read into the design. To calculate the power of a pattern, both patterns can be obtained and used simultaneously.

[0074] This overlap means that the generated power depends on the order of the test types, and the power can be optimized by reordering the test types. A combination of two types may cause a high power spike, but no spike is observed when each of the individual types is paired with a different type.

[0075] In one embodiment, as the scan chain is ordered based on layout or other information, the scan triggers in the design are in some arbitrary but fixed order. The combinational logic driven by a set of sequential elements will have data from both the new scan pattern and the results from the previous pattern.

[0076] Peak power from various types can occur at different cycles within each type. Figures 10A to 10C Explain the typical peak power type.

[0077] For example, if the patterns are executed in the order of 1+2+3, the peak power of the scan output (cycle 5) of pattern #2 is aligned with the peak power of the scan input (cycle -5) of pattern #3. If the patterns are reordered as 3+2+1, these peaks will not be aligned and the maximum power will be reduced.

[0078] In one embodiment, each model can be executed using the next / previous data with fixed 0x0 and 0x1, and the model power from the two runs can be averaged. Then, the power maps of each pair of models can be summed, with the scan output + scan input time aligned and the peak power calculated.

[0079] In one embodiment, each power value is placed in an NxN matrix—one column for each model that runs first and one column for each model that runs next. When rows equal columns, the matrix will have a set of empty entries. This matrix is ​​also called a power matrix.

[0080] Figure 11A Explain the instance matrix.

[0081] In one embodiment, the process then removes all entries in which the power exceeds the maximum value. Figure 11B This describes the matrix after removing such entries. If any row is empty, then the power of this type with any other type will exceed the maximum power value. In one embodiment, the solution is to remove this type and regenerate the type. The system can repeat this process until all rows have one or more valid entries.

[0082] In one embodiment, the process iterates over the matrix and labels each entry in the matrix with a priority. In one embodiment, the entry with the maximum power value in the matrix is ​​the starting point, and the process then proceeds in descending order. In one embodiment, the system removes the entry with the maximum value while maintaining two values ​​per column and two values ​​per row.

[0083] In one embodiment, the evaluation process is as follows:

[0084] • Traverse the matrix to generate the test pattern order.

[0085] • Start with the cell that has the minimum value (in this example, cell 1120 at row 4, column 5 has the value 1.11).

[0086] • Identify the test type associated with the cell (in this example, test type #4 is followed by test type #5, represented by rows and columns).

[0087] • Invalidate column #4, because this test type is now in the test list.

[0088] • Find the minimum value in the row of the second test pattern (row #5 in this case, cell 1130, row #5 and column #6, has a value of 1.19).

[0089] • Invalidate column #5.

[0090] Repeat until the matrix traversal is complete.

[0091] Selecting the minimum of the column associated with the minimum unit will select the next form with the lowest power. As the system traverses the matrix in this way, it will end with the lowest power path or the near-lowest power path. It may be impossible to identify the lowest power path because identifying the absolute lowest power path is an NP-incomplete problem. However, even if it may not be the absolute lowest possible order, this process selects the near-optimal order.

[0092] In one embodiment, the process uses each of the tests in the test sequence to perform power estimation and utilizes an overlapping pattern to measure power. The test pattern power may differ because this uses the actual pattern value of the previous-next pattern instead of the fixed 0x0 / 0x1 values ​​used earlier in the algorithm. The patterns are loaded via a serial scan chain, so the power used during this loading period can be calculated from the value each flip-flop will have during this loading. However, in one embodiment, as a pattern is loaded, a previous pattern is unloaded simultaneously. For example, if the pattern is 1k flip-flops long—the first 500 bits of the scan chain are known from this pattern when the system has loaded 500 bits. But the next 500 bits are still set to the value of the previous pattern being unloaded because loading and unloading occur simultaneously. This means the system cannot easily calculate the active power of the unloaded portion because that active power can be any value. Power is the flip-flops that drive all combinational logic in the design. For example, in one design, there is an AND gate using flip-flops 500+501. The value at trigger 500 is known because it has just been loaded, but the value at trigger 501 is unknown. Therefore, the system can calculate the power of the N loaded triggers, but must guess the 0x0 or 0x1 of the remaining triggers (which are not yet loaded but are being unloaded).

[0093] If any type exceeds the maximum power, the process updates these values ​​in the matrix and repeats matrix optimization and traversal to obtain the new type order. This process is repeated as needed until the minimum test type power is reached. In this way, the system provides a method for evaluating the power usage of a design without requiring gate-level simulation or modeling.

[0094] Figure 12 This describes a set of process instances 1200 used during the design, verification, and manufacturing of, for example, an integrated circuit, to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be structured and enabled as multiple modules or operations. The term 'EDA' stands for 'Electronic Design Automation'. These processes begin with the creation of a product concept 1210 using information provided by a designer, which is then transformed to create an article of art using the EDA process set 1212. When the design is complete, the design exits 1234, at which point the original of the integrated circuit (e.g., a geometric pattern) is sent to a manufacturing plant to create a mask set, which is then used to manufacture the integrated circuit. After exiting, semiconductor dies are manufactured 1236, and packaging and assembly processes 1238 are performed to produce the finished integrated circuit 1240.

[0095] Specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. Using hardware description languages ​​('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera, higher representation levels are used to design circuits and systems. HDL descriptions can be transformed into logic-level register-transfer-level (RTL) descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower representation level, as a more detailed description, adds more useful details to the design description, such as more details about the modules contained in the description. Lower representation levels, as more detailed descriptions, can be computer-generated, exported from design libraries, or created by another design automation process. An example of a specification language at a lower representation language level used to specify more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. Descriptions at each representation level are enabled for use by the corresponding tools (e.g., formal verification tools) at that level. The design process can use... Figure 12 The sequence described herein. The described process can be enabled by EDA products (or tools).

[0096] During system design 1214, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics (e.g., power consumption, performance, area (physical and / or lines of code), and cost reduction). At this stage, the design can be divided into different types of modules or components.

[0097] During logic design and functional verification 1216, modules or components in the circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, components of the circuit can be verified to generate outputs that match the specifications of the circuit or system being designed. Functional verification can use simulators and other programs, such as testbed generators, static HDL checkers, and formal verifiers. In some embodiments, a special system for components, referred to as a 'simulator' or 'prototype system', is used to accelerate functional verification. In one embodiment, this power type testing falls within logic design and functional verification 1216.

[0098] During the synthesis and design phase 1218 of the test, the HDL code is transformed into a netlist. In some embodiments, the netlist may be a graphical structure, wherein the edges of the graphical structure represent components of the circuit and the nodes of the graphical structure represent the interconnections of the components. Both the HDL code and the netlist are layered artifacts that can be used by EDA products to verify that the integrated circuit operates according to a specified design when it is manufactured. The netlist can be optimized for a target semiconductor manufacturing technology. In addition, the finished integrated circuit can be tested to verify that the integrated circuit meets specifications.

[0099] During netlist verification (1220), the compliance of the netlist with timing constraints and its correspondence with HDL code are checked. During design planning (1222), the overall layout of the integrated circuit is constructed and analyzed for timing control and top-level routing.

[0100] During layout or physical implementation 1224, physical placement (e.g., the positioning of circuit components such as transistors or capacitors) and wiring (connection of circuit components via multiple conductors) occur, and cell selection from a library can be performed to enable specific logic functions. As used herein, the term 'cell' can specify a group of transistors, other components, and interconnects that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit 'block' can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are enabled both as physical structures and in simulation. Parameters, such as size, are specified for the selected cell (based on 'standard cells') and these parameters are made accessible in a database for use in EDA products.

[0101] During the analysis and extraction phase 1226, circuit functionality is verified at the layout level, allowing for improvements to the layout design. During physical verification 1228, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, and lithographic constraints, and that the circuit system functionality matches the HDL design specifications. During resolution enhancement 1230, the geometry of the layout is transformed to improve the fabrication methods of the circuit design.

[0102] During the exit phase, data is created for the production of the photomask (where appropriate, after applying lithographic enhancement). During mask data preparation 1232, the 'exit' data is used to produce the photomask for manufacturing the finished integrated circuit.

[0103] Computer systems (e.g.) Figure 12 The storage subsystem of the computer system 1200 or the host system 1007 of Figure 10 can be used to store programs and data structures used by some or all of the EDA products described herein, as well as by the physical and logical design of products for the development of libraries and the use of libraries.

[0104] Figure 13An example machine of computer system 1300 is described, within which an instruction set for causing the machine to perform any one or more of the methods discussed herein can be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer computer in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0105] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) specifying the actions to be taken by that machine. Furthermore, while a single machine is described, the term "machine" should also be understood to include any collection of machines that individually or collectively execute a set of instructions (or more sets of instructions) to perform any of the methods or methods discussed herein.

[0106] The example computer system 1300 includes a processing device 1302, a main memory 1304 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM)), a static memory 1306 (e.g., flash memory, static random access memory (SRAM) and the like), and a data storage device 1318, which communicate with each other via a bus 1330.

[0107] Processing device 1302 represents one or more processors, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 1302 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1302 may be configured to execute instructions 1326 to perform the operations and steps described herein.

[0108] The computer system 1300 may further include a network interface device 1308 for communication via a network 1320. The computer system 1300 may also include a video display unit 1310 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1312 (e.g., a keyboard), a cursor control device 1314 (e.g., a mouse), a graphics processing unit 1322, a signal generation device 1316 (e.g., a speaker), a video processing unit 1328, and an audio processing unit 1332.

[0109] Data storage device 1318 may include machine-readable storage medium 1324 (also referred to as non-transitory computer-readable medium) on which one or more instruction sets 1326 or software embodying any one or more methods or functions described herein are stored. Instructions 1326 may also reside wholly or at least partially in main memory 1304 and / or processing device 1302 during execution by computer system 1300, which also constitute machine-readable storage medium.

[0110] In some embodiments, instruction 1326 includes instructions for implementing functionality corresponding to this disclosure. While machine-readable storage medium 1324 is shown as a single medium in example embodiments, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated cache and server) storing one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding sets of instructions for machine execution and causing the machine and processing device 1302 to perform any one or more methods of this disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0111] The algorithms and symbolic representations for manipulating data bits within computer memory have been described in detail above. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. An algorithm is a sequence of operations that yields a desired result. These operations are those that require physical manipulation of physical quantities. Such quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0112] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. As will be apparent from this disclosure, unless specifically stated otherwise, it should be understood that certain terms throughout the description refer to the operation and processes of a computer system or similar electronic computing device that manipulates and transforms data representing physical (electronic) quantities in the registers and memories of the computer system into other data representing physical quantities similarly represented in the memory or registers or other such information storage devices of the computer system.

[0113] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically configured for its intended purpose, or may comprise a computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0114] The algorithms and displays presented herein are not inherently associated with any particular computer or other device. Various other systems may be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0115] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0116] In the foregoing disclosure, embodiments of this disclosure have been described with reference to specific example embodiments thereof. A detailed description of embodiments of the invention is given with reference to the accompanying drawings, wherein similar references indicate similar elements, illustrating specific embodiments for practicing the invention by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Those skilled in the art will understand that other embodiments and logical, mechanical, electrical, functional, and other changes may be made without departing from the scope of the invention.

[0117] It will be apparent to you that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Where elements are referred to in a singular sense in this disclosure, more than one element may be depicted in the figures and similar elements may be labeled with similar numbers. Therefore, this disclosure and the accompanying drawings should be considered illustrative rather than restrictive, and the scope of this disclosure is defined only by the appended claims.

Claims

1. A method for power estimation as a part of an integrated circuit design, comprising: In scan mode, the test vector is loaded into the first trigger sequence; The test vector is evaluated in scanning mode and the evaluation result is stored in a second trigger sequence; Read the result from the second trigger sequence into the scan chain; The power used by the portion of the integrated circuit design is calculated based on the results, and the results are used to evaluate the power of each test vector; The test vectors are reordered; and Calculate the power of the reordered test vectors.

2. The method of claim 1, wherein a serial scan chain is used to load the test vector.

3. The method of claim 1, wherein the automatic test pattern generator provides the test vector for the power estimation, the test vector including the initial states of a plurality of elements in the integrated circuit design, such that gate-level simulation is not used.

4. The method of claim 3, wherein the automatic test pattern generator generates the test vector of the pattern of interest for evaluation by the power estimation.

5. The method according to claim 1, wherein: The test vectors are cascaded to form a series of scan tests; and Each of the test vectors overlaps with both the next set of test vectors and the previous set of test vectors.

6. The method of claim 1, further comprising: Calculate the power for all combinations of types.

7. The method of claim 6, wherein a power matrix is ​​used to calculate the combination.

8. The method of claim 7, further comprising: Remove the elements representing power levels above the threshold from the power matrix.

9. The method of claim 8, further comprising: The evaluation is iterated over the power matrix, and each entry in the power matrix is ​​marked with a priority, such that the maximum power value in the matrix is ​​the starting point.

10. A power estimation system for integrated circuit design, comprising: Scan logic, configured to load test vectors into a first trigger sequence in scan mode; A waveform evaluator configured to evaluate the test vector in a scan mode and store the evaluation result in a second trigger sequence; The scan logic is further configured to read the result from the second trigger sequence into the scan chain; and A power estimator, configured to: Based on the results, calculate the power used by the portion designed by the integrated circuit. Evaluate the power of each test vector. The test vectors are reordered, and Calculate the power of the reordered test vectors.

11. The system of claim 10, further comprising: A serial scan chain, wherein the test vector is loaded using the serial scan chain.

12. The system of claim 10, further comprising: An automatic test pattern generator is configured to provide an initial state for the components of the integrated circuit design, the initial state including the test vector, such that gate-level simulation is not used.

13. The system of claim 12, wherein the automatic test pattern generator generates the test vector of the pattern of interest for evaluation by the power estimation system.

14. The system of claim 10, wherein the test vectors are cascaded to form a series of scan tests, and each of the test vectors overlaps with the next set of test vectors and the previous set of test vectors.

15. The system of claim 10, further comprising: The power estimator is configured to calculate the power for all combinations of types.

16. The system of claim 15, wherein a power matrix is ​​used to calculate the combination.

17. The system of claim 16, further comprising: The matrix logic is further configured to remove elements representing power levels above a threshold from the power matrix.

18. A power estimation system, comprising: An automatic test pattern generator, configured to evaluate test vectors for multiple components in a selected pattern generation circuit; A power analysis system for receiving the test vector from the automatic test pattern generator, the power analysis system comprising: Scan logic, configured to load test vectors into a first trigger sequence in scan mode; A waveform evaluator configured to evaluate the test vector in a scan mode and store the evaluation result in a second trigger sequence; The scan logic is further configured to read the result from the second trigger sequence into the scan chain; and A power estimator configured to calculate power generation based on the results, evaluate the power of each test vector, reorder the test vectors, and calculate the power of the reordered test vectors.

19. The system of claim 18, wherein the automatic power test pattern generator receives one or more selected cycles as input for evaluation.

20. The system of claim 18, wherein the power analysis system further comprises: A matrix logic configured to select a pairing pattern from a power matrix containing power values ​​for all pattern combinations, wherein the matrix logic selects the lowest power pattern combination.

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