Amplitude Limiting Device and Method for a Signal Processing Chain

Abstract

The method (800) includes receiving (850-1) input samples of a signal to be processed by a subsequent device, clipping, and performing a limiting process on at least one of the input samples (850-2), the limiting process including generating an inter-sample prediction value by applying a sub-filter to a corresponding plurality of input samples including the relevant input sample, the sub-filter modeling the inter-sample behavior of the subsequent device, generating an inter-sample prediction value by applying a sub-filter to a corresponding plurality of input samples including the relevant input sample, and replacing the relevant input sample with a reduced sample by applying an offset to the relevant input sample, the reduced sample having the same sign as the relevant input sample but having an amplitude smaller than that of the relevant input sample, and the offset being calculated based on a parameter of the sub-filter and an overshoot difference between a threshold and one of the inter-sample prediction values.

Description

Technical Field

[0001] Various exemplary embodiments generally relate to amplitude limiting devices and corresponding methods for a signal processing chain.

Background Art

[0002] A discrete-time signal needs to be band-limited before being used to modulate a second signal (e.g., a subcarrier). For example, in a system for FM (Frequency Modulation) broadcasting, amplitude overshoot may occur from band-limiting and / or interpolation, which should be avoided or corrected before modulation.

[0003] In another system where input samples representing a band-limited discrete-time signal are converted to a continuous-time signal, amplitude overshoot may occur during conversion, for example, if the discrete-time signal contains out-of-band peripheral frequencies from clipping, or if a low-pass filter, band filter, or interpolation filter is applied during conversion. One solution could be to apply an attenuation gain and / or a low threshold clipping to all input samples to always keep the amplitude of the continuous-time output below the maximum level. However, this represents an excessive reduction in the available output amplitude range.

[0004] Note that continuous-time analog signals from a DAC (Digital to Analog Converter) may generate some artifacts when amplified by an audible amplifier (e.g., a Pulse Width Modulation (PWM) amplifier) before the output amplified signal is supplied to a loudspeaker. In particular, a PWM power amplifier is sensitive to an overly high output voltage that causes overmodulation of the PWM modulator, and may generate audible fractional harmonics when the amplitude of the input voltage amplified by this amplifier is too large and causes an output voltage too close to the rail voltage.

[0005] There appears to be a need for an improved solution to avoid amplitude overshoot generated by a subsequent device (e.g., performing at least one of band limiting, interpolation, upsampling, and possibly DAC conversion on the signal). Such a signal may be any signal, e.g., an audible signal, a broadcast signal, or a signal representing a variation (e.g., over time) of a physical parameter (e.g., voltage, or mechanical position, etc.).

[0006] A typical use case or application is given where a subsequent device may generate "ringing" in the output signal (as a result of the Gibbs phenomenon) in response to a clipped input signal or an input signal containing peaks or steps. SUMMARY OF THE INVENTION

[0007] The scope of protection is indicated by the independent claims. Embodiments, examples, and features described herein that do not fall within the scope of protection, if any, should be construed as useful examples for understanding the various embodiments or examples that do fall within the scope of protection.

[0008] According to a first aspect, there is provided a device comprising signal processing means for performing a method including receiving and clipping input samples of a signal to be processed by a subsequent device and performing a limiting step (hereinafter, the first limiting step) on at least one input sample, wherein the limiting step comprises a corresponding plurality of input samples including the relevant input sample A step of generating an inter-sample prediction value by applying a sub-filter to a sample, the sub-filter including: a step of generating an inter-sample prediction value by applying the sub-filter to a corresponding plurality of input samples including relevant input samples that model the inter-sample behavior of a subsequent device; and a step of replacing the relevant input samples with reduced samples by applying an offset to the relevant input samples, the reduced samples having the same sign as the relevant input samples but having an amplitude smaller than that of the relevant input samples, the offset being calculated based on a parameter of the sub-filter and an overshoot difference between a threshold value and one of the inter-sample prediction values.

[0009] The parameter may include an actual coefficient or an estimated coefficient of an interpolation filter in a subsequent device. The parameter may include a parameter of an actual impulse or an estimated impulse response of a subsequent device.

[0010] The sub-filter that models the behavior of a subsequent device may be a sub-filter of a Finite Impulse Response filter (FIR filter). The parameter may include the coefficients of the FIR filter.

[0011] The method may include calculating a scaled overshoot difference for each of the sub-filters, each scaled overshoot difference being calculated based on an overshoot difference between a threshold value and each inter-sample prediction value generated by the relevant sub-filter.

[0012] The offset may be calculated based on the maximum scaled overshoot difference.

[0013] The offset may be calculated based on the largest coefficient in the absolute value of the sub-filter for which the maximum scaled overshoot difference is calculated.

[0014] The offset may be applied to the input sample to which the largest coefficient is applied in the sub-filter where the largest scaled overshoot difference is calculated.

[0015] The scaled overshoot difference may be scaled based on the largest coefficient in the absolute value of the sub-filter where the largest scaled overshoot difference is calculated.

[0016] The offset may be calculated based on the weighting coefficient in the limiting process.

[0017] The method may include a step of sequentially performing a plurality of limiting steps. Each limiting step after the first limiting step may be applied to an intermediate sample, and the intermediate sample is a sample that has been processed by one or more preceding limiting steps. For each of at least one intermediate sample, each limiting step after the first limiting step may replace the related intermediate sample with a reduced sample by applying the current offset to the related intermediate sample. The reduced sample has the same sign but has an amplitude smaller than the related intermediate sample. The current offset may be calculated based on the sub-filter parameters, the current overshoot difference between the threshold value and the current predicted sample intermediate value generated by applying one of the sub-filters to a plurality of intermediate samples that have been processed by the preceding limiting steps.

[0018] The plurality of limiting steps may include a last limiting step. The method may include a step of applying at least one smoothing step, and each of the at least one smoothing steps is applied after one of the limiting steps but before the last limiting step.

[0019] The subsequent device may be a band-limiting device or an interpolation device.

[0020] The subsequent device may be an interpolation filter of a digital-to-analog converter (DAC).

[0021] The signal processing means may comprise a circuit configured to perform one or more or all of the steps of the method. The signal processing means may comprise at least one processor and at least one memory containing computer program instructions, and the at least one memory and the computer program instructions are configured to cause the device to perform one or more or all of the steps of the method using the at least one processor. The signal processing means may be a signal processor.

[0022] According to a second aspect, there is provided a method comprising receiving and clipping input samples of a signal to be processed by a subsequent device, and performing a limiting step on at least one input sample, the limiting step comprising generating an inter-sample prediction value by applying a sub-filter to a corresponding plurality of input samples including the relevant input sample, the sub-filter modelling the inter-sample behaviour of the subsequent device, generating an inter-sample prediction value by applying a sub-filter to a corresponding plurality of input samples including the relevant input sample, and replacing the relevant input sample with a reduced sample by applying an offset to the relevant input sample, the reduced sample having the same sign as the relevant input sample but a smaller amplitude than the relevant input sample, and the offset being calculated based on a parameter of the sub-filter and an overshoot difference between a threshold value and one of the inter-sample prediction values.

[0023] According to another aspect, there is provided a computer program comprising instructions which, when executed by at least one processor, cause a device to perform the method according to the second aspect. In general, the instructions may cause the device to perform one or more or all of the steps of the methods disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Exemplary embodiments will be more fully understood from the detailed description given hereinafter and the accompanying drawings, which are given by way of illustration only and thus are not limiting of the present disclosure.

[0025] In the following, a digital signal represents a discrete-time signal having a quantized amplitude suitable for digital signal processing (DSP). Clipped samples represent samples from an input signal modified by a clipping method. Reduced samples represent samples from a signal modified by the amplitude limiting method described herein. Reduced samples have the same sign (positive or negative) but have an amplitude smaller than the original input samples.

[0026]

Figure 1A

Figure 1A

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Figure 1B

Figure 1C

Figure 2

Figure 3A

Figure 3B

Figure 3C

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 5

Figure 6

Figure 7

Figure 8A

Figure 8B

Figure 8C

Mode for Carrying Out the Invention

[0027] It should be noted that these figures are intended to illustrate the general features of the methods, circuits, or structures utilized in some exemplary embodiments and to supplement the written description provided below. These drawings should not be construed as defining or limiting the range of values or characteristics encompassed by the exemplary embodiments. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features.

[0028] The features and aspects of the amplitude limiting method and the corresponding amplitude limiting device will be disclosed with reference to the accompanying drawings, taking the DAC as an example of a subsequent device. However, the same principle is applicable to other subsequent devices that can generate overshoot.

[0029] The subsequent device may be a band-limiting device and / or an interpolation device. The subsequent device may be, for example, by a band-limiting filter such as a low-pass filter or a band filter, or by executing an equivalent algorithm, or by a circuit that executes band-limiting , and may be any device that executes a frequency band-limiting function. The subsequent device may be an interpolation device that generates interpolated signal values between samples of a digital input signal. Not only band-limiting filters, but also band-limiting devices or interpolation devices may include a signal processing circuit that executes one or more further signal processing functions such as upsampling, interpolation, or DAC conversion.

[0030] Figures 1A to 1C show the linearity of a digital input signal (here, a frequency sweep sampled at 96 kHz) (

Number

[0031] In Figure 1A, the input samples and the interpolated signal values have

Number

[0032] In Figure 1B, the input samples are clipped to ±1 as indicated by the dashed arrows. Here, the limitations according to this specification do not apply. As can be seen from the figure, despite the clipping, the upsampled and interpolated digital signal may have an amplitude (absolute value amplitude) greater than 1, especially near (before / after) the clipped input samples.

[0033] In FIG. 1C, the input sample is clipped to ±1 and then limited to ±1 as indicated by the dashed and thick arrows. The dashed arrows indicate the clipped and / or reduced samples. The thick arrows indicate further reduced samples. The illustrated samples have been processed by the amplitude limiting device according to this specification. As can be seen from the figure, the upsampled and interpolated digital signal does not have an amplitude exceeding 1.

[0034] From these examples, it can be understood that even when the input sample is clipped to the maximum level, subsequent band limiting or interpolation (e.g., by the FIR filter of the DAC) may generate an amplitude overshoot, also referred to as an inter-sample peak in the art. This inter-sample amplitude overshoot may cause signal distortion (or other undesirable effects) in such a device when a downstream device (e.g., a PWM amplifier) is connected to the output of a subsequent device that performs band limiting or interpolation. When connected to the output of such a device, in such a device, it may cause signal distortion (or other undesirable effects).

[0035] A signal processing system including an amplitude limiting device will be described in detail. The amplitude limiting device is introduced in a signal processing chain including subsequent devices (e.g., a band limiting device or an interpolation device). The subsequent device may include an interpolation filter (or equivalent digital signal processing) or an analog circuit that performs band limiting. The subsequent device may further include at least one of an upsampling stage and a DAC.

[0036] The amplitude limiting device receives input samples to be processed by a subsequent device. The amplitude limiting device predicts the signal value at the output of the subsequent device (e.g., in the subsequent device, generated as the analog or digital output of that subsequent device), and is configured to implement an amplitude limiting method that replaces the input sample with a reduced sample if an overshoot is detected. The input sample is replaced with a reduced sample by applying an offset to the associated input sample. The reduced sample has the same sign but has an amplitude smaller than the associated input sample, i.e., the amplitude limiting method performs amplitude reduction. The prediction and limitation are performed by taking into account the effect on the amplitude of the output signal of a band-limiting or interpolation filter implemented by the subsequent device in order to avoid reducing the amplitude of the sample more than necessary.

[0037] The amplitude limiting method estimates the behavior of the subsequent device and uses a filter that models the behavior of the subsequent device to perform an overshoot prediction. The overshoot difference may be determined between a threshold value and a predicted output value at the output of the subsequent device, and the predicted output value is generated by applying a filter to a plurality of input samples.

[0038] In an embodiment, the filter that models the behavior of the subsequent device is implemented by a sub-filter (e.g., operating in parallel) that generates a predicted output value, also referred to as a predicted inter-sample value, which is used to detect the occurrence of an inter-sample overshoot.

[0039] The offset to be applied to the input sample may be calculated based on the parameters of the filter that models the behavior of the subsequent device and the overshoot difference. For example, the parameters may include one or more coefficients (either actual or estimated coefficients) of the interpolation filter used within the subsequent device. Alternatively, the parameters may include one or more samples from the impulse response measured at the output of the subsequent device (or derived from the step response). These parameters may be used in the analysis of the input sample to predict whether an overshoot (absolute value) exceeding a threshold can occur at the output of the subsequent device.

[0040] At least one limiting step is applied to the input sample. The overshoot detected for the predicted output signal means that a non-zero offset has been calculated. Such an offset (which may be weighted) is applied to one of the input samples contributing to the overshoot of the predicted output signal to generate a reduced sample (having the same sign but a reduced amplitude compared to the corresponding input sample). The reduced sample is supplied to the subsequent device within the signal processing chain (including the subsequent device) instead of the input sample. The subsequent device may or may not be the first subsequent device within the signal processing chain connected to the output of the amplitude limiting device.

[0041] Only one input sample may be limited among the input samples contributing to the overshoot. The input sample to be corrected may be the sample that contributes most to the overshoot.

[0042] The number of limiting steps may be two or three or more. The limiting steps may be executed sequentially one after another. At least one smoothing step to correct for unwanted "notches" The process may be applied (e.g., after one of the limiting processes but before the last limiting process) to remove these notches introduced by the preceding limiting processes. For example, the first smoothing process may be applied after the first limiting process and before the second limiting process, and the second smoothing process may be applied after the second limiting process and before the third (last) limiting process.

[0043] The amplitude limiting method requires a small amount of look-ahead. When the input samples are not known in advance, it may introduce additional latency between the input samples and the processed and / or reduced samples depending on the number of limiting processes, the application of the smoothing process, the upsampling factor, and / or the length of the applied interpolation filter. Integer upsampling factor Given an integer upsampling factor M and a symmetric interpolation FIR filter LP of length N, assuming that LP can be divided into M subfilters of odd length L = N / M, the latency for each limiting process is (L - 1) / 2 samples. As an example with M = 4, N = 36, and L = 9, each limiting process introduces a 4-sample latency between the input and output of block 600. The amplitude limiting method with 3 limiting processes (+ a smoothing process with 1-sample latency) adds a latency of 3·4 + 1 = 13 samples.

[0044] FIG. 2 shows the coefficients of an FIR filter that can be used to model the behavior of a subsequent device according to an embodiment. When the subsequent device is a DAC, the FIR filter may be the interpolation filter used within the DAC. As shown in FIG. 2, the filter coefficients of the FIR filter may be obtained from the impulse response (or derived from the step response) at the output of the filter for interpolation within the subsequent device, or by similar measurements at the digital or analog output of that device. The interpolation filter may be modeled as a low-pass FIR filter with a symmetric impulse response. In this embodiment, the symmetric 36-tap prototype of the interpolation filter is derived from the step response measured at the output of the DAC.

[0045] Figure 3A shows a block diagram 300A of a FIR filter that can be used to model the behavior of a subsequent device according to an embodiment. The subsequent device may be a device that performs upsampling and interpolation, such as a DAC. A digital input signal 301 (e.g., a digital signal sampled at 96 kHz) is received. The upsampling stage 310 is configured to upsample the digital input signal (e.g., by a factor of 4) by zero padding to generate an upsampled digital signal 302 (e.g., at 384 kHz). Following the upsampling stage 310 is a FIR filter 320 (low pass, LP) configured to filter the upsampled digital signal. By attenuating the high-frequency content introduced by zero padding, the FIR filter 320 generates an interpolated digital signal 303 (e.g., at 384 kHz). In the embodiment of Figure 3A, the FIR filter 320 has coefficients of N = 36. The digital output signal 303 is the result of the convolution between the upsampled digital signal and the coefficients of the FIR filter 320. If adjustment of the output signal level is required, this can be achieved, for example, by scaling the coefficients of the FIR filter 320.

[0046] Figure 3B shows a block diagram 300B of a FIR filter that can be used to model the behavior of a subsequent device according to an embodiment. The subsequent device may be a device that performs upsampling and interpolation, such as a DAC. In this embodiment, the FIR filter has a polyphase structure and a length of N = 36. This FIR filter may be divided into four parallel subfilters 300-1 to 300-4 of length L = 9 such that each subfilter performs the convolution by applying a 9-tap FIR filter.

[0047] Let the samples of the digital input signal supplied to sub - filters 300 - 1 to 300 - 4 be x(k). Here, k indicates the index of the samples of the digital signal. The input samples may or may not have an amplitude clipped between a positive clipping threshold and a negative clipping threshold. Sub - filter 300 - 1 has filter coefficients numbered 1, 5, 9, 13, 17, 21, 25, 29, 33. For each of the sub - filters 300 - 1 to 300 - 4, the filter coefficients are numbered in ascending steps of 4.

[0048] When n = 1...4, the sub - filters 300 - 1 to 300 - 4 are named "LP(n:4:n + 32)". The output value of the nth sub - filter is given by the following formula.

Equation

[0049] ​Let the limiting threshold related to the amplitude of the maximum output of the subsequent device be th. The limiting threshold th may be equal to the clipping threshold ct used for clipping when the input sample is a clipped sample. This limiting threshold th can be set by considering the maximum input voltage of one or more subsequent devices (such as a PWM amplifier or an analog amplifier, etc.) following the amplitude limiting device in the signal processing chain. This limiting threshold th is a linear value (i.e., not a threshold given in dB).

[0050] Figure 3C shows a block diagram of a clipper 400 (also referred to herein as the clipping device 400). The clipper is configured to implement a clipping function by setting all input samples above the positive clipping threshold 410 to the value ct, u(k)=min{x(k),ct}, and all input samples below the negative clipping threshold 420 to the value -ct, z(k)=max{u(k),-ct}. Here, x(k) is a sample of the digital input signal, u(k) is a sample of the intermediate digital signal, and z(k) is a sample of the digital output signal of the clipping device 400. Here, x(k) is a sample of the digital input signal, u(k) is a sample of the intermediate digital signal, and z(k) is a sample of the digital output signal of the clipping device 400.

[0051] Figure 4A shows a block diagram 500 of a filter that can be used to model the behavior of a subsequent device according to an embodiment. In this embodiment, the filter includes two parallel FIR filters, namely, a 5-tap FIR filter having the digital input signal x(k) and a 4-tap FIR filter having a second digital input signal z(k) and an initial delay of one sample. The outputs of both FIR filters are summed to obtain the digital output signal yn(k). This is an alternative to the sub-filters 300-1 to 300-4 shown in Figure 3B.

[0052] When samples of the second digital input signal z(k) depend on the first digital input signal x(k) where z(k) = x(k - 4), then, according to Equation 1, block 500 operates as a 9 - tap sub - filter LP(n:4:32 + n) for n = 1...4. When samples of the second digital input signal z(k) have arbitrary values, the following equation holds. [Number] In a software implementation of this method, the processor has read and write access to the delayed input samples x(k - i) and can replace Equation 2 with Equation 1, which is the case when the value of the sample x(k - 4) is corrected "in place" at each index k by setting x(k - 4)=z(k) before advancing the index k + 1.

[0053] Instead of using a single linear - phase FIR low - pass filter split into M sub - filters, it is possible to use M independent IIR filters (Infinite Impulse Response filters) operating in parallel. Each IIR filter approximates a different "group delay" for the input data.

[0054] Figure 4B shows a block diagram of a single - step limiting device 600 configured to perform only one limiting step of the disclosed amplitude - limiting method. This figure illustrates how the parallel - phase filters, each following the block diagram 500 of Figure 4A for n = 1...4, can be used to model the behavior of a subsequent device, estimate, and correct overshoot. Here, x(k) is a sample of the digital input signal, vn(k) and vn(k) and d(k) are samples of different intermediate digital signals for n = 1...4, and z(k) is a sample of the digital output signal of the single - step limiting device 600.

[0055] As shown in Equation 2, the individual sub-filter output values yn(k) of the four FIR sub-filters 500-1 to 500-4 (n = 1...4) are calculated from the input sample x(k) and the feedback sample z(k) corresponding to the output samples generated by the amplitude single-step limiting device 600. Each sub-filter output yn(k) is used to determine the overshoot difference between the threshold th and the predicted output value: |yn(k)| - th. Here, the absolute values 610-1 to 610-4 of the sub-filter output yn(k) are taken and the limiting threshold th is subtracted.

[0056] In this embodiment, it is assumed that for each sub-filter, the central coefficient LP(16 + n) where i = 4 and n = 1...4 has the maximum amplitude. Therefore, the corresponding input sample x(k - 4) to which this central coefficient is applied is the input sample that most contributes to the overshoot difference for each sub-filter. Regarding convolution, reducing the amplitude of the corresponding input sample x(k - 4) has the greatest effect on the sub-filter output yn(k) for overshoot reduction. However, the adjacent sub-filter coefficients LP(12 + n) where i = 3 and n = 1...4, and LP(20 + n) where i = 5 and n = 1...4 may be negative. Therefore, keeping the amplitude of yn(k) below the threshold by reducing the amplitude of x(k - 4) may increase the amplitude of the previous sub-filter output yn(k - 1) and / or the next sub-filter output yn(k + 1). This potential problem is addressed by cascading two or more single-step limiting devices 600 each performing a single limiting step.

[0057] In this embodiment, it is assumed that the central coefficient within each sub-filter has the maximum amplitude. If the maximum amplitude is located at another position but is in the same position for most sub-filters or all sub-filters the selection index LP(16 + n) where i = 4 and n = 1...4 may be adjusted accordingly, similar to the latency of the delay block 630.

[0058] To scale each overshoot difference, the overshoot difference is multiplied by the inverse center coefficients of the applied subfilters n = 1...4, here by LP(16 + n).

Number

[0059] The subfilters model the behavior between samples of subsequent devices. Embodiments disclosed herein use at least two subfilters.

[0060] In some embodiments, a weighting coefficient w is applied to the offset in each limiting step to control the amount of limitation applied. The weighting coefficient w is in the range of 0 to 1, for example w = 0.5, 0.6, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1. The weighting coefficient may be the same for all samples processed during the limiting step, but may vary from one limiting step to the next. For example, for the first limiting step, the first weighting coefficient w1 may be set to 0.5 to 0.75, while the coefficients w2, w3, etc. are set to values increasing up to 1 for subsequent limiting steps. In combination with the smoothing step, these weighting coefficients make it possible to avoid reducing the amplitude of the reduced samples more than necessary.

[0061] In the embodiment of FIG. 4B, the offset d(k) is multiplied by the weighting factor w. Next, this weighted offset is multiplied by the sign 640 of the time-aligned input sample x(k−4). When calculating the sub-filter output yn(k), a four-sample latency is introduced into each block 500-1 to 500-4, so the time alignment is realized by the four-sample delay block 630. Finally, the sign-corrected and weighted offset is subtracted from the time-aligned input sample x(k−4): z(k)=x(k−4)−sign{x(k−4)}·w·d(k) (Equation 5) The sign function can be defined as follows:

Number

[0062] FIG. 4C shows a block diagram of a smoothing device 700 configured to perform an optional smoothing step as part of the disclosed amplitude limiting method. Here, x(k) is a sample of the digital input force signal, u(k) and m(k) are samples of the intermediate digital signal, b(k) is a sample of the digital bypass signal, and z(k) is a sample of the digital output signal of the smoothing device 700.

[0063] The reduced samples (i.e., the samples modified by one or more limiting steps 600) may have an amplitude smaller than the previous and next samples, thus generating an unwanted "notch" in the amplitude-limited digital signal, i.e., adding a high-frequency oscillation that does not exist in the digital input signal. The filter generation m(k) may be implemented in several ways.

[0064] According to some embodiments, a comparison between the input sample and the reduced sample may be performed to determine whether the smoothing process must be applied. This means that, depending on a second digital signal or digital bypass signal, named BYPASS, corresponding to the delayed sample b(k) to which the limiting process is not applied, some of the input samples are replaced by the average of their previous and next samples (i.e., the arithmetic mean or another filter): m(k)=(x(k)+x(k - 2)) / 2 (Equation 6) The sign function enables the combined calculation to process positive and negative input samples and / or bypass samples, and both the time - aligned input sample x(k - 1) and the averaged sample m(k) are multiplied by the sign 730 of the bypass sample b(k). From these two, the larger value is taken by the maximum function 740: u(k)=max{x(k - 1)·sign{b(k)},m(k)·sign{b(k)}} (Equation 7) The amplitude 745 of the sample u(k) is compared with the amplitude 735 of the bypass sample b(k), and a smaller value is taken by the minimum function 750 to ensure that the corrected output sample z(k) cannot have an amplitude larger than the corresponding bypass sample b(k). Finally, the result of the minimum function 750 is multiplied by the sign of the bypass sample b(k): z(k)=min{|u(k)|,|b(k)|}·sign{b(k)} (Equation 8)

[0065] Figure 4D shows a block diagram of an amplitude limiting device 800 implementing the disclosed amplitude limiting method with several limiting steps. Here, the device 800 includes a clipping device 400, three single-step limiting devices 600-1 to 600-3 for implementing three limiting steps, and a smoothing device 700. The clipping device may correspond to the clipping device 400 described with reference to FIG. 3C. Each of the single-step limiting devices 600-1 to 600-3 may correspond to the limiting device 600 described with reference to FIG. 4B. The smoothing device may correspond to the smoothing device 700 described with reference to FIG. 4C.

[0066] After applying a clipping threshold ct to the input sample x(k) (by the clipping device 400), two limiting steps are sequentially applied. The two single-step limiting devices 600-1 and 600-2 use a limiting threshold th that may be equal to the clipping threshold ct, as well as a first weighting coefficient w2 and a second weighting coefficient w1. A smoothing step applied by the smoothing device 700 follows, and the time-aligned digital signal (using the delay block 810) bypasses the two single-step limiting devices 600-1 and 600-2 and serves as a digital bypass signal to the smoothing device 700. The time alignment takes into account that each limiting step causes a four-sample latency and the smoothing step causes a one-sample latency. After the smoothing device 700, the third single- step limiting device 600-3 applies an additional limiting step using a third weighting coefficient w3. As an example, the first weighting coefficient w1 may be set in the range from 1 / 2 to 3 / 4, and the second weighting coefficient w2 and the third weighting coefficient w3 are set to 1. Assuming that the clipping device 400 has no latency, the complete amplitude limiting device 800 causes a 13-sample latency.

[0067] The limiting step 650 is illustrated by the flowchart of FIG. 5. The limiting step corresponds to the process executed by the single-step limiting device disclosed with reference to FIG. 4B.

[0068] In sub-step 650-1, the overshoot difference |yn(k)|-th is calculated from the input sample x(k). When a parallel filter is used as disclosed with reference to FIGS. 4A and 4B, some output samples z(k) at the output of the single-step limiting device 600 are used as feedback samples and supplied to the parallel filters 500-1 to 500-4. When a polyphase implementation is used, some overshoot differences are calculated for a given time-aligned input sample (k-4), and one overshoot difference is calculated for each sub-filter.

[0069] In sub-step 650-2, each overshoot difference is scaled based on the maximum filter coefficient of the relevant filter (or each sub-filter) to calculate the scaled overshoot difference vn(k). Equation 3 above may be used for the calculation of the scaled overshoot difference.

[0070] In sub-step 650-3, an offset d(k) is selected as the maximum scaled overshoot difference for the polyphase implementation of the filter that models the behavior of the subsequent device.

[0071] In sub-step 650-4, the selected offset d(k) may be weighted based on the weighting factor w, as described with reference to FIG. 4B or FIG. 4D for example. This step may be omitted if the weighting factor w is equal to 1.

[0072] In sub-step 650-5, a reduced input sample z(k) is generated by subtracting the sign-corrected weighted offset from the time-aligned input sample x(k-4). Equation 5 above may be used for the calculation of z(k).

[0073] The amplitude limiting method is illustrated in the flow chart of FIG. 6. The amplitude limiting method corresponds to the processing performed by the device 800 disclosed with reference to FIG. 4D. This amplitude limiting method is performed for each input sample. The amplitude limiting method includes at least one limiting step, and may include, for example, two or three limiting steps. It may include one or more smoothing steps, for example a smoothing step after at least one of the first limiting step and / or the second limiting step, but before the last limiting step. It may include a clipping step before the first limiting step. Exemplary embodiments are disclosed below.

[0074] In step 850-1 (clipping step), input samples of a signal to be processed by a subsequent device are received. The subsequent device may be a band-limiting device or an interpolation device. Each input sample x(k) may be clipped to a clipping threshold ct to generate a clipped sample u1(k).

[0075] In step 850-2 (first limiting step), a limiting step is performed during which at least one input sample (the clipped sample u1(k) or the input sample x(k) in the case where no clipping step is performed) is limited by applying an offset to the associated input sample. The offset may be a weighted offset, weighted by a weighting factor w1 to generate the reduced sample u2(k). If no overshoot is detected (overshoot difference is zero), the input sample is not modified, or at the same time, an offset equal to zero is applied during the limiting step, in which case the reduced sample u2(k) is equal to the time-aligned input sample x(k-4) or, if step 850-1 is performed, equal to the clipped sample u1(k-4). Step 850-2 may be performed as disclosed by reference to FIG. 5 and / or FIG. 4B.

[0076] In operation 850-3 (the second limiting operation), the limiting operation is performed, during which at least one input sample u2(k) is replaced with a reduced sample u3(k) by applying an offset to the associated input sample. The offset may be a weighted offset that is weighted by a weighting factor w2 to produce the reduced sample u3(k). If no overshoot is detected (the overshoot difference is zero), the reduced sample u3(k) is equal to the time-aligned input sample u2(k-4). Operation 850-3 may be performed as disclosed by referring to FIGS. 5 and / or 4B.

[0077] In operation 850-4, it is determined whether the low latency form of the method or the non-omitted form (with a smoothing operation) is applied. If the low latency form is applied, the method ends at operation 850-5. If the non-omitted form is applied, operation 850-6 is performed after operation 850-4.

[0078] For example, for the filter coefficients of FIG. 2, it has been found by simulation that a three-stage limit sufficiently reduces overshoot. If the low latency form is applied, the method may have a sample latency of 8, and otherwise the method may have a sample latency of 13. The total number of limiting operations may be adapted to the length of the interpolation filter and / or the transfer function.

[0079] In operation 850-6, a smoothing operation is applied to the sample u3(k) obtained after the second limiting operation 850-3 to produce a sample u4(k). The smoothing operation may use the time-aligned sample u1(k-9) for internal calculations. The smoothing operation makes it possible to remove the notch introduced by either the first limiting operation 850-2 or the second limiting operation 850-3. This smoothing operation may be performed as disclosed by referring to FIG. 4C. If the sample is not modified during the smoothing operation, the sample u4(k) is equal to the time-aligned sample u3(k-1) obtained after the second limiting operation 850-3.

[0080] In Engineering 850-7 (the third limiting process), the limiting process is executed, during which at least one input sample u4(k) is replaced by a reduced sample z(k) by applying an offset to the relevant input sample. The offset may be a weighted offset that is weighted by a weighting factor w3 to generate the reduced sample z(k). If no overshoot is detected (the overshoot difference is zero), the reduced sample z(k) is equal to the time-aligned input sample u4(k-4). Engineering 850-7 may be executed as disclosed by referring to FIG. 5 and / or FIG. 4B.

[0081] The method ends in Engineering 850-8 after Engineering 850-7.

[0082] For each of the limiting processes 850-2, 850-3, or 850-7, the reduced sample has the same sign but has an amplitude smaller than the relevant input sample.

[0083] For each of the limiting processes 850-2, 850-3, or 850-7, a filter that models the behavior of the subsequent device is used to determine the offset to be applied. The predicted output value at the output of the subsequent device is generated by applying the filter to a plurality of corresponding (i.e., time-aligned) input samples. The overshoot difference between the threshold th and the predicted output value is calculated. The offset is calculated based on the overshoot difference.

[0084] For each of the limiting processes 850-2, 850-3, or 850-7, the plurality of input samples for which the predicted output value is generated includes the input sample to which the offset is applied, such that reducing this input sample also reduces the overshoot difference calculated for the relevant predicted output value.

[0085] For example, when a filter that models the behavior of a subsequent device is modeled by a finite impulse response filter (FIR filter), the parameters of the filter include the coefficients of the FIR filter. The offset may be calculated based on the maximum coefficient in the absolute value of the FIR filter. The offset may be applied to the input sample to which the maximum coefficient is applied in the FIR filter to generate a predicted output value.

[0086] For example, when a filter that models the behavior of a subsequent device has a polyphase structure including parallel subfilters, the overshoot difference is calculated for each of the subfilters, and each overshoot difference is calculated between a threshold value and each output value generated by the associated subfilter. The maximum coefficient of each subfilter is used to derive a scaled overshoot difference for each subfilter. The offset may be calculated based on the maximum scaled overshoot difference. The offset may be applied to the input sample to which the maximum coefficient is applied in the subfilter for which the maximum scaled overshoot difference is calculated. The offset may be a weighted offset weighted using the weighting coefficients disclosed herein.

[0087] FIG. 7 shows sections of the digital signal after clipping and limiting by the disclosed amplitude limiting method according to the flowchart of FIG. 6. Here, a low-latency form of a method having only two limiting steps and no smoothing step is compared with a non-omitted form of a method having three limiting steps and a smoothing step. Using the notation of FIG. 4D, the sample u3(k) from the output of the low-latency form (clipped and limited in two steps) is indicated by a gray asterisk (*). The sample z(k) from the output of the non-omitted form (clipped, limited in three steps, and having a smoothing step) is indicated by a black circle. In this embodiment, the first weighting factor w1 is set to 3 / 4, and the second weighting factor w2 and the third weighting factor w3 are set to 1. As can be seen, the notch from the two-step limit (low-latency form, see asterisk) can be adequately corrected by adding a smoothing step and a third limiting step.

[0088] FIG. 8A shows a block diagram of an audible system 900A as a possible application of the disclosed amplitude limiting method. The audible system includes - an audible device 910 configured to generate input samples, - a digital signal processor (DSP) 920 configured (e.g., using DSP code) to implement a clipping function (as disclosed with reference to FIG. 3C) and the amplitude limiting method as disclosed herein and generate reduced samples that replace input samples in the event of overshoot prediction, - a digital-to-analog converter (DAC) 950 for converting input samples or reduced samples to an analog voltage for a subsequent audible amplifier 960, - an audible amplifier (e.g., a PWM amplifier) 960 configured to amplify the analog voltage generated by the DAC.

[0089] The amplitude limiting method implemented by the DSP920 ensures that the analog output signal of the DAC950 does not exceed the analog threshold that can be the digital threshold th shown in FIG. 4D for the amplitude limiting device 800. In this way, the amplifier 960 is protected from generating an output voltage amplitude that is too high.

[0090] FIG. 8B shows an alternative block diagram of an audible system 900B as a possible application of the disclosed amplitude limiting method. The audible system includes - an audible device 910 configured to generate input samples, and - a digital signal processor (DSP) 920 configured (e.g., using DSP code) to implement a clipping function (such as disclosed with reference to FIG. 3C) and the amplitude limiting method as disclosed herein to generate reduced samples that replace input samples when overshoot is predicted, and - a digital data storage device 930 or a digital data transmission device 930, and - a playback device 940 that retrieves digital data from the storage device, or a receiving device that receives digital data from the transmission device, and - a digital-to-analog converter (DAC) 950 for converting the playback samples or received samples into an analog voltage for a subsequent audible amplifier 960, and - an audible amplifier (e.g., a PWM amplifier) 960 configured to amplify the analog voltage generated by the DAC.

[0091] It can be seen that blocks 940, 950, and 960 do not have to be in the same position and / or time as the DSP 920 during the execution of the disclosed amplitude limiting method. Thus, the amplitude limiting method executed by the DSP920 may be implemented, for example, in a circuit physically separate from the circuit including blocks 940, 950, and 960.

[0092] FIG. 8C shows an alternative block diagram of an audible system 900C as a possible application of the disclosed amplitude limiting method. Compared to FIG. 8B, the insertion of block 930 in combination with block 940 can be implemented at different positions in the signal processing chain. In this embodiment, it can be seen that blocks 910 and 930 are not required at the position of DSP 920 or at runtime of amplitude limiting method 920 to perform the disclosed amplitude limiting method.

[0093] Embodiments of the method disclosed herein include receiving input samples of a signal to be processed by a subsequent device and, for at least one sample, performing a first limiting step that includes replacing a related input sample with a reduced sample by applying an offset to the related input sample, the reduced sample having the same sign as the related input sample but a smaller amplitude than the related input sample, the offset being calculated based on parameters of a filter that models the behavior of the subsequent device and an overshoot difference between a threshold and a predicted output value generated by this filter, performing a first limiting step that includes replacing a related input sample with a reduced sample. The predicted output value may be generated by applying a filter to a plurality of input samples. The plurality of input samples may include the related input sample.

[0094] Any functions, engines, block diagrams, flowcharts, state transition diagrams, flowcharts, and / or data structures described herein represent an exemplary circuit concept embodying the principles of the present invention It should be understood by those skilled in the art that the figures are represented. Similarly, any flowchart, flow diagram, state transition diagram, pseudocode, etc. are substantially represented in a computer-readable medium and, thus, represent various processes that can be executed by such a computer or processing device, whether or not a computer or processing device is explicitly shown.

[0095] A flowchart may describe operations as sequential processes, but many of the operations may be performed in parallel, concurrently, or simultaneously. Also, some operations may be omitted, combined, or performed in a different order. The process may end when its operations are completed, but may have additional steps not disclosed in the figures or description. The process may correspond to a method, function, procedure, subroutine, subprogram, etc. When the process corresponds to a function, its end may correspond to the return of the function to the calling function or main function.

[0096] Each of the described functions, engines, blocks, and processes described herein may be implemented in hardware, software, firmware, middleware, microcode, or any suitable combination thereof.

[0097] In this description, the expression "means for performing a function" or "means configured to perform a function" may correspond to one or more functional blocks comprising a circuit adapted or configured to perform this function. The block may perform this function itself, or may cooperate and / or communicate with one or more other blocks to perform this function. "Means" may correspond to or be implemented as "one or more modules", "one or more devices", "one or more units", etc., and may include at least one processor and at least one memory storing instructions configured to cause the target device / target system to perform functions related thereto.

[0098] The amplitude limiting device may be implemented by software and / or hardware.

[0099] When implemented in software, the amplitude limiting device may be implemented by a circuit (e.g., one or more circuits). The following types of circuits may be used: digital signal processing (DSP) hardware, a processor or microprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc. The circuit may be, for example, a programmable processor that executes hardware, programmable logic, software or firmware, and / or any combination of these (e.g., a processor, a control unit / entity, a controller) for transmitting and receiving signals, and a memory for storing data and / or instructions, or may include these. When implemented in software, firmware, middleware, or microcode, the instructions for performing the necessary tasks may be stored on a computer-readable medium that may or may not be included in the target device or system. The instructions may be transmitted via the computer-readable medium and loaded into the target device or system. The instructions are configured to cause the target device / target system to perform one or more functions disclosed herein. For example, as described above, according to one or more embodiments, at least one memory may contain or store instructions, and at least one memory and instructions may be

[0100] configured to cause one or more functions to be performed by the target device / target system using at least one processor. Note that the processor, memory, and instructions act as means for providing or causing the execution of one or more functions by the target device / target system disclosed herein.

[0101] ​The instructions may correspond to computer program instructions, computer program code, and may include one or more code segments. A code segment may represent a processing procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program states.

[0102] When provided by a processor, the functionality may be provided by a single dedicated processor, by a single shared processor, or by multiple individual processors, some of which may be shared. The term "processor" should not be construed as exclusively referring to hardware capable of executing software, and may implicitly include one or more processing circuits, whether programmable or not. Processing circuits include digital signal processors (DSPs), network processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), system-on-chips (SoCs), central processing units (CPUs ) processing units (PUs), arithmetic logic units (ALUs), programmable logic units (PLUs), processing cores, programmable logic, microprocessors, controllers, microcontrollers, microcomputers, and any device capable of responding to and / or executing instructions in accordance with defined methods and / or defined logic. Other conventional or custom hardware may also be included. The processor may be configured to execute instructions adapted to cause execution by one or more of the target devices or systems of the functionality disclosed herein for the associated device or system.

[0103] A computer-readable medium or computer-readable storage medium may be any storage medium suitable for storing instructions readable by a computer or processor. More generally, a computer-readable medium may be any storage medium capable of storing and / or containing and / or carrying instructions and / or data. A computer-readable medium may be a portable storage medium or a fixed storage medium. A computer-readable medium may include one or more storage devices such as a permanent mass storage device, a magnetic storage medium, an optical storage medium, a digital storage disk (CD-ROM, DVD, Blue Ray, etc.), a USB key or dongle or peripheral device, a memory card, a random access memory (RAM), a read only memory (ROM), a core memory, a flash memory, or any other non-volatile storage device.

[0104] A memory suitable for storing instructions may be a random access memory (RAM), a read only memory (ROM), and / or a permanent mass storage device such as a disk drive, a memory card, a random access memory (RAM), a read only memory (ROM), a core memory, a flash memory, or any other non-volatile storage device.

[0105] The terms first, second, etc. may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0106] When an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", etc.). )", "adjacent" versus "directly adjacent", etc.).

[0107] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to be limiting. As used in this specification, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", and / or "including", as used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It will be further understood that

[0108] To provide a thorough understanding of some embodiments, specific details are provided in the following description. However, it will be understood by those skilled in the art that the exemplary embodiments may be practiced without these specific details. For example, the system may be shown in block diagrams so as not to obscure the embodiments with unnecessary detail. In other instances, well-known processes, structures, and techniques may be shown without unnecessary detail to avoid obscuring the embodiments.

[0109] Advantages, other benefits, and solutions to problems have been described above with respect to specific embodiments of the invention. However, an advantage, a benefit, a solution to a problem, and any element that may cause or result in such an advantage, benefit, or solution, or that may make such an advantage, benefit, or solution more pronounced, should not be construed as an important, necessary, or essential feature or element of the invention.

Claims

1. A device (600, 800, 920) comprising signal processing means for performing a method, wherein the method is - Receiving and clipping input samples of the signal to be processed by a subsequent device (850-1), - Including performing a limiting step for at least one input sample (850-2), The aforementioned limiting step is - A step of generating predicted inter-sample values ​​by applying a subfilter to a plurality of corresponding input samples, including the aforementioned related input samples, wherein the subfilter generates predicted inter-sample values ​​that model the inter-sample behavior of the subsequent device. - A step of replacing the relevant input samples with reduced samples by applying an offset to the relevant input samples, The reduced sample has the same sign as the relevant input sample, but has a smaller amplitude than the relevant input sample. A device (600, 800, 920) comprising signal processing means for performing a method in which the offset is calculated based on the parameters of the subfilter and the overshoot difference between a threshold and one of the predicted inter-sample values.

2. The device (600, 800, 920) according to claim 1, wherein the parameters include actual or estimated coefficients of the interpolation filter in the subsequent device.

3. The device (600, 800, 920) according to claim 1, wherein the parameters include parameters for the actual or estimated impulse response of the subsequent device.

4. The device according to any one of claims 1 to 3 (600, 800, 920), wherein the subfilter that models the behavior of the subsequent device is a subfilter of a finite impulse response filter (FIR filter), and the parameters include the coefficients of the FIR filter.

5. The method described above is This includes calculating a scaled overshoot difference for each of the subfilters, where each scaled overshoot difference is calculated based on the overshoot difference between the threshold and the respective predicted inter-sample values ​​generated by the relevant subfilters. The device (600, 800, 920) according to any one of claims 1 to 3, wherein the offset is calculated based on the maximum scaled overshoot difference.

6. The aforementioned offset is, The offset is calculated based on the largest coefficient in the absolute value of the subfilter to which the maximum scaled overshoot difference is calculated, and the offset is applied to the input sample to which the largest coefficient is applied in the subfilter to which the maximum scaled overshoot difference is calculated. The device (600, 800, 920) according to claim 5, wherein the scaled overshoot difference is scaled based on the largest coefficient in the absolute value of the subfilter from which the largest scaled overshoot difference is calculated.

7. The device (600, 800, 920) according to any one of claims 1 to 3, wherein the offset is calculated based on a weighting coefficient in the limiting step.

8. The method includes sequentially performing a plurality of limiting steps (850-2, 850-3, 850-7), wherein the plurality of limiting steps include the limiting step (850-2) and at least one further limiting step (850-3, 850-7), Each of the further limiting steps (850-3, 850-7) is applied to the intermediate sample, which is the sample that has been processed by the preceding limiting steps. Each of the further limiting steps (850-3, 850-7) includes replacing each of at least one intermediate sample with the relevant intermediate sample by applying the current offset to the relevant intermediate sample, The reduced sample has the same sign as the relevant intermediate sample, but has a smaller amplitude than the relevant intermediate sample. The device (800, 920) according to any one of claims 1 to 3, wherein the current offset is calculated based on the parameters of the subfilter and the current overshoot difference between the threshold and the current predicted intersample value generated by applying one of the subfilters to a plurality of intermediate samples processed by the preceding limiting step.

9. The device (800, 920) according to claim 8, wherein the plurality of limiting steps include a final limiting step (850-7), and the method includes applying at least one smoothing step, each of the at least one smoothing step (850-6) is applied after one of the limiting steps but before the final limiting step (850-7).

10. The device according to any one of claims 1 to 3 (800, 920), wherein the subsequent device is a bandwidth limiting device or an interpolation device.

11. The aforementioned subsequent device is a Digital to Analog Converter (DA The device (800, 920) according to any one of claims 1 to 3, which is an interpolation filter of C).

12. The device (800, 920) according to any one of claims 1 to 3, wherein the signal processing means comprises a circuit configured to perform at least one step of the method.

13. The device according to any one of claims 1 to 3 (800, 920), wherein the signal processing means comprises at least one processor and at least one memory containing computer program instructions, and the at least one memory and the computer program instructions are configured to cause the device to perform at least one step of the method using the at least one processor.

14. It is a method, - Receiving and clipping input samples of the signal to be processed by a subsequent device (850-1), - Including performing a limiting step for at least one input sample (850-2), The aforementioned limiting step is - A step of generating predicted inter-sample values ​​by applying a subfilter to a plurality of corresponding input samples, including the aforementioned related input samples, wherein the subfilter generates predicted inter-sample values ​​that model the inter-sample behavior of the subsequent device. - A step of replacing the relevant input samples with reduced samples by applying an offset to the relevant input samples, The reduced sample has the same sign as the relevant input sample, but has a smaller amplitude than the relevant input sample. A method in which the offset is calculated based on the parameters of the subfilter and the overshoot difference between a threshold and one of the predicted inter-sample values.

15. A computer program that, when executed by at least one processor, includes instructions that cause a device to perform the method described in claim 14.

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