Domain Clock and Power Activation Control Circuit and Related Method for Reducing Voltage Droop
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- MICROSOFT TECHNOLOGY LICENSING LLC
- Filing Date
- 2023-05-18
- Publication Date
- 2026-06-16
Smart Images
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Abstract
Description
Technical Field
[0001] The technology of the present disclosure generally relates to the management of power in integrated circuits (ICs), and more particularly to reducing voltage droop during activation of logic circuits in clock domains of ICs.
Background Art
[0002] Integrated circuits (ICs) include digital and analog circuits that provide functional capabilities to a wide variety of electronic devices. Digital circuits include logic circuits that are synchronized by clock signals distributed through a clock tree. Logic circuits synchronized by one clock signal are included in the same domain. An IC may have multiple domains, each domain being controlled by its own clock and able to communicate with each other when the clocks are synchronized. Logic circuits receive power and continue to consume power even when not in use as long as their clock signals remain active. When the functions performed by the logic circuits within a domain are not in use, one or more domains may be shut off to maintain the power of the IC. One or more domains of the IC may be shut off by deactivating the clock signal for those domains. This can be accomplished by activating a clock gate signal to gate control (e.g., block) the root clock signal supplied to the domain clock tree for distribution to the entire domain. When the functions of the logic circuits in the clock domain are needed again, the clock signal for the domain can be activated by deactivating the clock gate signal. When all the logic circuits in the clock domain begin to be clocked again, a voltage droop occurs on the power rail of the power distribution network of the IC due to a sudden surge in power consumption of the domain. The voltage droop may slow down the performance of the logic circuits and may even cause logic errors.
Summary of the Invention
[0003] Exemplary aspects disclosed herein include a domain clock and a power control circuit for reducing voltage droop. Related methods for reducing voltage droop are also disclosed. Digital circuits within an integrated circuit can be divided into different domains having their own clock signals. When not in use, the domains can be deactivated to minimize power consumption by deactivating the domain clock signals. An exemplary domain control circuit includes a sequencing circuit for controlling a clock gate signal that gates the domain clock signal of a first domain and controls a power regulator that supplies power on a power rail to the first domain. The sequencing circuit receives a domain control signal to control activation and deactivation of the domain. The domain control circuit deactivates the clock gate signal for the domain after controlling the power regulator to supply power on the power rail to the domain. In this way, the voltage droop of the supply voltage on the power rail is significantly reduced or avoided. In some examples, the clock gate signal for the domain is deactivated after the voltage increases on the power rail. In some examples, the power regulator includes a plurality of parallel regulator circuits and a regulator control circuit for determining the number of parallel regulator circuits to be activated to supply power to the domain. In some examples, the domain control signal is supplied to the domain control circuit from an always-on domain that remains active during a low power mode.
[0004] In an exemplary aspect disclosed herein, a domain control circuit is included that comprises a power regulator including at least one regulator circuit configured to supply power on a power rail to a first domain of an integrated circuit (IC). The domain control circuit also includes an ordering circuit configured to receive a domain control signal indicative of one of activation and deactivation of the first domain. The ordering circuit is configured to generate a power control signal to control at least one regulator circuit to supply the power on the power rail to the first domain in response to the domain control signal indicating activation of the first domain, and further configured to generate a clock gate signal in a first state to activate a clock signal of the first domain after generating the power control signal to control at least one regulator circuit to supply the power on the power rail to the first domain.
[0005] In another exemplary aspect, a system is provided that includes an IC having a first domain that includes a chip-to-chip interface circuit and a domain control circuit. The domain control circuit includes a power regulator having at least one regulator circuit configured to supply power on a power rail to the first domain of the IC. The domain control circuit includes an ordering circuit configured to receive a domain control signal indicative of one of activation and deactivation of the first domain. The ordering circuit is configured to generate a power control signal to control at least one regulator circuit to supply the power on the power rail to the first domain in response to the domain control signal indicating activation of the first domain, and further configured to generate a clock gate signal in a first state to activate a clock signal of the first domain after generating the power control signal to control at least one regulator circuit to supply the power on the power rail to the first domain. The system further includes a clock distribution circuit configured to receive the clock gate signal, receive a system clock signal, and distribute a chip clock signal to the first domain based on the clock gate signal.
[0006] In another exemplary aspect, a method for controlling a first domain of an IC is disclosed. The method includes supplying power on a power rail to the first domain of the IC by a power regulator including at least one regulator circuit, and receiving, in an ordering circuit, a domain control signal indicating one of activation and deactivation of the first domain. The method also includes generating a power control signal to control at least one regulator circuit to supply the power on the power rail to the first domain in response to the domain control signal indicating activation of the first domain, and generating a clock gate signal in a first state to activate a clock signal of the first domain after generating the power control signal to control at least one regulator circuit to supply the power on the power rail to the first domain.
[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate some aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
Brief Description of the Drawings
[0008]
Figure 1
Figure 2
Figure 3
Figure 4
DETAILED DESCRIPTION OF THE INVENTION
[0009] With reference to the drawings, some exemplary aspects of the present disclosure are described. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects.
[0010] The exemplary aspects disclosed herein include a domain clock and a power control circuit for reducing voltage droop. Related methods for reducing voltage droop are also disclosed. Digital circuits within an integrated circuit can be divided into different domains having their own clock signals. When not in use, the domains can be deactivated to minimize power consumption by deactivating the domain clock signal. An exemplary domain control circuit includes a sequencing circuit for controlling a clock gate signal that gates the domain clock signal of a first domain and controls a power regulator that supplies power on a power rail to the first domain. The sequencing circuit receives a domain control signal to control the activation and deactivation of the domain. The domain control circuit controls the power regulator to supply power on the power rail to the domain and then deactivates the clock gate signal for the domain. In this way, the voltage droop of the supply voltage on the power rail is significantly reduced or avoided. In some examples, the clock gate signal for the domain is deactivated after the voltage increases on the power rail. In some examples, the power regulator includes a plurality of parallel regulator circuits and a regulator control circuit for determining the number of parallel regulator circuits to be activated to supply power to the domain. In some examples, the domain control signal is supplied to the domain control circuit from an always-on domain that remains active during the low-power mode.
[0011] Before describing the details of the exemplary domain control circuit 200 in FIG. 2, a system 100 in which the exemplary domain control circuit 200 can be utilized is illustrated in FIG. 1. System 100 includes a first IC 102A and a second IC 102B that communicate with each other. In the example of FIG. 1, the first IC 102A and the second IC 102B are each coupled to an interposer 104 that forms a medium for the movement of signals between the first IC 102A and the second IC 102B. The first IC 102A includes a plurality of domains 106(1) - 106(4) of digital circuits and an exemplary domain control circuit 108. The domain control circuit 108 receives a domain control signal DM-CTL-A, which can be a multi-bit signal, received at input 110. The domain control signal DM-CTL-A indicates whether each of the domains 106(1) - 106(4) is activated or deactivated. In response to the indication of the domain control signal DM-CTL-A, the domain control circuit 108 supplies appropriate power on the power rail 112 to each of the activated domains 106(1) - 106(4) and, as appropriate, activates or deactivates the respective clock gate signals CKGT1(1) - CKGT1(4).
[0012] Although only domains 106(1) and 106(2) are shown, each of domains 106(1) to 106(4) can include a clock distribution tree CLKTREE. The clock distribution tree CLKTREE of domain 106(1) is described as an example. The clock distribution tree CLKTREE of domain 106(1) receives a system clock signal SYSCLK and a clock gate signal CKGT1(1). When active (e.g., in an ON state indicated by a first voltage level), the clock gate signal CKGT1(1) gates or blocks the distribution of the system clock SYSCLK to interrupt the activity of digital circuits within domain 106(1). In contrast, in response to the clock gate signal CKGT1(1) being deactivated (e.g., in an OFF state indicated by a second voltage level), the clock distribution tree CLKTREE distributes a domain clock CLK-D1(1) to each of a plurality of digital circuits 114(1) to 114(4) within domain 106(1). Domain 106(2) receives a clock gate signal CKGT1(2) and also receives the system clock SYSCLK, although not shown. The clock distribution tree CLKTREE within domain 106(2) distributes a domain clock CLK-D1(2) to an interface circuit 116A when the clock gate signal CKGT1(2) is deactivated. Domains 106(3) and 106(4) that include the clock distribution tree CLKTREE receive the clock gate signals CKGT1(1) and CKGT1(2), respectively, as well as the system clock SYSCLK (not shown).
[0013] IC102B includes domain 118(1) to 118(5) and a domain control circuit 120. Domain 118(1) includes digital circuits 124(1) to 124(3). The domain control circuit 120 may correspond to the domain control circuit 108 in IC102A and may be programmed or modified according to IC102B. Each of domains 118(1) to 118(5) is coupled to a power rail 122 driven by the domain control circuit 120. Domains 118(1) to 118(5) receive clock gate signals CKGT2(1) to CKGT2(5) from the domain control circuit 120 to control the distribution of the system clock SYSCLK. The domain control circuit 120 receives an indication in the domain control signal DM-CTL-B as to whether each of domains 118(1) to 118(5) is activated or deactivated, and determines the states of the clock gate signals CKGT2(1) to CKGT2(5).
[0014] When activated, domain 118(2) of IC102B includes an interface circuit 116B that communicates with the interface circuit 116A of IC102A. When there is no communication between the interface circuit 116A and the interface circuit 116B, the domain control circuit 108 can activate the clock gate signal CLKGT1(2) to stop the distribution of the system clock SYSCLK to the interface circuit 116A, and the domain control circuit 120 can activate the clock gate signal CLKGT2(2) to stop the distribution of the system clock SYSCLK to the interface circuit 116B. In this state, since domains 106(2) and 118(2) are not operating, their power consumption can be reduced to only leakage current. Therefore, less power is drawn from the power rails 112 and 122, and their respective driving capabilities can be reduced. When communication is again required between IC102A and IC102B, the clock gate signals CLKGT1(2) and CLKGT2(2) are deactivated, whereby the interface circuits 116A and 116B are activated to communicate.
[0015] As further described with reference to FIG. 2, when communication resumes between IC102A and IC102B, domain control circuits 108 and 120 reduce voltage droops on power rails 112 and 122. Thus, reducing the voltage droop includes increasing the driving capabilities on power rails 112 and 122 before deactivating clock gate signals CLKGT1(2) and CLKGT2(2). When clock gate signal CLKGT1(2) is deactivated, domain clock signal DCLK1 is distributed to domain 106(2), turning on (activating) interface circuit 116A, and domain clock signal DCLK2 is distributed to domain 118(2), turning on interface circuit 116B. By providing increased driving capabilities on power rails 112 and 122 before activating the domain clock signals, a sudden drop (droop) in voltage when domains 106(2) and 118(2) become active and power draw starts is reduced.
[0016] FIG. 2 is a configuration diagram of a domain control circuit 200 corresponding to domain control circuits 108 and 120 of FIG. 1 that reduces voltage droop when activating a first domain of an IC. In this context, "activation" of the first domain indicates that power is supplied to the first domain and the clock signal provided to the first domain is cyclic, and "deactivation" indicates that the circulation of the clock signal has stopped and further indicates that power is no longer supplied to the first domain. In the following description of FIG. 2, references to the first domain and the IC may correspond to one of domains 106(1)-106(4) of IC102A in FIG. 1, for example, although not shown in FIG. 2. Domain control circuit 200 includes a power regulator 202 and an ordering circuit 204. Power regulator 202 regulates the supply voltage V on power rail 208 DDincludes a regulator circuit 206 for supplying power, and the power rail 208 can be coupled to a plurality of domains within the IC, such as domains 106(1) - 106(4) of IC102A in FIG. 1. In this example, since the regulator circuit 206 supplies power to the "always-on" domains, it is not controlled by the sequencing circuit 204.
[0017] In this context, the term "always-on" related to a domain indicates that the domain is active while power is being supplied to the power regulator 202 and is not deactivated by the sequencing circuit 204. For example, when an electronic device including the IC is put into sleep mode or low power mode (e.g., by power-saving software), the domains within the IC can be deactivated, but at least some circuits within the IC need to remain active to recognize a wake-up signal or wake-up command to return to normal operation. Thus, at least one domain within the IC is maintained in an always-on state (e.g., by an active clock signal). Such a domain may be small to minimize power consumption during sleep mode, or may include circuits that remain active in low power mode for other reasons. In some examples, the clock of the "always-on" domain of the IC can be shut off even while power is being supplied to the IC.
[0018] The sequencing circuit 204 can be provided to control the clock and supply power to the remaining domains in the IC's domain to reduce voltage droop. The power regulator 202 of FIG. 2 includes regulator circuits 210(1) - 210(N) for providing current driving capability to the power rail 208 with respect to the power demand of a domain, which is hereinafter referred to as the first domain DM1 in this specification but not shown in FIG. 2. For example, the first domain DM1 can be any of the domains 106(1) - 106(4) of FIG. 1. Power is supplied to the first domain DM1 and the always-on domain by the power rail 208. Since the regulator circuit 206 supplies only enough current capacity to well match the power needs of the always-on domain, the regulator circuits 210(1) - 210(N) may be activated in addition to the regulator circuit 206. The regulator circuits 210(1) - 210(N) are activated to realize the additional current carrying capacity required for the first domain DM1. The sequencing circuit 204 receives at input 212 a domain control signal DM-CTL indicating whether the first domain DM1 is to be activated or deactivated. The domain control signal DM-CTL can be provided to the domain control circuit 200 from the always-on domain that remains active while the first domain DM1 is deactivated. Alternatively, the domain control signal DM-CTL can be provided to the domain control circuit 200 from an input to the IC. The domain control signal DM-CTL is activated to activate the first domain DM1. An example of the domain control signal DM-CTL is shown in the timing diagram 214 of FIG. 2. The timing diagram 214 shows the state of the domain control signal DM-CTL as a binary signal that can be based on the voltage level supplied to the input 212. In response to the activation of the domain control signal DM-CTL, the sequencing circuit 204 first generates a power control signal 216 to control the regulator circuits 210(1) - 210(N) to supply power on the power rail 208 to the first domain DM1. After generating the power control signal 216 to control the regulator circuits 210(1) - 210(N) to supply power, the sequencing circuit 204 generates a clock gate signal 218 in an inactive state to activate the first domain DM1.In other words, in response to the domain control signal DM-CTL indicating the activation of the first domain DM1, before the activation of the clock of the first domain DM1, at least one of the regulator circuits 210(1) to 210(N) is first turned on, whereby the power rail voltage V on the power rail 208. PWR can be increased. After a predetermined delay period, the clock gate signal 218 is deactivated to activate the domain clock of the first domain DM1. In response to the clock gate signal 218 being deactivated, the first domain DM1 begins to consume power. In an IC that does not include the domain control circuit 200, due to the sudden demand for power on the power rail 208, the power rail voltage may decrease below a threshold level at which performance can be degraded and / or an error can occur. However, in an IC that includes the domain control circuit 200, after the regulator circuits 210(1) to 210(N) are activated, the clock gate signal 218 is deactivated, so the power rail voltage V on the power rail 208 PWR is at an increased level when power consumption surges in the first domain DM1. That is, in response to at least one of the regulator circuits 210(1) to 210(N) supplying power to the first domain DM1, after the power rail voltage V PWR has increased, the sequencing circuit 204 generates the clock gate signal 218 in a deactivated state. As a result, due to the sudden power demand, the voltage V PWR temporarily drops slightly below the voltage threshold, and then the power rail voltage V PWR returns to the normal level.
[0019] The first domain DM1 is also deactivated based on the domain control signal DM-CTL. In response to the domain control signal DM-CTL indicating the deactivation of the first domain DM1, the sequencing circuit 204 generates an active clock gate signal 218, whereby the domain clock signal of the first domain DM1 will be deactivated. After generating the deactivated clock gate signal 218, the sequencing circuit 204 generates a power control signal 216 to control the regulator circuits 210(1) to 210(N) to stop supplying power on the power rail 208 to the first domain DM1. The stop of the power supply to the first domain DM1 is delayed for a predetermined delay period after generating the deactivated clock gate signal 218 to ensure that the operation of the first domain DM1 is terminated before the power is interrupted. If the power is interrupted from the first domain DM1 before the domain clock stops, the power rail voltage V PWR may drop below the threshold, thereby potentially causing a data error.
[0020] The power control signal 216 generated by the sequencing circuit 204 can activate and deactivate the regulator circuits 210(1) to 210(N). In some examples, all of the regulator circuits 210(1) to 210(N) are activated in response to the power control signal 216 and supply power to the power rail 208 for the first domain DM1. In FIG. 2, the regulator circuits 210(1) to 210(N) are coupled in parallel to each other between the supply voltage node 220 and the power rail 208. The capacitor 222 is coupled between the power rail 208 and the ground GND. The domain control circuit 200 can handle the maximum power requirement that does not exceed the power level supplied by all of the regulator circuits 210(1) to 210(N) for the first domain DM1. In some examples where the power requirement of the first domain DM1 is lower, any number (e.g., from 1 to N) of the regulator circuits 210(1) to 210(N) may be activated by the regulator control circuit 224. The regulator control circuit 224 controls the number of the regulator circuits 210(1) to 210(N) that are activated to supply power to the first domain DM1 based on the power level signal DM1-PWR received at the input 226. In FIG. 2, the regulator control circuit 224 is shown as part of the power regulator 202, but the regulator control circuit may be external to the power regulator 202 and may also be included in the sequencing circuit 204. The power level signal DM1-PWR indicates the number of the regulator circuits 210(1) to 210(N) that are activated in response to the activation of the power control signal 216. In this regard, the flexibility provided by the domain control circuit 200 can be beneficial when the overall power consumption of the first domain DM1 is not known in advance or can vary. For example, in a domain that includes an instruction processing circuit that consumes power at a rate that varies in response to the execution of instructions and the position of the instructions in the pipeline, the power level signal DM1-PWR can be dynamically adjusted when an instruction enters the pipeline to synchronize the delivery of power to the domain with a particular instruction at a particular location within the pipeline.
[0021] Each of the regulator circuits 210(1) to 210(N) includes a first transistor 228 configured to couple the supply voltage node 220 to the intermediate node 230 based on the regulator control signals 232(1) to 232(N) generated in the regulator control circuit 224. Each of the regulator circuits 210(1) to 210(N) also includes a second transistor 234 that couples the intermediate node 230 to the power rail 208 based on the PWR power rail voltage V.
[0022] The sequencing circuit 204 includes a delay circuit 236 that includes one or more buffer circuits 238(1) to 238(X) coupled in series, where X is selected based on the respective delays of the buffer circuits 238(1) to 238(X) and a predetermined delay period. The predetermined delay period is the time by which the generation of the power control signal 216 is to be delayed after the generation of the clock gate signal 218, or vice versa. The delay circuit 236 receives the domain control signal DM-CTL and generates a delayed domain control signal DM-CTL-DLY, where the delayed domain control signal DM-CTL-DLY is the domain control signal DM-CTL temporally (i.e., delayed) adjusted by a predetermined delay period provided by the delay circuit 236.
[0023] The sequencing circuit 204 includes a first multiplexer 240 and a second multiplexer 242. The first multiplexer 240 generates a power control signal 216 to control at least one of the regulator circuits 210(1) to 210(N) for supplying power to the first domain DM1. The power control signal 216 is generated when the domain control signal DM-CTL is activated (e.g., the supply voltage V DDThe binary "1" indicated by [[ID=]], and in response to the fact that the delayed domain control signal DM-CTL-DLY is also activated, it is generated by the first multiplexer 240. The second multiplexer 242 generates a clock gate signal 218 to deactivate the clock signal of the first domain DM1 in two situations. The first situation where the clock gate signal 218 is activated is in response to the domain control signal DM-CTL being activated and the delayed domain control signal DM-CTL-DLY being deactivated (e.g., low voltage, ground, or V SS The binary "0" indicated by [[ID=]]. This first situation occurs after the domain control signal DM-CTL is activated, but this state change has not propagated to the delay circuit 236. The second situation where the clock gate signal 218 is activated is in response to the delayed domain control signal DM-CTL-DLY being activated. In this way, when the first domain DM1 is turned off, which can also be referred to as shutting down or entering sleep mode, for the first domain DM1, the domain clock is deactivated by activating the clock gate signal 218, and after a predetermined delay period, the power control signal 216 is activated to stop supplying power to the first domain DM1 on the power rail 208.
[0024] This is shown in timing diagram 214 which shows the sequence of the domain control signal DM-CTL, clock gate signal 218, and power control signal 216 when the first domain DM1 is deactivated. At time point T1, the domain control signal DM-CTL is activated (e.g., a transition from "0" to "1"). In response to the transition of the domain control signal DM-CTL and the short propagation delay to the second multiplexer 242, the clock gate signal 218 transitions at time point T2 to deactivate the domain clock of the first domain DM1. The transition of the domain control signal DM-CTL also propagates to the delay circuit 236 and the first multiplexer 240, causing the power control signal 216 to transition to time point T3 at which any active circuit among the regulator circuits 210(1) to 210(N) is deactivated. Until time point T4, the first domain DM1 remains quiescent and the domain control signal DM-CTL remains active, but at that point, the domain control signal DM-CTL transitions again (e.g., returns from "1" to "0") to turn on the first domain DM1. The power control signal 216 is activated at time point T5 to turn on M regulator circuits 210(1) to 210(N), where M is determined by the power level signal DM-PWR1 received by the regulator control circuit 224. Also, the transition of the domain control signal DM-CTL propagates to the delay circuit 236 during a predetermined delay period, and the clock gate signal 218 is deactivated at time point T6 to turn on the domain clock of the first domain DM1.
[0025] As shown in FIG. 2, the power regulator 202 can also include regulator circuits 250(1) to 250(Y), and the regulator circuits 250(1) to 250(Y) can be one or more regulator circuits coupled in parallel corresponding to the regulator circuits 210(1) to 210(N). The regulator circuits 250(1) to 250(Y) can supply power on the power rail 208 to a second domain coupled to the power rail 208. To control the regulator circuit 250, the power regulator includes a regulator control circuit 252, and the regulator control circuit 252 receives a second domain power level signal DM2-PWR. In this regard, the domain control circuit 200 can further include a second sequencing circuit 254 that operates in the same manner as the sequencing circuit 204 to control the second domain DM1. The second sequencing circuit 252 receives a second domain control signal DM2-CTL and can generate a second power control signal 256 to activate and deactivate the second domain. Alternatively, the second sequencing circuit 252 can receive a domain control signal DM-CTL. In this regard, the domain control signal DM-CTL may be a multi-bit signal for separately controlling the sequencing circuit 204 and the second sequencing circuit 252. In some examples, the domain control circuit 200 can include additional sequencing circuits and additional corresponding regulator circuits for controlling additional domains within the power regulator 202.
[0026] FIG. 3 is a flowchart of a method 300 for controlling a first domain DM1 of the IC 102A. The method includes a step (block 302) of supplying power on the power rail 208 to the first domain DM1 of the IC 102A by a power regulator 202 including at least one regulator circuit 210(1) - 210(N). The method includes a step (block 304) of receiving, in an ordering circuit 204, a domain control signal DM-CTL indicating one of activation and deactivation of the first domain DM1. The method further includes, in response to the domain control signal DM-CTL indicating activation of the first domain DM1 (block 306), a step of generating a power control signal 216 (block 308) for controlling at least one regulator circuit 210(1) - 210(N) to supply the power on the power rail 208 to the first domain DM1, and a step of generating a clock gate signal 218 in a first state (block 310) for activating a clock signal of the first domain DM1 after generating the power control signal 216 for controlling at least one regulator circuit 210(1) - 210(N) to supply the power on the power rail 208 to the first domain DM1.
[0027] FIG. 4 is a block diagram of an exemplary processor-based system 400 that includes a processor 402 (e.g., a microprocessor) that includes an instruction processing circuit 404. The processor-based system 400 may be one circuit or a plurality of circuits included in an electronic board card such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and moreover, may correspond to, for example, a server or a user's computer. In this example, the processor-based system 400 includes a processor 402. The processor 402 corresponds to one or more general-purpose processing circuits such as a microprocessor or a central processing unit. More specifically, the processor 402 may be an EDGE instruction set microprocessor or any other processor that implements an instruction set that supports explicit consumer naming for communicating the produced value obtained from the execution of the manufacturer's instructions. The processor 402 is configured to execute the processing logic of instructions for performing the operations and the steps discussed herein. In this example, the processor 402 includes an instruction cache 406 for temporarily storing instructions for high-speed access, accessible by the instruction processing circuit 404. Instructions fetched or prefetched from a memory such as the main memory 408 via the system bus 410 are stored in the instruction cache 406. Data may be stored in a cache memory 412 coupled to the system bus 410 for low-latency access by the processor 402. The instruction processing circuit 404 is configured to process the instructions fetched into the instruction cache 406 and process them to execute the instructions.
[0028] Processor 402 and main memory 408 are coupled to system bus 410 and can be interconnected to peripheral devices included in processor-based system 400. As is well known, processor 402 communicates with these other devices by exchanging address, control, and data information via system bus 410. For example, processor 402 can transmit a burst transaction request to memory controller 414 within main memory 408 as an example of a slave device. Although not shown in FIG. 4, a plurality of system buses 410 may be provided, where each system bus 410 has a different structure. In this example, memory controller 414 is configured to make a memory access request to memory array 416 within main memory 408. Memory array 416 is composed of an array of storage bit cells for storing data. Main memory 408 may be, by way of non-limiting example, dynamic random access memory (DRAM) such as read-only memory (ROM), flash memory, synchronous DRAM (SDRAM), etc., and / or static memory (e.g., flash memory, SRAM, etc.).
[0029] Other devices may be connected to the system bus 410. As shown in FIG. 4, these devices may include, by way of example, main memory 408, one or more input devices 418, one or more output devices 420, a modem 422, and one or more display controllers 424. The input device(s) 418 can include any type of input device including, but not limited to, input keys, switches, voice processors, etc. The output device(s) 420 can include any type of output device including, but not limited to, audio, video, other visual indicators, etc. The modem 422 can be any device configured to enable the exchange of data to and from the network 426. The network 426 can be any type of network including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH (trademark) network, and the Internet. The modem 422 may be configured to support any desired type of communication protocol. The processor 402 may be further configured to access the display controller(s) 424 via the system bus 410 to control information sent to one or more displays 428. The display(s) 428 can include any type of display including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.
[0030] The processor - based system 400 of FIG. 4 may include an instruction set 430 to be executed by a processor 402 for any desired application by instruction. The instructions 430 may be stored in a main memory 408, a processor 402, and / or an instruction cache 406 as examples of non - transitory computer - readable media 432. The instructions 430 may be fully or at least partially present in the main memory 408 and / or within the processor 402 during their execution. The instructions 430 may further be transmitted or received via a modem 422 over a network 426 including a computer - readable media 432.
[0031] Any of the circuits within the processor - based system 400 can include the domain control circuit 200 shown in FIG. 2 for clock control of the domain and power control to reduce voltage droop.
[0032] Although the computer - readable media 432 is shown as a single medium in the exemplary embodiment, the term "computer - readable media" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "computer - readable media" should also be understood to include any medium that can store, encode, or carry a set of instructions that cause a processing device to execute any one or more of the methods of the embodiments disclosed herein for execution by the processing device. Thus, the term "computer - readable media" should be understood to include, without limitation, solid - state memory, optical media, and magnetic media.
[0033] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with the instructions to execute the steps. Alternatively, the steps may be executed by a combination of hardware and software.
[0034] The embodiments disclosed herein may be provided as a computer program product or software that may include a machine-readable medium (or computer-readable medium) on which instructions for programming a computer system (or other electronic device) to execute a process according to the embodiments disclosed herein are stored. The machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, the machine-readable medium includes machine-readable storage media (e.g., ROM, random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.).
[0035] Unless otherwise specifically stated, as will be apparent from the foregoing discussion, throughout this description, discussions using terms such as "processing," "computing," "determining," or "displaying" relate to the operation and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers of the computer system and other data similarly represented as physical quantities within the computer system memory or registers or other such information storage, transmission, or display devices.
[0036] The algorithms and displays presented in this specification are in essence not associated with any particular computer or other device. It may become apparent that various systems may be used with the programs according to the teachings herein, or that it may be convenient to construct more specialized devices to perform the required method steps. The structures required for these various systems will be apparent from the above description. In addition, the embodiments described herein are not described in relation to any particular programming language. It will be understood that various programming languages may be used to implement the teachings of the embodiments described herein.
[0037] One of ordinary skill in the art will further understand that the various exemplary logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium, executed by a processor or other processing device, or a combination of both. The components of the distributed antenna system described herein may be utilized, for example, in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be of any type and size and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. One of ordinary skill in the art can implement the described functionality in various ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the present embodiments.
[0038] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or executed by a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gates or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a controller may be a processor. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
[0039] The embodiments disclosed herein may be implemented in hardware and in instructions stored in hardware, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a remote station. In the alternative, the processor and the storage medium can reside as discrete components in a remote station, base station, or server.
[0040] It should also be noted that the operation steps described in any of the exemplary embodiments of this specification are described for the purpose of providing examples and considerations. The described operations may be performed in many different sequences different from the illustrated sequence. Further, the operations described in a single operation step may actually be performed in many different steps. Also, one or more operation steps discussed in the exemplary embodiments may be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of techniques and methodologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields, optical fields or particles, or any combination thereof.
[0041] Unless otherwise expressly stated, in no way should any method recited in this specification be construed as requiring that its steps be performed in a particular order. Thus, here, method claims do not actually recite the order that the steps should follow, nor are steps in a claim or description otherwise specifically stated to be limited to a particular order, and in no way is any particular order to be inferred.
[0042] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. The integration of the modifications, combinations, sub-combinations and variations of the disclosed embodiments with the spirit and content of the invention can be conceived by those skilled in the art, and the invention should be construed to include all those within the scope of the appended claims and their equivalents.
Claims
1. A power regulator comprising a plurality of regulator circuits, each configured to supply power on a power rail to a first domain of an integrated circuit (IC), It is an ordering circuit, Receiving a domain control signal indicating either activation or deactivation of the first domain, In response to the domain control signal indicating activation of the first domain, To generate a power control signal to control the plurality of regulator circuits so as to supply power on the power rail to the first domain, In response to the generation of the power control signal to control the plurality of regulator circuits to supply power on the power rail to the first domain, a first state clock gate signal is generated to activate the clock signal of the first domain. A sequencing circuit configured to perform the following: A domain control circuit including, The aforementioned power regulator is A regulator control circuit, Receiving power level signals, The power control signal and the power level signal indicate the number of regulating circuits of the first plurality of regulating circuits to be activated, and the first plurality of regulating circuits are controlled to supply power in parallel to the power rail. A domain control circuit further includes a regulator control circuit configured to perform the following actions.
2. A domain control circuit according to Claim 1, wherein the ordering circuit is further configured to generate the clock gate signal of a first state after generating the power control signal to control the plurality of regulating circuits to supply power on the power rail to the first domain.
3. A domain control circuit according to Claim 1, wherein the ordering circuit is further configured to generate the clock gate signal of the first state after the voltage on the power rail has increased in response to the plurality of regulator circuits supplying power to the first domain.
4. The domain control circuit according to Claim 1, wherein each of the plurality of regulator circuits is A first transistor configured to connect a supply voltage node to an intermediate node based on the regulator control circuit, A second transistor configured to couple the intermediate node to the power rail based on the voltage on the power rail, A domain control circuit, including one.
5. A domain control circuit according to claim 1, wherein the ordering circuit responds to the domain control signal indicating the deactivation of the first domain, To deactivate the clock signal of the first domain, a clock gate signal of the second state is generated, In response to generating the clock gate signal in the second state, the power control signal is generated to control the plurality of regulator circuits to stop supplying power on the power rail to the first domain. A domain control circuit further configured to perform the following actions.
6. A domain control circuit according to claim 5, wherein the ordering circuit is further configured to generate the power control signal to control the plurality of regulator circuits to stop supplying power on the power rail to the first domain for a predetermined delay period after generating the clock gate signal for the second state.
7. The domain control circuit according to claim 1, wherein the ordering circuit is A delay circuit comprising at least one buffer circuit, wherein the at least one buffer circuit is Receiving the aforementioned domain control signal, To generate a delayed domain control signal that includes the domain control signal delayed by a predetermined delay period. A delay circuit configured to perform the following: A first multiplexer configured to control the plurality of regulating circuits to supply power for the first domain in response to the domain control signal including a first state and the delayed domain control signal including the first state, The second multiplexer, The domain control signal includes the first state, and the delayed domain control signal includes the second state, The delayed domain control signal includes the first state. A second multiplexer configured to generate the clock gate signal in response to the clock signal of the first domain, Domain control circuits, which further include this.
8. A domain control circuit according to Claim 1, wherein the power regulator further includes at least one always-on regulator circuit for supplying power on the power rail to the always-on domain.
9. A domain control circuit according to claim 1, A second power regulator including a second plurality of regulator circuits configured to supply power on the power rail to a second domain of the IC, A second ordering circuit, Receiving a second domain control signal indicating either activation or deactivation of the second domain, In response to the second domain control signal indicating activation of the second domain, To generate a second power control signal to control the second plurality of regulator circuits to supply power on the power rail to the second domain, After generating the second power control signal to control the second plurality of regulating circuits to supply power on the power rail to the second domain, the second clock gate signal of the first state is generated to activate the second clock signal of the second domain, A second ordering circuit configured to perform the following: A domain control circuit further includes this.
10. A system including an integrated circuit (IC), A first domain including a chip-to-chip interface circuit, Domain control circuit, A power regulator including a plurality of regulator circuits configured to supply power on a power rail to a first domain of an integrated circuit (IC), It is an ordering circuit, Receiving a domain control signal indicating either activation or deactivation of the first domain, In response to the domain control signal indicating activation of the first domain, To generate a power control signal to control the plurality of regulator circuits so as to supply power on the power rail to the first domain, After generating the power control signal to control the plurality of regulator circuits to supply power on the power rail to the first domain, a first state clock gate signal is generated to activate the clock signal of the first domain. A sequencing circuit configured to perform the following: A domain control circuit including, A clock distribution circuit, Receiving the aforementioned clock gate signal, Receiving the system clock signal, Based on the clock gate signal, the system clock signal is distributed to the first domain, A clock distribution circuit configured to perform the following: Includes, The aforementioned power regulator is A regulator control circuit, Receiving power level signals, The power control signal and the power level signal indicate the number of regulating circuits of the first plurality of regulating circuits to be activated, and the first plurality of regulating circuits are controlled to supply power in parallel to the power rail. A domain control circuit further includes a regulator control circuit configured to perform the following actions.
11. The system according to claim 10, wherein the IC further includes an always-on domain configured to provide the domain control signal to the ordering circuit.
12. The system according to claim 11, The second IC is A second power regulator including a second plurality of regulator circuits configured to supply power on a second power rail to a second domain, A second ordering circuit, Receiving a second domain control signal indicating either activation or deactivation of the second domain, In response to the second domain control signal indicating activation of the second domain, To generate a second power control signal to control the second plurality of regulator circuits to supply power on the second power rail to the second domain, After generating the second power control signal to control the second plurality of regulating circuits to supply power on the second power rail to the second domain, a second clock gate signal of the first state is generated to activate the second clock signal of the second domain, A second ordering circuit configured to perform the following: The second IC including A system that further includes this.
13. A method for controlling a first domain of an integrated circuit, A power regulator, including multiple regulator circuits, supplies power on a power rail to a first domain of an integrated circuit (IC), In an ordering circuit, the steps include receiving a domain control signal indicating either activation or deactivation of the first domain, In response to the domain control signal indicating activation of the first domain, The steps include generating a power control signal to control the plurality of regulator circuits to supply power on the power rail to the first domain, In response to the generation of the power control signal to control the plurality of regulator circuits to supply power on the power rail to the first domain, the steps include generating a first state clock gate signal to activate the clock signal of the first domain, The steps include receiving a power level signal in the power regulator, The steps include controlling the first plurality of regulator circuits to supply power in parallel to the power rail in response to the power control signal and the power level signal indicating the number of first plurality of regulator circuits to be activated, A method that includes this.
14. A method according to claim 13, further comprising the step of generating a power control signal to control the plurality of regulating circuits to supply power on the power rail to the first domain, and then generating the clock gate signal of the first state.
15. A method according to claim 13, further comprising the step of generating the clock gate signal in the first state after the voltage on the power rail has increased in response to the plurality of regulator circuits supplying power to the first domain.
16. The method according to claim 13, In response to the domain control signal indicating the deactivation of the first domain, The steps include generating the clock gate signal in a second state in order to deactivate the clock signal of the first domain, The steps include generating the clock gate signal for the second state, and then generating the power control signal to control the plurality of regulator circuits to stop supplying power on the power rail to the first domain, A method that further includes this.
17. A method according to claim 16, further comprising the step of generating the power control signal to control the plurality of regulator circuits to stop supplying power on the power rail to the first domain for a predetermined delay period, after generating the clock gate signal for the second state.
18. The method according to claim 13, The steps include receiving the domain control signal in the delay circuit, A step of generating a delayed domain control signal that includes the domain control signal delayed by a predetermined delay period, The steps of controlling the plurality of regulator circuits to supply power for the first domain in response to the domain control signal including a first state and the delayed domain control signal including the first state, The domain control signal includes the first state, and the delayed domain control signal includes the second state, The delayed domain control signal includes the first state. In response to this, the steps include generating the clock gate signal to deactivate the clock signal of the first domain and A method that further includes this.
19. The method according to claim 18, wherein in each of the plurality of regulator circuits, The steps include connecting a supply voltage node to a first node in response to the power control signal and the power level signal, The steps of connecting the first node to the power rail based on the voltage on the power rail, A method that further includes this.
20. A method according to claim 13, further comprising the step of an always-on domain providing the domain control signal to the domain control circuit.
21. A memory configured to store instructions, A processing circuit, In response to executing the memory stored in the aforementioned memory, Controlling a power regulator, which includes multiple regulator circuits, to supply power on the power rail to a first domain of an integrated circuit (IC), Controlling the ordering circuit, Receiving a domain control signal indicating either activation or deactivation of the first domain, In response to the domain control signal indicating activation of the first domain, To generate a power control signal to control the plurality of regulator circuits so as to supply power on the power rail to the first domain, In response to generating the power control signal to control the plurality of regulator circuits to supply power on the power rail to the first domain, a first state clock gate signal is generated to activate the clock signal of the first domain. To have them do that and A processing circuit configured to perform the following: A processor system including, The power regulator includes at least one regulator circuit, The processing circuit controls the power regulator, Receiving power level signals, The power control signal and the power level signal indicate the number of first multiple regulator circuits to be activated, and the first multiple regulator circuits are controlled to supply power to the power rail in parallel. A processor system further configured to perform the following actions.