Domain Clock and Power Activation Control Circuit and Related Method for Reducing Voltage Droop
JP2025521426A5Pending Publication Date: 2026-06-16MICROSOFT TECHNOLOGY LICENSING LLC
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Patent Information
- Application Number
- JP2024570761
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-06-29
- Filing Date
- 2023-05-18
- Publication Date
- 2026-06-16
AI Technical Summary
Technical Problem
Voltage droop occurs in integrated circuits due to sudden power consumption when logic circuits are activated, leading to performance slowdowns and potential logic errors.
Method used
Implement a domain control circuit with a sequencing circuit to control clock gate signals and power regulators, ensuring power is supplied to domains before activating clock signals, and deactivating them after voltage stabilization.
Benefits of technology
Significantly reduces voltage droop during domain activation, maintaining stable power supply and preventing performance degradation and errors.
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Abstract
The domain control circuit includes a power regulator for supplying power on the power rail to a first domain, a sequencing circuit for controlling the power regulator, and a clock gate signal for activating the domain. The sequencing circuit receives a domain control signal to control the activation and deactivation of the domain. The domain control circuit controls the power regulator to supply power on the power rail to the domain, and then deactivates the clock gate signal for the domain. In this way, the voltage droop of the supply voltage on the power rail is reduced. In some examples, the clock gate signal for the domain is deactivated after the voltage increases on the power rail. In some examples, the power regulator includes a plurality of parallel regulator circuits and a regulator control circuit for determining the number of parallel regulator circuits activated to supply power to the domain.
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