Memory system, its operation method, storage medium, and memory controller

Abstract

Some examples of the present disclosure provide a memory system, a method of operating the same, a storage medium, and a memory controller. The memory system includes at least one non-volatile memory device and a memory controller coupled to the at least one non-volatile memory device. A multi-level mapping table is stored in the memory device, and the multi-level mapping table is for performing mapping from a logical address to a physical address. The memory controller includes a buffer, and a part of the multi-level mapping table is stored in the buffer. The memory controller is configured to perform a random read operation on data stored in the memory device, and adjust a capacity for storing different-level mapping tables in the buffer in response to a random read range corresponding to the random read operation satisfying a preset condition.

Description

Technical Field

[0001] Examples of the present disclosure relate to the field of semiconductor technology, and more particularly, to memory systems and methods of operating the same, storage media, and memory controllers.

Background Art

[0002] A memory device is a memory device configured to maintain information in modern information technology. Flash memory has several advantages as a typical non-volatile semiconductor memory, such as high storage density, controllable manufacturing cost, appropriate speed of programming and erasing, and retention characteristics, and has gradually become mainstream in the storage market.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Memory systems such as solid state drives (SSDs) for personal computers and servers, and universal flash storage (UFS) for mobile phones and various embedded systems may include flash memory as a persistent storage medium. Therefore, how to further improve the read and write performance of data in memory systems has become an urgent problem to be solved in the industry.

Means for Solving the Problems

[0004] Examples of the present disclosure provide a memory system and a method of operating the same, a storage medium, and a memory controller.

[0005] In a first aspect, an example of the present disclosure provides a memory system, the memory system including at least one non-volatile memory device and a memory controller coupled to the at least one non-volatile memory device, a multi-level mapping table being stored in the memory device, the multi-level mapping table being for performing a mapping from a logical address to a physical address, the memory controller including a buffer, a part of the multi-level mapping table being stored in the buffer, and the memory controller being configured to perform a random read operation on data stored in the memory device and to adjust a capacity for storing different levels of mapping tables in the buffer in response to a random read range corresponding to the random read operation satisfying a preset condition.

[0006] In some examples, the multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table, a physical address of the second-level mapping table being stored in the first-level mapping table, a physical address of the third-level mapping table being stored in the second-level mapping table, a physical address of data being stored in the third-level mapping table, and the whole of the first-level mapping table, a part of the second-level mapping table, and a part of the third-level mapping table being stored in the buffer.

[0007] In some examples, the memory controller is configured to increase a ratio of a capacity for storing the second-level mapping table in the buffer to an overall capacity for storing the second-level mapping table and the third-level mapping table in the buffer in response to the random read range being greater than or equal to a preset value.

[0008] In some examples, the memory controller is configured to obtain a target buffer hit rate of the mapping table in response to a random read range being greater than or equal to a pre-set value, detect a current buffer hit rate of the mapping table, and increase a ratio of a capacity for buffering the second-level mapping table to an overall capacity for buffering the second-level mapping table and the third-level mapping table until the current buffer hit rate of the mapping table is greater than or equal to the target buffer hit rate of the mapping table in response to the current buffer hit rate of the mapping table being lower than the target buffer hit rate of the mapping table.

[0009] In some examples, the memory controller is configured to determine a difference between the current buffer hit rate of the mapping table and the target buffer hit rate of the mapping table, and determine an increase amount of the capacity for buffering the second-level mapping table in this adjustment according to the difference, and there is a positive correlation between the increase amount and the difference.

[0010] In some examples, the memory controller is configured to stop adjusting the capacity for buffering mapping tables at different levels in response to the current buffer hit rate of the mapping table being lower than the target buffer hit rate of the mapping table and the ratio of the current capacity for buffering the second-level mapping table to the overall capacity for buffering the second-level mapping table and the third-level mapping table reaching a pre-set ratio.

[0011] In some examples, the memory controller is configured to determine the target buffer hit rate of the mapping table according to the random read range.

[0012] In some examples, the memory controller is configured to keep invariant the capacity for storing the second-level mapping table in a buffer and the capacity for storing the third-level mapping table in a buffer in response to a random read range being less than a preset value.

[0013] In some examples, the memory controller is configured to determine a preset value according to the current capacity for storing the second-level mapping table in a buffer in combination with mapping rules for mapping tables at various levels.

[0014] In some examples, the memory controller is configured to increase the overall capacity for storing the second-level mapping table and the third-level mapping table in a buffer in response to a random read range being greater than or equal to a preset value.

[0015] In some examples, the multi-level mapping table includes a first-level mapping table and a second-level mapping table. The physical address of the second-level mapping table is stored in the first-level mapping table, the physical address of data is stored in the second-level mapping table, a part of the first-level mapping table and a part of the second-level mapping table are stored in a buffer, and the memory controller is configured to increase the ratio of the capacity for storing the first-level mapping table in the buffer to the overall capacity for storing the first-level mapping table and the second-level mapping table in the buffer in response to a random read range being greater than or equal to a preset value.

[0016] In some examples, the memory system includes a DRAM-less memory system and the buffer includes a static random access memory.

[0017] In some examples, the memory system includes flash storage and the memory device includes NAND memory.

[0018] In a second aspect, an example of the present disclosure provides a method of operating a memory system, the memory system including at least one non-volatile memory device and a memory controller coupled to the at least one non-volatile memory device, a multi-level mapping table being stored in the memory device, the multi-level mapping table being for performing a mapping from a logical address to a physical address, the memory controller including a buffer, a portion of the multi-level mapping table being stored in the buffer, the method including the steps of performing a random read operation on data stored in the memory device, and adjusting a capacity for storing different levels of the mapping table in the buffer in response to a random read range corresponding to the random read operation satisfying a preset condition.

[0019] In some examples, the multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table, a physical address of the second-level mapping table being stored in the first-level mapping table, a physical address of the third-level mapping table being stored in the second-level mapping table, a physical address of the data being stored in the third-level mapping table, an entirety of the first-level mapping table, a portion of the second-level mapping table, and a portion of the third-level mapping table being stored in the buffer, and the step of adjusting a capacity for storing different levels of the mapping table in the buffer in response to a random read range corresponding to the random read operation satisfying a preset condition includes increasing a ratio of a capacity for storing the second-level mapping table in the buffer to an entire capacity for storing the second-level mapping table and the third-level mapping table in the buffer in response to the random read range being equal to or greater than a preset value.

[0020] In some examples, in response to the random read range being greater than a pre-set value, the step of increasing the ratio of the capacity for storing the second-level mapping table to the overall capacity for storing the second-level mapping table and the third-level mapping table in the buffer includes: obtaining a target buffer hit rate of the mapping table in response to the random read range being greater than a pre-set value; detecting a current buffer hit rate of the mapping table; and in response to the current buffer hit rate of the mapping table being lower than the target buffer hit rate of the mapping table, increasing the ratio of the capacity for storing the second-level mapping table to the overall capacity for storing the second-level mapping table and the third-level mapping table in the buffer until the current buffer hit rate of the mapping table is greater than or equal to the target buffer hit rate of the mapping table.

[0021] In some examples, the method further includes: determining a difference between the current buffer hit rate of the mapping table and the target buffer hit rate of the mapping table; and determining an increase amount of the capacity for storing the second-level mapping table in the buffer in this adjustment according to this difference, and there is a positive correlation between the increase amount and the difference.

[0022] In some examples, the method further includes stopping adjusting the capacity for storing mapping tables at different levels in the buffer in response to the current buffer hit rate of the mapping table being lower than the target buffer hit rate of the mapping table and the current ratio of the capacity for storing the second-level mapping table to the overall capacity for storing the second-level mapping table and the third-level mapping table in the buffer reaching a pre-set ratio.

[0023] In a third aspect, an example of the present disclosure provides a storage medium storing executable instructions that, when executed by a processor, perform the operations of any one of the examples described above.

[0024] In a fourth aspect, an example of the present disclosure provides a memory controller including a buffer and a control component, the buffer being configured to store a portion of a multi-level mapping table in a non-volatile memory device, the multi-level mapping table being configured to perform a mapping from a logical address to a physical address, and the control component being configured to perform a random read operation on data stored in the memory device and adjust a capacity for storing different levels of mapping tables in the buffer in response to a random read range corresponding to the random read operation satisfying a preset condition.

[0025] In some examples, the memory controller further includes a flash translation layer connecting the control component and the buffer, and the flash translation layer is configured to convert a logical address into a corresponding physical address according to mapping information in the multi-level mapping table stored in the buffer.

[0026] In some examples, the control component is further configured to receive instructions from a host for performing read, write, and erase operations on the memory device, the buffer is further configured to temporarily store data transferred between the host and the memory device, and the memory controller further includes an encoder / decoder for encoding and decoding data transferred between the host and the memory device.

[0027] Examples of the present disclosure further provide another memory system, the memory system including at least one non-volatile memory device and a memory controller coupled to the at least one non-volatile memory device, a multi-level mapping table being stored in the memory device, the multi-level mapping table being for implementing a mapping from a logical address to a physical address, the memory controller including a buffer, a part of the multi-level mapping table being stored in the buffer, and the memory controller being configured to perform a random read operation on data stored in the memory device and, in response to a random read range corresponding to the random read operation satisfying a preset condition, adjust an amount of capacity for storing mapping tables of different levels in one load from the memory device to the buffer.

[0028] In the memory system provided by examples of the present disclosure, the memory device stores a multi-level mapping table, the buffer of the memory controller is configured to load a part of the multi-level mapping table, and when the random read range satisfies a preset condition, the memory controller adjusts the capacity for storing mapping tables of different levels in the buffer. In this way, in one aspect, when a wide range of random read operations are performed, the memory controller may increase the capacity for storing at least one level of the mapping table in the buffer to improve the buffer hit rate of the mapping table, thereby reducing the number of times of updating the mapping table from the memory device to the buffer and reducing the time overhead for searching for the corresponding mapping table, and improving the performance of a wide range of random reads in the memory system. In another aspect, dynamically adjusting the capacity for storing mapping tables of different levels in the buffer can improve the buffer utilization rate and hardly affect other task scheduling, so problems such as buffer resource competition can be reduced.

Brief Description of the Drawings

[0029]

Figure 1

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Figure 2b

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DETAILED DESCRIPTION OF THE INVENTION

[0030] The illustrated examples of the present disclosure will be described in more detail below with reference to the accompanying drawings. It should be understood that the illustrated examples of the present disclosure are shown in the accompanying drawings, but the present disclosure may be implemented in various forms and should not be limited to the specific examples described herein. Rather, these examples are provided so that the present disclosure can be more fully understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0031] In the following description, numerous specific details are provided in order to afford a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these specific details. In other instances, in order to avoid obscuring the present disclosure, some well-known technical features have not been described. That is, not all features of actual examples are described herein, and well-known functions and structures are not described in detail.

[0032] In the accompanying drawings, the sizes of layers, regions, and elements, as well as their relative sizes, may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0033] When an element or layer is referred to as being "in contact with", "adjacent to", "connected to", or "coupled to" another element or layer, it will be understood that it may be in direct contact with, directly adjacent to, directly connected to, or directly coupled to the other element or layer, or that intervening elements or layers may be present. In contrast, when an element is referred to as being "directly in contact with", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, no intervening elements or layers are present. Terms such as first, second, third, etc. may be configured to describe various elements, components, regions, layers, and / or portions, but it will be understood that these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only configured to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, the first element, component, region, layer, or portion discussed below may be named the second element, component, region, layer, or portion without departing from the teachings of the present disclosure. A second element, component, region, layer, or portion is discussed, but this does not indicate that a first element, component, region, layer, or portion must necessarily be present in the present disclosure.

[0034] Spatial relationship terms such as "beneath", "below", "lower", "under", "above", "on", etc. may be used herein to simplify the description for describing the relationship of one element or feature to another element or feature as shown in the figures. It will be understood that the spatial relationship terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the attached drawings is inverted, an element or feature described as being "below" or "beneath" or "under" another element or feature will now be "above" another element or feature. Thus, the exemplary terms "below" and "under" can encompass both upward and downward directions. The device may be in a different orientation (rotated 90 degrees or otherwise), and the spatial relationship descriptors used herein should be interpreted accordingly.

[0035] The terms used herein are for the purpose of describing particular examples only and should not be regarded as limitations of the present disclosure. As used herein, the singular forms "a", "an", and "said / the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. The terms "consisting of" and / or "comprising" when used in this description specify the presence of the stated features, integers, operations, elements, and / or parts, but do not preclude the presence or addition of one or more other features, integers, operations, elements, parts, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0036] For a more detailed understanding of the characteristics and technical content of the examples of the present disclosure, the examples of the present disclosure will be described in detail below in connection with the accompanying drawings, which are for reference and illustration only and are not intended to limit the examples of the present disclosure.

[0037] The memory device in an example of the present disclosure includes, but is not limited to, 3D NAND memory, and for ease of understanding, 3D NAND memory is used as an example for explanation.

[0038] FIG. 1 shows a block diagram of an exemplary system 100 with a memory device, according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device. As shown in FIG. 1, system 100 may include a host 108 and a memory system 102, and the memory system 102 has one or more memory devices 104 and a memory controller 106. The host 108 can be a processor (e.g., a central processing unit (CPU)) of the electronic device or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 can be configured to transmit data to, or receive data from, the memory device 104.

[0039] According to some examples, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some examples, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some examples, the memory controller 106 is designed to operate in a solid state drive or an embedded multimedia card (eMMC) in a high duty cycle environment, and the SSD or eMMC is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, and enterprise storage arrays.

[0040] Memory controller 106 may be configured to control the operations of memory device 104, such as read operations, erase operations, and program operations. Memory controller 106 may also be configured to manage various functions related to data stored or to be stored in memory device 104, including but not limited to bad block management, garbage collection, translation from logical address to physical address, wear leveling, etc. In some examples, memory controller 106 is also configured to process error correction codes (ECCs) for data read from or written to memory device 104. Memory controller 106 may also perform any other suitable functions, such as formatting mapping of memory device 104. Memory controller 106 may communicate with a host (e.g., host 108) according to a specific communication protocol. For example, memory controller 106 may communicate with the host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0041] Memory controllers 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage package or eMMC package). That is, the memory system 102 can be implemented and packaged in various types of end electronic products. In one example as shown in FIG. 2, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, personal computer memory card international association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can further include a memory card connector 24 that couples the memory card 202 to a host (e.g., the host 108 in FIG. 1). In another example as shown in FIG. 2b, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can further include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG. 1). In some examples, at least one of the memory capacity or the operating speed of the SSD 206 is greater than at least one of the memory capacity or the operating speed of the memory card 202.

[0042] In some examples, as shown in FIG. 3, the memory system 300 uses a non-volatile memory device 310 (such as a NAND memory) for storing user data and a logical-to-physical mapping table (L2P mapping table) corresponding to the user data. When data is being read, a portion of the L2P mapping table is loaded into a buffer 321 of the memory controller 320, and the memory controller 320 uses the logical address provided by the host 400 and utilizes that portion of the L2P mapping table loaded into the buffer 321 to search for a physical address in the memory device 310, and then reads the corresponding data in the memory device 310 using the found physical address. In some examples, the buffer 321 in the memory controller 320 includes, but is not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

[0043] To store and maintain the L2P mapping table, several methods can be applied. One method is single-level direct L2P mapping, which may include mapping information for data across the entire memory device. Thus, the single-level direct page mapping method requires a large amount of storage space to store the L2P mapping table (for 1GB of data, it corresponds to storing an L2P mapping table of about 1 - 2MB), which is a challenge for large-capacity memory devices. Another method for storing and maintaining the L2P mapping table is the multi-level mapping method. Here, as shown in FIG. 4, a three-level mapping method is used as an example for illustration. The physical address of the second-level mapping table is stored in the first-level mapping table, each item of the mapping in the first-level mapping table points to the second-level mapping table, the physical address of the third-level mapping table is stored in the second-level mapping table, each item of the mapping in the second-level mapping table points to the third-level mapping table, the physical address of the data (physical block number, physical page number, etc.) is stored in the third-level mapping table, and each item of the mapping in the third-level mapping table points to a physical block or physical page in the memory device. In some examples, for a memory device with a data storage capacity of 128G, the size of the corresponding three-level mapping table is 128M, the size of the corresponding second-level mapping table is 128K, and the size of the corresponding first-level mapping table is 128 bytes.

[0044] The flash translation layer (FTL) 322 may be located within the memory controller 320 and is configured to convert logical addresses into physical addresses. Due to the limited capacity of the buffer 321 within the memory controller 320, in the multi-level mapping method, it is impossible to load all of the multi-level mapping table into the buffer 321. Therefore, the entire first-level mapping table may be loaded into the buffer 321, that is, the first-level mapping table exists within the buffer 321, while the second-level mapping table and the third-level mapping table may be partially loaded into the buffer 321. If the flash translation layer 322 is unable to obtain the mapping information required for data reading from the current buffer 32, it is necessary to update at least one of the second-level mapping table or the third-level mapping table stored in the buffer 321, that is, until the required mapping information is found, at least one of a portion of the second-level mapping table or a portion of the third-level mapping table is reloaded from the memory device 310 into the buffer 321, which can be understood. In sequential reading, since the mapping information is continuous, the performance of sequential reading in the multi-level mapping method is better. In random reading, since the mapping information is scattered, in order to find the mapping information required for random reading, multiple read operations to the memory device 310 may be further added to update at least one of the second-level mapping table or the third-level mapping table in the buffer 321. Therefore, the performance of random reading in the multi-level mapping method is relatively low. Here, the read delay of the buffer 321 may be on the order of several microseconds, but the read delay of the memory device 310 may be even larger, for example, it may be several tens of microseconds.

[0045] In some examples, the memory system 300 may be a DRAM-less memory system, i.e., it does not include DRAM. For example, the memory system 300 may be UFS, and the buffer 321 in the memory system 300 may be SRAM. The fixed capacity of the SRAM may be divided through a static allocation method to store the multi-level mapping table. Maintaining the SRAM capacity is used as buffer space used by other task scheduling of the firmware (FW). Here, the firmware is stored in the storage medium of the memory device 310 and can be executed by a control component 323 (such as a processor) in the memory controller 320.

[0046] For example, when using a memory device with a data storage capacity of 128G as an example, as shown in FIG. 5, the total capacity of the SRAM in the memory controller may be 2M, and in order to ensure that the random read operation within the range of 8G does not update the second-level mapping table stored in the SRAM, the SRAM can store a 128-byte first-level mapping table (i.e., the entire first-level mapping table in the memory device), an 8K second-level mapping table, and a 256K third-level mapping table. In order to perform a random read operation within 1G without updating the three-level mapping table stored in the SRAM, that is, to achieve a 100% buffer hit rate of the mapping table, the capacity for storing the third-level mapping table in the SRAM can be expanded from 256K to 1024K. However, based on the fact that the capacities for storing the second-level mapping table and the third-level mapping table in the SRAM are 8K and 1024K respectively, when a wide range of random read operations are performed, additional table lookups are executed, which greatly reduces the performance of a wide range of random reads. Taking 1000 random reads (i.e., full disk random reads) within the range of 128G as an example, as shown in Table 1, the ratio of the random read command, the number of reads for additionally loading the second-level mapping table, and the number of reads for additionally loading the third-level mapping table is approximately 1:1:1. The 1000 random read commands result in a total of 2931 reads, and the additional 1931 reads have a significant impact on the performance of the memory system.

[0047] The buffer space of the memory controller is limited, and random reading is for a wide range. When the buffer space of the third-level mapping table continues to increase, it will be understood that the efficiency of the firmware when performing other tasks will decrease. On the other hand, if the buffer spaces of the second-level mapping table and the third-level mapping table are not increased, the additional number of reads for loading the mapping table will increase, the time overhead for random reading will increase, and the performance of random reading will decrease.

[0048]

Table 1

[0049] Referring to FIG. 3, an example of the present disclosure provides a memory system 300, the memory system 300 includes at least one non-volatile memory device 310 and a memory controller 320 coupled to the at least one non-volatile memory device 310. The multi-level mapping table is stored in the memory device 310, and the multi-level mapping table is for performing a mapping from a logical address to a physical address. The memory controller 320 includes a buffer 321, a part of the multi-level mapping table is stored in the buffer 321, and the memory controller 320 is configured to perform a random read operation on the data stored in the memory device 310 and adjust the capacity for storing different levels of mapping tables in the buffer 321 in response to the random read range corresponding to the random read operation satisfying a preset condition.

[0050] In an example of the present disclosure, the memory controller 320 can be connected to at least one memory device 310. The memory controller 320 communicates with the host 400 through the host interface 301. The host 400 can send at least one of a command or data through the host interface 301 to request the memory controller 320 to execute a read operation, a program operation, and an erase operation of the memory device 310. The memory controller 320 can be configured to retrieve data from one or more memory devices 310 and send the data to the host 400 via a data bus. The memory device 310 may include one or more memory cell arrays of NAND flash memory, and the storage medium of the memory device 310 may store executable instructions such as the firmware of the example described above. The memory controller 320 may include one or more buffers 321, the buffer 321 may be a high-speed buffer (such as SRAM), and since the buffer 321 can be applied to store any appropriate information including an L2P mapping table, software code, commands, and firmware, the memory controller 320 can execute various commands and operations quickly. In some examples, as shown in FIG. 6, the memory device 310 may be flash memory, and the buffer 321 may be SRAM. The memory controller 320 includes a processor, the processor is connected to the host 400 through the host interface, and is connected to the memory device 310 through the flash memory interface. The processor is also connected to the buffer 321 and can obtain L2P mapping information from the buffer 321.

[0051] The memory device 310 stores a multi-level L2P mapping table, and the multi-level mapping table may indicate a mapping from a logical address to a physical address corresponding to data stored in the memory device 310. When data is being read, a portion of the multi-level mapping table is loaded from the memory device 310 into the buffer 321, and the memory controller 320 uses the logical address provided by the host 400 and utilizes that portion of the L2P mapping table loaded into the buffer 321 to search for a physical address in the memory device 310, and then reads the corresponding data in the memory device 310 using the found physical address.

[0052] In some examples, the memory controller 320 is configured to perform a random read operation on the data stored in the memory device 310 in response to a read command from the host 400. The memory controller 320 detects a random read range using the firmware stored in the memory device 310. When the random read range meets a preset condition (for example, the random read range is larger than a certain value), the memory controller 320 adjusts the capacity for storing mapping tables at various levels in the buffer 321.

[0053] Taking the three-level mapping method as an example, it is possible to increase the capacity for the second-level mapping table and decrease the capacity for the third-level mapping table while keeping the overall capacity for the second-level mapping table and the third-level mapping table unchanged (in order to adjust the capacity ratio between the second-level mapping table and the third-level mapping table). It is also possible to increase the capacity for the second-level mapping table and the third-level mapping table simultaneously, or to increase the capacity for one of the second-level mapping table and the third-level mapping table (the overall capacity for the second-level mapping table and the third-level mapping table increases). When the random read range does not meet the preset conditions, the memory controller 320 does not adjust the capacity for storing the mapping tables at various levels in the buffer 321.

[0054] The memory controller 320 transmits a mapping table load command for receiving an adjusted multi-level mapping table with a corresponding capacity from the memory device 310 and loading it into the buffer 321. Here, the load command may include the capacity information of the adjusted mapping tables at various levels. The larger the capacity for storing the mapping tables at various levels in the buffer 321, the more mapping information is obtained from the memory device 310 in one load. Thereafter, the memory controller 320 searches for the corresponding physical address of the memory device 310 according to the logical address provided by the host 400 and through that part of the multi-level mapping table loaded into the buffer 321, and then can read the corresponding data in the memory device 310 using the found physical address.

[0055] Examples of the present disclosure may also include mapping schemes with more than three levels, such as a mapping scheme with four or more levels, and it should be noted that this is not limited here. When the memory system includes a mapping scheme with more than four levels, the adjustment object may be adjusted accordingly according to the actual situation. For example, when the memory system includes four levels, the capacities for the second-level mapping table, the third-level mapping table, and the fourth-level mapping table may be adjusted, and it will be understood that the capacities for the third-level mapping table and the fourth-level mapping table may also be adjusted. The specific adjustment method can be adjusted according to the mapping strategy.

[0056] In some examples, when the random read range is less than a certain value, the memory controller 320 may also reduce the capacity for storing different-level mapping tables in the buffer 321 (such as reducing the capacity for at least one of the second-level mapping table or the third-level mapping table), allocate additional buffer capacity for executing other tasks of the firmware, and improve the utilization rate of the buffer. In scenarios such as a narrow range of sequential read operations or random read operations, it will be understood that the memory controller 320 may not need to adjust the capacity for storing different-level mapping tables in the buffer 321.

[0057] In this way, in one aspect, when a wide range of random read operations are performed, the memory controller 320 may increase the capacity for storing at least one level of the mapping table in the buffer 321 (such as increasing the capacity for the second level of the mapping table) in order to improve the buffer hit rate of the mapping table. Thereby, the number of updates of the mapping table from the memory device 310 to the buffer 321 is reduced, the time overhead for searching the corresponding mapping table is reduced, and the performance of a wide range of random reads in the memory system 300 is improved. In another aspect, dynamically adjusting the capacity for storing mapping tables of various levels in the buffer 321 may improve the utilization rate of the buffer 321 and may hardly affect other task schedulings, thus reducing problems such as buffer resource contention.

[0058] In some examples, the memory system 300 includes a DRAM - less memory system, and the buffer 321 includes a static random - access memory.

[0059] In the examples of the present disclosure, the memory system 300 may not include DRAM, that is, it may be a DRAM - less memory system. In some examples, the buffer 321 in the memory controller 320 may employ SRAM instead of DRAM. Compared with DRAM, SRAM has a higher access speed and lower power consumption, which is beneficial to improving the performance of the memory system 300.

[0060] In some examples, the memory system 300 includes flash storage, and the memory device 310 includes NAND memory.

[0061] In some examples of the present disclosure, the memory system 300 may be UFS, and the memory device 310 therein may include NAND memory. UFS has the characteristics of small size, high performance, and low power consumption, which are convenient for applications in embedded devices and mobile devices. Compared with NOR flash memory, NAND flash memory has a higher storage density, a larger number of erasable times, and a lower cost per bit. In some examples, the memory system 300 may also include an SSD, an SD card, a CF card, etc.

[0062] In some examples, the multi-level mapping table includes a first-level mapping table, a second-level mapping table,..., an N-level mapping table, where N is an integer greater than or equal to 3. The physical address of the next-level mapping table is stored in the previous-level mapping table, the physical address of the data is stored in the last-level mapping table, and the buffer stores the entirety of at least the first M levels of mapping tables (where M is greater than or equal to 1 and less than N) and a portion of each of the subsequent N - M levels of mapping tables. In some specific examples, as shown in FIG. 4, the multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table. The physical address of the second-level mapping table is stored in the first-level mapping table, the physical address of the third-level mapping table is stored in the second-level mapping table, the physical address of the data is stored in the third-level mapping table, and the entirety of the first-level mapping table, a portion of the second-level mapping table, and a portion of the third-level mapping table are stored in the buffer.

[0063] In this example of the present disclosure, since the capacity occupied by the first-level mapping table is small (for example, the size of the first-level mapping table corresponding to a memory device with a storage capacity of 128G is only 128 bytes), the entire first-level mapping table may be loaded into the buffer. On the other hand, the second-level mapping table and the third-level mapping table in the memory device are partially loaded into the buffer to reduce problems such as resource competition in the buffer.

[0064] For the sake of simplicity of understanding, the following multi-level mapping table is described by taking the three-level mapping table described above as an example. In some examples, the memory controller 320 is configured to increase the ratio of the capacity for storing the second-level mapping table in the buffer 321 to the total capacity for storing the second-level mapping table and the third-level mapping table in the buffer 321 in response to the random read range being greater than or equal to a preset value.

[0065] In an example of the present disclosure, the memory controller 320 may detect the random read range using the firmware stored in the memory device 310, and when the random read range is greater than a preset value, increase the ratio of the capacity for storing the second-level mapping table in the buffer 321 to the total capacity for storing the second-level mapping table and the third-level mapping table in the buffer 321. That is, here, on the premise of not increasing the total capacity for storing the second-level mapping table and the third-level mapping table in the buffer 321 and keeping the total capacity for storing the second-level mapping table and the third-level mapping table in the buffer 321 unchanged, the capacity for the second-level mapping table may be increased and the capacity for the third-level mapping table may be decreased.

[0066] In some examples, as shown in Table 2, using 1000 random reads in the range of 128G (the memory data capacity of the memory device is 128G, for example, full disk random reads) as an example, compared with the example corresponding to Table 1, the memory controller reduces the capacity for the third-level mapping table in the buffer from 1024K to 904K, and allocates the reduced 120K capacity for the third-level mapping table to the second-level mapping table, that is, the capacity for the second-level mapping table in the buffer is increased from the original 8K to 128K. In this way, random reads within the range of 128G do not update the second-level mapping table loaded into the buffer, that is, the number of reads for additionally loading the second-level mapping table is 0, and the increase in the number of reads for additionally loading the third-level mapping table is small, and finally it is guaranteed that the total number of reads is reduced from 2931 to 1994, which greatly improves the random read performance of the memory system.

[0067]

Table 2

[0068] In some examples, the memory controller 320 is configured to obtain the target buffer hit rate of the mapping table, detect the current buffer hit rate of the mapping table, and in response to the current buffer hit rate of the mapping table being lower than the target buffer hit rate of the mapping table, increase the ratio of the capacity for storing the second-level mapping table in the buffer 321 to the total capacity for storing the second-level mapping table and the third-level mapping table in the buffer 321 until the current buffer hit rate of the mapping table is greater than or equal to the target buffer hit rate of the mapping table, in response to the random read range being greater than or equal to a preset value.

[0069] In some examples, the memory controller 320 is configured to determine a target buffer hit rate of the mapping table according to a random read range.

[0070] In some examples, in response to the random read range being less than a preset value, the memory controller 320 is configured to keep the capacity for storing the second-level mapping table in the buffer 321 and the capacity for storing the third-level mapping table in the buffer 321 unchanged.

[0071] In an example of the present disclosure, referring to FIG. 7, the memory controller 320 may detect a random read range using the firmware stored in the memory device 310. When the random read range is greater than or equal to a preset value, the memory controller 320 may calculate a target buffer hit rate of the mapping table according to the random read range and through the firmware. The memory controller 320 may detect the current buffer hit rate of the mapping table. When the current buffer hit rate of the mapping table is lower than the target buffer hit rate of the mapping table, the memory controller 320 adjusts the capacity for storing the second-level mapping table in the buffer 321 and the capacity for storing the third-level mapping table in the buffer 321. When the current buffer hit rate of the mapping table is greater than or equal to the target buffer hit rate of the mapping table, the memory controller 320 stops adjusting the capacity for storing different levels of mapping tables in the buffer 321. In addition, when the random read range is smaller than a preset value, the memory controller 320 may keep the capacity for storing the second-level mapping table and the third-level mapping table in the buffer 321 unchanged.

[0072] In this way, the memory controller 320 can adjust multiple times the capacity for storing the second-level mapping table in the buffer 321 and the capacity for storing the third-level mapping table in the buffer 321 until the current buffer hit rate of the mapping table becomes equal to or higher than the target buffer hit rate of the mapping table. By dynamically adjusting multiple times the capacities of the mapping tables at different levels in the buffer 321, the target buffer hit rate of the mapping table can be accurately achieved without greatly exceeding the target buffer hit rate of the mapping table. Therefore, the limited buffer resources can be fully utilized, reducing the buffer resource contention while improving the performance of a wide range of random reads in the memory system.

[0073] In some examples, the memory controller 320 is configured to increase the overall capacity for storing the second-level mapping table and the third-level mapping table in the buffer 321 in response to the random read range being equal to or greater than a preset value.

[0074] In some examples of the present disclosure, when the random read range is greater than or equal to a preset value, the method by which the memory controller 320 adjusts the capacity for storing the second-level mapping table in the buffer 321 and the capacity for storing the third-level mapping table in the buffer 321 is not limited, but includes the following. One method is that, on the premise of keeping the total capacity for the second-level mapping table and the third-level mapping table in the buffer 321 unchanged, the memory controller 320 increases the capacity for the second-level mapping table and decreases the capacity for the third-level mapping table. Another method is that the memory controller 320 increases the capacity for at least one of the second-level mapping table and the third-level mapping table in the buffer 321 so that the total capacity for the second-level mapping table and the third-level mapping table increases. Here, increasing the total capacity for storing the second-level mapping table and the third-level mapping table in the buffer 321 can also be implemented by increasing the capacity for one of the second-level mapping table and the third-level mapping table and decreasing the capacity for the other.

[0075] It can be understood that increasing the total capacity for storing the second-level mapping table and the third-level mapping table in the buffer 321 can further improve the buffer hit rate of the mapping table and improve the performance of a wider range of random reads in the memory system.

[0076] In some examples, the memory controller 320 is configured to determine the difference between the current buffer hit rate of the mapping table and the target buffer hit rate of the mapping table, and according to the difference, determine the increase amount of the capacity for storing the second-level mapping table in the buffer 321 in this adjustment, and there is a positive correlation between the increase amount and the difference.

[0077] In some examples of the present disclosure, the memory controller 320 calculates the target buffer hit rate of the mapping table using the firmware stored in the memory device 310 and according to a random read range, whereby the difference between the current buffer hit rate of the mapping table and the target buffer hit rate of the mapping table can be calculated. Next, the memory controller 320 may determine an increase amount of the capacity for storing the second-level mapping table in the buffer 321 according to the difference. The greater the difference, the greater the increase amount of the capacity for the second-level mapping table in this adjustment. The smaller the difference, the smaller the increase amount of the capacity for the second-level mapping table in this adjustment.

[0078] In this way, when the difference is large, the increase amount in this adjustment is large (i.e., the width of a single adjustment is large), thereby reducing the number of times of adjusting the capacity for the multi-level mapping table in the buffer 321 aimed at achieving the target buffer hit rate of the mapping table, accelerating the adjustment of the mapping table buffer capacity, and improving the performance of the memory system. When the difference is small, the increase amount in this adjustment is small in order to accurately achieve the target buffer hit rate of the mapping table, so that the limited buffer resources can be fully utilized.

[0079] In some examples, the memory controller 320 is configured to stop adjusting the capacity for storing the mapping tables at different levels in the buffer 321 in response to the current buffer hit rate of the mapping table being less than the target buffer hit rate of the mapping table and the ratio of the current capacity for storing the second-level mapping table in the buffer 321 to the total capacity for storing the second-level mapping table and the third-level mapping table reaching a preset ratio.

[0080] In some examples of the present disclosure, the memory controller 320 may also set a pre-set ratio, that is, a threshold of the current capacity ratio for storing the second-level mapping table in the buffer 321 with respect to the overall capacity for storing the second-level mapping table and the third-level mapping table. When the current buffer hit rate of the mapping table is still less than the target buffer hit rate of the mapping table, and the capacity ratio of the second-level mapping table in the buffer 321 reaches the pre-set ratio, the memory controller 320 may stop adjusting the capacity for storing mapping tables of different levels in the buffer 321. In this way, the capacity for the second-level mapping table in the buffer 321 does not become too large, thereby preventing the buffer resources required by the third-level mapping table from being occupied. The aforementioned pre-set ratio may be determined according to the proportional relationship between the overall capacity for the second-level mapping table and the overall capacity for the third-level mapping table in the memory device 310.

[0081] As shown in FIG. 8, one example of the present disclosure includes a negative feedback dynamic adjustment mechanism based on the current buffer hit rate of the mapping table. The input is the target buffer hit rate Y_In of the mapping table of the second-level mapping table and the third-level mapping table, the output is the current buffer hit rate Y_out of the mapping table of the second-level mapping table and the third-level mapping table, and X represents the comparison node of Y_in and Y_out. Based on the current dynamic L2P mapping table buffer algorithm, according to the formula Y_out = (Y_in - Y_out), with K as the adjustment coefficient, in order to achieve the target buffer hit rate of the mapping table, the current buffer hit rate of the mapping table may be dynamically adjusted, thereby improving the performance of a wide range of random reads in the memory system.

[0082] In some examples, the memory controller 320 is configured to determine a preset value according to the current capacity for storing the second-level mapping table in the buffer 321 and in combination with the mapping rules for the mapping tables at various levels.

[0083] In an example of the present disclosure, the memory controller 320 may calculate a preset value corresponding to a random read range by using the firmware stored in the memory device 310 and according to the capacity for storing the second-level mapping table in the current buffer 321 and the mapping rules for the mapping tables at various levels. Here, the mapping rules may refer to a proportional relationship regarding the capacity between adjacent-level mapping tables and between the data stored in the memory device and the lowest-level mapping table.

[0084] In some examples, taking the three-level mapping method as an example, the mapping rules may be that the size of the third-level mapping table is 1 / 1024 of the data storage capacity in the corresponding memory device, the size of the second-level mapping table is 1 / 1024 of the size of the corresponding third-level mapping table, and the size of the first-level mapping table is 1 / 1024 of the size of the corresponding second-level mapping table. That is, when the capacity for storing the second-level mapping table in the buffer 321 is 8K, it may be guaranteed that random reads within the range of 8G do not update the second-level mapping table in the buffer 321. That is, the preset value may be set to 8G at this time. When the random read range exceeds 8G, additional reads are performed to reload the second-level mapping table from the memory device. At this time, the capacity for storing the multi-level mapping table in the buffer 321 may be adjusted to improve the random read performance of the memory system.

[0085] In some examples, the multi-level mapping table includes a first-level mapping table and a second-level mapping table. The physical address of the second-level mapping table is stored in the first-level mapping table, the physical address of the data is stored in the second-level mapping table, a part of the first-level mapping table and a part of the second-level mapping table are stored in buffer 321, and the memory controller 320 is configured to increase the ratio of the capacity for storing the first-level mapping table in buffer 321 to the total capacity for storing the first-level mapping table and the second-level mapping table in buffer 321 in response to the random read range being equal to or greater than a preset value.

[0086] In an example of the present disclosure, the multi-level mapping table may be two-level, that is, it only includes a first-level mapping table and a second-level mapping table. In this way, when the random read range is equal to or greater than a preset value, the memory controller 320 may increase the ratio of the capacity for storing the first-level mapping table in buffer 321 to the total capacity for storing the first-level mapping table and the second-level mapping table in buffer 321 in order to improve the buffer hit rate of the mapping table, thereby reducing the number of times of updating the mapping table from the memory device 310 to buffer 321, reducing the time overhead for searching for the corresponding mapping table, and improving the performance of a wide range of random reads in the memory system 300.

[0087] Referring to FIG. 3, an example of the present disclosure provides a memory controller 320 including a buffer 321 and a control component 323. The buffer 321 is configured to store a portion of a multi-level mapping table in the memory device 310, and the multi-level mapping table is configured to perform a mapping from a logical address to a physical address. The control component 323 is configured to perform a random read operation on the data stored in the memory device 310 and adjust the capacity for storing different levels of mapping tables in the buffer 321 in response to satisfying a preset condition for a random read range corresponding to the random read operation.

[0088] In some examples, the memory controller 320 further includes a flash translation layer 322 connecting the control component 323 and the buffer 321. The flash translation layer 322 is configured to convert a logical address into a corresponding physical address according to the mapping information in the multi-level mapping table stored in the buffer 321.

[0089] In some examples, the control component 323 is further configured to receive instructions from the host 400 for performing read, write, and erase operations on the memory device 310. The buffer 321 is further configured to temporarily store data transferred between the host 400 and the memory device 310. The memory controller 320 further includes an encoder / decoder 324 for encoding and decoding data transferred between the host 400 and the memory device 310.

[0090] In an example of the present disclosure, the memory controller 320 may include the buffer 321, the flash translation layer 322, the control component 323, and the encoder / decoder 324.

[0091] The memory controller 320 may include one or more buffers 321, the buffer 321 may include a high-speed buffer (such as SRAM), and since the buffer 321 can be applied to store any appropriate information including the L2P mapping table, software code, commands, and firmware, the memory controller 320 can execute various commands and operations quickly. The flash translation layer 322 may be implemented using a allocated portion of the circuitry of the memory controller 320 and control software, and is configured to convert logical addresses to physical addresses.

[0092] The control component 323 may include any appropriate integrated circuit (for example, one or more processors), which receives instructions from the host 400 through the host interface 301 and communicates at least one of commands or data with one or more memory devices 310 via the interface 302 to perform read operations, program operations, and erase operations on the memory device 310. For example, the control component 323 receives a request from the host 400 to access the flash memory medium. The control component 323 may also communicate with other components of the memory controller 320 and be configured to control these components. For example, the control component 323 may instruct the flash translation layer 322 to scan the buffer 321 to obtain mapping information and may transmit / receive address mapping information from the flash translation layer 322. The control component 323 may also communicate with the encoder / decoder 324 and other appropriate components of the memory controller 320.

[0093] The encoder / decoder 324 may provide encoding and decoding of data processed by the memory controller 320. The encoder / decoder 324 may also generate and store error correction codes (ECC) and metadata, and the encoder / decoder 324 may be configured to detect and correct errors in the data stored by the memory device.

[0094] In some examples, the multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table. The physical address of the second-level mapping table is stored in the first-level mapping table, the physical address of the third-level mapping table is stored in the second-level mapping table, the physical address of the data is stored in the third-level mapping table, and the whole of the first-level mapping table, a part of the second-level mapping table, and a part of the third-level mapping table are stored in buffer 321. When the random read range is equal to or greater than a preset value, control component 323 is configured to increase the ratio of the capacity for storing the second-level mapping table in buffer 321 to the total capacity for storing the second-level mapping table and the third-level mapping table in buffer 321.

[0095] In some examples, memory control 323 is configured to obtain the target buffer hit rate of the mapping table, detect the current buffer hit rate of the mapping table, and when the current buffer hit rate of the mapping table is lower than the target buffer hit rate of the mapping table, increase the ratio of the capacity for storing the second-level mapping table in buffer 321 to the total capacity for storing the second-level mapping table and the third-level mapping table in buffer 321 until the current buffer hit rate of the mapping table is equal to or greater than the target buffer hit rate of the mapping table.

[0096] In some examples, memory control 323 is configured to determine the difference between the current buffer hit rate of the mapping table and the target buffer hit rate of the mapping table, and determine the amount of increase in the capacity for storing the second-level mapping table in buffer 321 in this adjustment according to this difference, and there is a positive correlation between the amount of increase and the difference.

[0097] In some examples, the memory control 323 is configured to stop adjusting the capacity for storing mapping tables of different levels in buffer 321 when the current buffer hit rate of the mapping table is lower than the target buffer hit rate of the mapping table and when the ratio of the current capacity for storing the second-level mapping table in buffer 321 to the total capacity for storing the second-level mapping table and the third-level mapping table in buffer 321 reaches a preset ratio.

[0098] In some examples, the memory control 323 is configured to determine the target buffer hit rate of the mapping table according to a random read range.

[0099] In some examples, the memory control 323 is configured to keep the capacity for storing the second-level mapping table in buffer 321 and the capacity for storing the third-level mapping table in buffer 321 unchanged when the random read range is less than a preset value.

[0100] In some examples, the memory control 323 is configured to determine a preset value according to the current capacity for storing the second-level mapping table in buffer 321 and in combination with mapping rules for mapping tables of various levels.

[0101] In some examples, the memory control 323 is configured to increase the total capacity for storing the second-level mapping table and the third-level mapping in buffer 321 when the random read range is greater than or equal to a preset value.

[0102] Referring to FIG. 3, an example of the present disclosure further provides another memory system. The memory system 300 includes at least one non-volatile memory device 310 and a memory controller 320 coupled to the at least one non-volatile memory device 310. The multi-level mapping table is stored in the memory device 310 and is for implementing the mapping from a logical address to a physical address. The memory controller 320 includes a buffer 321, and a part of the multi-level mapping table is stored in the buffer 321. The memory controller 320 is configured to perform a random read operation on the data stored in the memory device 310, and in response to the random read range satisfying a preset condition (for example, the random read range is larger than a certain value), adjust the amount of capacity for different levels of the mapping table in one load from the memory device 310 to the buffer 321.

[0103] In this example of the present disclosure, the memory controller 320 issues a mapping table load command when the random read range satisfies a preset condition (for example, the random read range is larger than a certain value), and is configured to adjust the amount of capacity for different levels of the mapping table in one load from the memory device 310 to the buffer 321. "One load" refers to one read operation of the mapping table.

[0104] Taking the three-level mapping method as an example, without increasing the overall capacity for the second-level mapping table and the third-level mapping table in one load, the memory controller 320 can increase the ratio of the capacity for the second-level mapping table to the overall capacity for the second-level mapping table and the third-level mapping table in one load of the mapping table. In this way, the capacity for storing the second-level mapping table in the buffer 321 increases, but the overall capacity for storing the multi-level mapping table in the buffer 321 remains unchanged. Thereby, the buffer hit rate of the mapping table is improved, the number of additional loads of the mapping table from the memory device 310 to the buffer 321 is reduced, the time overhead for searching the corresponding mapping table is reduced, and the performance of a wide range of random reads in the memory system 300 is improved. In addition, dynamically adjusting the amount of capacity for the mapping tables of different levels in one load from the memory device 310 to the buffer 321 can improve the utilization rate of the buffer 321 and hardly affect other task schedulings, so problems such as buffer resource competition can be reduced.

[0105] If there is at least one random read operation among a plurality of random read operations that satisfies the condition that the random read range is preset, the memory controller 320 adjusts the amount of capacity for the mapping tables of different levels in one load from the memory device 310 to the buffer 321, so it can be understood that the capacity for the second-level mapping table loaded by at least one random read operation is different from the capacity for the second-level mapping table loaded by other random read operations (here, it is also possible that the capacity for the third-level mapping table loaded by at least one random read operation is different from its capacity at other times).

[0106] In some examples, the memory controller 320 may load a multi-level mapping table corresponding to a random read operation into the buffer 321 during a pre-set number of reads, that is, in order to achieve a 100% buffer hit rate of the mapping table, it is not limited to one load of the multi-level mapping table, and there is no read for loading the L2P mapping table except for the pre-set number of reads. Here, the memory controller 320 may calculate the pre-set number of reads through firmware and according to the buffer hit rate of the target mapping table, and the buffer hit rate of the target mapping table is less than 100%.

[0107] Examples of the present disclosure also provide a method of operating a memory system, the memory system including at least one non-volatile memory device and a memory controller coupled to the at least one non-volatile memory device, a multi-level mapping table being stored in the memory device, the multi-level mapping table being for performing a mapping from a logical address to a physical address, the memory controller including a buffer, a portion of the multi-level mapping table being stored in the buffer, the method including the steps of performing a random read operation on data stored in the memory device and adjusting a capacity for storing different levels of mapping tables in the buffer in response to a random read range corresponding to the random read operation satisfying pre-set conditions.

[0108] In some examples, the multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table. The physical address of the second-level mapping table is stored in the first-level mapping table, the physical address of the third-level mapping table is stored in the second-level mapping table, the physical address of the data is stored in the third-level mapping table, and the whole of the first-level mapping table, a part of the second-level mapping table, and a part of the third-level mapping table are stored in a buffer. In response to the random read range meeting the preset conditions for the random read operation, the step of adjusting the capacity for storing different levels of mapping tables in the buffer includes increasing the ratio of the capacity for storing the second-level mapping table in the buffer to the total capacity for storing the second-level mapping table and the third-level mapping table in the buffer in response to the random read range being greater than or equal to a preset value.

[0109] In some examples, the step of increasing the ratio of the capacity for storing the second-level mapping table in the buffer to the total capacity for storing the second-level mapping table and the third-level mapping table in the buffer in response to the random read range being greater than or equal to a preset value includes obtaining a target buffer hit rate of the mapping table in response to the random read range being greater than or equal to a preset value, detecting the current buffer hit rate of the mapping table, and increasing the ratio of the capacity for storing the second-level mapping table in the buffer to the total capacity for storing the second-level mapping table and the third-level mapping table in the buffer until the current buffer hit rate of the mapping table is greater than or equal to the target buffer hit rate of the mapping table in response to the current buffer hit rate of the mapping table being lower than the target buffer hit rate of the mapping table.

[0110] In some examples, referring to FIG. 7, the method of operating the memory system provided in the present disclosure may include the following operations.

[0111] S101. Detect, by the firmware, the random read range of the random read operation.

[0112] S102. Determine whether the random read range is greater than or equal to a preset value, and if so, execute operation S103.

[0113] S103. Obtain the target buffer hit rate of the mapping table.

[0114] S104. Detect the current buffer hit rate of the mapping table, determine whether the current buffer hit rate of the mapping table is greater than or equal to the target buffer hit rate of the mapping table, and if not, execute operation S105.

[0115] S105. Adjust the capacity for storing different levels of the mapping table in the buffer, and then re-execute operation S104.

[0116] The detailed method of operating the memory system can be understood by referring to the specific examples in the foregoing examples, and thus will not be repeated here.

[0117] In some examples, the method further includes determining the difference between the current buffer hit rate of the mapping table and the target buffer hit rate of the mapping table, and determining, according to this difference, the increase amount of the capacity for storing the second-level mapping table in this adjustment, and there is a positive correlation between the increase amount and this difference.

[0118] In some examples, the method further includes stopping adjusting the capacity for storing mapping tables of different levels in response to the current buffer hit rate of the mapping table being lower than the target buffer hit rate of the mapping table and the ratio of the current capacity for storing the second-level mapping table to the overall capacity for storing the second-level mapping table and the third-level mapping table in the buffer reaching a preset ratio.

[0119] One example of the present disclosure provides a storage medium storing executable instructions that, when executed by a processor, perform the operations of any one of the methods of the examples described above.

[0120] In an example of the present disclosure, the storage medium may include a NAND flash memory in the memory device 310, the executable instructions are stored in the storage medium, and the executable instructions may include the firmware of the examples described above. In this way, the control component 323 including the processor in the memory controller 320 may execute the executable instructions in the storage medium to perform the operations of any one of the methods of the examples described above.

[0121] It should be understood that references to "one example" or "an example" throughout the description mean that a particular feature, structure, or characteristic of the example is included in at least one example of the present disclosure. Thus, the appearances of "in one example" or "in an example" in various places throughout the description are not necessarily referring to the same example. Further, these particular features, structures, or characteristics may be combined in any suitable manner in one or more examples. In various examples of the present disclosure, the sequence numbers of the processes described above do not mean the execution order, and the execution order of each process should be determined by its function and internal logic and should not be any constraint on the exemplary processes of the examples of the present disclosure. The serial numbers of the examples of the present disclosure described above are for illustrative purposes only and do not represent the advantages and disadvantages of the examples.

[0122] The above is only an example of the present disclosure, which does not limit the scope of the present disclosure. Under the inventive concept of the present disclosure, any equivalent structural transformation performed by using the content of the present disclosure and the accompanying drawings, or direct / indirect applications in other related technical fields, are included in the scope of the claims of the present disclosure.

Industrial Applicability

[0123] In the memory system provided by an example of the present disclosure, the memory device stores a multi-level mapping table, and the buffer of the memory controller is for storing a part of the multi-level mapping table. When a randomly read range meets a preset condition, the memory controller adjusts the capacity for storing different levels of mapping tables in the buffer. In this way, in one aspect, when a wide range of random read operations are executed, the memory controller may increase the capacity for storing at least one level of the mapping table in the buffer to improve the buffer hit rate of the mapping table. Thereby, the number of times of updating the mapping table from the memory device to the buffer is reduced, the time overhead for searching the corresponding mapping table is reduced, and the performance of a wide range of random reads in the memory system is improved. In another aspect, dynamically adjusting the capacity for storing different levels of mapping tables in the buffer may improve the utilization rate of the buffer and may hardly affect other task schedulings, thus reducing problems such as buffer resource competition.

Description of Reference Numerals

[0124] 102 Memory system 104 Memory device 106 Memory controller 108 Host 202 Memory card 206 SSD 208 SSD connector 300 Memory system 301 Host Interface 302 Interface 310 Memory Device 320 Memory Controller 321 Buffer 322 Flash Translation Layer 323 Control Component 324 Encoder / Decoder 400 Host

Claims

1. At least one non-volatile memory device in which a multi-level mapping table is stored, the multi-level mapping table being for performing mapping from a logical address to a physical address, and at least one non-volatile memory device, A memory controller coupled to the at least one non-volatile memory device and including a buffer in which a part of the multi-level mapping table is stored Including, the memory controller Performing a random read operation on the data stored in the memory device; Adjusting a capacity for storing different-level mapping tables in the buffer in response to a random read range corresponding to the random read operation satisfying a preset condition A memory system configured to perform.

2. The multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table, The physical address of the second-level mapping table is stored in the first-level mapping table, the physical address of the third-level mapping table is stored in the second-level mapping table, and the physical address of the data is stored in the third-level mapping table, The memory system according to claim 1, wherein the whole of the first-level mapping table, a part of the second-level mapping table, and a part of the third-level mapping table are stored in the buffer.

3. The memory controller Configured to increase a ratio of a capacity for storing the second-level mapping table in the buffer to an overall capacity for storing the second-level mapping table and the third-level mapping table in the buffer in response to the random read range being equal to or greater than a preset value, the memory system according to claim 2.

4. The memory controller Obtaining a target buffer hit rate of the mapping table in response to the random read range being equal to or greater than the preset value; Detecting a current buffer hit rate of the mapping table; In response to the current buffer hit rate of the mapping table being lower than the target buffer hit rate of the mapping table, increasing the ratio of the capacity for storing the second-level mapping table in the buffer to the overall capacity for storing the second-level mapping table and the third-level mapping table in the buffer until the current buffer hit rate of the mapping table becomes equal to or higher than the target buffer hit rate of the mapping table The memory system according to claim 3, configured to perform the above. **Claim 5** The memory controller determines the difference between the current buffer hit rate of the mapping table and the target buffer hit rate of the mapping table and determines an increase amount of the capacity for storing the second-level mapping table in the buffer in this adjustment according to the difference and is configured to perform the above The memory system according to claim 4, wherein there is a positive correlation between the increase amount and the difference **Claim 6** The memory controller is configured to stop adjusting the capacity for storing mapping tables at different levels in the buffer in response to the current buffer hit rate of the mapping table being lower than the target buffer hit rate of the mapping table and the ratio of the current capacity for storing the second-level mapping table in the buffer to the overall capacity for storing the second-level mapping table and the third-level mapping table in the buffer reaching a preset ratio. The memory system according to claim 4 **Claim 7** The memory controller is configured to determine the target buffer hit rate of the mapping table according to the random read range. The memory system according to claim 4 **Claim 8** The memory controller is configured to keep the capacity for storing the second-level mapping table in the buffer and the capacity for storing the third-level mapping table in the buffer unchanged in response to the random read range being less than the preset value. The memory system according to claim 3 **Claim 9** The memory controller The memory system according to claim 3, configured to determine the preset value according to the current capacity for storing the second-level mapping table in the buffer in combination with mapping rules for mapping tables of various levels.

10. The memory controller The memory system according to claim 2, configured to increase the overall capacity for storing the second-level mapping table and the third-level mapping table in the buffer in response to the random read range being equal to or greater than a preset value.

11. The multi-level mapping table includes a first-level mapping table and a second-level mapping table, The physical address of the second-level mapping table is stored in the first-level mapping table, the physical address of the data is stored in the second-level mapping table, and a part of the first-level mapping table and a part of the second-level mapping table are stored in the buffer, The memory controller The memory system according to claim 1, configured to increase the ratio of the capacity for storing the first-level mapping table in the buffer to the overall capacity for storing the first-level mapping table and the second-level mapping table in the buffer in response to the random read range being equal to or greater than a preset value. in the buffer.

12. The memory system according to claim 1, wherein the memory system includes a DRAM-less memory system and the buffer includes a static random access memory.

13. The memory system according to claim 1, wherein the memory system includes a flash storage and the memory device includes a NAND memory.

14. A method of operating a memory system, the memory system including at least one non-volatile memory device in which a multi-level mapping table is stored, the multi-level mapping table being for implementing mapping from a logical address to a physical address. A memory controller coupled to the at least one non-volatile memory device and including a buffer in which a portion of the multi-level mapping table is stored and including, the method comprising executing a random read operation on data stored in the memory device and adjusting a capacity for storing different-level mapping tables in the buffer in response to a random read range corresponding to the random read operation satisfying a preset condition The method includes

15. The multi-level mapping table includes a first-level mapping table, a second-level mapping table, and a third-level mapping table wherein a physical address of the second-level mapping table is stored in the first-level mapping table, a physical address of the third-level mapping table is stored in the second-level mapping table, and a physical address of data is stored in the third-level mapping table wherein the whole of the first-level mapping table, a portion of the second-level mapping table, and a portion of the third-level mapping table are stored in the buffer and the step of adjusting the capacity for storing different-level mapping tables in the buffer in response to a random read range corresponding to the random read operation satisfying a preset condition includes increasing a ratio of the capacity for storing the second-level mapping table in the buffer to the whole capacity for storing the second-level mapping table and the third-level mapping table in the buffer in response to the random read range being equal to or greater than a preset value, according to the method of claim 14

16. The step of increasing a ratio of the capacity for storing the second-level mapping table in the buffer to the whole capacity for storing the second-level mapping table and the third-level mapping table in the buffer in response to the random read range being equal to or greater than a preset value includes obtaining a target buffer hit rate of a mapping table in response to the random read range being equal to or greater than the preset value Detecting the current buffer hit rate of the mapping table; In response to the current buffer hit rate of the mapping table being lower than the target buffer hit rate of the mapping table, increasing the ratio of the capacity for storing the second-level mapping table to the total capacity for storing the second-level mapping table and the third-level mapping table in the buffer until the current buffer hit rate of the mapping table is equal to or higher than the target buffer hit rate of the mapping table; The method according to claim 15, comprising:

17. Determining the difference between the current buffer hit rate of the mapping table and the target buffer hit rate of the mapping table; Determining an increase amount of the capacity for storing the second-level mapping table in the buffer in this adjustment according to the difference; further comprising: The method according to claim 16, wherein there is a positive correlation between the increase amount and the difference.

18. The method according to claim 16, further comprising stopping adjusting the capacity for storing mapping tables of different levels in the buffer in response to the current buffer hit rate of the mapping table being lower than the target buffer hit rate of the mapping table and the ratio of the current capacity for storing the second-level mapping table in the buffer to the total capacity for storing the second-level mapping table and the third-level mapping table in the buffer reaching a preset ratio.

19. A storage medium storing executable instructions that, when executed by a processor, perform the operations of the method according to any one of claims 14 to 18.

20. A buffer, configured to store a part of a multi-level mapping table in a non-volatile memory device, wherein the multi-level mapping table is configured to perform mapping from a logical address to a physical address; and A control component, performing a random read operation on the data stored in the non-volatile memory device; Adjusting the capacity for storing different-level mapping tables in the buffer in response to the random read range corresponding to the random read operation satisfying a preset condition A control component configured to perform A memory controller including

21. Further including a flash translation layer, the flash translation layer connecting the control component and the buffer, Converting the logical address into a corresponding physical address according to the mapping information in the multi-level mapping table stored in the buffer The memory controller according to claim 20, configured as such.

22. The control component is Further configured to receive instructions from a host for performing read, write, and erase operations on the non-volatile memory device And the buffer is Further configured to temporarily store data transferred between the host and the non-volatile memory device And the memory controller is Further including an encoder / decoder for encoding and decoding data transferred between the host and the non-volatile memory device The memory controller according to claim 20, including The memory controller according to claim 20, further including The memory controller according to claim 20, further including an encoder / decoder for encoding and decoding data transferred between the host and the non-volatile memory device

23. At least one non-volatile memory device storing a multi-level mapping table, the multi-level mapping table being for performing mapping from a logical address to a physical address, and A memory controller coupled to the at least one non-volatile memory device and including a buffer storing a part of the multi-level mapping table Including, and the memory controller is Performing a random read operation on the data stored in the memory device, and Adjusting the amount of capacity for storing different-level mapping tables in one-time loading from the memory device to the buffer in response to the random read range corresponding to the random read operation satisfying a preset condition A memory system configured to perform.

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