Memory device, method of operating the same, and memory system

Abstract

In an example of the present disclosure, a memory device, a method of operating the same, and a memory system are provided. The memory device includes a memory cell array and peripheral circuits coupled to the memory cell array. The method of operating the memory device includes receiving a first instruction instructing to write dummy data to a specified location within the memory cell array, generating dummy data to be written in response to the first instruction, and writing the dummy data to be written to the specified location.

Description

Technical Field

[0001] Examples of the present disclosure relate to the field of semiconductor technology, and more particularly, to memory devices, methods of operating the same, and memory systems.

Background Art

[0002] Memory devices and their systems serve as storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) type memory has become the mainstream product in the market due to its high storage density, controllable production cost, suitable programming and erasing speeds, and retention characteristics.

Summary of the Invention

Problems to be Solved by the Invention

[0003] However, due to the increasing demands of people for storage devices, there is still much room for improvement in memory devices and their systems.

Means for Solving the Problems

[0004] Examples of the present disclosure provide a memory device, a method of operating the same, and a memory system.

[0005] In a first aspect, an example of the present disclosure provides a memory device, which includes a memory cell array and peripheral circuits coupled to the memory cell array. The peripheral circuits are configured to receive a first command instructing to write dummy data to a specified location within the memory cell array, generate dummy data to be written in response to the first command, and be configured to write the dummy data to be written to the specified location.

[0006] In one example, the first command is constituted by a set feature command, or the first command includes a first flag set on a reserved field of a write command.

[0007] In one example, when the first command is constituted by a set feature command, the command where the first command is arranged does not include dummy data to be written. When the first command includes a first flag set on a reserved field of a write command, the peripheral circuit is configured to directly generate dummy data to be written without receiving data information included in the write command in response to the first command.

[0008] In one example, the peripheral circuit randomly generates dummy data to be written, or or is configured to generate dummy data to be written in combination with a preset algorithm according to data stored in a location adjacent to the specified location.

[0009] In one example, the preset algorithm relates to the coupling effect between memory cells in a memory cell array.

[0010] In one example, the memory cell array includes a plurality of memory blocks, and each of the memory blocks includes a plurality of valid memory pages and a plurality of dummy memory pages. The specified location includes at least one of the plurality of memory blocks, at least one of the valid memory pages in the erased state in one of the memory blocks, and at least one of the dummy memory pages in one of the memory blocks. of which one is included.

[0011] In one example, the specified location includes at least one valid memory page in an erased state among the memory blocks, and the memory pages adjacent to the specified location are in a programmed state.

[0012] In one example, the peripheral circuit receives a second instruction indicating to perform a read operation on data in the memory cell array, and in response to the second instruction, is further configured to return the data to be read, and when the data to be read includes dummy data, a second flag is set on a reserved field of the frame header of the returned data frame, and the second flag indicates that the read data includes dummy data.

[0013] In one example, the peripheral circuit after writing dummy data to be written to the specified location, saves the specified location, before returning the data to be read, checks whether the address corresponding to the data to be read is within the address range corresponding to the saved specified location, and when the address corresponding to the data to be read is within the address range corresponding to the saved specified location, is further configured to determine that the data to be read includes dummy data.

[0014] On the other hand, one example of the present disclosure provides a memory system, which includes one or more memory devices as described in the foregoing examples of the present disclosure, and a memory controller coupled to the memory device and configured to control the memory device.

[0015] In one example, the memory system includes a solid state disk.

[0016] In yet another aspect, an example of the present disclosure provides a memory system, which includes at least one memory device and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array. The memory controller is configured to send a first command, which includes a first instruction and a plurality of address instructions. The first instruction instructs to write dummy data to a specified location corresponding to the plurality of address instructions. The peripheral circuitry within the memory device is configured to receive the first command, generate dummy data to be written in response to the first command, and write the dummy data to be written to the specified locations corresponding to the plurality of address instructions.

[0017] In one example, the memory controller is configured to send a second command, which includes a second instruction. The second instruction instructs to perform a read operation on the data within the memory cell array. The peripheral circuitry is configured to receive the second instruction and, in response to the second instruction, return the data to be read. When the data to be read includes dummy data, a second flag is set on a reserved field of the frame header of the returned data frame. The second flag indicates that the read data includes dummy data. The memory controller is further configured to receive the returned data to be read and, when the returned data frame includes the second flag, stop receiving the remaining data frames or not perform a decoding operation on the returned data to be read.

[0018] In one example, the memory controller is configured to send a second command, which includes a second instruction. The second instruction instructs to perform a read operation on the data within the memory cell array. The peripheral circuit is configured to receive a second instruction and, in response to the second instruction, return data to be read, and the data to be read includes dummy data. The memory controller is further configured to receive the data to be read that is returned and discard the data to be read when decoding of the data to be read that is returned fails.

[0019] In yet another aspect, an example of the present disclosure provides a method of operating a memory device, which includes receiving a first instruction that instructs writing dummy data to a specified location in a memory cell array of the memory device, generating, in response to the first instruction, the dummy data to be written, and writing the dummy data to be written to the specified location.

[0020] In one example, the first instruction is constituted by a set feature command, or the first instruction includes a first flag set on a reserved field of a write command.

[0021] In one example, when the first instruction is constituted by a set feature command, the command in which the first instruction is arranged does not include the dummy data to be written. When the first instruction includes a first flag set on a reserved field of a write command, in response to the first instruction, the data information included in the write command is not received, and the dummy data to be written is directly generated.

[0022] In one example, generating the dummy data to be written includes randomly generating the dummy data to be written, or or generating the dummy data to be written in combination with a preset algorithm according to data stored in a location adjacent to the specified location.

[0023] In one example, the method includes: receiving a second instruction that instructs to perform a read operation on data in a memory cell array; and in response to the second instruction, further returning the data to be read, wherein when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header of a returned data frame, and the second flag indicates that the read data includes dummy data.

[0024] In one example, the method includes: writing dummy data to be written to a specified location, and then saving the specified location; before returning the data to be read, checking whether an address corresponding to the data to be read is within an address range corresponding to the saved specified location; and when the address corresponding to the data to be read is within the address range corresponding to the saved specified location, further determining that the data to be read includes dummy data.

[0025] Examples of the present disclosure propose a memory device, an operation method thereof, and a memory system. The operation method of the memory device includes receiving a first instruction that instructs to write dummy data to a specified location in a memory cell array of the memory device, generating the dummy data to be written in response to the first instruction, and writing the dummy data to be written to the specified location. The memory device in the example of the present disclosure generates dummy data based on its own characteristics after receiving the dummy data filled in the specified location, and stores the dummy data in the specified location. In this way, instead of the memory controller transmitting the dummy data to the memory device, the memory device generates the dummy data according to its own characteristics, thereby saving the transmission time of the dummy data, shortening the time for filling the dummy data, and improving the throughput of the memory system.

Brief Description of Drawings

[0026]

Figure 1

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Embodiments for Carrying Out the Invention

[0027] Examples of the present disclosure are described in more detail below with reference to the accompanying drawings. Although examples of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various ways and should not be limited to the "Mode for Carrying Out the Invention" described herein. Rather, these examples are provided so that the present disclosure can be more fully understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0028] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, some technical features well known in the art are not described in order to avoid obscuring the present disclosure; that is, not all features of the actual examples are described herein, and well-known functions and structures are not described in detail.

[0029] In the drawings, the size of layers, regions, elements, and their relative sizes may be exaggerated for clarity. Throughout, like reference numerals refer to like elements.

[0030] When an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it will be understood that this can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. The terms first, second, third, etc. may be used to describe at least one of the various elements, components, regions, layers, or sections, but it will be understood that at least one of these elements, components, regions, layers, or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another. Thus, the first element, component, region, layer, or section described below could equally well be referred to as the second element, component, region, layer, or section without departing from the teachings of the present disclosure. When the second element, component, region, layer, or section is described, this does not indicate that the first element, component, region, layer, or section is present in the present disclosure.

[0031] Spatial terms such as "lower", "below", "under", "directly below", "upper", "above", etc. may be used herein for convenience to describe the relationship between one element or feature and other elements or features shown in the figures. It is understood that spatial relational terms are used in addition to the orientation depicted in the figures and include different orientations of the device in operation. For example, if the device in the figure is turned over, an element or feature described as being "below" or "directly under" or "under" another element or feature will then be oriented "above" the other element or feature. Thus, exemplary terms such as "lower" and "below" can include both upper and lower orientations. The device may be oriented in some other way (rotated 90 degrees or in some other orientation), and the spatial descriptors used herein can be interpreted accordingly.

[0032] The terms used herein are for the purpose of describing only specific examples and should not be regarded as limitations of the present disclosure. As used herein, the singular forms "a (or sometimes none)" and "the / said (or sometimes none)" (the singular articles "a", "an", and "said / the" in the English original) are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that at least one of the phrases "consisting of" or "comprising / including", when used within this specification, identifies the presence of at least one of the recited features, integers, operations, elements, or components, but does not exclude the presence or addition of at least one of one or more other features, integers, operations, elements, components, or groups. As used herein, the phrase "at least one of..." includes any and all combinations of the associated listed items.

[0033] To make the characteristics and technical content of examples of the present disclosure more easily and clearly understood in detail, examples of the present disclosure are described in detail below in conjunction with the accompanying drawings. The accompanying drawings are provided for reference and explanation only and are not intended to limit the examples of the present disclosure.

[0034] Memory devices in examples of the present disclosure include, but are not limited to, 3D NAND-type memory, and for ease of understanding, 3D NAND-type memory is used as an example for illustration.

[0035] FIG. 1 illustrates a block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 1, system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be a processor of an electronic device such as a central processing unit (CPU), or a system-on-chip (SoC) such as an application processor (AP). Host 108 can be configured to transmit or receive data to / from memory device 104.

[0036] According to some examples, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some examples, the memory controller 106 is designed to operate in a low-load environment such as a Secure Digital (SD) card, a CompactFlash (registered trademark) (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones. In some examples, the memory controller 106 is designed to operate in a high-load environment as data storage for mobile devices such as smartphones, tablets, laptop computers, and solid state drives (SSDs) or embedded multimedia cards (eMMCs) for enterprise storage arrays.

[0037] Memory controller 106 may be configured to control the operation of memory device 104, such as read, erase, and program operations. Memory controller 106 may also be configured to manage various functions related to data stored in or to be stored in memory device 104, including but not limited to bad block management, garbage collection, translation from logical address to physical address, wear leveling, etc. In some examples, memory controller 106 is further configured to process error correction codes (ECC) with respect to data read from memory device 104 or written to memory device 104. Any other suitable functions may also be performed by memory controller 106, for example, formatting memory device 104 may also be performed. Memory controller 106 can communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, memory controller 106 can communicate with an external device through at least one of various interface protocols such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI-express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial-ATA protocol, parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0038] Memory controllers 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged in different types of end electronic products. In one example as shown in FIG. 2a, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can further include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG. 1). In another example as shown in FIG. 2b, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can further include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG. 1). In some examples, at least one of the storage capacity or the operating speed of the SSD 206 is greater than that of the memory card 202.

[0039] FIG. 3a is a schematic diagram of the structure of a memory cell array of a 3D NAND type memory. As shown in FIG. 3a, the memory cell array of the 3D NAND type memory consists of several memory cell rows arranged alternately and parallel to the gate insulation structure. The memory cell rows are separated in pairs by the gate insulation structure and the top selective gate isolation structure, and each memory cell row contains a plurality of memory cells. The gate insulation structure may include a first gate insulation structure and a second gate insulation structure. The first gate insulation structure divides the memory cell array into a plurality of memory blocks, and the plurality of second gate insulation structures can divide the memory blocks into a plurality of memory fingers. The top selective gate insulation structure provided in the middle of each memory finger can divide the memory finger into two parts, whereby the memory finger is divided into two memory strings. The memory block shown in FIG. 3a contains six memory strings. In an actual application, the number of memory strings in a memory block is not limited to this.

[0040] In some examples, each memory block may be coupled to a plurality of word lines, and the plurality of memory cells coupled to each individually controlled word line form a memory page. The pages described herein are physical pages. For example, all the memory cells coupled to one word line within each memory string in FIG. 3a form one page.

[0041] Note that the number of memory cell rows between the gate insulation structure and the top selective gate insulation structure shown in FIG. 3a is merely an example and is not used to limit the number of memory cell rows included in one memory finger of the 3D NAND type memory in the present disclosure. In an actual application, the number of memory cell rows included in one memory finger can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0042] FIG. 3b is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits, according to some aspects of the present disclosure. The memory device 300 can be an example of the memory device 104 in FIG. 1. The memory device 300 can include a memory cell array 301 and peripheral circuits 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as an example of a 3D NAND type memory cell array, and the memory cells 306 are NAND type memory cells, each provided in the form of an array of memory strings 308 that extend vertically upward from a substrate (not shown). In some examples, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked in the vertical direction. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 can be either a floating gate type memory cell including a floating gate transistor or a charge trap type memory cell including a charge trap transistor.

[0043] In some examples, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can thus store 1 bit of data. For example, a first memory state “0” can correspond to a first range of voltages, and a second memory state “1” can correspond to a second range of voltages. In some examples, each memory cell 306 is a multi-level cell (MLC) that can store more than 4 memory states and more than a single bit of data. For example, an MLC can store 2 bits per cell (also called a double-level cell), 3 bits per cell (also called a triple-level cell (TLC)), 4 bits per cell (also called a quad-level cell (QLC)), 5 bits per cell (also called a penta-level cell (PLC)), or more than 5 bits per cell. Each MLC can be programmed to take on a range of possible nominal stored values. In one example, when each MLC stores 2 bits of data, the MLC can be programmed to take on one of three possible programming levels out of an erased state by writing one of three possible nominal stored values to the cell. A fourth nominal stored value can be used for the erased state.

[0044] As shown in FIG. 3b, each memory string 308 includes a bottom selective transistor 310 (also referred to as a source side selective transistor and including a source selective gate BSG) on its source side, and can include a top selective transistor 312 (also referred to as a drain side selective transistor and including a drain selective gate TSG) on its drain side. The source selective transistor BSG 310 and the drain selective transistor TSG 312 can be configured to activate the selected memory string 308 during read and program operations. In some examples, the sources of the memory strings 308 within the same memory block 304 are coupled through the same source line (SL) 314, e.g., a common SL. In other words, according to some examples, all the memory strings 308 within the same memory block 304 have an array common source (ACS). The TSG 312 of each memory string 308 is coupled to a respective bit line 316 through which data can be read and written through an output bus (not shown) in some examples. In some examples, each memory string 308 is configured to be selected or deselected by applying at least one of a select voltage (e.g., above the threshold voltage of the transistor having TSG 312) or a deselect voltage (e.g., 0V) to the respective TSG 312 through one or more TSG lines 313, or applying a select voltage (e.g., above the threshold voltage of the transistor having BSG 310) or a deselect voltage (e.g., 0V) to the respective BSG 310 through one or more BSG lines 315.

[0045] As shown in FIG. 3b, the NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have, for example, a common source line 314 coupled to ground. In some examples, each memory block 304 is a basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 within a selected memory block 304, the source line 314 coupled to the selected memory block 304, as well as unselected memory blocks 304 in the same plane as the selected memory block 304, can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or more). In some examples, it is understood that the erase operation can be performed at a 1 / 2 memory block level, a 1 / 4 memory block level, or a level having any suitable number of memory blocks or any suitable portion of a memory block. Memory cells 306 of adjacent memory strings 308 can be coupled through word lines 318 that select which rows of memory cells 306 are affected by read and program operations. In some examples, referring to FIG. 3a above, it can be seen that a plurality of memory cells are insulated by a top select gate insulating structure and a gate insulating structure. A plurality of memory cells between the top select gate insulating structure and the gate insulating structure are arranged and configured in a plurality of memory cell rows, and each memory cell row is parallel to the gate insulating structure and the top select gate insulating structure. Memory cells within a string sharing the same word line form a physical page 320, and each physical page 320 can be mapped to at least one logical page based on the storage mode of the corresponding memory cells 306 (e.g., SLC or MLC as described above). A logical page can constitute a basic data unit for program and read operations.

[0046] Referring to FIGS. 3a and 3b, each memory cell 306 of the plurality of memory cells is coupled to a respective word line 318, and each memory string 308 is coupled to a respective bit line 316 via a respective selective transistor (such as top selective transistor (TSG) 312).

[0047] FIG. 4 shows a schematic cross-sectional view of an exemplary memory cell array 301 including a memory string 308 exemplified by NAND according to an aspect of the present disclosure. As shown in FIG. 4, the NAND memory cell array 301 may include a stacked structure 410 including a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in order, and a channel structure vertically penetrating the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to a plurality of gate layers in the stacked structure 410 to form a memory string 308. The gate layers 411 and the insulating layers 412 may be stacked alternately, and two adjacent gate layers 411 are separated by an insulating layer 412.

[0048] The constituent material of the gate layer 411 may include a conductive material. The conductive material may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some examples, each gate layer 411 may include a metal layer, for example, a tungsten layer. In some examples, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding the memory cell. The gate layer 411 on top of the stacked structure 410 may extend horizontally as a top selective gate line, and the gate layer 411 at the bottom of the stacked structure 410 may extend horizontally as a bottom selective gate line, and the gate layer 411 extending horizontally between the top selective gate line and the bottom selective gate line may be used as a word line layer.

[0049] In some examples, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0050] In some examples, the memory string 308 includes a channel structure that extends vertically through the stacked structure 410. In some examples, the channel structure includes a channel hole filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). In some examples, the semiconductor channel includes silicon, e.g., polysilicon. In some examples, the memory film is a composite dielectric layer including a tunnel layer, a storage layer (also referred to as a "charge trap / storage layer"), and a blocking layer. The channel structure may have a cylindrical shape (e.g., a columnar shape). According to some examples, the semiconductor channel, the tunnel layer, the storage layer, and the blocking layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0051] Referring back to FIG. 3b, the peripheral circuit 302 can be coupled to the memory cell array 301 through bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include any suitable analog, digital, and mixed-signal circuitry for smoothing the operation of the memory cell array 301 by applying and sensing at least one of a voltage signal or a current signal between the peripheral circuit 302 and each target memory cell 306 through the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG. 5 illustrates some exemplary peripheral circuits, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an I / F interface 516, and a data bus 518. It is understood that in some examples, additional peripheral circuits not shown in FIG. 5 may also be included as well.

[0052] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed in the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verify operation to confirm that data is properly programmed in the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify it to a logic level recognizable with a small voltage amplitude in a read operation. The column decoder / bit line driver 506 can be configured to select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510 under the control of the control logic 512.

[0053] The row decoder / word line driver 508 can be configured to select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304 under the control of the control logic 512. The row decoder / word line driver 508 can be further configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some examples, the row decoder / word line driver 508 can also select / deselect and drive the BSG line 315 and the TSG line 313 in the same way. As will be described in detail below, the row decoder / word line driver 508 is configured to perform a program operation on the memory cell 306 coupled to the selected word line 318. The voltage generator 510 can be configured to generate a word line voltage (e.g., read voltage, program voltage, pass voltage, channel boost voltage, verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301 under the control of the control logic 512.

[0054] The control logic 512 can be coupled to each other part of the peripheral circuits described above and configured to control the operation of each other part of the peripheral circuits. The register 514 can be coupled to the control logic 512 and include status registers, command registers, and address registers that store status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and operate as a control buffer that buffers and relays control commands received from a host (not shown) to the control logic 512 and buffers and relays status information received from the control logic 512 to the host. The interface 516 can further be coupled to the column decoder / bit line driver 506 via the data bus 518 and operate as a data I / O interface and data buffer that buffers and relays data between the memory cell array 301.

[0055] In the process of writing data, it should be understood that multiple operations are required and both the performance of writing data and the correctness of the data are important characteristics of the memory system. Therefore, high requirements are imposed on the process of writing data. In the existing process of writing data, some special processing can be performed to ensure the stability of the data. For example, an operation of filling the memory cell array with dummy data may be performed. The dummy data here can be any random data. Although the dummy data is not intended for reading, it plays a specific role such as mitigating the coupling effect of the memory pages where data has not been written on the adjacent memory pages where data has been written, thereby making the data retention in the written memory cells better.

[0056] A memory system may include a memory controller and a memory device. The memory device may include a memory cell array and peripheral circuits. The memory cell array may include a plurality of memory blocks, and each memory block may include a plurality of memory pages. In the process of writing data, a part of the memory blocks in the memory device may be in a situation where the data is not completely written, and the physical characteristics of the memory system require that an operation of filling dummy data to the memory blocks that are not completely written be performed when the power is turned off (or shut down), or under specific conditions, to ensure the stability of the written data. In some examples, the method of filling dummy data is that the memory controller sends a special command to the memory device, and the special command instructs that some memory pages in the memory device should be filled with dummy data, including sending the corresponding dummy data to be written to the memory device, and after the memory device receives the special command and the dummy data to be written, filling the received dummy data into the memory pages that need to be filled with dummy data. However, the above process of filling dummy data is a time-consuming operation, and the content of the filled dummy data is data that the user does not care much about.

[0057] Based on one or more of the above problems, in an example of the present disclosure, a memory device, an operation method thereof, and a memory system are proposed. Referring to FIGS. 1 and 6, it can be seen that the memory system 102 includes at least one memory device 104 and a memory controller 106 coupled to the memory device and configured to control the memory device. The memory controller 106 can access or control the memory device 104 according to specific timing rules. The memory controller 106 enables the host 108 (a device that accesses the memory device) to use the storage resources on the memory device 104 according to its own requirements via an address signal (address information / address instruction, ADDR), a data signal (data instruction, DATA), a control signal (control instruction, CTRL), and various command signals (CMD). The memory device 104 includes, in this specification, a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. Referring to FIG. 7, the operation method of the memory device includes the following operations. Operation S701: Receive a first instruction instructing to write dummy data to a specified location within the memory cell array 301. Operation S702: Generate the dummy data to be written in response to the first instruction. Operation S703: Write the dummy data to be written to the specified location.

[0058] The memory cell array 301 may include a plurality of memory planes, each memory plane may include a plurality of memory blocks, and each memory block may include a plurality of memory pages. A memory page is the minimum unit for read and write (i.e., program) operations, and a memory block is the minimum unit for erase operations. In some examples, each memory block may include a plurality of valid memory pages and a plurality of dummy memory pages. It should be understood that the foregoing memory pages are references to valid memory pages and dummy memory pages in this specification. A valid memory page is a memory page included in a region corresponding to a word line (WL) or a channel hole (CH), is configured to store user data (actual data), and a storage channel structure is formed within the storage channel hole. A dummy memory page is a memory page included in a region corresponding to a dummy word line (DWL) or a dummy channel hole (DCH), is configured for special functions such as support, defect repair, bad block handling, and the like, and is not configured to store actual data. Here, a dummy channel structure is formed within the dummy channel hole. The plurality of valid memory pages and the plurality of dummy memory pages may be arranged configured at intervals or adjacent to each other. It should be understood that the plurality of valid memory pages and the plurality of dummy memory pages are all physical memory pages.

[0059] The peripheral circuit 302 may include at least one of any suitable digital, analog, or mixed-signal circuit configured to facilitate various operations of the memory device, such as read, write, erase, and similar operations. For example, the peripheral circuit may include control logic (such as a control circuit or controller), a data buffer, a decoder (which may also be referred to as an encoder), a driver, and read and write circuits. When the control logic receives commands and address data for read and write operations, the decoder applies corresponding voltages from the driver to the corresponding bit lines and word lines based on the address decoded under the control logic, enabling data read and write and data interaction with the outside through the data buffer.

[0060] Note that the execution targets of operations S701 to S703 may include the peripheral circuit. Referring to FIG. 5, more specifically, it can be seen that the I / F interface 516 is used to receive a first instruction and transmit the first instruction to the control logic 512. The control logic 512 is used to generate dummy data according to the first instruction, and the page buffer / sense amplifier 504, column decoder / bit line driver 506, row decoder / word line driver 508, voltage generator 510, and control logic 512 are used to collectively execute the writing of the dummy data.

[0061] In operation S701, a first instruction is received.

[0062] In some examples, when there are memory blocks in the memory cell array that are not fully filled, the memory controller or host sends a first command to instruct to fill the specified location of the memory device with dummy data. Here, the first command may include a first instruction CMD and a plurality of address instructions ADDR. Here, the memory device 104 is used to receive the first command, and the first instruction CMD is used to instruct to write dummy data to the specified location of the memory cell array 301. For example, referring to FIG. 8, it can be seen that the plurality of address instructions ADDR include 4-bit row addresses (R1, R2, R3, R4) that are the addresses of the specified locations within the memory cell array 301. In some examples, the first command is configured by a set feature command, or the first command includes a first flag set on a reserved field of a write command.

[0063] In some specific examples, the first command is configured by a set feature command. Here, it is a prerequisite that the memory device supports the set feature command, and the set feature command may also be supported by the memory controller or host. Under this prerequisite, the first command can be directly configured by the set feature command. The set feature command enables user-defined protocols such as the first command to be directly edited to realize communication regarding the first command between the memory device and the memory controller or host. When the first command is configured by the set feature command, note that the command in which the first command is placed does not include the dummy data to be written, and the command in which the first command is placed includes a page program command, that is, a dummy data write command and the address of the dummy data to be written. In one example, the first command of the dummy data write command in the ONFI protocol is the 81h command.

[0064] In some specific examples, the first instruction includes a first flag set on the reserved field of the write command. That is, in some examples, the first instruction can be embedded within the normal write command of the memory device. The normal write command may include a first part and a second part, where the first part includes an address instruction (address information) and the second part includes data information. In the examples of the present disclosure, the first instruction includes a first flag set on the reserved field of the write command, that is, the first instruction is embedded on the reserved field of the write command (hereinafter, this type of write command is abbreviated as a special write command). For example, referring to FIG. 9, FIG. 9 shows a schematic diagram of the address information of the write command corresponding to a triple-level cell (TLC). The write command includes six sets of address information (the first, the second, the third, the fourth, the fifth, the sixth), and the sixth set of address information (the sixth) is set with a plurality of reserved addresses (a plurality of LOWs shown by the dotted boxes in FIG. 9), and the reserved field of the write command can be any one of the plurality of reserved addresses within the sixth set of address information (the sixth). In other words, any one of the plurality of reserved addresses shown by the dotted boxes in FIG. 9 can be used to set the first flag.

[0065] When the first instruction includes a first flag set on the reserved field of the write command, the peripheral circuit, in response to the first instruction, does not receive the data information included in the write command and directly generates dummy data to be written. Since the memory device does not receive the data information, the memory controller or the host may randomly generate invalid data information to meet the format requirements of the write command when generating the corresponding special write command. Further, when transmitting these special write commands, the memory controller or the host may transmit only the address instruction without transmitting the data information. In this way, the memory device side can receive only the address information by the first instruction without receiving the data information.

[0066] In some other examples, the first instruction may be further configured by a vendor command. Here, the vendor-specific command is generally not available and is a command used only for a specific vendor agreed upon, such as a manufacturer. The vendor-specific command is available only when the user is the agreed-upon vendor. When configured by the vendor command, it is necessary to update the protocols on the memory device side and the memory controller side, that is, to reach an agreement on the protocol again between the two. Similarly, the command in which the first instruction is placed does not need to include data information.

[0067] In some examples, when transmitting the first instruction instructing to write dummy data to a specified location in the memory cell array, the memory controller or the host does not generate dummy data.

[0068] Here, the specified location may include any location within the memory cell array of the memory device where data has not been written. In some examples, the specified location is at least one of a plurality of memory blocks, At least one of the valid memory pages in the erased state in one of the memory blocks, and At least one of the dummy memory pages in one of the memory blocks includes one of them.

[0069] In some examples, the specified location may include at least one of a plurality of memory blocks. When there is no data stored in a particular one or more memory blocks (i.e., blank memory blocks) of the memory cell array and some special test operations need to be performed, such as checking whether the programming count and the erase count are normal and checking the erase time, it is necessary to write data to these memory blocks, but the written data itself is not of concern. At this time, dummy data is written into these memory blocks, and the purpose of the quick test can be achieved. In some examples, the specified location may well include at least one of the valid memory pages in the erased state in one of the memory blocks, and the memory pages adjacent to the specified location are in the program state. When a part of the memory pages in the memory block is written with data, that is, when a part of the memory pages is in the program state and the remaining memory pages are not written with data, that is, another part of the memory pages is in the erased state, it can be understood. The level of the memory pages in the erased state is different from the level of the memory pages in the program state, and the electrons in the memory pages in the program state adjacent to the memory pages in the erased state are shifted, that is, the electron coupling effect occurs. As a result, the retention of the data in the memory pages in the program state decreases. Based on this, when some memory pages in the memory block are written with data, dummy data is stored in one or more memory pages adjacent to the memory pages written with data where no data is written, whereby the electron coupling effect of the memory pages in the program state can be reduced.

[0070] In some examples, the specified location may include all remaining valid memory pages in an erased state in one of the memory blocks. It can be understood that the memory block is the minimum execution unit for the erase operation. In the process of performing the erase operation on a memory block, not only the memory pages in the erased memory block where data has been written are erased, but also the valid memory pages in the memory block where no data has been written, that is, in the erased state, are erased. As a result, the valid memory pages in the erased state are over-erased, which may cause problems such as leakage current of memory cells. At this time, by writing dummy data to all remaining valid memory pages in the erased state within the memory block, the probability of over-erasure can be reduced, and the performance of the memory device can be improved. In some examples, as described above, a plurality of memory pages within a memory block are divided into valid memory pages and dummy memory pages. The valid memory pages are memory pages configured to store data, and the dummy memory pages are configured for special functions such as support, failure recovery, defective block processing, etc. When the dummy memory page is set adjacent to the valid data memory page, there may also be the aforementioned electron coupling effect between the dummy memory page and the valid data memory page. When there is no data stored in the dummy memory page, that is, when the dummy memory page is in the erased state, it can be understood that the aforementioned problem of over-erasure exists. In this case, by storing dummy data in the dummy memory page, the electron offset of the valid memory page adjacent to the dummy memory page can be reduced, and the over-erasure problem can be alleviated, thereby improving the performance of the memory device.

[0071] In operation S702, the memory device autonomously generates dummy data written in response to the first instruction.

[0072] In some examples, generating the dummy data to be written Including generating dummy data to be written randomly, or generating dummy data to be written in combination with a preset algorithm according to the data stored in a location adjacent to the specified location.

[0073] It is understood that the user does not care much about the content of the dummy data, and the dummy data does not need to be read out and reused later. Based on this, the dummy data can be randomly generated by the memory device according to its own characteristics, or can be calculated according to its own actual requirements.

[0074] In some specific examples, the randomly generated dummy data can all be "0", or can all be "1", or can be a random combination of "1" and "0".

[0075] In some other specific examples, in order to reduce the electron coupling effect between adjacent memory pages, a set of dummy data can be calculated based on the data of the memory page in the program state and in combination with a preset algorithm. Here, the adjacent memory pages can be the memory page where data is written and the adjacent memory page where data is not written. The preset algorithm is related to the coupling effect between the memory cells in the memory cell array.

[0076] When the stored data corresponding to the memory cells of a specific memory page contains "1" or "0", it can be understood that electrons are arranged in different layers of the channel structure. At this time, when the adjacent memory page is in the erased state, the position of the electrons is fixed, and the electrons at the fixed position have different coupling effects on the adjacent electrons in different layers. At this time, the dummy data that minimizes the coupling effect is derived from the data in the memory page where the data is written, so that more accurate dummy data to be written can be obtained, thereby more accurately reducing the electron coupling effect between adjacent memory pages and improving the stability of the data.

[0077] In operation S703, the generated dummy data to be written is written to the specified location.

[0078] It should be noted that the generated dummy data to be written first enters the page buffer and then is written from the page buffer to the specified location of the memory cell.

[0079] Based on this, after receiving the first instruction instructing to fill the specified location with dummy data, the memory device in the above example of the present disclosure generates dummy data according to its own characteristics and stores the dummy data at the specified location. In this way, on the one hand, the memory device generates dummy data according to its own characteristics instead of the memory controller transmitting the dummy data to the memory device. Therefore, the transmission time of the dummy data can be saved, the time for filling the dummy data is shortened, and the throughput of the memory system is improved. On the other hand, by storing the dummy data at the specified location, the coupling effect between the memory pages where data is written and the memory pages where data is not written in the memory device is reduced, and the stability of the written data can be improved.

[0080] In actual operation, in some application scenarios, it is necessary to perform a read operation on the data in the memory cell array. For example, after the memory device encounters an abnormal power failure, all the data currently stored in the memory device is read out, and based on the read result, a judgment is made after the abnormal power failure, and a data recovery strategy is determined. Hereinafter, a method for dealing with the situation where the dummy data already stored in the memory device is read out in these scenarios will be introduced.

[0081] In some examples, this method includes receiving a second instruction instructing to perform a read operation on the data in the memory cell array, and Further including returning data to be read in response to the second instruction, when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header of a returned data frame, and the second flag indicates that the read data includes dummy data.

[0082] The second instruction received by the memory device is a read instruction, and the second instruction includes address information for performing a read operation. For example, referring to FIG. 10, the read instruction shown in FIG. 10 includes data bus DQ[7:0], cycle type of the read operation, column address information (C1, C2), row address information (R1, R2, R3, R4), lengths of waiting times (tWB, tR, tRR) after sending the read instruction, and the like. The memory device reads a memory page corresponding to the column address information (C1, C2) and the row address information (R1, R2, R3, R4) according to the instruction of the second instruction, reads the data of the corresponding memory page, and then returns the read data to the memory controller or the host. The memory controller or the host can determine whether the read data includes dummy data according to the returned data.

[0083] In some examples, when the data to be read includes dummy data, the second flag is set on the reserved field of the frame header of the returned data frame. After receiving the returned data to be read, the memory controller or host determines whether to decode the returned data to be read according to whether there is a second flag in the returned data frame. When there is a second flag in the returned data frame, this indicates that the returned data to be read contains dummy data. At this time, stop receiving the remaining data frames or do not perform a decoding operation on the returned data to be read. When there is no second flag in the returned data frame, this indicates that the returned data to be read does not contain dummy data. At this time, continue to receive the remaining data frames and perform a decoding operation on the returned data to be read.

[0084] Note that there are two situations for the returned data. One is the situation where there is no dummy data in the returned data (all of the data is actual data), and at this time, the memory controller performs normal operations. The other is the situation where there is dummy data in the returned data, and at this time, two methods can be used to distinguish the dummy data. The first situation is that when the returned dummy data has a corresponding flag such as the second flag described above, the dummy data can be selected using the flag. The second situation is that when the returned dummy data has no flags, and at this time, considering that the dummy data is generated by the memory device according to its own characteristics, its address is not stored in the logical-physical mapping table (LTP). At this time, the actual data may be selected according to the logical-physical mapping table, and the remaining data is dummy data.

[0085] It should also be noted that when dummy data is written to a memory device, the dummy data is not encoded like normal data. Based on this, the write duration of the dummy data is shorter than that of normal valid data. However, there is a decoding failure when decoding the dummy data. Since the user does not care about the dummy data, the dummy data can be directly discarded.

[0086] In some examples, this method further includes writing the dummy data to be written to the specified location, then saving the specified location, checking whether the address corresponding to the data to be read is within the address range corresponding to the saved specified location before returning the data to be read, and determining that the data to be read contains dummy data when the address corresponding to the data to be read is within the address range corresponding to the saved specified location.

[0087] That is, after writing dummy data to a specified location in the memory cell array of the memory device, the memory device stores the address corresponding to the specified location. After reading the address of the data to be read in the memory cell array according to the instruction of the second instruction, the memory device checks whether the address corresponding to the data to be read is within the address range corresponding to the stored specified location. If the address corresponding to the data to be read is within the address range corresponding to the stored specified location, this indicates that the data to be read contains dummy data. At this time, the second flag can be set on the reserved field of the frame header of the returned data frame. If the address corresponding to the data to be read is not within the address range corresponding to the stored specified location, this indicates that the data to be read does not contain dummy data, and at this time, the second flag is not set on the reserved field of the frame header of the returned data frame. In this way, a criterion for whether dummy data is included in the returned data can be provided.

[0088] On the other hand, an example of the present disclosure further provides a memory device, which includes a memory cell array and peripheral circuits coupled to the memory cell array. The peripheral circuits receive a first instruction instructing to write dummy data to a specified location in the memory cell array, generate the dummy data to be written in response to the first instruction, and are configured to write the dummy data to be written to the specified location.

[0089] In some examples, the first instruction is configured by a set feature command, or the first instruction includes a first flag set on the reserved field of a write command.

[0090] In some examples, when the first instruction is configured by a set feature command, the command where the first instruction is located does not include dummy data to be written. When the first instruction includes a first flag set on the reserved field of the write command, the peripheral circuit is configured to directly generate dummy data to be written without receiving the data information included in the write command in response to the first instruction.

[0091] In some examples, the peripheral circuit generates the dummy data to be written randomly, or is configured to generate the dummy data to be written in combination with a preset algorithm according to the data stored in a location adjacent to the specified location.

[0092] In some examples, the preset algorithm is related to the coupling effect between memory cells in the memory cell array.

[0093] In some examples, the memory cell array includes a plurality of memory blocks, and each of the memory blocks includes a plurality of valid memory pages and a plurality of dummy memory pages. The specified location is at least one of the plurality of memory blocks, at least one of the valid memory pages in the erased state in one of the memory blocks, and at least one of the dummy memory pages in one of the memory blocks including one of them.

[0094] In some examples, the specified location includes at least one of the valid memory pages in the erased state in one of the memory blocks, and the memory pages adjacent to the specified location are in the programmed state.

[0095] In some examples, the peripheral circuit receives a second instruction instructing to perform a read operation on data in the memory cell array, and in response to the second instruction, is further configured to return the data to be read. When the data to be read includes dummy data, a second flag is set on a reserved field of the frame header of the returned data frame. The second flag indicates that the read data includes dummy data.

[0096] In some examples, the peripheral circuit after writing the dummy data to be written to the specified location, saves the specified location, before returning the data to be read, checks whether the address corresponding to the data to be read is within the address range corresponding to the saved specified location, and when the address corresponding to the data to be read is within the address range corresponding to the saved specified location, is further configured to determine that the data to be read includes dummy data.

[0097] In some examples, the memory device includes a NAND-type memory.

[0098] It should be noted that the normal operating principles of the above-mentioned hardware part and the memory device can be understood corresponding to FIGS. 3a to 5 described above, and the above-mentioned method of processing dummy data by the memory device may refer to what has been described above regarding the method of processing dummy data in the operating method of the memory device.

[0099] In yet another aspect, examples of the present disclosure further disclose a memory system. The memory system includes one or more memory devices as described in the foregoing examples of the present disclosure, and A memory controller coupled to and configured to control a memory device, the memory controller being configured to control the memory device to perform read, write, and erase operations. Here, the memory controller and the memory device can be coupled in any suitable manner. In an example of the present disclosure, the memory device may be a semiconductor memory that stores data in a non-volatile manner, such as a NAND-type memory. The memory system is connected to a host, and the host may be an electronic device such as a personal computer and a mobile terminal.

[0100] In some examples, the memory system includes a Universal Flash Storage (UFS) device or a solid state disk.

[0101] In yet another aspect, an example of the present disclosure further discloses a memory system, which includes at least one memory device and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes a memory cell array and peripheral circuits coupled to the memory cell array. The memory controller is configured to send a first command, the first command including a first instruction and a plurality of address instructions, the first instruction instructing to write dummy data to a specified location corresponding to the plurality of address instructions. The peripheral circuits in the memory device are configured to receive the first command, generate dummy data to be written in response to the first command, and write the dummy data to be written to the specified locations corresponding to the plurality of address instructions.

[0102] Here, in this example, the first command is issued by the memory controller.

[0103] In some examples, the memory controller is configured to send a second command, the second command includes a second instruction, and the second instruction instructs to perform a read operation on data in the memory cell array. The peripheral circuit receives the second instruction and is configured to return the data to be read in response to the second instruction. When the data to be read includes dummy data, a second flag is set on a reserved field of the frame header of the returned data frame, and the second flag indicates that the read data includes dummy data. The memory controller receives the data to be read that is returned, and when the returned data frame includes the second flag, it is further configured to stop receiving the remaining data frames or not perform a decoding operation on the data to be read that is returned.

[0104] Here, in this example, the second command is issued by the memory controller.

[0105] In some examples, the memory controller is configured to send a second command, the second command includes a second instruction, and the second instruction instructs to perform a read operation on data in the memory cell array. The peripheral circuit receives the second instruction and is configured to return the data to be read in response to the second instruction, and the data to be read includes dummy data. The memory controller receives the data to be read that is returned and is further configured to discard the data to be read when the decoding of the data to be read that is returned fails.

[0106] Examples of the present disclosure provide a storage medium storing executable instructions, and when the executable instructions are executed by a memory controller, any one of the operations of the methods described in the foregoing examples can be implemented.

[0107] In an example of the present disclosure, the storage medium may be a NAND-type memory within a memory device, the executable instructions are stored in the NAND-type memory, and the executable instructions may be firmware in the above example. In this way, the memory controller can execute the executable instructions in the storage medium, thereby implementing the operation in any one of the methods in the above examples.

[0108] Throughout this specification, when described as "some examples" or "an example", it should be understood that this means that the specific features, structures, or characteristics related to the example are included in at least one example of the present disclosure. Therefore, although the phrases "in some examples" or "in an example" are described in various places throughout this specification, they do not necessarily all refer to the same example. Furthermore, these specific features, structures, or characteristics may be combined in one or more examples in any suitable manner. In various examples of the present disclosure, the sequential numbers of the above processes do not mean the execution order, and it should be understood that the execution order of the processes should not limit the exemplary processes of the examples of the present disclosure, but rather should be determined by their functions and inherent logic. The serial numbers of the above examples of the present disclosure are for illustrative purposes only and do not represent the advantages and disadvantages of the examples.

[0109] The above are only preferred examples of the present disclosure and do not limit the scope of the patent of the present disclosure. Under the inventive concept of the present disclosure, equivalent structural conversions made by using the content of the present disclosure and the accompanying drawings, or any other direct / indirect applications in other related technical fields, are included in the patent protection scope of the present disclosure.

Description of Reference Numerals

[0110] 100 System 102 Memory System 104 Memory Device 106 Memory Controller 108 Host 202 Memory Card 204 Memory Card Connector 206 SSD 208 SSD Connector 300 Memory Device 301 Memory Cell Array 302 Peripheral Circuit 304 Memory Block 306 Memory Cell 308 Memory String 310 Bottom Selective Transistor 312 Top Selective Transistor 313 TSG Line 314 Source Line (SL) 315 BSG Line 316 Bit Line 318 Word Line 320 Physical Page 401 Substrate 410 Stacked Structure 411 Gate Layer 412 Insulating Layer 504 Page Buffer / Sense Amplifier 506 Column Decoder / Bit Line Driver 508 Row Decoder / Word Line Driver 510 Voltage Generator 512 Control Logic 514 Register 516 I / F Interface 518 Data Bus

Claims

1. A memory device, comprising: a memory cell array; and peripheral circuitry coupled to the memory cell array, the peripheral circuitry being configured to: receive a first command instructing to write dummy data to a specified location within the memory cell array; generate the dummy data to be written in response to the first command; and write the dummy data to be written to the specified location, the memory device.

2. The first command is constituted by a set feature command, or the first command includes a first flag set on a reserved field of a write command, the memory device according to claim 1.

3. When the first command is constituted by the set feature command, the command in which the first command is arranged does not include the dummy data to be written, when the first command includes the first flag set on the reserved field of the write command, the peripheral circuitry is configured to: receive no data information included in the write command in response to the first command, and directly generate the dummy data to be written, the memory device according to claim 2.

4. The peripheral circuitry is configured to: generate the dummy data to be written randomly, or generate the dummy data to be written in combination with a preset algorithm according to data stored in a location adjacent to the specified location, the memory device according to claim 1.

5. The preset algorithm is related to a coupling effect between memory cells within the memory cell array, the memory device according to claim 4.

6. The memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of valid memory pages and a plurality of dummy memory pages, the specified location includes: at least one of the plurality of memory blocks; at least one of the valid memory pages in an erased state in one of the memory blocks; and at least one of the dummy memory pages in one of the memory blocks the memory device according to claim 1.

7. The specified location is The memory device according to claim 6, including at least one of the valid memory pages in the erased state in one of the memory blocks, wherein the memory pages adjacent to the specified location are in the programmed state.

8. The peripheral circuit receives a second instruction for instructing to execute a read operation on the data in the memory cell array, and is further configured to return the data to be read in response to the second instruction, wherein when the data to be read includes the dummy data, a second flag is set on a reserved field of a frame header of a returned data frame, and the second flag indicates that the read data includes the dummy data. The memory device according to claim 1.

9. The peripheral circuit writes the dummy data to be written to the specified location and then stores the specified location, checks whether an address corresponding to the data to be read is within an address range corresponding to the stored specified location before returning the data to be read, and is further configured to determine that the data to be read includes the dummy data when the address corresponding to the data to be read is within the address range corresponding to the stored specified location. The memory device according to claim 8.

10. A memory system, comprising one or more memory devices according to any one of claims 1 to 9, and a memory controller coupled to the memory device and configured to control the memory device.

11. The memory system according to claim 10, including a solid state disk.

12. A memory system, comprising at least one memory device, comprising a memory cell array, and a peripheral circuit coupled to the memory cell array, and a memory controller coupled to the memory device and configured to control the memory device, wherein the memory controller configured to send a first command, the first command including a first instruction and a plurality of address instructions, the first instruction instructing to write dummy data to a designated location corresponding to the plurality of address instructions, the peripheral circuit within the memory device, receives the first command, generates the dummy data to be written in response to the first command, A memory system configured to write the dummy data to be written to the designated location corresponding to the plurality of address instructions.

13. The memory controller, configured to send a second command, the second command including a second instruction, the second instruction instructing to perform a read operation on data in the memory cell array, the peripheral circuit, receives the second instruction, configured to return the data to be read in response to the second instruction, when the data to be read includes the dummy data, a second flag is set on a reserved field of a frame header of a returned data frame, the second flag indicating that the read data includes the dummy data, The memory controller, receives the data to be read that is returned, The memory system according to claim 12, further configured to stop receiving the remaining data frames when the returned data frame includes the second flag, or not to perform a decoding operation on the data to be read that is returned.

14. The memory controller, configured to send a second command, the second command including a second instruction, the second instruction instructing to perform a read operation on data in the memory cell array, the peripheral circuit, receives the second instruction, configured to return the data to be read in response to the second instruction, the data to be read includes the dummy data, The memory controller, receives the data to be read that is returned, The memory system according to claim 12, further configured to discard the data to be read when decoding of the data to be read that is returned fails.

15. A method for operating a memory device, Receiving a first instruction instructing to write dummy data to a specified location in a memory cell array of the memory device; Generating the dummy data to be written in response to the first instruction; Writing the dummy data to be written to the specified location, and an operation method.

16. The first instruction is configured by a set feature command, or The operation method according to claim 15, wherein the first instruction includes a first flag set on a reserved field of a write command.

17. When the first instruction is configured by the set feature command, the command in which the first instruction is arranged does not include the dummy data to be written, When the first instruction includes the first flag set on the reserved field of the write command, without receiving data information included in the write command in response to the first instruction, directly generating the dummy data to be written, The operation method according to claim 16.

18. The step of generating the dummy data to be written includes Randomly generating the dummy data to be written, or Generating the dummy data to be written in combination with a preset algorithm according to data stored in a location adjacent to the specified location, The operation method according to claim 17.

19. Receiving a second instruction instructing to perform a read operation on data in the memory cell array; Further including returning the data to be read in response to the second instruction, When the data to be read includes the dummy data, a second flag is set on a reserved field of a frame header of a returned data frame, and the second flag indicates that the read data includes the dummy data, The operation method according to claim 15.

20. After writing the dummy data to be written to the specified location, saving the specified location; Before returning the data to be read, checking whether the address corresponding to the data to be read is within the address range corresponding to the stored specified location; The method of operation according to claim 19, further comprising: determining that the data to be read contains the dummy data when the address corresponding to the data to be read is within the address range corresponding to the stored specified location.

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