Display panel, display device, and wearable device

Abstract

The present application provides a display panel, a display device, and a wearable device. The display panel includes a display area (AA) and a peripheral area surrounding the display area (AA). The area other than the binding sub-area (B-D) in the peripheral area includes a first test unit group (T1) and a second test unit group (T2). The first test unit group (T1) and the second test unit group (T2) each include at least one circuit test unit (CP pad). The display area (AA) extends along a first direction (OA1) and includes a first side (L1) and a second side (L2) that are oppositely arranged. The first direction (OA1) is the direction in which the binding sub-area (B-D) points to the display area (AA). The maximum distance (d3) from the first test unit group (T1) to the first side (L1) in the direction perpendicular to the first direction (OA1) is equal to the maximum distance from the second test unit group (T2) to the second side (L2) in the direction perpendicular to the first direction (OA1). The display panel has low design difficulty and good display effect.

Description

Technical Field

[0001] This application relates to the technical field of displays, and particularly to display panels, display devices, and wearable devices.

Background Art

[0002] With the continuous development of display technology, silicon-based organic light-emitting diode (OLED) display products have attracted wide attention due to advantages such as high resolution, low power consumption, small size, and light weight. Applications in high-resolution near-eye display industries such as wearable devices, industrial security, and medical treatment are expected.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The embodiments of this application adopt the following technical solutions.

Means for Solving the Problems

[0004] In a first aspect, the embodiments of this application include a display area and a peripheral area surrounding the display area, the peripheral area includes a binding sub-area located on one side of the display area, the area other than the binding sub-area in the peripheral area includes a first test unit group and a second test unit group, the first test unit group and the second test unit group each include at least one circuit test unit, the display area extends along a first direction and includes a first side and a second side arranged oppositely, the first direction is the direction in which the binding sub-area points to the display area, and provides a display panel in which a maximum distance from the first test unit group to the first side in a direction perpendicular to the first direction is equal to a maximum distance from the second test unit group to the second side in a direction perpendicular to the first direction.

[0005] In some embodiments of the present application, the minimum distance from the first test unit group to the first side in the direction perpendicular to the first direction is equal to the minimum distance from the second test unit group to the second side in the direction perpendicular to the first direction.

[0006] In some embodiments of the present application, the region other than the binding sub-region in the peripheral region includes a light-shielding layer whose inner contour of the orthographic projection on the substrate of the display panel contacts the edge of the display region. Both the first test unit group and the second test unit group are located on the side away from the display region of the light-shielding layer, and the orthographic projections of the first test unit group and the second test unit group on the substrate do not overlap with the orthographic projection of the light-shielding layer on the substrate.

[0007] In some embodiments of the present application, the peripheral region includes a first peripheral sub-region located on the side away from the binding sub-region of the display region. A part of the circuit test units of the first test unit group is located in the first peripheral sub-region, and another part of the circuit test units of the first test unit group is located in the region close to the first side of the peripheral region. A part of the circuit test units of the second test unit group is located in the first peripheral sub-region, and another part of the circuit test units of the second test unit group is located in the region close to the second side of the peripheral region.

[0008] In some embodiments of the present application, the connecting lines of the geometric centers of the circuit test units of the first test unit group and the connecting lines of the geometric centers of the circuit test units of the second test unit group respectively form two intersecting line segments. Alternatively, the connecting lines of the geometric centers of the circuit test units of the first test unit group and the connecting lines of the geometric centers of the circuit test units of the second test unit group are respectively arc lines.

[0009] In some embodiments of the present application, the geometric centers of the circuit test units in the first test unit group are on the same line segment, and the geometric centers of the circuit test units in the second test unit group are on the same line segment.

[0010] In some embodiments of the present application, each of the circuit test units in the first test unit group is located in a region close to the first side of the peripheral region, and each of the circuit test units in the second test unit group is located in a region close to the second side of the peripheral region.

[0011] In some embodiments of the present application, the first test unit group and the second test unit group each include a first end close to the binding sub-region and a second end away from the binding sub-region. The minimum distance between the first end and the display region in a direction perpendicular to the first direction is greater than or equal to the minimum distance between the second end and the display region in a direction perpendicular to the first direction.

[0012] In some embodiments of the present application, each of the circuit test units in the first test unit group and the second test unit group is located in the first peripheral sub-region, and the circuit test units in the same group are arranged perpendicular to the first direction. The first test unit group and the second test unit group are arranged along the first direction. Alternatively, the first test unit group and the second test unit group are arranged perpendicular to the first direction.

[0013] In some embodiments of the present application, each of the circuit test units is arranged in mirror symmetry.

[0014] In some embodiments of the present application, in a direction parallel to the plane where the substrate is located, the minimum distance from the circuit test units in the first test unit group and the second test unit group to the light-shielding layer is less than the minimum distance from the binding terminals in the binding sub-region to the light-shielding layer.

[0015] In some embodiments of the present application, the display panel includes a plurality of transistor test units and at least one third test unit group located in the first peripheral sub-region. The distance from the transistor test unit to the light-shielding layer is greater than or equal to the distance from the circuit test unit to the light-shielding layer.

[0016] In some embodiments of the present application, the third test unit group is located on the side away from the display region of all the circuit test units, there is a gap between the third test unit group and the light-shielding layer, and both the first test unit group and the second test unit group are located in the gap.

[0017] In some embodiments of the present application, the display panel includes two third test unit groups arranged perpendicular to the first direction, the first peripheral sub-region includes a code pattern located between the two third test unit groups, and the minimum distance from the code pattern to the light-shielding layer is greater than or equal to the minimum distance from the transistor test unit to the light-shielding layer.

[0018] In some embodiments of the present application, the peripheral region further includes a second peripheral sub-region located between the binding sub-region and the display region, and the orthographic projection of the light-shielding layer on the substrate is within the region of the peripheral region other than the binding sub-region. The distance from the portion of the outer contour of the light-shielding layer within the first peripheral sub-region to the edge of the display region in the first direction is less than the distance from the portion of the outer contour of the light-shielding layer within the second peripheral sub-region to the edge of the display region in the first direction.

[0019] In some embodiments of the present application, the shape of the orthographic projection of the light-shielding layer on the substrate includes a rectangle with four fillets. The radii of curvature of the two fillets close to the binding sub-region of the rectangle are larger than the radii of curvature of the two fillets close to the first peripheral sub-region of the rectangle.

[0020] In some embodiments of the present application, the display panel includes a cover that covers a part of the region of the light-shielding layer and the display region, and the outer contour of the orthographic projection on the substrate is within the orthographic projection of the light-shielding layer on the substrate. The four apex angles of the outer contour of the orthographic projection of the cover on the substrate are respectively located at the four fillets.

[0021] In some embodiments of the present application, the area of the region of the portion of the light-shielding layer located in the first peripheral sub-region that does not overlap with the cover is less than the area of the region of the portion of the light-shielding layer located in the second peripheral sub-region that does not overlap with the cover.

[0022] In some embodiments of the present application, the number of the circuit test units is more than the number of the binding terminals.

[0023] In some embodiments of the present application, in a direction parallel to the plane where the substrate is located, the size of the region of the cover that overlaps with the light-shielding layer in the direction in which the display region points to the peripheral region is larger than the size of the circuit test unit in the first direction.

[0024] In some embodiments of the present application, the area of the orthographic projection figure of the circuit test unit on the substrate is less than or equal to the area of the orthographic projection figure of the binding terminal on the substrate.

[0025] In some embodiments of the present application, the display panel further includes a detection unit, the detection unit includes a plurality of auxiliary sub-pixels, the auxiliary sub-pixels are located in a region close to the first side of the peripheral region, and / or the auxiliary sub-pixels are located in a region close to the second side of the peripheral region, the structure of the auxiliary sub-pixels is the same as the structure of the sub-pixels in the display region, and the light-shielding layer covers the detection unit.

[0026] In some embodiments of the present application, the display panel further includes four mark patterns located on a side of the light-shielding layer away from the substrate, and a positive projection of the apex angle of the cover on the substrate at least partially overlaps a positive projection of the mark pattern on the substrate.

[0027] In a second aspect, an embodiment of the present application includes the display panel described in the first aspect, further includes a flexible circuit board and a driving chip, or includes a display control unit, and further includes a flexible circuit board, to provide a display device.

[0028] In a third aspect, an embodiment of the present application includes two display devices described in the second aspect, further includes two annular first holders, the display device is fixed to the first holder, the first holder covers an area where no light-shielding layer is provided in a peripheral area of the display panel, and each circuit test unit of one display device and each circuit test unit of the other display device are provided in a mirror-symmetrical manner, to provide a wearable device.

[0029] In some embodiments of the present application, a positive projection of the first holder on the substrate of the display panel overlaps a positive projection of the light-shielding layer on the substrate.

[0030] In some embodiments of the present application, an inner contour of a positive projection of the first holder on the substrate is at least partially in contact with an outer contour of a positive projection of the cover on the substrate.

[0031] In some embodiments of the present application is configured to be wearable, includes a main body portion and two temples, a driving plate and two of the first holders are respectively fixed to the main body portion, and further includes a second holder to which the driving plate is electrically connected to flexible circuit boards of the two display devices respectively. The two display panels are provided in mirror symmetry, and the geometric centers of the display areas of the two display panels and the geometric center of the main body of the second holder are on the same straight line. The two flexible circuit boards are provided in central symmetry with the geometric center of the second holder as the center of symmetry.

[0032] The above description is only a summary of the technical solution of the present application. In order to more clearly understand the technical solution of the present application, it can be implemented according to the content of the specification. And in order to more clearly and easily understand the above and other objects, features and advantages of the present application, specific embodiments of the present application are given below.

Brief Description of the Drawings

[0033] In order to more clearly describe the technical solutions in the embodiments or related technologies of the present application, the drawings required for describing the embodiments or the prior art will be briefly described below. However, the drawings in the following description are only some embodiments of the present application. It is obvious that those skilled in the art can obtain other drawings based on these drawings without paying creative labor.

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Modes for Carrying Out the Invention

[0034] Hereinafter, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the present application.

[0035] In the figures, for clarity, the regions and layer thicknesses may be enlarged. Since the same reference numerals in the figures indicate the same or similar structures, detailed descriptions are omitted. Furthermore, the drawings are only schematic illustrations of the present application and are not necessarily drawn to scale.

[0036] Unless otherwise required by context, throughout the specification and claims, the term "comprising" shall be construed as open and inclusive in the sense of "including, but not limited to". In the description of the specification, terms such as "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples", or "some examples" are intended to indicate that specific features, structures, materials, or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics can be included in any one or more embodiments or examples in any suitable manner.

[0037] Also, when the elements of the present application and their embodiments are described, terms such as "a", "one", "the", and "said" are intended to indicate the presence of one or more elements, and unless otherwise specified, "a plurality" means two or more. The terms "comprising", "including", and "having" are intended to be inclusive and mean that additional elements other than the described elements may exist. The terms "first", "second", "third", etc. are used only for the purpose of explanation and are not to be understood as indicating or suggesting relative importance and formation order.

[0038] In this specification, "electrically connecting" includes the case where components are connected via an element having some electrical effect. The "element having some electrical effect" is not particularly limited as long as electrical signals can be transmitted and received between the connected components. Examples of the "element having some electrical effect" include not only electrodes and wirings but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0039] The polygons in this specification are exact, such as approximately triangular, approximately rectangular, approximately trapezoidal, approximately pentagonal, approximately hexagonal, etc., and some deformations due to tolerances, chamfers, fillets, arc edges, and deformations are allowed.

[0040] As used herein, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. Further, "perpendicular" refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and also includes an angle of 85° or more and 95° or less.

[0041] Next, exemplary embodiments will be described in more detail with reference to the drawings.

[0042] With the continuous development of display technology, silicon-based organic light-emitting diode (OLED) display products have features such as being small-sized and having high resolution. Their backplane is made using a mature complementary metal oxide semiconductor (CMOS) process, which realizes active addressing of pixels and includes circuits such as a timer control register (TCON) and over current protection (OCP), enabling weight reduction.

[0043] Silicon-based OLED display products are widely used in near-eye displays and virtual reality (VR) or augmented reality (AR), particularly AR / VR head-mounted display devices. Currently, silicon-based OLED display products used in AR / VR devices require a high number of pixels per inch (PPI), and thus high requirements are imposed on the design of pixel arrangement and pixel area of silicon-based OLED display products. Also, in highly integrated and miniaturized silicon-based OLED display products, in order to achieve a better display effect and save design space, the designs of related technologies can no longer meet the needs.

[0044] To achieve this object, embodiments of the present application expand the usage scenarios of silicon-based display products, enabling broader application in high-resolution near-eye display industries such as wearable devices, industrial security, and medical fields, and also capable of improving the display effect and user experience, by providing a newly designed display panel.

[0045] Embodiments of the present application adopt the following technical solutions.

[0046] Embodiments of the present application provide a display panel. As shown in FIGS. 1 to 7, this display panel includes a display area AA and a peripheral area surrounding the display area. The peripheral area includes binding sub-areas B-D located on one side of the display area. The area other than the binding sub-areas B-D in the peripheral area includes a first test unit group T1 and a second test unit group T2. The first test unit group T1 and the second test unit group T2 each include at least one circuit test unit CP pad. The display area AA extends along a first direction, for example OA1, and includes a first side L1 and a second side L2 arranged oppositely. The first direction, for example the OA1 direction, is the direction in which the binding sub-areas B-D point to the display area AA. The maximum distance d3 from the first test unit group T1 to the first side L1 in a direction perpendicular to the first direction is equal to the maximum distance d3 from the second test unit group T2 to the second side L2 in a direction perpendicular to the first direction.

[0047] Here, the specific type of the above display panel is not limited, and specifically, it may be determined according to the actual situation.

[0048] As an example, the above display panel may be an organic light-emitting diode (OLED) display panel. The OLED display panel includes an OLED display panel having a silicon substrate (Si Substrate) and an OLED display panel having a glass substrate.

[0049] As an example, the above display panel may be a Micro-Organic Light Emitting Diode (Micro-OLED). Alternatively, the above display panel may be a Mini-Organic Light Emitting Diode (Mini-OLED). The Micro-OLED display panel and the Mini-OLED display panel also each include two types of a glass substrate and a silicon substrate.

[0050] Here, the silicon substrate may be a P-type single crystal silicon substrate or an N-type single crystal silicon substrate, and specifically, it may be determined according to the actual product. In the embodiments of the present application, the description will be given by taking the above display panel as a display panel having a silicon substrate as an example.

[0051] Here, the planar figure of the above display area AA is not limited.

[0052] As an example, the planar figure of the display area AA may be a rectangle illustrated in FIGS. 1 to 7, or may be other polygons such as a pentagon, a hexagon, etc., and specifically, it may be determined according to the usage scene and usage needs.

[0053] Here, the planar figure of the peripheral area may be annular. Since the planar figure of the display area AA is different, the planar figure of the peripheral area is also different, and the planar figure of the peripheral area is determined according to the planar figure of the display area AA.

[0054] The above planar figure refers to the figure of the orthographic projection on the substrate of the display panel.

[0055] The above bonding sub-regions B-D refer to the regions for bonding a driving chip (IC) and a flexible circuit board (FPC) in the peripheral area.

[0056] In some embodiments, in order to save design space and improve the resolution of the product, related circuits and modules in the driving chip IC are integrated on the driving substrate of the display panel. In this case, the driving chip may not be provided on the display panel. Therefore, the bonding sub-region B-D refers to the region for bonding the flexible circuit board (FPC) in the peripheral region with bonding.

[0057] In some embodiments, in order to reduce costs, when the display panel includes both a driving chip (IC) and a flexible circuit board (FPC), the above-mentioned bonding sub-region B-D refers to the region for bonding with each of the driving chip (IC) and the flexible circuit board (FPC) in the peripheral region.

[0058] The above-mentioned first test unit group T1 and second test unit group T2 each include at least one circuit test unit CP pad. In the embodiments of the present application, the case where the above-mentioned first test unit group T1 and second test unit group T2 each include a plurality of circuit test units CP pad will be taken as an example for explanation.

[0059] When the above-mentioned first test unit group T1 and second test unit group T2 each include a plurality of circuit test units CP pad, the specific number of each set of circuit test units CP pad is not limited, and this number may be determined according to the design of the driving circuit of the driving substrate of the display panel.

[0060] The circuit test unit CP pad is used to test the electrical characteristics of the entire driving circuit of the driving substrate after the manufacture of the driving substrate of the display panel and the manufacture of the display panel are completed, to check whether there is an abnormality in this driving circuit. If an abnormality exists, repair or adjustment of the abnormality is performed according to the situation. It should be noted that when the display panel is used as a display device and the user uses this display device, the circuit test unit CP pad is not used.

[0061] Here, the shape of the orthographic projection of the display panel substrate of the circuit test unit CP pad is not limited. As an example, as shown in FIGS. 1 to 7, the shape of the orthographic projection of the display panel substrate of the circuit test unit CP pad may be rectangular. Of course, the shape of the orthographic projection of the display panel substrate of the circuit test unit CP pad may be a polygon other than circular or rectangular, and specifically, it may be determined according to the actual product design. The size of the circuit test unit CP pad is not limited.

[0062] There is no limitation on whether the sizes of the circuit test unit CP pads in the same test unit group are the same. In the drawings related to the embodiments of the present application, the case where all the sizes of the circuit test unit CP pads are the same will be taken as an example for explanation.

[0063] There is also no limitation on whether the number of circuit test unit CP pads in the first test unit group T1 is the same as the number of circuit test unit CP pads in the second test unit group T2.

[0064] In some embodiments, for the sake of simplifying the design, the number of circuit test unit CP pads in the first test unit group T1 may be the same as the number of circuit test unit CP pads in the second test unit group T2.

[0065] The first side L1 and the second side L2 of the above display area AA are two opposite sides extending along the first direction in the display area AA. The display area AA may further include a third side L3 and a fourth side L4 as shown in FIGS. 1 to 7, or may further include a third side, a fourth side, a fifth side, and a sixth side. Here, the extending direction of the sides other than the first side L1 and the second side L2 is not limited.

[0066] Note that the extending directions of the first side L1 and the second side L2 of the display area AA are the same (i.e., parallel), and therefore, the planar figure of the display area AA cannot be a triangle.

[0067] In an exemplary embodiment, the maximum distance d3 from the first test unit group T1 to the first side L1 in a direction perpendicular to the first direction refers to the distance from the circuit test unit CP pad of the first test unit group T1 that is farthest from the first side L1 in the direction perpendicular to the first direction to the first side L1.

[0068] In an exemplary embodiment, the maximum distance d4 from the second test unit group T2 to the second side L2 in a direction perpendicular to the first direction refers to the distance from the circuit test unit CP pad of the second test unit group T2 that is farthest from the second side L2 in the direction perpendicular to the first direction to the second side L2.

[0069] In an embodiment of the present application, by configuring the maximum distance d3 from the first test unit group T1 to the first side L1 in a direction perpendicular to the first direction to be equal to the maximum distance d4 from the second test unit group T2 to the second side L2 in a direction perpendicular to the first direction, the arrangement form in the peripheral region of the first test unit group T1 and the arrangement form in the peripheral region of the second test unit group T2 are as similar as possible. In this way, when later testing the electrical characteristics of the entire driving circuit of the driving substrate, it is easier to electrically connect each circuit test unit CP pad to the corresponding interface of the external test device, reducing the probability of connection and signal transmission confusion, shortening the manufacturing cycle of the product, while making the arrangement in the peripheral region of the first test unit group T1 and the arrangement in the peripheral region of the second test unit group T2 as symmetric as possible, improving the regularity of these distributions, and reducing the design difficulty.

[0070] In some embodiments of the present application, as shown in FIGS. 1 to 7, the minimum distance d1 from the first test unit group T1 to the first side L1 in a direction perpendicular to the first direction is equal to the minimum distance d2 from the second test unit group T2 to the second side L2 in a direction perpendicular to the first direction.

[0071] The minimum distance d1 from the first test unit group T1 to the first side L1 in the direction perpendicular to the first direction refers to the distance from the circuit test unit CP pad closest to the first side L1 in the direction perpendicular to the first direction among the circuit test unit CP pads of the first test unit group T1 to the first side L1.

[0072] The minimum distance d2 from the second test unit group T2 to the second side L2 in the direction perpendicular to the first direction refers to the distance from the circuit test unit CP pad closest to the second side L2 in the direction perpendicular to the first direction among the circuit test unit CP pads of the second test unit group T2 to the second side L2.

[0073] In some embodiments, as shown in FIG. 4, the minimum distance d1 from the first test unit group T1 to the first side L1 in the direction perpendicular to the first direction is equal to the maximum distance d3 from the first test unit group T1 to the first side L1 in the direction perpendicular to the first direction, and the minimum distance d2 from the second test unit group T2 to the second side L2 in the direction perpendicular to the first direction is equal to the maximum distance d4 from the second test unit group T2 to the second side L2 in the direction perpendicular to the first direction.

[0074] As an example, as shown in FIG. 4, the four distances, namely, the minimum distance d1 from the first test unit group T1 to the first side L1 in the direction perpendicular to the first direction, the minimum distance d2 from the second test unit group T2 to the second side L2 in the direction perpendicular to the first direction, the maximum distance d3 from the first test unit group T1 to the first side L1 in the direction perpendicular to the first direction, and the maximum distance d4 from the second test unit group T2 to the second side L2 in the direction perpendicular to the first direction, are equal.

[0075] In the embodiment of the present application, in the direction perpendicular to the first direction, the maximum distance d3 from the first test unit group T1 to the first side L1 is equal to the maximum distance d4 from the second test unit group T2 to the second side L2, and in the direction perpendicular to the first direction, the minimum distance d1 from the first test unit group T1 to the first side L1 is equal to the minimum distance d2 from the second test unit group T2 to the second side L2. By being configured in this way, when later testing the electrical characteristics of the entire driving circuit of the driving substrate, it is further facilitated to electrically connect each circuit test unit CP pad to an external test device, the probability of continuous confusion is reduced, and the arrangement in the peripheral region of the first test unit group T1 and the arrangement in the peripheral region of the second test unit group T2 are made as symmetrical as possible, the regularity of these distributions is further improved, and the design difficulty can be reduced.

[0076] In some embodiments of the present application, as shown in FIGS. 1 to 7, the region other than the binding sub-regions B-D in the peripheral region includes a light-shielding layer ZG whose inner contour of the orthographic projection on the substrate of the display panel contacts the edge of the display region AA. Both the first test unit group T1 and the second test unit group T2 are located on the side away from the display region AA of the light-shielding layer ZG, and the orthographic projections of the first test unit group T1 and the second test unit group T2 on the substrate do not overlap with the orthographic projection of the light-shielding layer ZG on the substrate.

[0077] In an exemplary embodiment, the light-shielding layer ZG located in the peripheral region surrounds the display region AA. Understandably, the shape of the projection of the light-shielding layer ZG may be annular. Here, the specific shape of the above annular shape is not limited. As an example, the annular shape includes a ring shape, an elliptical ring shape, a polygonal ring shape, etc.

[0078] In addition, the above "contact" means that the inner contour of the projection of the light-shielding layer ZG contacts the outer contour of the projection of the display region AA, and the light-shielding layer ZG does not cover the display region AA.

[0079] That both the first test unit group T1 and the second test unit group T2 are located on the side away from the display area AA of the light-shielding layer ZG means that both the first test unit group T1 and the second test unit group T2 are located outside the light-shielding layer ZG. Here, the outside refers to the area outside the outer contour of the light-shielding layer ZG.

[0080] In the embodiments of the present application, in the peripheral region, other circuits, a plurality of wirings, for example, a cascade type shift register (GOA), a light emission control circuit (EOA), etc. may be further provided in addition to the first test unit group T1 and the second test unit group T2.

[0081] In some embodiments, at least a part of the shift register (GOA), the light emission control circuit (EOA), and the plurality of wirings may be provided between the substrate of the display panel and the light-shielding layer ZG. That is, the light-shielding layer ZG covers at least a part of the shift register (GOA), the light emission control circuit (EOA), and the plurality of wirings, thereby avoiding a reduction in the display effect due to light reflection by the circuits and wirings.

[0082] As an example, as long as the conditions of the manufacturing process permit, the light-shielding layer ZG covers as many circuits and wirings in the area other than the binding sub-area in the peripheral region as possible.

[0083] In an exemplary embodiment, the material of the light-shielding layer ZG includes an insulating material having a light-shielding function.

[0084] As an example, the light-shielding layer ZG may be manufactured simultaneously by the same patterning process using the same material as the black matrix layer BM.

[0085] As an example, the light-shielding layer ZG may include a plurality of sub-layers. For example, the light-shielding layer ZG is obtained by laminating a first sub-layer manufactured using the same material as the red color filter pattern, a second sub-layer manufactured using the same material as the green color filter pattern, and a third sub-layer manufactured using the same material as the blue color filter pattern. Here, the arrangement order of the first sub-layer, the second sub-layer, and the third sub-layer is not limited. For example, in the direction away from the substrate, the first sub-layer, the second sub-layer, and the third sub-layer are provided in this order. For example, in the direction away from the substrate, the first sub-layer, the third sub-layer, and the second sub-layer are provided in this order. For example, in the direction away from the substrate, the second sub-layer, the first sub-layer, and the third sub-layer are provided in this order. Of course, other cases are also assumed, specifically, it is determined according to the order of the processes for manufacturing the red color filter pattern, the green color filter pattern, and the blue color filter pattern.

[0086] In the embodiments of the present application, when the light-shielding layer ZG is provided, the light-shielding layer ZG shields at least some of the circuits and wirings in the peripheral region, thereby avoiding a decrease in the display effect due to light reflection by these. In this case, both the first test unit group T1 and the second test unit group T2 are located on the side away from the display region AA of the light-shielding layer ZG, and the orthographic projections of the first test unit group T1 and the second test unit group T2 on the substrate do not overlap with the orthographic projection of the light-shielding layer ZG on the substrate. In this way, the light-shielding layer ZG exposes each circuit test unit CP pad of the first test unit group T1 and the second test unit group T2, facilitates electrical connection with external test equipment, and reduces the probability of continuous confusion.

[0087] In some embodiments of the present application, as shown in FIGS. 1 to 7, the peripheral region includes a first peripheral sub-region B1 located on the side away from the binding sub-region B-D of the display region AA. Taking the case where the planar figure of the display area AA of the display panel according to the embodiment of the present application is rectangular as an example, the first peripheral sub-region B1 is located on the side away from the binding sub-region B-D of the display area AA. Since the first side L1 and the second side L2 are two opposite sides, the third side L3 and the fourth side L4 opposite to each other are included between the first side L1 and the second side L2, which means that a closed figure may be obtained. Here, the first peripheral sub-region B1 and the binding sub-region B-D are respectively located outside the two opposite sides of the display area AA. For example, the first peripheral sub-region B1 is located outside the third side L3 of the display area AA, and the binding sub-region B-D is located outside the fourth side L4 of the display area AA.

[0088] As shown in FIG. 3, a part of the circuit test unit CP pad of the first test unit group T1 is located in the first peripheral sub-region B1, and another part of the circuit test unit CP pad of the first test unit group T1 is located in a region close to the first side L1 of the peripheral region. A part of the circuit test unit CP pad of the second test unit group T2 is located in the first peripheral sub-region B1, and another part of the circuit test unit CP pad of the second test unit group T2 is located in a region close to the second side L2 of the peripheral region.

[0089] In addition, in the embodiment of the present application, expressions such as "a part, another part" do not necessarily mean only including two parts, but may further include a third part, a fourth part, etc., and specifically, it is determined according to the design.

[0090] In some embodiments, as shown in FIG. 3, the number of circuit test unit CP pads located in the first peripheral sub-region B1 of the first test unit group T1 is equal to the number of circuit test unit CP pads located in the region close to the first side L1 of the peripheral region of the first test unit group T1. The number of circuit test unit CP pads located in the first peripheral sub-region B1 of the second test unit group T2 is equal to the number of circuit test unit CP pads located in the region close to the second side L2 of the peripheral region of the second test unit group T2.

[0091] In some other embodiments, the number of circuit test unit CP pads located in the first peripheral sub-region B1 of the first test unit group T1 may be greater than the number of circuit test unit CP pads located in the region close to the first side L1 of the peripheral region of the first test unit group T1, and the number of circuit test unit CP pads located in the first peripheral sub-region B1 of the second test unit group T2 may be configured to be greater than the number of circuit test unit CP pads located in the region close to the second side L2 of the peripheral region of the second test unit group T2. In this case, in the left region of the display area AA (the region close to the first side L1 of the peripheral region) and the right side of the display area AA (the region close to the second side L2 of the peripheral region), a larger design space for arranging the GOA circuit, EOA circuit, and various signal lines can be achieved. Here, the signal lines may include power lines, ground lines, clock signal lines, and the like.

[0092] In some embodiments of the present application, each circuit test unit CP pad of the first test unit group T1 is arranged in an L shape, and each of the circuit test unit CP pads of the second test unit group T2 is arranged in an L shape.

[0093] In some embodiments, the connection line of the geometric centers of each circuit test unit CP pad of the first test unit group T1 may be two intersecting line segments. Here, although the angle formed by these two intersecting line segments is not limited, as an example, the range of this angle may be 0° to 180°, for example, 90°, 85°, or 80°.

[0094] The connection line of the geometric centers of each circuit test unit CP pad of the second test unit group T2 may also be two intersecting line segments, and the angle formed by these two line segments is the same as the above angle. As an example, the angle formed by the connection line of the geometric centers of each circuit test unit CP pad of the first test unit group T1 and the angle formed by the connection line of the geometric centers of each circuit test unit CP pad of the second test unit group T2 may be the same.

[0095] In some embodiments, the connecting lines of the geometric centers of the circuit test unit CP pads of each circuit test unit in the first test unit group T1 and the connecting lines of the geometric centers of the circuit test unit CP pads of each circuit test unit in the second test unit group T2 may both be arc lines. However, here, the radians of the above arc lines are not limited.

[0096] As an example, the arc lines formed by the connecting lines of the geometric centers of the circuit test unit CP pads of each circuit test unit in the first test unit group T1 and the arc lines formed by the connecting lines of the geometric centers of the circuit test unit CP pads of each circuit test unit in the second test unit group T2 may be distributed symmetrically with respect to a mirror plane.

[0097] In an exemplary embodiment, as shown in FIG. 3, between the circuit test unit CP pads located in the first peripheral sub-region B1 of the first test unit group T1 and the circuit test unit CP pads located in a region close to the first side L1 of the peripheral region of the first test unit group T1, an island pattern for alignment may be provided when manufacturing the circuit test unit CP pads. Between the circuit test unit CP pads located in the first peripheral sub-region B1 of the second test unit group T2 and the circuit test unit CP pads located in a region close to the second side L2 of the peripheral region of the second test unit group T2, an island pattern for alignment and marking may be provided.

[0098] The same test unit group is located in two different regions respectively. By providing one island pattern for alignment between these two regions, one island pattern can be provided to save the design space, while improving the alignment accuracy and reducing the difficulty of the manufacturing process.

[0099] In addition, in the structure shown in FIG. 3, in actual application, when manufacturing the circuit test unit CP pad, if the island pattern corresponding to the first test unit group T1 is used, the island pattern of the second test unit group T2 may be used as an alignment reference. Similarly, when the island pattern corresponding to the second test unit group T2 is used, the island pattern of the first test unit group T1 may be used as an alignment reference. In this way, the design space can be saved and the alignment accuracy can be improved.

[0100] Of course, the island patterns for alignment and marking may be provided at both ends of the same test unit group. Understandably, in this case, two island patterns for alignment and marking are provided for one test unit group.

[0101] In some embodiments of the present application, as shown in FIGS. 1, 2, and 4 to 6, the geometric centers of the circuit test unit CP pads of the first test unit group T1 are on the same line segment, and the geometric centers of the circuit test unit CP pads of the second test unit group T2 are on the same line segment.

[0102] Here, there is no limitation on whether the connecting line of the geometric centers of the circuit test unit CP pads of the first test unit group T1 and the connecting line of the geometric centers of the circuit test unit CP pads of the second test unit group T2 are the same line, intersect, or are parallel.

[0103] In some embodiments, as shown in FIG. 1, the connecting line of the geometric centers of the circuit test unit CP pads of the first test unit group T1 and the connecting line of the geometric centers of the circuit test unit CP pads of the second test unit group T2 are on the same line.

[0104] In some other embodiments, as shown in FIGS. 2 and 4, the connecting line of the geometric centers of the circuit test unit CP pads of the first test unit group T1 and the connecting line of the geometric centers of the circuit test unit CP pads of the second test unit group T2 are parallel.

[0105] In yet another embodiment, as shown in FIGS. 5 and 6, the connection lines of the geometric centers of the circuit test unit CP pads of each circuit test unit in the first test unit group T1 and the connection lines of the geometric centers of the circuit test unit CP pads of each circuit test unit in the second test unit group T2 may intersect.

[0106] In some embodiments of the present application, as shown in FIGS. 4, 5, and 6, each circuit test unit CP pad of the first test unit group T1 is located in a region close to the first side L1 of the peripheral region, and each circuit test unit CP pad of the second test unit group T2 is located in a region close to the second side L2 of the peripheral region.

[0107] In some embodiments of the present application, as shown in FIGS. 4, 5, and 6, the first test unit group T1 and the second test unit group T2 each include a first end close to the binding sub-region B-D and a second end away from the binding sub-region B-D, and the minimum distance from the first end to the display region AA in a direction perpendicular to the first direction (for example, the OA1 direction) is greater than or equal to the minimum distance from the second end to the display region AA in a direction perpendicular to the first direction.

[0108] In some embodiments, as shown in FIG. 4, the minimum distance from each circuit test unit CP pad to the edge of the display region AA is equal.

[0109] In some other embodiments, as shown in FIGS. 5 and 6, in the first direction (for example, the OA1 direction), the minimum distance from each circuit test unit CP pad to the edge of the display region AA gradually decreases.

[0110] In yet another embodiment, in the first direction (for example, the OA1 direction), the minimum distance from each circuit test unit CP pad to the edge of the display region AA gradually increases.

[0111] In some embodiments of the present application, as shown in FIGS. 5 and 6, the orthographic projection pattern of the circuit test unit CP pad on the substrate of the display panel includes a first edge, and the first edge is provided near the first side L1 of the display area AA or near the second side L2 of the display area AA. As an example, as shown in FIG. 6, the first edges of each circuit test unit CP pad all extend in a first direction (for example, the OA1 direction). In this case, the first edges of each circuit test unit CP pad in the same group of circuit test unit groups have the same extension direction, and each first edge may be on the same line.

[0112] As an example, as shown in FIG. 5, the extension directions of the first edges of each circuit test unit CP pad all intersect the first direction (for example, the OA1 direction). In this case, the first edges of each circuit test unit group in the same group of circuit test unit groups may intersect.

[0113] In actual applications, according to the arrangement of circuits and wirings provided in the area located on the first side L1 of the peripheral area and the area located on the second side L2 of the peripheral area, the arrangement positions of each circuit test unit CP pad that contribute to space saving may be determined.

[0114] In some embodiments of the present application, as shown in FIGS. 1 and 2, each circuit test unit CP pad of the first test unit group T1 and the second test unit group T2 is all located in the first peripheral sub-area B1, and the circuit test unit CP pads of the same set are arranged in a direction perpendicular to the first direction (for example, the OA1 direction). As shown in FIG. 2, the first test unit group T1 and the second test unit group T2 are arranged in the first direction (for example, the OA1 direction). Alternatively, as shown in FIG. 1, the first test unit group and the second test unit group are arranged perpendicular to the first direction.

[0115] In some embodiments of the present application, each circuit test unit CP pad is arranged in mirror symmetry.

[0116] In an exemplary embodiment, when each circuit test unit CP pad is arranged in a mirror-symmetrical manner, its axis of symmetry (a virtual concept, not actually existent) extends in the first direction (e.g., the OA1 direction).

[0117] In this way, the display panel has circuit test unit CP pads provided symmetrically, thereby simplifying the design, reducing the design difficulty, and improving the appearance of the display panel.

[0118] In some embodiments of the present application, as shown in FIGS. 1 and 2, in a direction parallel to the plane in which the substrate exists, the minimum distance from the circuit test unit CP pads of the first test unit group T1 and the second test unit group T1 to the light-shielding layer ZG is less than the minimum distance from the binding terminal (not shown) of the binding sub-region B-D to the light-shielding layer ZG. In this case, the size of the portion of the light-shielding layer ZG located outside the third side L3 of the display region AA in the first direction (e.g., the OA1 direction) is less than the size of the portion of the light-shielding layer ZG located outside the fourth side L3 of the display region AA in the first direction (e.g., the OA1 direction).

[0119] Note that in the embodiments of the present application, expressions such as "a direction parallel to the plane in which the substrate exists" mean that since the thickness of the substrate is small, its thickness is ignored, and for the convenience of explanation, the two-dimensional substrate is regarded as a two-dimensional plane. Actually, the substrate is not a two-dimensional plane, and the above is only for explanation. Since the related expressions above and below have the same meaning, they will not be described in detail here.

[0120] In some embodiments of the present application, as shown in FIGS. 1 to 7, the display panel includes at least one third test unit group T3, the third test unit group T3 includes a plurality of transistor test units TEG, and the third test unit group T3 is located in the first peripheral sub-region B1. The distance from the transistor test unit TEG to the light-shielding layer ZG is greater than or equal to the distance from the circuit test unit CP pad to the light-shielding layer ZG.

[0121] In some embodiments, as shown in FIGS. 1 and 2, the distance from the transistor test unit TEG to the light shielding layer ZG is greater than the distance from the circuit test unit CP pad to the light shielding layer ZG.

[0122] In some other embodiments, the distance from the transistor test unit TEG to the light shielding layer ZG is equal to the distance from the circuit test unit CP pad to the light shielding layer ZG.

[0123] As an example, the plurality of transistor test units TEG of one third test unit group T3 are divided into two parts, one part is provided on the left side of each circuit test unit CP pad shown in FIG. 2, and the other part is provided on the right side of each circuit test unit CP pad shown in FIG. 2. Also, the plurality of transistor test units TEG of this third test unit group T3 are all arranged side by side with the first test unit group T1.

[0124] Also, the plurality of transistor test units TEG of another third test unit group T3 are divided into two parts, one part is provided on the left side of each circuit test unit CP pad shown in FIG. 2, and the other part is provided on the right side of each circuit test unit CP pad shown in FIG. 2. Also, the plurality of transistor test units TEG of this third test unit group T3 are all arranged side by side with the second test unit group T2. Here, only the arrangement positions of each circuit test unit CP pad as shown in FIG. 2 are referred to, and the conventional third test unit group T3 in FIG. 2 is not considered.

[0125] Note that the above transistor test unit TEG tests the electrical characteristics of each transistor in the driving circuit of the display panel, and after the manufacturing of each transistor is completed, stably ensures its electrical characteristics. When electrical abnormalities or instabilities occur in a specific transistor, adjustments and repairs are performed on the electrical characteristics of the transistor as needed.

[0126] In some embodiments of the present application, as shown in FIGS. 1 and 2, the third test unit group T3 is located on the side away from all the display areas AA of the circuit test unit CP pad, there is a gap between the third test unit group T3 and the light-shielding layer ZG, and both the first test unit group T1 and the second test unit group T2 are located in the gap.

[0127] In some embodiments of the present application, as shown in FIGS. 1, 2, and 7, the display panel includes two third test unit groups T3, and the two third test unit groups T3 are arranged in a direction perpendicular to the first direction, for example, the OA1 direction. The first peripheral sub-region B1 includes a code pattern located between the two third test unit groups T3. The minimum distance d5 from the code pattern to the light-shielding layer ZG is equal to or greater than the minimum distance d6 from the transistor test unit TEG to the light-shielding layer ZG.

[0128] As an example, the code pattern, for example, the ID, is used to distinguish different display panels produced in the same batch and is similar to the identity of the display panel. The code pattern includes at least one of numbers, letters, symbols, and patterns.

[0129] In some embodiments, as shown in FIGS. 1 and 2, the minimum distance d5 from the code pattern to the light-shielding layer ZG is greater than the minimum distance d6 from the transistor test unit TEG to the light-shielding layer ZG. Since the mark space is limited, the marks d5 and d6 are not shown in FIGS. 1 and 2, but the marks in FIG. 7 can be referred to.

[0130] In some embodiments, as shown in FIG. 7, the minimum distance d5 from the code pattern to the light-shielding layer ZG is greater than the minimum distance d6 from the transistor test unit TEG to the light-shielding layer ZG.

[0131] In the embodiments of the present application, by configuring the minimum distance d5 from the code pattern to the light-shielding layer ZG to be equal to or greater than the minimum distance d6 from the transistor test unit TEG to the light-shielding layer ZG, the code pattern is placed as far as possible from the circuit test unit CP pad, so that when the code pattern is manufactured, the heat from the laser does not negatively affect the circuit test unit CP pad, thereby improving the stability of the circuit test unit CP pad.

[0132] In some embodiments of the present application, as shown in FIGS. 1 to 7, the peripheral region further includes a second peripheral sub-region B-F located between the binding sub-region B-D and the display region AA, and the orthographic projection of the light-shielding layer ZG on the substrate is within the region other than the binding sub-region B-D in the peripheral region. As shown in FIG. 6, in the first direction, for example, the OA1 direction, the distance d7 from the portion of the outer contour of the light-shielding layer ZG within the first peripheral sub-region B1 to the edge of the display region AA is less than the distance d8 from the portion of the outer contour of the light-shielding layer ZG within the second peripheral sub-region B-F to the edge of the display region AA in the first direction, for example, the OA1 direction.

[0133] In some embodiments, the second peripheral sub-region B-F may be a fan-out sub-region, and fan-out wirings are provided in the fan-out sub-region. The fan-out wirings electrically connect the data lines (Data) in the display region AA and the binding terminals in the binding sub-region B-D.

[0134] In some other embodiments, the second peripheral sub-region B-F may not be provided with fan-out wirings (not a fan-out sub-region). Instead, through metal holes, such as tungsten holes, between the multilayer conductive layers located in the array substrate of the display panel, the data lines (Data) in the display region AA and the binding terminals in the binding sub-region B-D are electrically connected, thereby reducing the size of the peripheral region and facilitating the manufacture of narrow-bezel display products.

[0135] In the embodiment of the present application, the light-shielding layer ZG covers the second peripheral sub-region B-F and extends to the edge of the binding sub-region B-D, and the orthographic projection of the light-shielding layer ZG on the substrate does not overlap with the orthographic projection of the binding sub-region on the substrate.

[0136] In the embodiment of the present application, as long as the manufacturing process permits, the light-shielding layer ZG is made to cover as much as possible the regions other than the binding terminals (binding sub-regions) in the peripheral region, the circuit test unit CP pad, and the transistor test unit TEG. Thereby, light reflection caused by the wiring in the peripheral region is reduced, and the display effect is improved. Also, since the binding terminals (binding sub-regions), the circuit test unit CP pad, and the transistor test unit TEG are to be electrically connected to other members later, these are exposed and not covered by the light-shielding layer ZG.

[0137] In some embodiments of the present application, as shown in FIGS. 1 to 7, the shape of the orthographic projection of the light-shielding layer ZG on the substrate includes a rectangle having four fillets. The radii of curvature of the two fillets closer to the rectangular binding sub-region B-D are larger than the radii of curvature of the two fillets closer to the first peripheral sub-region B1 of the rectangle.

[0138] In the embodiment of the present application, by configuring the radii of curvature of the two fillets closer to the rectangular binding sub-region B-D to be larger than the radii of curvature of the two fillets closer to the first peripheral sub-region B1 of the rectangle, the light-shielding layer ZG covers more regions of the second peripheral sub-region B-F and shields the wiring in the second peripheral sub-region B-F as much as possible. Thereby, light reflection caused by the wiring is avoided, and the display effect of the display panel is improved.

[0139] In some embodiments of the present application, as shown in FIGS. 1 to 7, the display panel includes a cover CG that covers a part of the region of the light-shielding layer ZG and the display region AA, and the outer contour of the orthographic projection on the substrate is within the orthographic projection of the light-shielding layer ZG on the substrate. The four apex angles of the outer contour of the orthographic projection of the cover CG on the substrate are respectively located at the four fillets.

[0140] In the embodiments of the present application, in order to make the structure other than the cover CG of the display panel visible, only the outer contour of the cover CG is shown in the drawings for the cover CG in the drawings. In an exemplary embodiment, the material of the cover CG may be a light-transmissive material, such as glass or a light-transmissive resin.

[0141] In some embodiments of the present application, as shown in FIGS. 1 to 7, the area of the region that does not overlap with the cover CG among the portions located in the first peripheral sub-region B1 of the light-shielding layer ZG is less than the area of the region that does not overlap with the cover CG among the portions located in the second peripheral sub-region B-F of the light-shielding layer ZG.

[0142] In an exemplary embodiment, as shown in FIG. 6, the region that does not overlap with the cover CG among the portions located in the first peripheral sub-region B1 of the light-shielding layer ZG may be the region marked as Area1, and the region that does not overlap with the cover CG among the portions located in the second peripheral sub-region B-F of the light-shielding layer ZG may be the region marked as Area2.

[0143] In some embodiments of the present application, as shown in FIG. 6, in the direction parallel to the plane where the substrate exists, the size d9 of the display area AA of the region of the cover CG that overlaps with the light-shielding layer ZG in the direction pointing to the peripheral region is larger than the size d10 of the circuit test unit CP pad in the first direction (for example, the OA1 direction).

[0144] In an exemplary embodiment, the size of the display area AA of the region that overlaps with the portion located in the first binding sub-region B1 of the light-shielding layer ZG of the cover CG in the direction pointing to the peripheral region, the size of the display area AA of the region that overlaps with the portion located in the second peripheral sub-region B-F of the light-shielding layer ZG of the cover CG in the direction pointing to the peripheral region, the size of the display area AA of the region that overlaps with the portion close to the first side L1 of the peripheral region of the light-shielding layer ZG of the cover CG in the direction pointing to the peripheral region, and the size of the display area AA of the region that overlaps with the portion located on the second side L2 of the peripheral region of the light-shielding layer ZG of the cover CG in the direction pointing to the peripheral region are all equal.

[0145] In some embodiments of the present application, the area of the orthographic projection pattern of the circuit test unit CP pad on the substrate is less than or equal to the area of the orthographic projection pattern of the B-D binding terminal (not shown) of the binding sub-region on the substrate.

[0146] In an exemplary embodiment, the size of the display area AA of the orthographic projection pattern of the binding terminal on the substrate in the direction pointing to the peripheral area is larger than the size of the display area AA of the orthographic projection pattern of the circuit test unit CP pad on the substrate in the direction pointing to the peripheral area.

[0147] For example, the size of the display area AA of the orthographic projection pattern of the binding terminal on the substrate in the direction pointing to the peripheral area may be 5 to 20 times the size of the display area AA of the orthographic projection pattern of the circuit test unit CP pad on the substrate in the direction pointing to the peripheral area.

[0148] In actual application, after the test of the display panel is completed and it is used by the user for the display product, the circuit test unit CP pad is not used. Therefore, when providing the circuit test unit CP pad, within the range permitted by the test process and the manufacturing process, the size of the circuit test unit CP pad can be made as small as possible, thereby reducing the occupied space of the circuit test unit CP pad, improving the utilization rate of the design space of the peripheral area, and facilitating the manufacture of narrow bezel products.

[0149] In some embodiments of the present application, the number of circuit test unit CP pads is more than the number of binding terminals.

[0150] As an example, the number of circuit test unit CP pads is 2 times or more the number of binding terminals.

[0151] In the embodiments of the present application, the number of circuit test unit CP pads is configured to be larger than the number of binding terminals. When detecting the driving circuit of the array substrate by the circuit test unit CP pads, it is possible to more accurately detect whether there is an abnormality in the circuit. Furthermore, it is possible to accurately detect the area and position of the device in which the abnormality of the driving circuit has occurred, which is advantageous for repairing the abnormality before manufacturing the display panel into a display device, and improving the yield and quality of the display product.

[0152] In some embodiments of the present application, the display panel further includes a detection unit. The detection unit includes a plurality of auxiliary sub-pixels, is located in an area close to the first side L1 of the peripheral area, and / or is located in an area close to the second side L2 of the peripheral area. The structure of the auxiliary sub-pixels is the same as that of the sub-pixels in the display area AA, and the light-shielding layer ZG covers the detection unit.

[0153] The situation where the auxiliary sub-pixels are located in an area close to the first side L1 of the peripheral area and / or the auxiliary sub-pixels are located in an area close to the second side L2 of the peripheral area includes the following cases. 1. All the auxiliary sub-pixels are located in an area close to the first side L1 of the peripheral area. 2. All the auxiliary sub-pixels are located in an area close to the second side L2 of the peripheral area. 3. Some of the auxiliary sub-pixels are located in an area close to the first side L1 of the peripheral area, and the remaining auxiliary sub-pixels are located in an area close to the second side L2 of the peripheral area.

[0154] In some embodiments, the emission colors of each auxiliary sub-pixel may be the same. For example, all the emission colors are white, or all the emission colors are blue. In some other embodiments, the emission colors of each auxiliary sub-pixel may not be exactly the same. For example, the emission color of some of the auxiliary sub-pixels is red, the emission color of some of the auxiliary sub-pixels is green, and the emission color of some of the auxiliary sub-pixels is blue.

[0155] In the embodiments of the present application, a plurality of auxiliary sub-pixels are provided in the peripheral region, and since the structure of the auxiliary sub-pixels is the same as the structure of the sub-pixels in the display region AA, by monitoring the state of the auxiliary sub-pixels of the detection unit, the light emission status of the sub-pixels in the display region can be determined. Specifically, in the OLED display panel, by monitoring the temperature of the auxiliary sub-pixels of the detection unit, the difference in the temperatures of the auxiliary sub-pixels of various colors is determined. Since the light emission efficiency of the OLED sub-pixels is sensitive to temperature, related parameters such as the driving voltage can be adjusted according to the temperature difference, and the display effect of the display panel can be improved.

[0156] In some embodiments of the present application, as shown in FIG. 7, the display panel further includes four mark patterns BJ located on the side away from the substrate of the light-shielding layer ZG, and the orthographic projection of the apex angle of the cover CG on the substrate at least partially overlaps with the orthographic projection of the mark pattern BJ on the substrate.

[0157] Note that the mark pattern BJ is an alignment mark for attaching the cover CG, and it improves the alignment accuracy of the cover CG.

[0158] For the sake of distinction, the mark pattern BJ described in the embodiments of the present application is an alignment mark for attaching the cover CG, and the island pattern described in the embodiments of the present application is an alignment mark when manufacturing the circuit test unit CP pad.

[0159] The fact that the orthographic projection of the apex angle of the cover CG on the substrate at least partially overlaps with the orthographic projection of the mark pattern BJ on the substrate includes, but is not limited to, the following cases. 1. The orthographic projection of the apex angle of the cover CG on the substrate partially overlaps with the orthographic projection of the mark pattern BJ on the substrate. 2. The orthographic projection of the apex angle of the cover CG on the substrate completely overlaps with the orthographic projection of the mark pattern BJ on the substrate. In an embodiment of the present application, the orthogonal projection of the top corner of the cover CG on the substrate overlaps at least partially with the orthogonal projection of the mark pattern BJ on the substrate, thereby saving the design space of the mark pattern BJ and optimizing the design of the display panel.

[0160] An embodiment of the present application includes the display panel, and provides a display device that may further include a flexible circuit board FPC and a driving chip IC.

[0161] Alternatively, the display panel includes a display control unit, and the display device further includes a flexible circuit board FPC.

[0162] In an exemplary embodiment, when the substrate of the display panel is a silicon substrate, the array substrate of the silicon substrate of the display device can integrate the pixel driving circuit array, source driver, gate driver, emission control driver, oscillator (OSC), gamma register, and the integrated circuit of the display control unit on the same chip. In this case, an additional driving chip is not required, and the display panel is directly electrically connected to the flexible circuit board FPC, which is called One Chip technology. The display device manufactured by One Chip technology has a high integration degree but a small size, and can be applied to high-resolution display products, such as virtual reality (VR) or augmented reality (AR) near-eye displays.

[0163] In an exemplary embodiment, when the substrate of the display panel is a silicon substrate, the array substrate of the silicon substrate may also separate the analog circuit parts such as the pixel driving circuit array, Source driver, Gate driver, and Emission driver (i.e., the EOA unit group of the present application) from the OSC, Gamma register, Interface, and display control unit, and change the One Chip technology to Two Chip technology. In this case, the display panel is electrically connected to the flexible circuit board FPC and the driving chip IC respectively. Compared with the products of One Chip technology, such products have lower requirements for the manufacturing process and can reduce production costs by using low-tech processes.

[0164] The display device may be a flexible display device (referred to as a flexible screen), or a rigid display device (i.e., a display device that cannot be curved), but is not limited here. The display device may be an OLED (Organic Light-Emitting Diode) display device, or any product or component with a display function, such as a TV, digital camera, mobile phone, tablet terminal, etc. that includes an OLED. The display device has advantages such as good display effect, long lifespan, and high stability.

[0165] The embodiment of the present application provides a wearable device. As shown in FIGS. 8 to 11 and FIGS. 13 to 14, the wearable device includes two of the above-mentioned display devices, and further includes two annular first holders ZJ1 shown in FIG. 12. The display device is fixed to the first holder ZJ1, and the first holder ZJ1 covers the area where the light-shielding layer ZG is not provided in the peripheral area of the display panel. The circuit test unit CP pads of one display device and the circuit test unit CP pads of the other display device are provided in mirror symmetry.

[0166] In an exemplary embodiment, the binding terminals (binding sub-regions B-D), the circuit test unit CP pad, and the transistor test unit TEG need to be exposed and not covered by the light-shielding layer ZG because they are electrically connected to other members in a process after the display panel is manufactured in order to test the characteristics of the circuit or transistor. When the display panel is manufactured as a display device (at this time, the binding terminals have a flexible circuit board provided thereon and are not exposed), the test of the characteristics of the circuit or transistor is completed. However, light is reflected by this exposed portion of the circuit test unit CP pad and the transistor test unit TEG, resulting in a reduction in the display effect and a decline in the user experience. Therefore, when attaching the first holder ZJ1, the first holder ZJ1 should shield the exposed circuit test unit CP pad and the transistor test unit TEG, thereby avoiding light reflection and improving the display effect and the user experience.

[0167] In some embodiments of the present application, in order to enhance the shielding effect and avoid light reflection due to slits or the like between the first holder ZJ1 and the light-shielding layer ZG, the orthographic projection of the first holder ZJ1 on the substrate of the display panel is configured to overlap the orthographic projection of the light-shielding layer ZG on the substrate. In this way, the exposed circuit test unit CP pad and the transistor test unit TEG can be further shielded, thereby avoiding light reflection and improving the display effect and the user experience.

[0168] Also, by configuring each circuit test unit CP pad of one display device and each circuit test unit CP pad of another display device to be provided in a mirror-symmetrical manner, the display regions of the two display devices are provided as symmetrically as possible, thereby improving to some extent the problem of ghost images caused by the difference in the center points of the visual fields of the left and right eyes of the wearable device, and thereby improving the user experience.

[0169] In some embodiments of the present application, each circuit test unit CP pad of one display device and each circuit test unit CP pad of another display device are provided in mirror symmetry, and the display area of one display device and the display area of another display device are provided in mirror symmetry. Thereby, the problem of ghost images caused by the different center points of the visual fields of the left and right eyes of the wearable device can be improved to a certain extent, thereby improving the user experience.

[0170] In some embodiments of the present application, the inner contour of the orthographic projection of the substrate of the first holder ZJ1 is at least partially in contact with the outer contour of the orthographic projection of the substrate of the cover CG. In this way, at least a part of the outer edge of the cover CG is engaged on the inner contour of the first holder ZJ1 to play a fixing role.

[0171] In some embodiments, as shown in FIG. 12, the first holder ZJ1 further includes a stop portion 206, and the stop portion 206 contacts the back surface of the display device, thereby avoiding movement and looseness in a direction perpendicular to the plane where the substrate of the display device of the wearable device is located. The above-mentioned back surface refers to the surface opposite to the light-emitting surface.

[0172] In some embodiments, as shown in FIG. 12, the first holder ZJ1 further includes two first attachment members 204 and two second attachment members 205.

[0173] In some embodiments of the present application, it further includes a second holder configured to be wearable. When the wearable device is glasses, the second holder includes a main body portion ZJ2-1 shown in FIG. 13 and two temples connected to the main body portion ZJ2-1. A driving plate and two first holders ZJ1 are respectively fixed to the main body portion ZJ2-1 of the second holder, and the driving plate is electrically connected to the flexible circuit boards FPC of the two display devices respectively. The main body ZJ2-1 of the second holder shown in FIG. 13 includes a connecting member 209, two third attachment members 207, and two fourth attachment members 208. The second attachment member 205 of the first holder ZI1 is attached to and fixed to the third attachment member 207 of the second holder, and the first attachment member 204 of the first holder ZI1 is attached to and fixed to the fourth attachment member 208 of the second holder.

[0174] The above drive plate provides information such as image signals to the display device.

[0175] Here, the specific structure of the above attachment member is not limited. As an example, the first attachment member 204 and the third attachment member 207 shown in FIGS. 12 and 13 may both have an annular structure, and the second attachment member 205 and the fourth attachment member 208 shown in FIGS. 12 and 13 may both have a columnar structure.

[0176] In some embodiments, as shown in FIGS. 8 to 11, the two display panels are provided in mirror symmetry, and the geometric centers of the display areas AA of the two display panels and the geometric center of the main body ZJ2-1 of the second holder are on the same straight line. Hereinafter, the binding flexible circuit board 201 of the display panel is referred to as a display device.

[0177] Here, the shape and size of the above flexible circuit board 201 are not limited, and specifically, they may be determined according to the actual design. As an example, the shape of the flexible circuit board 201 may be rectangular or L-shaped.

[0178] In the embodiments of the present application, two display panels of the wearable device are provided in mirror symmetry, and the geometric centers of the display areas AA of the two display panels and the geometric center of the main body ZJ2-1 of the second holder are on the same straight line. When the user uses this device, the centers of the visual fields of the user's left eye and the user's right eye are on the same straight line. Compared with the device according to the related art shown in FIG. 16, the problem of ghost images caused by different centers of the visual fields of the left and right eyes of the wearable device can be improved to a certain extent, thereby improving the user experience.

[0179] In some embodiments, as shown in FIGS. 8-9, the two display devices are provided in mirror symmetry, and the display device includes a display panel and a flexible circuit board 201.

[0180] In an exemplary embodiment, the flexible circuit board 201 is provided with a connection interface 202 (also known as a connector) for electrically connecting the connection interface and an external circuit.

[0181] In some embodiments, as shown in FIGS. 10-11, the two flexible circuit boards 201 are provided in central symmetry with the geometric center of the main body of the second holder as the symmetry point.

[0182] It should be noted that FIGS. 8-11 are all schematic diagrams of the intermediate structure of the wearable device.

[0183] FIGS. 14 and 15 show schematic structural diagrams of two types of wearable devices. Here, the wearable device further includes a driving plate, and the driving plate may be provided at the position of Mark 1, Mark 2, or Mark 3 and is electrically connected to the two flexible circuit boards 201 respectively.

[0184] As an example, by providing the drive plate at the position of Mark 1 of the wearable device, the balance of the device is maintained. In this case, the two flexible circuit boards 201 may be bent along the direction of the arrow mark as shown in FIG. 10 or FIG. 11, and may be electrically connected to the drive plate provided at the position of Mark 1. In this case, the two flexible circuit boards 201 are provided symmetrically about the geometric center of the second holder as the center of symmetry.

[0185] In an exemplary embodiment, the wearable device further includes a first lens and a second lens provided on the light-emitting side of the display device. For the related content of the first lens and the second lens, reference may be made to the related art, but it will not be described in detail here.

[0186] In addition, in the wearable devices shown in FIGS. 14 and 15, the light-emitting surfaces of the two display devices are both facing the position of the human eye. Also, at the temple positions of the wearable devices shown in FIGS. 14 and 15, two wirings electrically connected to the two flexible circuit boards are respectively provided. Among them, the component 4 is used to connect the two wirings in parallel and electrically connect to an external device, and the external device is used to provide a control signal to the wearable device.

[0187] The above are only specific embodiments of the present application, and the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present application shall be included within the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. a display area and a peripheral area surrounding the display area, the peripheral area including a binding sub-area located on one side of the display area; an area in the peripheral area other than the binding sub-area includes a first test unit group and a second test unit group, the first test unit group and the second test unit group each including at least one circuit test unit; the display area includes a first side edge and a second side edge extending along a first direction and arranged opposite to each other, the first direction being a direction in which the binding sub-area points to the display area; A display panel, wherein the maximum distance from the first test unit group to the first side edge in a direction perpendicular to the first direction is equal to the maximum distance from the second test unit group to the second side edge in a direction perpendicular to the first direction.

2. 2. The display panel of claim 1, wherein a minimum distance from the first test unit group to the first side edge in a direction perpendicular to the first direction is equal to a minimum distance from the second test unit group to the second side edge in a direction perpendicular to the first direction.

3. an inner contour of an area other than the binding sub-area in the peripheral area, when orthogonally projected onto a substrate of the display panel, includes a light-shielding layer that contacts an edge of the display area; 3. The display panel of claim 2, wherein the first test unit group and the second test unit group are both located on the side away from the display area of the light-shielding layer, and the orthogonal projections of the first test unit group and the second test unit group on the substrate do not overlap with the orthogonal projections of the light-shielding layer on the substrate.

4. the peripheral region includes a first peripheral sub-region located on a side of the display region away from the binding sub-region; some of the circuit test units of the first test unit group are located in the first peripheral sub-region, and other some of the circuit test units of the first test unit group are located in an area close to the first side edge of the peripheral region; 4. The display panel of claim 3, wherein some of the circuit test units of the second test unit group are located in the first peripheral sub-region, and other some of the circuit test units of the second test unit group are located in an area close to the second side edge of the peripheral region.

5. a connection line of the geometric center of each of the circuit test units in the first test unit group and a connection line of the geometric center of each of the circuit test units in the second test unit group each constitute two intersecting line segments; Alternatively, the connection line of the geometric center of each of the circuit test units of the first test unit group and the connection line of the geometric center of each of the circuit test units of the second test unit group are each an arc line.

6. 4. The display panel according to claim 3, wherein the geometric centers of the circuit test units in the first test unit group are on the same line segment, and the geometric centers of the circuit test units in the second test unit group are on the same line segment.

7. 7. The display panel of claim 6, wherein each of the circuit test units of the first test unit group is located in an area close to the first side edge of the peripheral area, and each of the circuit test units of the second test unit group is located in an area close to the second side edge of the peripheral area.

8. the first group of test units and the second group of test units each include a first end proximate to the binding sub-area and a second end remote from the binding sub-area; 8. The display panel of claim 7, wherein a minimum distance between the first end and the display area in a direction perpendicular to the first direction is equal to or greater than a minimum distance between the second end and the display area in a direction perpendicular to the first direction.

9. each of the circuit test units of the first test unit group and the second test unit group is located in the first peripheral sub-region, and the circuit test units of the same group are arranged perpendicular to the first direction; the first test unit group and the second test unit group are arranged along the first direction, The display panel according to claim 6 , wherein the first test unit group and the second test unit group are arranged perpendicular to the first direction.

10. A display panel as described in claim 9, wherein in a direction parallel to the plane on which the substrate exists, the minimum distance from the circuit test units of the first test unit group and the second test unit group to the light-shielding layer is less than the minimum distance from the binding terminals in the binding sub-region to the light-shielding layer.

11. at least one third test unit group including a plurality of transistor test units and located in the first peripheral sub-region; The display panel according to claim 9 , wherein the distance from the transistor test unit to the light-shielding layer is equal to or greater than the distance from the circuit test unit to the light-shielding layer.

12. The display panel described in claim 11, wherein the third test unit group is located on the side away from the display area of all the circuit test units, there is a gap between the third test unit group and the light-shielding layer, and the first test unit group and the second test unit group are both located in the gap.

13. 13. The display panel of claim 12, wherein the display panel includes two third test unit groups arranged perpendicular to the first direction, the first peripheral sub-region includes a code pattern located between the two third test unit groups, and a minimum distance from the code pattern to the light-shielding layer is equal to or greater than a minimum distance from the transistor test unit to the light-shielding layer.

14. Each of the circuit test units is arranged in mirror symmetry, the peripheral region further includes a second peripheral subregion located between the binding subregion and the display region, and the orthogonal projection of the light-shielding layer on the substrate is within an area of the peripheral region other than the binding subregion; 5. The display panel of claim 4, wherein the distance in the first direction from a portion of the outer contour of the light-shielding layer that is within the first peripheral sub-region to the edge of the display region is less than the distance in the first direction from a portion of the outer contour of the light-shielding layer that is within the second peripheral sub-region to the edge of the display region.

15. a shape of the light-shielding layer when orthogonally projected onto the substrate includes a rectangle having four fillets; The display panel of claim 14 , wherein the radius of curvature of the two fillets closer to the binding sub-region of the rectangle is greater than the radius of curvature of the two fillets closer to the first peripheral sub-region of the rectangle.

16. a cover that covers a part of the area of the light-shielding layer and the display area, and an outer contour of the orthogonal projection of the light-shielding layer on the substrate is within the orthogonal projection of the light-shielding layer on the substrate; The display panel according to claim 15 , wherein four apex angles of an outer contour of the cover when orthogonally projected onto the substrate are located at four of the fillets, respectively.

17. 17. The display panel of claim 16, wherein an area of a portion of the light-shielding layer located in the first peripheral sub-region that does not overlap with the cover is less than an area of a portion of the light-shielding layer located in the second peripheral sub-region that does not overlap with the cover.

18. 11. The display panel according to claim 10, wherein an area of the orthographic projection of the circuit test unit on the substrate is equal to or less than an area of the orthographic projection of the binding terminal on the substrate.

19. The display panel according to any one of claims 1 to 18, a flexible circuit board and a driver chip; or a display control unit; The display device further includes a flexible circuit board.

20. A wearable device comprising two display devices according to claim 19, and further comprising two ring-shaped first holders, wherein the display devices are fixed to the first holders, the first holders cover areas of the peripheral region of the display panel where no light-shielding layer is provided, and each circuit test unit of one of the display devices and each circuit test unit of the other of the display devices are arranged in mirror symmetry.

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