Device for integrated front-end circuit

Abstract

The wireless front-end can include multiple circuits such as a power amplifier (PA), a low-noise amplifier (LNA), and an RF switch. To reduce the size of the front-end and improve its performance, various circuits of the front-end can all be formed from the same epitaxial material structure and include N-polarity III-N transistors monolithically integrated on one chip. Since different performance requirements for different transistors exist among different circuits, parameters such as gate length, distance between the gate and the channel, and distance between the surface and the channel in the access region of the device can be varied to meet the required performance requirements.

Description

Technical Field

[0001] [Technical Field] The present disclosure relates to semiconductor material structures and devices, particularly devices formed from N-polar III-nitride layers.

Background Art

[0002] [Background] III-nitride semiconductor devices such as III-N high electron mobility transistors (HEMTs) are typically formed from III-N material structures grown on a substrate in a group-III polar orientation (i.e., the

[0001] direction). An example of a group-III polar III-N HEMT device 100 is shown in FIG. 1. In device 100, III-N layers 111, 112, and 113 are formed on a suitable substrate 110 such as silicon (Si), silicon carbide (SiC), sapphire, or GaN in a group-III polar orientation (i.e., the

[0001] direction as shown). III-N layer 111 is a buffer layer and can be formed of AlN, AlGaN, GaN, or combinations thereof. III-N layer 112 is a channel layer and is, for example, GaN. III-N layer 113 is a barrier layer and is, for example, AlGaN. The composition of III-N layers 112 and 113 is selected such that a two-dimensional electron gas (2DEG) channel 120 is induced in the III-N channel layer 112 extending from source 121 to drain 122. Gate insulator 132 is formed on III-N barrier layer 113, and gate 123 is formed on gate insulator 132. The voltage applied to gate 123 with respect to source 121 modulates the charge of 2DEG 120 directly below gate 123, thereby modulating the current flowing between source 121 and drain 122 during operation of the device.

[0003] A nitrogen-polarity (N-polarity) III-N HEMT device 200 (i.e., a device in which III-N layers 211, 213, and 212 are oriented in the [000-1] direction on a substrate 210) is shown in FIG. 2. In device 200, a III-N channel layer 212 (i.e., the layer containing the 2DEG channel 220) is formed on a III-N barrier layer 213 (thus, in an N-polarity III-N HEMT, the barrier layer is often referred to as the “back barrier”). The gate insulator 232 can serve to reduce gate leakage. In an N-polarity device, since the III-N barrier layer (e.g., layer 213) is not between the gate 223 and the channel, gate leakage may be more persistent in the N-polarity device compared to a group-III-polarity device. Depending on the specific device shape, the N-polarity III-N transistor may have characteristics and features suitable for various circuit applications. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0004] [Summary] In a first aspect, a semiconductor device includes a semiconductor wafer including a III-N material structure, the III-N material structure including a III-N back barrier and a III-N channel layer on an N surface of the III-N back barrier, the III-N channel layer having a group-III surface adjacent to the III-N back barrier and an N surface opposite the group-III surface, the III-N back barrier having a larger bandgap than the III-N channel layer. The semiconductor device includes a first transistor in a first region of the semiconductor wafer, the first transistor including a first portion of the III-N back barrier, a first portion of the III-N channel layer having a first 2DEG channel, the first portion of the III-N channel layer having a first recess adjacent to its N surface, the first recess having a first bottom surface, a first gate at least partially present in the first recess, and a first source and a first drain, the first gate being between the first source and the first drain. The semiconductor device includes a second transistor in a second region of the semiconductor wafer, the second transistor including a second portion of the III-N back barrier, a second portion of the III-N channel layer having a second 2DEG channel, the second portion of the III-N channel layer having a second recess adjacent to its N surface, the second recess having a second bottom surface, a second gate at least partially present in the second recess, and a second source and a second drain, the second gate being between the second source and the second drain. A thickness of the first portion of the III-N channel layer in a region between the first gate and the first drain is greater than 1.2 times a thickness of the second portion of the III-N channel layer in a region between the second gate and the second drain.

Brief Description of the Drawings

[0005]

Figure 1

[0006]

Figure 2

[0007]

Figure 3

[0008]

Figure 4

[0009]

Figure 5

[0010]

Figure 6A

Figure 6B

Figure 6C

Figure 6D

Figure 6E

[0011]

Figure 7

[0012]

Figure 8

[0013]

Figure 9A

Figure 9B

Figure 9C

Figure 9D

Figure 9E

[0014]

Figure 10

[0015]

Figure 11

[0016]

Figure 12A

Figure 12B

Figure 12C

[0017]

Figure 13

[0018]

Figure 14A

Figure 14B

[0019]

Figure 15

[0020]

Figure 16

[0021]

Figure 17

[0022]

Figure 18

[0023] Similar numbers in the figures represent similar elements.

Best Mode for Carrying Out the Invention

[0024] [Detailed Description]

[0025] A wireless front end typically includes multiple circuits that include both active transistor-based circuits and active diode-based circuits, as well as passive electromagnetic-based circuits and passive acoustic-based circuits. Examples of available transistor-based circuits include power amplifiers (PAs), low noise amplifiers (LNAs), switches (e.g., RF switches), active filters (e.g., N-path filters), frequency conversion circuits (such as frequency multipliers and mixers), and / or beamforming circuits, and the beamforming circuits include phase shifters, variable gain amplifiers or variable attenuators, and / or switched delay lines. Examples of available passive electromagnetic-based or passive acoustic-based circuits include filters (e.g., bandpass filters, highpass filters, or lowpass filters), multiplexing filters (e.g., diplexers, triplexers, n-plexers), and / or antennas. In the case of transistor-based circuits, each circuit includes transistors that are specially designed and configured to meet the performance requirements of a particular circuit. Since the performance requirements vary between different circuits, it is common to design and manufacture each circuit separately and then connect them to each other to form the front end. A block diagram showing an example of a transmit / receive (T / R) front end 300 connected to an antenna 308 is shown in FIG. 3. As shown, the T / R front end 300 includes a PA 302, an LNA 304, and a T / R switch 306.

[0026] In the front end 300 shown in FIG. 3, the PA 302 may be formed of or may include N-polarity III-N transistors having a first shape that provides optimal performance for the PA. The LNA 304 may be formed of or may include N-polarity III-N transistors having a second shape that provides optimal performance for the LNA. The switch 306 may be formed of or may include N-polarity III-N transistors having a third shape that provides optimal performance for the switch. As used herein, the term III-nitride or III-N materials, layers, devices, etc. refers to the stoichiometric formula Sc vB w Al x In y Ga z N a (D) b refers to a material or device composed of a compound semiconductor material that follows the formula. Here, v + w + x + y + z is approximately 1, where 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1; a + b is approximately 1, where 0.9 < a ≦ 1 and 0 ≦ b < 0.1; and (D) is any Group V element other than nitrogen. In an III-N transistor device, the channel through which current conducts may be included within one or more III-N layers of the device.

[0027] This specification describes a semiconductor device that includes transistors of two or more circuits (e.g., front-end circuits) monolithically integrated on a single semiconductor wafer. That is, a set of common semiconductor material layers, such as an N-polarity Group III nitride layer formed (e.g., by epitaxial growth) on a common substrate, is used to form the transistors of two or more circuits. The design and shape of each transistor may be optimized according to the particular circuit or portion of the circuit in which it is used. Optionally, the interconnecting metal that connects the transistors to each other or to other circuit components is also formed on the common semiconductor material layer. Integrating these transistors on a single wafer can reduce the total cost, shrink the size or footprint, and / or improve the front-end performance.

[0028] FIG. 4 is a plan view of a semiconductor device 400 formed from a semiconductor wafer 410. The semiconductor wafer 410 includes a plurality of III-N semiconductor layers (shown in FIG. 5) that form a III-N material structure. The semiconductor device 400 includes a first transistor 600A formed from a first portion of the III-N material structure (the portion included in region 420A), a second transistor 600B formed from a second portion of the III-N material structure (the portion included in region 420B), and a third transistor 600C formed from a third portion of the III-N material structure (the portion included in region 420C). As shown, transistors 600A, 600B, and 600C are monolithically integrated on the semiconductor wafer 410. Transistors 600A, 600B, and 600C may each be components of different front-end circuits. For example, as will be described in detail below, transistor 600A may be part of a PA, transistor 600B may be part of an LNA, and transistor 600C may be part of a switch (e.g., an RF switch operable as a T / R switch). In FIG. 4, all three transistors 600A - 600C are integrated on the semiconductor wafer 410, but a semiconductor device with any two of these three transistors integrated on the semiconductor wafer can also be formed. As used herein, "semiconductor wafer" refers to a continuous structure including one or more semiconductor layers, and for each semiconductor layer, the layer (and each portion of the layer) is formed by a single epitaxial growth.

[0029] FIG. 5 is a cross-sectional view of an epitaxially formed N-polar III-N material structure 500 from which the semiconductor wafer 410 of FIG. 4 can be formed. The material structure 500 includes a substrate 510 and a plurality of III-N layers 511, 513, and 512 formed on the substrate 510 in an N-polar orientation (i.e., in the [000-1] direction as shown). The substrate 510 may be any substrate suitable for epitaxially growing III-N layers thereon, such as silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), or sapphire (Al2O3). The III-N layer 511 is a buffer layer and may be formed of AlN, AlGaN, GaN, or a combination thereof. The III-N layer 513 formed on the N surface of the III-N buffer layer 511 functions as a back barrier. The III-N layer 512 is formed on the N surface of the III-N back barrier 513, and since the group-III surface of the III-N layer 513 is adjacent to the III-N back barrier 513 and the N surface is on the opposite side of the group-III surface, it functions as a channel layer.

[0030] The compositions of the III-N back barrier 513 and the III-N channel layer 512 are selected such that a two-dimensional electron gas (2DEG) channel 520 is induced in the III-N channel layer 512 adjacent to the interface between the III-N channel layer 512 and the III-N back barrier 513. To induce the 2DEG channel 520, the compositions of the III-N layers 512 and 513 can be selected such that the conduction band energy of the III-N back barrier 513 adjacent to the interface between the layer 512 and the layer 513 is greater than the conduction band energy of the III-N channel layer 512. That is, at the interface between the III-N layers 512 and 513, the conduction band energy is discontinuous, and the conduction band energy on the back barrier side of the interface is greater than the conduction band energy on the channel layer side of the interface. Such a conduction band energy discontinuity can typically be achieved by selecting, as the material of the III-N channel layer 512, a material having a bandgap smaller than the bandgap of the III-N back barrier 513. For example, the III-N channel layer 512 is formed of GaN, and the III-N back barrier 513 is Alx Ga 1-x It is formed of GaN, and the aluminum fraction composition x may be in the range of 0.1 ≦ x ≦ 0.6 (for example, in the range of 0.2 ≦ x ≦ 0.4).

[0031] The III-N back barrier 513 may be formed as a single III-N layer or as a plurality of III-N layers. For example, in FIG. 5, the back barrier 513 is implemented as a plurality of III-N layers, and the III-N back barrier 513 may include a first III-N layer 541 and a second III-N layer 542. When the III-N back barrier 513 is formed as a single layer, the entire III-N back barrier 513 is implemented as the first III-N layer. When the III-N back barrier 513 is formed as a plurality of III-N layers, the first III-N layer 541 may be adjacent to the III-N channel layer 512 and may be in direct contact with the III-N channel layer 512. As a result, the 2DEG channel 520 is adjacent to the interface between the III-N channel layer 512 and the first III-N layer 541 of the III-N back barrier 513. In this case, the first III-N layer 541 may have a larger bandgap than the III-N channel layer 512. In some embodiments, the first III-N layer 541 is formed of AlN.

[0032] FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, and FIG. 6E are cross-sectional views of N-polarity III-N transistor structures 600A, 600B, 600C, 600D, and 600E, respectively. Any two or more of these transistor structures may be monolithically integrated from the N-polarity III-N material structure 500 of FIG. 5 and can be used in the formation of the device 400 of FIG. 4. Referring to FIG. 6A, transistor 600A includes a first portion 513A of the III-N back barrier 513 (i.e., the portion of the back barrier 513 in the first region 420A of the semiconductor wafer 410) and a first portion 512A of the channel layer 512, and the portion 512A of the channel layer has a first 2DEG channel 520A. A first recess 551A is formed adjacent to the N surface 515A of the first portion 512A of the III-N channel layer, and the first recess has a first bottom surface 552A. The first recess 551A can be formed by etching the first portion 512A of the III-N channel layer. Transistor 600A further includes a first gate 533A formed of metal or other conductive material and at least partially within the first recess 551A. Transistor 600A further includes a first source 531A and a first drain 532A, each formed of metal or other conductive material and arranged such that the first gate 533A is between the first source 531A and the first drain 532A. Optionally, a regrown n+ region 530A may be formed under each of the source contact / drain contact and the first 2DEG channel 520A to reduce the contact resistance therebetween.

[0033] Referring to FIG. 6B, similar to transistor 600A, transistor 600B includes a second portion 513B of the III-N back barrier 513 (i.e., the portion of the back barrier 513 in the second region 420B of the semiconductor wafer 410) and a second portion 512B of the channel layer 512, and the portion 512B of the channel layer has a second 2DEG channel 520B. Also, similar to transistor 600A, in transistor 600B, a second recess 551B is formed adjacent to its N face 515B in the second portion 512B of the III-N channel layer, and the second recess has a second bottom surface 552B. The second recess 551B can be formed by etching the second portion 512B of the III-N channel layer. Transistor 600B further includes a second gate 533B formed of metal or other conductive material and at least partially within the second recess 551B. Transistor 600B further includes a second source 531B and a second drain 532B, each formed of metal or other conductive material and arranged such that the second gate 533B is between the second source 531B and the second drain 532B. Optionally, a regrown n+ region 530B may be formed under each of the second source 531B and the second drain 532B to reduce the contact resistance between the second source contact / second drain contact and the second 2DEG channel 520B.

[0034] Regarding the transistor 600B in FIG. 6B, before forming the second recess 551B, the second portion 512B of the III-N channel layer can be thinned, for example, by etching. Therefore, the total thickness of the channel layer in the access region of the device 600A (i.e., the thickness 516A of the first portion 512A of the III-N channel layer in the region between the first gate 533A and the first drain 532A) is greater than the total thickness of the channel layer in the access region of the device 600B (i.e., the thickness 516B of the second portion 512B of the III-N channel layer in the region between the second gate 533B and the second drain 532B). For example, the thickness 516A can be greater than 1.1 times the thickness 516B (e.g., greater than 1.2 times, greater than 1.3 times, greater than 1.4 times, greater than 1.5 times, greater than 1.6 times, greater than 1.8 times, or greater than 2 times). As used herein, the "gate region" of a transistor refers to the region under the gate, the "contact region" of a transistor refers to the regions under the source contact and the drain contact, and the "access region" of a transistor refers to the region between the gate region and the contact region. The "source access region" refers to the access region between the source contact region and the gate region, and the "drain access region" refers to the access region between the drain contact region and the gate region.

[0035] Referring now to FIG. 6C, similar to transistors 600A and 600B, transistor 600C includes a third portion 513C of the III-N back barrier 513 (i.e., the portion of the back barrier 513 in the third region 420C of the semiconductor wafer 410) and a third portion 512C of the channel layer 512, and the portion 512C of the channel layer has a third 2DEG channel 520C. Also, similar to transistors 600A and 600B, in transistor 600C, a third recess 551C is formed adjacent to its N face 515C in the third portion 512C of the III-N channel layer, and the third recess has a third bottom surface 552C. The third recess 551C can be formed by etching the third portion 512C of the III-N channel layer. Transistor 600C further includes a third gate 533C formed of metal or other conductive material and at least partially within the third recess 551C. Transistor 600C further includes a third source 531C and a third drain 532C, each formed of metal or other conductive material and arranged such that the third gate 533C is between the third source 531C and the third drain 532C. Optionally, a regrown n+ region 530C may be formed under each of the third source 531C and the third drain 532C to reduce the contact resistance between the third source / drain contact and the third 2DEG channel 520C.

[0036] Transistor 600C is different from transistor 600A in that the thickness of channel layer 512C removed to form the third recess 551C is thinner compared to the thickness of channel layer 512A removed to form the first recess 551A. Therefore, the distance 561A between the bottom surface 552A of the first recess 551A and the group-III surface of the first portion 513A of the III-N back barrier in transistor 600A is greater than the distance 561C between the bottom surface 552C of the third recess 551C and the group-III surface of the third portion 513C of the III-N back barrier in transistor 600C. The distance 561C may be, for example, greater than 1.1 times, greater than 1.2 times, greater than 1.3 times, greater than 1.4 times, greater than 1.5 times, greater than 1.6 times, greater than 1.8 times, or greater than 2 times the distance 561A. Optionally, the gate length 562C of transistor 600C may be greater than the gate length 562A of transistor 600A, and may be, for example, 1.1 times, 1.2 times, 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.8 times, 2 times, 2.5 times, or 3 times greater than the gate length 562A of transistor 600A.

[0037] Next, referring to FIG. 6D, transistor 600D is similar to transistor 600B, but differs in that instead of thinning the entire channel layer 512D before forming the recess 551D, the channel layer is thinned in the source access region (i.e., between the source 531D and the gate 533D) and not thinned in the drain access region (i.e., between the drain 532D and the gate 533D). Thus, the thickness 516DA of the channel layer 512D in the drain access region is the same as the thickness 516A in FIG. 6A, and the thickness 516DB of the channel layer 512D in the source access region can be made smaller than the thickness 516DA. In some cases, the thickness 516DB may be substantially the same as the thickness 516B in FIG. 6B.

[0038] In some embodiments, the distance 561C in transistor 600C is approximately the same as the thickness 516B of the thinned channel layer 512B in transistor 600B. For example, the thickness 516B can range from 0.9 times the distance 561C to 1.1 times the distance 561C. When two devices are monolithically integrated on the same wafer, by making these two thicknesses approximately the same, the same etching can be used for both forming the recess 551C of transistor 600C and thinning the channel layer 512B of transistor 600B, simplifying the manufacturing process. For similar reasons, the channel layer 512D of transistor 600D can have a thickness 516DB that is approximately the same as the distance 561C of transistor 600C in the source access region. That is, the thickness 516DB can range from 0.9 times the spacing 561C to 1.1 times the spacing 561C.

[0039] Next, referring to FIG. 6E, transistor 600E is the same as transistor 600A, except that the shape of the recess 551E of transistor 600E is different from that of transistor 600A. Specifically, the recess 551E includes one or more steps as shown. The recess 551E can be formed by multiple processes. First, the upper part of the recess (i.e., above the step) can be formed by etching to the depth of the step. Next, a second etching can be performed to form the bottom of the recess 551E. In some embodiments, the etching for forming the upper part of the recess 551E is the same as the etching used to form the recess 551C of transistor 600C (i.e., the upper part of the recess 551E and the recess 551C are formed simultaneously). Therefore, the distance 561EC between the step in transistor 600E and the interface between layer 512E and layer 541E can be approximately the same as the distance 561C in transistor 600C. For example, the distance 561EC can be between 0.9 times the distance 561C and 1.1 times the distance 561C.

[0040] The structures of transistors 600A, 600D, or 600E may all be optimal for use in a power amplifier (PA) because a high gain can be obtained due to a small gate-to-channel spacing, and the channel layer in the access region (especially the drain access region) is thick, resulting in good dispersion control (i.e., minimum dispersion) during high-power operation. The structure of transistor 600B may be optimal for use in a low-noise amplifier (LNA). Similar to the PA, the LNA requires a high-gain transistor, which is obtained by transistor 600B due to its small gate-to-channel spacing. However, in the LNA, dispersion control is not as important as in the PA, but it is desirable to reduce the capacitance to achieve a high gain and a low noise figure. This is achieved by thinning the channel layer in the access region in transistor 600B. The structure of transistor 600C has a large gate-to-channel spacing (compared to transistors 600A and 600B), which may increase the channel conductivity and the maximum device current, allow for a longer gate length, and thus improve the yield. Also, the channel layer in the access region is thick, resulting in good dispersion control under high-current operation. Therefore, it may be optimal for use in an RF switch.

[0041] A method 700 of forming a semiconductor device (e.g., device 400) comprising monolithically integrated transistors 600A, 600B, and / or 600C is shown in FIG. 7. First, a semiconductor wafer including an III-N material structure is formed or provided. The III-N material structure includes an N-polarity III-N channel layer on an N surface of an N-polarity III-N back barrier (step 701). The III-N material structure may be the same as that shown in FIG. 5. A first transistor (e.g., transistor 600A) is formed in a first region of the semiconductor wafer by: (i) etching through a portion of the III-N channel layer to form a first recess; (ii) depositing at least partially a first gate in the first recess; and (iii) depositing a first source and a first drain on opposite sides of the first gate (step 702). A second transistor (e.g., transistor 600B) is formed in a second region of the semiconductor wafer by: (i) thinning the entire III-N channel layer by etching in a second region of the semiconductor wafer; (ii) etching through a portion of the III-N channel layer in the second region to form a second recess; (iii) depositing at least partially a second gate in the second recess; and (iv) depositing a second source and a second drain on opposite sides of the second gate (step 703). A third transistor (e.g., transistor 600C) is formed in a third region of the semiconductor wafer by: (i) etching through a portion of the III-N channel layer in a third region of the semiconductor wafer to form a third recess having a depth different from that of the first recess; (ii) depositing at least partially a third gate in the third recess; and (iii) depositing a third source and a third drain on opposite sides of the third gate (step 704).In some embodiments, the gates of two or more transistors are deposited simultaneously, and / or the sources and drains of two or more transistors are deposited simultaneously, and / or the gate recesses of two or more transistors are formed at least partially simultaneously (e.g., by etching), and / or thinning the III-N channel layer of one transistor and forming the gate recess of another transistor are performed simultaneously (e.g., by etching both simultaneously).

[0042] The monolithically integrated semiconductor device 400 and the method of forming the device 400 described above are enabled by the fact that in an N-polarity III-N transistor, the (back) barrier is below the channel layer. Thus, unlike in the case of a group-III-polarity III-N transistor, the thickness of the channel layer in the access region can be easily changed by etching the (uncovered) channel layer, whereby both the transistor 600A and the transistor 600B can be formed from a single common epitaxial material structure. Further, in an N-polarity transistor, when the semiconductor material is thinned (e.g., by etching) to form the transistor 600B from the same epitaxial material as the transistor 600A, the 2DEG charge density in the access region may not change substantially, so that the transistor 600B can maintain a low on-resistance. In a group-III-polarity transistor, when the semiconductor material is thinned by etching, the barrier layer in the device access region becomes thinner (the channel layer does not necessarily become thinner), and the 2DEG charge density in the access region may decrease significantly, resulting in an increase in the on-resistance and a possible decrease in the maximum current density during device operation.

[0043] Although not shown in FIGS. 5, 6A, 6B, or 6C, transistors 600A, 600B, and 600C may each further include a dielectric layer that functions as a passivation layer formed on the upper surface of the transistor. In some embodiments, the same dielectric layer may be formed on all three transistors, and a first portion of the dielectric layer may be over transistor 600A, a second portion of the dielectric layer may be over transistor 600B, and a third portion of the dielectric layer may be over transistor 600C. Optionally, the first portion of the dielectric layer may be thicker than the second portion of the dielectric layer. The thicker the dielectric layer, the more likely it is that passivation and dispersion control will be improved, which is generally preferred. However, when transistor 600B is used in an LNA, the thinner the passivation layer, the more likely it is that the gain will be improved. Since dispersion control is not as important in an LNA as in a PA, having the first portion of the dielectric layer thicker than the second portion of the dielectric layer may improve the performance of the overall device.

[0044] FIG. 8 is a cross-sectional view of another epitaxially formed N-polarity III-N material structure 800 from which the semiconductor wafer 410 of FIG. 4 can be formed. FIGS. 9A, 9B, 9C, 9D, and 9E each show a monolithically integrated transistor structure 900A, 900B, 900C, 900D, and 900E obtained from the material structure 800. Similar to the material structure 500 of FIG. 5, the material structure 800 includes a substrate 810 and a plurality of III-N layers in an N-polarity orientation (i.e., in the [000-1] direction as shown) on the substrate 810. The substrate 810 may be the same as the substrate 510 of the material structure 500. The plurality of N-polarity III-N layers on the substrate 810 may include an III-N buffer layer 811, an III-N back barrier 813, and an III-N channel layer 812. The compositions of layers 811, 813, and 812 may each be the same as the compositions of layers 511, 513, and 512, respectively.

[0045] The material structure 800 further includes a III-N etch stop layer 814 on the N surface of the III-N channel layer 812 and a III-N cap layer 817 on the N surface of the III-N etch stop layer 814. The total thickness 816 of the III-N channel layer 812, the III-N etch stop layer 814, and the III-N cap layer 817 in the material structure 800 may be the same as or approximately the same as the thickness 516 of the III-N channel layer 512 in the material structure 500. The compositions of the III-N cap layer 817 and the III-N etch stop layer 814 may be selected such that the III-N cap layer 817 is selectively etched at a faster rate than the III-N etch stop layer 814 using an etching process suitable for forming a gate recess, such as an F-containing plasma or an HCl-containing aqueous solution. For example, the III-N cap layer 817 is formed of GaN, and the III-N etch stop layer 814 is formed of Al y Ga 1-y N, where the aluminum fraction composition y is in the range of 0 < y ≤ 1 (for example, in the range of 0.05 ≤ y ≤ 0.6). The bandgap of the III-N etch stop layer 814 may be larger than the bandgap of the III-N cap layer 817. The bandgap and / or composition of the III-N cap layer 817 may be the same as or approximately the same as the bandgap and / or composition of the III-N channel layer 812. In some embodiments, the III-N etch stop layer 814 is formed of Al y Ga 1-y N (0 < y ≤ 1), and both the III-N channel layer 812 and the III-N cap layer 817 may be formed of GaN.

[0046] Next, referring to FIG. 9A, transistor 900A includes a first portion 813A of the III-N back barrier 813 (i.e., the portion of the back barrier 813 in the first region 420A of the semiconductor wafer 410) and a first portion 812A of the III-N channel layer 812, and the portion 812A of the channel layer has a first 2DEG channel 820A. Transistor 900A further includes a first portion 814A of the III-N etch stop layer 814 and a first portion 817A of the III-N cap layer 817. A first recess 851A is formed adjacent to the N-face 825A of the first portion 817A of the III-N cap layer, and the first recess has a first bottom surface 852A. The first recess 851A extends at least partially through the thickness of the first portion 817A of the III-N cap layer. In some embodiments, the first recess 851A extends through the entire thickness of the first portion 817A of the III-N cap layer but does not extend into the first portion 812A of the III-N channel layer.

[0047] The first recess 851A can be formed by etching a first portion 817A of the III-N cap layer using an etching process that etches the material of the III-N cap layer at a higher rate than the III-N etch stop layer 814A. Thus, the etching can be "stopped" at or near the surface of the etch stop layer 814A adjacent to the III-N cap layer 817. In this way, the depth of the first recess 851A, and the corresponding distance 861A between the bottom surface 852A of the first recess 851A and the group III plane of the first portion 813A of the III-N back barrier, can be controlled by epitaxial growth. This improves the uniformity and / or reproducibility compared to the transistor 600A. The etch stop layer enables precise control of the depth and smoothing of the etched surface, but residual by-products such as fluorine ions from selective etching remaining in the surface-near region can cause undesirable electrical instabilities, and similar behavior has been observed in N-polarity transistors fabricated using SF6-based plasma etching. These instabilities can be eliminated by removing the surface-near region by additional etching using plasma etching without leaving residual F and / or wet chemical etching.

[0048] The transistor 900A further includes a first gate 833A formed of metal or other conductive material and at least partially present within the first recess 851A. The transistor 900A further includes a first source 831A and a first drain 832A each formed of metal or other conductive material, and the first gate 833A is disposed to come between the first source 831A and the first drain 832A. Optionally, a regrown n+ region 830A may be formed under each of the source contact / drain contact and the first 2DEG channel 820A to reduce the contact resistance therebetween.

[0049] Referring to FIG. 9B, transistor 900B includes a second portion 813B of the III-N back barrier 813 (i.e., the portion of the back barrier 813 in the second region 420B of the semiconductor wafer 410) and a second portion 812B of the III-N channel layer 812, and the portion 812B of the channel layer has a second 2DEG channel 820B. Transistor 900B further includes a second portion 814B of the III-N etch stop layer 814 and a second portion 817B of the III-N cap layer 817. The second portion 817B of the III-N cap layer in transistor 900B is thinner than the first portion 817A of the III-N cap layer in transistor 900A. A second recess 851B is formed adjacent to its N face 825B in the second portion 817B of the III-N cap layer, and the second recess has a first bottom face 852B. The second recess 851B extends at least partially through the thickness of the second portion 817B of the III-N cap layer. In some embodiments, the second recess 851B extends through the entire thickness of the second portion 817B of the III-N cap layer but does not extend into the second portion 812B of the III-N channel layer.

[0050] Transistor 900B is formed of metal or other conductive material and further includes a second gate 833B that is at least partially present within the second recess 851B. Transistor 900B further includes a second source 831B and a second drain 832B each formed of metal or other conductive material, and the second gate 833B is disposed to be between the second source 831B and the second drain 832B. Optionally, a regrown n+ region 830B may be formed under each of the second source 831B and the second drain 832B to reduce the contact resistance between the second source contact / second drain contact and the second 2DEG channel 820B.

[0051] Transistor 900B is similar to transistor 600B in that it can be formed by thinning the second portion 817B of the III-N cap layer (e.g., by etching) and then forming the same transistor as transistor 900A. However, it differs in that the total thickness 816B of the layers 812B, 814B, and 817B in the access region of transistor 900B is thinner than the total thickness 816A of the layers 812A, 814A, and 817A in the access region of transistor 900A. Similar to transistor 900A, the distance 861B between the bottom surface 852B of the second recess 851B and the group III surface of the second portion 813B of the III-N back barrier can be controlled by epitaxial growth using a gate recess etching process that etches the material of the III-N cap layer 817 at a higher rate than the material of the III-N etch stop layer 814. In some embodiments, the thickness 816A may be greater than 1.1 times the thickness 816B (e.g., greater than 1.2 times, greater than 1.3 times, greater than 1.4 times, greater than 1.5 times, greater than 1.6 times, greater than 1.8 times, or greater than 2 times). In some embodiments, the thickness of the first portion 817A of the III-N cap layer in the region between the first gate 833A and the first drain 832A of transistor 900A may be greater than 1.1 times the thickness of the second portion 817B of the III-N cap layer in the region between the second gate 833B and the second drain 832B of transistor 900B (e.g., greater than 1.2 times, greater than 1.3 times, greater than 1.4 times, greater than 1.5 times, greater than 1.6 times, greater than 1.8 times, or greater than 2 times).

[0052] Next, referring to FIG. 9C, similar to transistors 900A and 900B, transistor 900C includes a third portion 813C of the III-N back barrier 813 (i.e., the portion of the back barrier 813 in the third region 420C of the semiconductor wafer 410), a third portion 812C of the channel layer 812 (the portion 812C of the channel layer has a third 2DEG channel 520C), a third portion 814C of the III-N etch stop layer 814, and a third portion 817C of the III-N cap layer 817. Also, similar to transistors 900A and 900B, a third recess 851C is formed adjacent to its N face 825C in the third portion 817C of the III-N cap layer of transistor 900C, and the third recess has a third bottom face 852C. The third recess 851C can be formed by etching the third portion 817C of the III-N cap layer. Transistor 900C further includes a third gate 833C formed of metal or other conductive material and at least partially present within the third recess 851C. Transistor 900C further includes a third source 831C and a third drain 832C each formed of metal or other conductive material, and the third gate 833C is disposed to come between the third source 831C and the third drain 832C. Optionally, a regrown n+ region 830C may be formed under each of the third source 831C and the third drain 832C to reduce the contact resistance between the third source / drain contact and the third 2DEG channel 820C.

[0053] Similar to the case of transistor 600C, the thickness of the III-N cap layer 817C removed to form the third recess 851C in transistor 900C is smaller compared to the thickness of the cap layer 817A removed to form the first recess 851A in transistor 900A. Therefore, the distance 861C between the bottom surface 852C of the third recess 851C and the group-III plane of the third portion 813C of the III-N back barrier in transistor 900C is larger than the distance 861A between the bottom surface 852A of the first recess 851A and the group-III plane of the first portion 813A of the III-N back barrier in transistor 900A. The distance 861C may be, for example, larger than 1.1 times, 1.2 times, 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.8 times, or 2 times the distance 861A. Optionally, the gate length 862C of transistor 900C may be larger than the gate length 562A of transistor 900A, for example, 1.1 times, 1.2 times, 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.8 times, 2 times, 2.5 times, or 3 times the gate length 862A of transistor 900A.

[0054] Next, referring to FIG. 9D, transistor 900D is similar to transistor 900B, but differs in that instead of thinning the entire cap layer 817D before forming the recess 851D, the cap layer is thinned in the source access region (i.e., between the source 831D and the gate 833D), but not in the drain access region (i.e., between the drain 832D and the gate 833D). Accordingly, the total thickness 816DA of the layers 817D, 814D, and 812D in the drain access region may be the same as the thickness 816A in FIG. 8A, and the total thickness 816DB of the layers 817D, 814D, and 812D in the source access region may be smaller than the thickness 816DA. In some cases, the thickness 816DB may be substantially the same as the thickness 816B in FIG. 6B.

[0055] In some embodiments, the distance 861C in transistor 900C may be approximately the same as the thickness 816B in transistor 900B. For example, the thickness 816B can range from 0.9 times the thickness 861C to 1.1 times the distance 861C. When two devices are monolithically integrated on the same wafer, by making their two thicknesses approximately the same, the same etching can be used for both forming the recess 851C of transistor 900C and thinning the cap layer 817B of transistor 900B, simplifying the manufacturing process. For the same reason, the thickness 816DB of the source access region in transistor 900D can be made approximately the same as the distance 861C in transistor 900C. That is, the thickness 816DB can range from 0.9 times the distance 861C to 1.1 times the distance 861C.

[0056] Referring next to FIG. 9E, transistor 900E is the same as transistor 900A except that the shape of recess 851E is different from the shape of the recess of transistor 900A. Specifically, recess 851E includes one or more steps as shown. Recess 851E can be formed by a plurality of steps. First, the upper part of the recess (i.e., above the step) can be formed by etching to the depth of the step. Next, a second etching can be performed to form the bottom of recess 851E. In some embodiments, the etching for forming the upper part of recess 851E is the same as the etching used to form recess 851C of transistor 900C (i.e., the upper part of recess 851E and recess 851C are formed simultaneously). Therefore, the distance 861EC between the step in transistor 900E and the interface between layer 812E and layer 841E may be approximately the same as the distance 861C in transistor 900C. For example, the distance 861EC may be between 0.9 times the distance 861C and 1.1 times the distance 861C.

[0057] For the same reasons described above with respect to transistors 600A, 600B, 600C, 600D, and 600E, the structure of any of transistors 900A, 900D, or 900E is optimal for use in a power amplifier (PA), the structure of transistor 900B is optimal for use in a low-noise amplifier (LNA), and the structure of transistor 900C may be optimal for use in an RF switch. Further, since the depth of the gate recesses of transistors 900A and 900B is determined by the thickness of the epitaxially grown cap layer 817, the reproducibility and yield of these transistors may be improved as compared to the case of transistors 600A and 600B.

[0058] A method 1000 of forming a semiconductor device (e.g., device 400) with monolithically integrated transistors 900A, 900B, and / or 900C is shown in FIG. 10. First, a semiconductor wafer including an III-N material structure is formed or provided. The III-N material structure includes an N-polarity III-N channel layer on the N surface of an N-polarity III-N back barrier, an N-polarity III-N etch stop layer on the III-N channel layer, and an N-polarity III-N cap layer on the III-N etch stop layer (step 1001). The III-N material structure may be the same as that shown in FIG. 8. By etching through the III-N cap layer in a first region of the semiconductor wafer to form a first recess, depositing at least partially a first gate in the first recess, and depositing a first source and a first drain on opposite sides of the first gate, a first transistor (e.g., transistor 900A) is formed in the first region of the semiconductor wafer (step 1002). By thinning the entire III-N cap layer by etching in a second region of the semiconductor wafer, etching through the III-N cap layer in the second region to form a second recess, depositing at least partially a second gate in the second recess, and depositing a second source and a second drain on opposite sides of the second gate, a second transistor (e.g., transistor 900B) is formed in the second region of the semiconductor wafer (step 1003). By etching through a part of the III-N cap layer in a third region of the semiconductor wafer to form a third recess having a depth different from that of the first recess, depositing at least partially a third gate in the third recess, and depositing a third source and a third drain on opposite sides of the third gate, a third transistor (e.g., transistor 900C) is formed in the third region of the semiconductor wafer (step 1004).In some embodiments, the gates of two or more transistors are deposited simultaneously, and / or the sources and drains of two or more transistors are deposited simultaneously, and / or the gate recesses of two or more transistors are formed at least partially simultaneously (e.g., by etching), and / or thinning the III-N channel layer of one transistor and forming the gate recess of another transistor are performed simultaneously (e.g., by etching both simultaneously).

[0059] Similar to transistors 600A, 600B, 600C, 600D, and 600E, although not shown in FIGS. 8, 9A, 9B, 9C, 9D, or 9E, transistors 900A, 900B, 900C, 900D, and 900E may each further include a dielectric layer that functions as a passivation layer formed on the upper surface of the transistor. The thickness and other characteristics of the dielectric layer may be the same as those described for transistors 600A, 600B, and 600C.

[0060] FIG. 11 is a cross-sectional view of another epitaxially formed N-polarity III-N material structure 1100 from which the semiconductor wafer 410 of FIG. 4 can be formed. FIGS. 12A, 12B, and 12C respectively show monolithically integrated transistor structures 1200A, 1200B, and 1200C obtained from the material structure 1100. Similar to the material structure 800 of FIG. 8, the material structure 1100 includes a substrate 1110 and a plurality of III-N layers in an N-polarity orientation (i.e., in the [000-1] direction as shown) on the substrate 1110. The substrate 1110 may be the same as the substrate 510 of the material structure 500. The plurality of N-polarity III-N layers on the substrate 1110 may include a III-N buffer layer 1111, a III-N back barrier 1113, a III-N channel layer 1112, a first III-N etch stop layer 1114, and a first III-N cap layer 1117. The compositions of layers 1111, 1113, 1112, 1114, and 1117 may each be the same as the compositions of layers 811, 813, 812, 814, and 817, respectively.

[0061] The material structure 1100 further includes a second III-N etch stop layer 1124 on the N surface of the first III-N cap layer 1117 and a second III-N cap layer 1127 on the N surface of the second III-N etch stop layer 1124. The total thickness 1116 of the III-N layers 1112, 1114, 1117, 1124, 1127 in the material structure 1100 may be the same as or approximately the same as the thickness 816 in the material structure 800. The compositions of the first and second III-N cap layers 1117 and 1127, and the compositions of the first and second III-N etch stop layers 1114 and 1124, can be selected such that, using an etching process suitable for forming a gate recess, the III-N cap layers 1117 and 1127 are selectively etched at a higher rate than the first and second III-N etch stop layers 1114 and 1124, respectively. For example, the III-N cap layers 1117 and 1127 are each formed of GaN, and the III-N etch stop layers 1114 and 1124 are each formed of Al y Ga 1-y N, where the aluminum fraction composition y is in the range of 0 < y ≤ 1 (for example, in the range of 0.1 ≤ y ≤ 0.6). The bandgap of each III-N etch stop layer may be greater than the bandgap of each III-N cap layer. The bandgap and / or composition of each III-N cap layer may be the same as or approximately the same as the bandgap and / or composition of the III-N channel layer 1112. In some embodiments, the III-N etch stop layers 1114 and 1117 are each formed of Al y Ga 1-y N (0 < y ≤ 1), and the III-N channel layer 1112 and each of the III-N cap layers 1117 and 1127 may all be formed of GaN.

[0062] Next, referring to FIG. 12A, transistor 1200A is similar to transistor 900A of FIG. 9A, except that a first recess 1151A is formed through both the III-N cap layers 1117A and 1127A and the second etch stop layer 1124A. Similar to transistor 900A, the etching used to form the first recess 1151A can be "stopped" at or near the surface of the first etch stop layer 1114C adjacent to the first III-N cap layer 1117C. Thus, the depth of the first recess 1151A, and the corresponding distance 1161A between the bottom surface 1152A of the first recess 1151A and the group III surface of the first portion 1113A of the III-N back barrier, can be controlled by epitaxial growth.

[0063] Referring to FIG. 12B, transistor 1200B is similar to transistor 900B of FIG. 9B, except that in a second region (the region of the wafer where transistor 1200B is formed), the entire second III-N cap layer (layer 1127 of FIG. 11) is removed (e.g., by etching), and a second recess 1151B is formed through layers 1124B and 1117B. When forming transistor 1200B, the second III-N etch stop layer 1124B can function as an etch stop layer for removing the second III-N cap layer, and the first III-N etch stop layer can function as an etch stop layer for forming the second recess 1151B.

[0064] Referring to FIG. 12C, transistor 1200C is similar to transistor 900C of FIG. 9B, except that a third recess 1151C is formed through the second III-N cap layer 1127C and can be formed to "stop" at or near the surface of the second etch stop layer 1124C adjacent to the second III-N cap layer 1127C. Thus, the depth of the third recess 1151C, and the corresponding distance 1161C between the bottom surface 1152C of the third recess 1151C and the group III surface of the first portion 1113C of the III-N back barrier, can be controlled by epitaxial growth.

[0065] Similar to the cases of transistors 900A, 900B, and 900C, the distance 1161A between the bottom surface 1152A of the first recess 1151A in transistor 1200A and the group-III surface of the first portion 1113A of the III-N back barrier is greater than the distance 1161C between the bottom surface 1152C of the third recess 1151C in transistor 1200C and the group-III surface of the third portion 1113C of the III-N back barrier. The distance 1161A may be, for example, greater than 1.1 times, 1.2 times, 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.8 times, or 2 times the distance 1161C. Optionally, the gate length 1162C of transistor 1200C may be greater than the gate length 1162A of transistor 1200A, for example, 1.1 times, 1.2 times, 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.8 times, 2 times, 2.5 times, or 3 times the gate length 1162A of transistor 1200A.

[0066] For the same reasons as described above for transistors 900A, 900B, and 900C, the structure of transistor 1200A may be optimal for use in a power amplifier (PA), the structure of transistor 1200B may be optimal for use in a low-noise amplifier (LNA), and the structure of transistor 1200C may be optimal for use in an RF switch. Furthermore, since the depth of the gate recesses for all three transistors is determined by the thickness of the epitaxially grown layer, the reproducibility and yield of these transistors may be further improved compared to the cases of transistors 900A, 900B, and 900C.

[0067] A method 1300 of forming a semiconductor device (e.g., device 400) comprising monolithically integrated transistors 1200A, 1200B, and / or 1200C is shown in FIG. 13. First, a semiconductor wafer including an III-N material structure is formed or provided. The III-N material structure includes an N-polarity III-N channel layer on the N surface of an N-polarity III-N back barrier, a first N-polarity III-N etch stop layer on the III-N channel layer, a first N-polarity III-N cap layer on the first III-N etch stop layer, a second N-polarity III-N etch stop layer on the first III-N cap layer, and a second N-polarity III-N cap layer on the second III-N etch stop layer (step 1301). The III-N material structure may be the same as that shown in FIG. 11. In a first region of the semiconductor wafer, the first and second III-N cap layers are penetrated, etched through the second III-N etch stop layer to form a first recess, at least partially deposit a first gate in the first recess, and deposit a first source and a first drain on the opposite side of the first gate, thereby forming a first transistor (e.g., transistor 1200A) in the first region of the semiconductor wafer (step 1302). In a second region of the semiconductor wafer, the entire second III-N cap layer is removed by etching, etched through the second III-N etch stop layer and through the first III-N cap layer in the second region to form a second recess, at least partially deposit a second gate in the second recess, and deposit a second source and a second drain on the opposite side of the second gate, thereby forming a second transistor (e.g., transistor 1200B) in the second region of the semiconductor wafer (step 1303). In a third region of the semiconductor wafer, the second III-N cap layer is etched through to form a third recess having a depth different from that of the first recess, at least partially deposit a third gate in the third recess, and deposit a third source and a third drain on the opposite side of the third gate, thereby forming a third transistor (e.g., transistor 1200C) in the third region of the semiconductor wafer (step 1304).In some embodiments, the gates of two or more transistors may be deposited simultaneously and / or the sources and drains of two or more transistors may be deposited simultaneously.

[0068] Similar to transistors 600A, 600B, and 600C, although not shown in FIGS. 11, 12A, 12B, or 12C, transistors 1200A, 1200B, and 1200C may each further include a dielectric layer that functions as a passivation layer formed on the upper surface of the transistor. The thickness and other characteristics of the dielectric layer may be the same as those described for transistors 600A, 600B, and 600C.

[0069] In the transistors described above, depending on the specific composition and thickness of the etch stop layer and the cap layer, one or more secondary 2DEGs may be formed in the III-N cap layer(s) of the transistor. For example, FIG. 14A shows the position of a possible secondary 2DEG 860C induced in the III-N cap layer 817C of transistor 900C (of FIG. 9C), and FIG. 14B shows the position of a possible secondary 2DEG 1160C induced in the first III-N cap layer 1117C of transistor 1200C (of FIG. 12C). The secondary 2DEGs 860C and 1160C extend continuously from the source region to the drain region and may be under the gate of their respective transistors when the transistor is biased on (i.e., when the gate-source voltage is greater than the threshold voltage of the transistor). In transistors such as the RF switches of FIGS. 14A and 14B, this secondary 2DEG increases the conductivity of the entire channel of the transistor and improves the switch performance, but a larger gate voltage amplitude may be required to switch the transistor from the on state to the off state.

[0070] In some cases, it may be desirable to suppress or prevent the formation of one or more of the two-dimensional electron gases (2DEGs). This can be achieved by including one or more p-type layers that directly overlap on any of the etching stop layers. FIG. 15 is a cross-sectional view of another epitaxially formed N-polarity III-N material structure 1500 that is the same as the material structure 1100, but further includes a first p-type III-N layer 1564 between the etching stop layer 1514 and the cap layer 1517, and a second p-type III-N layer 1574 between the etching stop layer 1524 and the cap layer 1527. Each of the p-type layers 1564 and 1574 may be formed of the same semiconductor material as the overlying cap layers 1517 and 1527, respectively, or may have the same bandgap. FIG. 16 is a cross-sectional view of a transistor 1600 that can be formed from the material structure 1500. The transistor 1600 is the same as the transistor 1200A, but further includes p-type layers 1564A and 1574A in the access regions, as shown. Similarly, any of the transistors described herein that include one or more etching stop layers can further include a p-type III-N layer directly on the etching stop layer (e.g., between the etching stop layer and the cap layer thereon).

[0071] FIG. 17 is a plan view of a semiconductor device 1700 in which transistors 600A and 600C of FIGS. 6A and 6C are monolithically integrated on a substrate 1710 and combined as a single hybrid device. In the configuration of the semiconductor device 1700, two transistors share a common drain 532A / 532C, a source pad 1731 connects the sources 531A and 531C of the two transistors to form a common source, and a gate pad 1733 connects the gates 533A and 533C of the two transistors to form a common gate. The active region of the hybrid device (i.e., the region including the 2DEG channels shown in FIGS. 6A and 6C) is within the dashed line 1775. In the non-active region surrounding the active region, for example, by etching away a part of the III-N layer or by ion implantation, the 2DEG channel is removed or made non-conductive. The hybrid device is configured such that the gate width 1771 of transistor 600A is different from the gate width 1772 of transistor 600C. The gate width 1771 of transistor 600A is shown to be smaller than the gate width 1772 of transistor 600C, but alternatively, the gate width 1771 of transistor 600A may be larger than the gate width 1772 of transistor 600C. Also, any combination of transistors 600A, 600B, and 600C can be combined to form a hybrid device as shown. Similarly, any combination of transistors 900A, 900B, and 900C can be combined to form a hybrid device as shown. Similarly, any combination of transistors 1200A, 1200B, and 1200C can be combined to form a hybrid device as shown. As used herein, the "gate width" of a transistor is the width of the portion of the gate metal directly above the active region of the transistor (e.g., in a direction substantially perpendicular to the direction of current flow) of the region including the channel of the transistor.

[0072] In some cases, in any of the transistors described herein in which the semiconductor material structure includes one or more etch stop layers, the etching used to form a recess (e.g., a gate recess) in the semiconductor material may not stop precisely at the top surface of the etch stop layer. For example, FIG. 18 is a cross-sectional view of a transistor 1800 that is the same as transistor 1200B of FIG. 12B except that recess 1851 extends through at least a portion or the entire thickness of etch stop layer 1814. When forming recess 1851, etch stop layer 1814 can improve the accuracy of the etching depth as compared to the recess formed in transistor 1200B. Further, in any of the other transistors described herein in which the semiconductor material structure includes one or more etch stop layers, the recesses of the illustrated gates or access regions etched to stop at the top surface of the etch stop layer may instead be formed to at least partially penetrate the etch stop layer, or to penetrate the entire thickness of the etch stop layer, and in some cases, may be formed to at least partially penetrate any layer directly beneath the etch stop layer.

[0073] Various devices and their material structures have been described above along with methods of forming the devices and material structures. However, it should be understood that these are presented by way of example only and are not limiting. Although embodiments have been specifically illustrated and described, it will be understood that various changes in form and detail can be made. For example, in any of the transistors described herein, a gate insulator or gate dielectric may be included between the gate metal and the underlying semiconductor material. Accordingly, other embodiments are also within the scope of the following claims.

Claims

1. A semiconductor wafer including an III-N material structure, wherein the III-N material structure includes an III-N back barrier, an III-N channel layer on the N surface of the III-N back barrier, having a group III surface adjacent to the III-N back barrier and an N surface on the opposite side of the group III surface, and the bandgap of the III-N back barrier is larger than the bandgap of the III-N channel layer, and the III-N channel layer A semiconductor wafer including a first transistor in a first region of the semiconductor wafer, a first portion of the III-N back barrier, a first portion of the III-N channel layer having a first 2DEG channel, having a first recess adjacent to its N surface, and the first recess having a first bottom surface, and the first portion of the III-N channel layer a first gate at least partially present in the first recess, a first source and a first drain A first transistor including, and the first gate is between the first source and the first drain, a second transistor in a second region of the semiconductor wafer, a second portion of the III-N back barrier, a second portion of the III-N channel layer having a second 2DEG channel, having a second recess adjacent to its N surface, and the second recess having a second bottom surface, and the second portion of the III-N channel layer a second gate at least partially present in the second recess, a second source and a second drain A second transistor including, and the second gate is between the second source and the second drain, Including A semiconductor device, wherein the thickness of the first portion of the III-N channel layer in the region between the first gate and the first drain is greater than 1.2 times the thickness of the second portion of the III-N channel layer in the region between the second gate and the second drain.

2. The semiconductor device according to claim 1, wherein the first transistor is part of a first circuit and the second transistor is part of a second circuit.

3. The semiconductor device according to claim 2, wherein the first circuit is a power amplifier or an RF switch, and the second circuit is a low-noise amplifier.

4. The first transistor further includes a first portion of a dielectric layer on the first portion of the III-N channel layer, The second transistor further includes a second portion of the dielectric layer on the second portion of the III-N channel layer, The semiconductor device according to claim 1, wherein the first portion of the dielectric layer is thicker than the second portion of the dielectric layer.

5. The semiconductor device according to claim 1, wherein a distance between a first bottom surface of the first portion of the III-N channel layer and the group III plane is at least 1.2 times a distance between a second bottom surface of the second portion of the III-N channel layer and the group III plane.

6. A semiconductor wafer including an III-N material structure, wherein the III-N material structure includes an III-N back barrier, an III-N channel layer on an N surface of the III-N back barrier, having a group III plane adjacent to the III-N back barrier and an N surface on an opposite side of the group III plane, and a bandgap of the III-N back barrier being larger than a bandgap of the III-N channel layer, the III-N channel layer and a semiconductor wafer, a first transistor in a first region of the semiconductor wafer, a first portion of the III-N back barrier, a first portion of the III-N channel layer having a first 2DEG channel, having a first recess adjacent to its N surface, and the first recess having a first bottom surface, the first portion of the III-N channel layer, a first gate at least partially present in the first recess, a first source and a first drain and including the first gate being between the first source and the first drain, the first transistor, a second transistor in a second region of the semiconductor wafer, a second portion of the III-N back barrier, a second portion of the III-N channel layer having a second 2DEG channel, having a second recess adjacent to its N surface, and the second recess having a second bottom surface, the second portion of the III-N channel layer, a second gate at least partially present in the second recess, a second source and a second drain and including the second gate being between the second source and the second drain, the second transistor and including A semiconductor device, wherein a distance between a first bottom surface of the first portion of the III-N channel layer and the group-III plane is at least 1.2 times a distance between a second bottom surface of the second portion of the III-N channel layer and the group-III plane. **Claim 7** The semiconductor device according to claim 6, wherein the first transistor is part of a first circuit and the second transistor is part of a second circuit. **Claim 8** The semiconductor device according to claim 7, wherein the first circuit is an RF switch and the second circuit is a power amplifier or a low-noise amplifier. **Claim 9** A semiconductor wafer including a III-N material structure, the III-N material structure including: a III-N back barrier; a III-N channel layer on an N surface of the III-N back barrier, having a group-III plane adjacent to the III-N back barrier and an N surface on an opposite side of the group-III plane, wherein a bandgap of the III-N back barrier is larger than a bandgap of the III-N channel layer; a III-N etch stop layer on the N surface of the III-N channel layer; a III-N cap layer on the N surface of the III-N etch stop layer and a semiconductor wafer; a first transistor in a first region of the semiconductor wafer, including: a first portion of the III-N back barrier; a first portion of the III-N channel layer having a first 2DEG channel; a first portion of the III-N etch stop layer; a first portion of the III-N cap layer, including a first recess extending at least partially through a thickness of the first portion of the III-N cap layer and having a first bottom surface; a first gate at least partially present within the first recess; a first source and a first drain and a first transistor, wherein the first gate is between the first source and the first drain; a second transistor in a second region of the semiconductor wafer, including: a second portion of the III-N back barrier; a second portion of the III-N channel layer having a second 2DEG channel; a second portion of the III-N etch stop layer; A second portion of the III-N cap layer, including a second recess extending at least partially through the thickness of the second portion of the III-N cap layer, the second recess having a second bottom surface, the second portion of the III-N cap layer; A second gate at least partially present within the second recess; A second source and a second drain; Including a second transistor, the second gate being between the second source and the second drain; Including; A semiconductor device, wherein the thickness of the first portion of the III-N cap layer in the region between the first gate and the first drain is greater than 1.2 times the thickness of the second portion of the III-N cap layer in the region between the second gate and the second drain. **Claim 10** The first recess extends partially through the thickness of the first portion of the III-N cap layer without extending through the entire thickness of the first portion of the III-N cap layer. The semiconductor device according to claim 9, wherein the second recess extends through the entire thickness of the second portion of the III-N cap layer. **Claim 11** The semiconductor device according to claim 10, wherein the distance between the first bottom surface of the first portion of the III-N channel layer and the group III plane is at least 1.2 times the distance between the second bottom surface of the second portion of the III-N channel layer and the group III plane. **Claim 12** The semiconductor device according to claim 9, wherein the first transistor is part of a first circuit and the second transistor is part of a second circuit. **Claim 13** The semiconductor device according to claim 12, wherein the first circuit is a power amplifier or an RF switch and the second circuit is a low-noise amplifier. **Claim 14** The first transistor further includes a first portion of a dielectric layer on the first portion of the III-N cap layer. The second transistor further includes a second portion of the dielectric layer on the second portion of the III-N cap layer. The semiconductor device according to claim 9, wherein the first portion of the dielectric layer is thicker than the second portion of the dielectric layer. **Claim 15** The distance between the first bottom surface of the first portion of the III-N channel layer and the group III surface is at least 1.2 times the distance between the second bottom surface of the second portion of the III-N channel layer and the group III surface, the semiconductor device according to claim 9.

16. A semiconductor wafer including a III-N material structure, wherein the III-N material structure includes a III-N back barrier, a III-N channel layer on the N surface of the III-N back barrier, having a group III surface adjacent to the III-N back barrier and an N surface on the opposite side of the group III surface, and the bandgap of the III-N back barrier is larger than the bandgap of the III-N channel layer, the III-N channel layer, a III-N etch stop layer on the N surface of the III-N channel layer, and a III-N cap layer on the N surface of the III-N etch stop layer comprising a semiconductor wafer, a first transistor in a first region of the semiconductor wafer, a first portion of the III-N back barrier, a first portion of the III-N channel layer having a first 2DEG channel, a first portion of the III-N etch stop layer, a first portion of the III-N cap layer, including a first recess that extends partially through the thickness of the first portion of the III-N cap layer without extending through the entire thickness of the first portion of the III-N cap layer, the first recess having a first bottom surface, the first portion of the III-N cap layer, a first gate at least partially present in the first recess, and a first source and a first drain comprising a first transistor, wherein the first gate is between the first source and the first drain, a second transistor in a second region of the semiconductor wafer, a second portion of the III-N back barrier, a second portion of the III-N channel layer having a second 2DEG channel, a second portion of the III-N etch stop layer, a second portion of the III-N cap layer, including a second recess that extends through the entire thickness of the second portion of the III-N cap layer, the second recess having a second bottom surface, the second portion of the III-N cap layer, a second gate at least partially present in the second recess, A second source and a second drain, and a second transistor including a second gate therebetween, between the second source and the second drain, and a semiconductor device including the second transistor. **Claim 17** The distance between the first bottom surface of the first portion of the III-N channel layer and the group III surface is at least 1.2 times the distance between the second bottom surface of the second portion of the III-N channel layer and the group III surface. The semiconductor device according to claim 16. **Claim 18** The first transistor is part of a first circuit, and the second transistor is part of a second circuit. The semiconductor device according to claim 16. **Claim 19** The first circuit is an RF switch, and the second circuit is a power amplifier or a low noise amplifier. The semiconductor device according to claim 18. **Claim 20** A semiconductor wafer including a III-N material structure, the III-N material structure including a III-N back barrier, and a III-N channel layer on the N surface of the III-N back barrier, having a group III surface adjacent to the III-N back barrier and an N surface on the opposite side of the group III surface, the bandgap of the III-N back barrier being larger than the bandgap of the III-N channel layer, the III-N channel layer, and a first III-N etch stop layer on the N surface of the III-N channel layer, and a first III-N cap layer on the N surface of the first III-N etch stop layer, and a second III-N etch stop layer on the N surface of the first III-N cap layer a semiconductor wafer including the above, and a first transistor in a first region of the semiconductor wafer, including a first portion of the III-N back barrier, and a first portion of the III-N channel layer having a first 2DEG channel, and a first portion of the first III-N etch stop layer, and a first portion of the first III-N cap layer, and a first portion of the second III-N etch stop layer, and a second III-N cap layer on the N surface of the second III-N etch stop layer, and a first recess extending through the entire thickness of the second III-N cap layer, having a first bottom surface, and a first gate at least partially present within the first recess, and a first source and a first drain, and A first transistor, including the first gate being between the first source and the first drain, A second transistor, A second part of the III-N back barrier, A second part of the III-N channel layer having a second 2DEG channel, A second part of the first III-N etch stop layer, A second part of the first III-N cap layer, A second part of the second III-N etch stop layer, A second recess extending through the entire thickness of both the second part of the second III-N etch stop layer and the second part of the first III-N cap layer, the second recess having a second bottom surface, A second gate at least partially present within the second recess, A second source and a second drain A second transistor, including the second gate being between the second source and the second drain A semiconductor device including

21. The semiconductor device according to claim 20, wherein the second III-N cap layer is not on the second part of the second III-N etch stop layer.

22. The semiconductor device according to claim 21, wherein the first recess further extends through the entire thickness of the first part of the second III-N etch stop layer.

23. The semiconductor device according to claim 22, wherein the first recess further extends through the entire thickness of the first part of the first III-N cap layer.

24. The semiconductor device according to claim 20, wherein the first transistor is part of a first circuit and the second transistor is part of a second circuit.

25. The semiconductor device according to claim 24, wherein the first circuit is a power amplifier or an RF switch, and the second circuit is a low noise amplifier.

26. The first transistor further includes a first part of a dielectric layer on the second III-N cap layer, The second transistor further includes a second part of the dielectric layer on the second part of the second III-N etch stop layer, The semiconductor device according to claim 20, wherein the first part of the dielectric layer is thicker than the second part of the dielectric layer.

27. The distance between the first bottom surface of the first portion of the III-N channel layer and the group-III surface is at least 1.2 times the distance between the second bottom surface of the second portion of the III-N channel layer and the group-III surface, the semiconductor device according to claim 20.

28. A method of forming a semiconductor device, comprising: providing a semiconductor wafer including a III-N material structure, the III-N material structure including: a III-N back barrier; and a III-N channel layer on the N surface of the III-N back barrier, wherein the III-N channel layer has a group-III surface adjacent to the III-N back barrier and an N surface on the opposite side of the group-III surface, and the bandgap of the III-N back barrier is larger than the bandgap of the III-N channel layer; forming a first transistor in a first region of the semiconductor wafer, the first transistor including a first portion of the III-N back barrier and a first portion of the III-N channel layer, the first portion of the III-N channel layer having a first 2DEG channel, and forming the first III-N transistor including: etching a portion adjacent to the N surface of the first portion of the III-N channel layer to form a first recess having a first bottom surface; depositing at least partially a first gate in the first recess; depositing a first source and a first drain, wherein the first gate is deposited between the first source and the first drain; forming a second transistor in a second region of the semiconductor wafer, the second transistor including a second portion of the III-N back barrier and a second portion of the III-N channel layer, the second portion of the III-N channel layer having a second 2DEG channel, and forming the second III-N transistor including: 3]]thinning the second portion of the III-N channel layer by etching; etching a portion adjacent to the N surface of the second portion of the III-N channel layer to form a second recess having a second bottom surface; depositing at least partially a second gate in the second recess; depositing a second source and a second drain, wherein the second gate is deposited between the second source and the second drain, comprising. A method in which a thickness of the first portion of the III-N channel layer in a region between the first gate and the first drain is greater than 1.2 times a thickness of the second portion of the III-N channel layer in a region between the second gate and the second drain.

29. The method according to claim 28, wherein thinning the second portion of the III-N channel layer includes thinning the entire second portion of the III-N channel layer.

Images