Driving chip, light emitting substrate and test method thereof, display device

Abstract

A driver chip is disclosed. The driver chip includes a logic control module, at least one output pin, and a first functional pin. The at least one output pin is electrically connected to the logic control module. The first functional pin is electrically connected to the logic control module. The first functional pin is capable of receiving a test signal. The logic control module is configured to generate a test current through one of the output pins in response to the test signal.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and more particularly to a driving chip, a light emitting substrate and a test method thereof, and a display device. [Background technology]

[0002] The display device may be used to display an image. With the rapid development of display technology, the display device is gradually becoming more prevalent in people's lives. Summary of the Invention [Means for solving the problem]

[0003] In one aspect, a driver chip is provided, the driver chip comprising a logic control module, at least one output pin, and a first functional pin, the at least one output pin electrically connected to the logic control module, the first functional pin electrically connected to the logic control module, the first functional pin capable of receiving a test signal, and the logic control module configured to generate a test current through each of the output pins in response to the test signal.

[0004] In some embodiments, the test signal comprises a switch signal, which is used to control the logic control module to generate a test current through one of the output pins, respectively.

[0005] In some embodiments, the driver chip further includes an address pin and a relay pin. The address pin is electrically connected to the logic control module. The address pin is capable of receiving drive data, and the drive data includes address check information and multiple pieces of drive information corresponding to multiple cascaded driver chips. The logic control module is configured to allocate one piece of drive information corresponding to the current driver chip according to the address check information, update the address check information, and generate drive data including the updated address check information. The relay pin is electrically connected to the logic control module. The relay pin is capable of outputting the drive data including the updated address check information.

[0006] In some embodiments, the test signal includes test data and general address information, and the general address information can match initialization address information of any of the driver chips. The logic control module is configured to generate a test current flowing through any of the output pins in response to the test data.

[0007] In some embodiments, the driver chip further comprises an address pin and a relay pin. The address pin is electrically connected to the logic control module. The address pin is capable of receiving an address signal. The logic control module is configured to configure address information of the driver chip and generate a relay signal in response to the address signal. The relay pin is electrically connected to the logic control module. The relay pin is capable of outputting the relay signal. The first function pin is further capable of receiving drive data. The drive data includes a plurality of address verification information pieces and a plurality of drive information pieces corresponding to the plurality of address verification information pieces. The logic control module is configured to receive corresponding drive information in response to the address verification information when the address verification information matches the address information of the driver chip, and generate a corresponding drive current for the at least one output pin in response to the received drive information.

[0008] In some embodiments, the driver chip further comprises a second functional pin and a first connecting line. The second functional pin is connected to the first functional pin via the first connecting line. The second functional pin is capable of outputting a test signal. The driver chip has first and second edges that are parallel to each other. One of the first and second functional pins is close to the first edge and the other is close to the second edge.

[0009] In some embodiments, the driver chip further includes a third edge located between a first end of the first edge and a first end of the second edge. When the driver chip includes address pins and relay pins, one of the address pins and the relay pins is closer to the first edge and the other is closer to the second edge. The address pins and the relay pins are closer to the third edge than the first functional pins and the second functional pins.

[0010] In some embodiments, the driver chip further comprises at least one ground pin, the at least one ground pin being electrically connected to the logic control module, the ground pin being capable of receiving a ground signal, and the ground pin being located between the address pin and the relay pin.

[0011] In some embodiments, the driver chip further comprises a first power pin, the first power pin is electrically connected to the logic control module, the first power pin is capable of receiving a power signal, and the first power pin is proximate to the first edge or the second edge.

[0012] In some embodiments, the driver chip further includes a second power supply pin and a second connecting line. The second power supply pin is connected to the first power supply pin via the second connecting line. The second power supply pin is capable of outputting the power supply signal. One of the first power supply pin and the second power supply pin is close to the first edge and the other is close to the second edge. The first power supply pin and the second power supply pin are farther from the third edge than the address pin and the relay pin.

[0013] In some embodiments, the driver chip further includes a fourth edge portion located between a second end of the first edge portion and a second end of the second edge portion, and the number of the output pins is plural, the plural output pins being close to the fourth edge portion and arranged along an extension direction of the fourth edge portion.

[0014] In another aspect, a light emitting substrate is provided, the light emitting substrate including a plurality of cascaded driver chips and a plurality of device groups, the driver chip being the driver chip according to any one of the above embodiments, wherein a first end of one device group corresponds to and is electrically connected to at least one output pin of one driver chip.

[0015] In some embodiments, when the driver chip further comprises an address pin, a relay pin, a first power supply pin, and at least one ground pin, the relay pin of the driver chip located in the previous level is electrically connected to the address pin of the driver chip located in the next level. The light emitting substrate further comprises a conductive layer. The conductive layer includes a second voltage line, an address signal line, a first voltage line, a test signal line, and a ground line. The second voltage line is electrically connected to a second end of each of the device groups. The address signal line is electrically connected to the address pin of the first driver chip. The first voltage line is electrically connected to the first power supply pin of the first driver chip. The test signal line is electrically connected to the first function pin of the first driver chip. The ground line is electrically connected to at least one ground pin of each of the driver chips. The second voltage line, the address signal line, the first voltage line, the test signal line, and the ground line do not overlap.

[0016] In some embodiments, when the driver chip further comprises a second functional pin, the second functional pin is electrically connected to the first functional pin of the driver chip at this level and the first functional pin of the driver chip at the next level, respectively.

[0017] In some embodiments, when the driver chip further comprises a second power pin, the second power pin is electrically connected to the first power pin of the driver chip at this level and the first power pin of the driver chip at the next level, respectively.

[0018] In some embodiments, the address signal lines are configured to transmit address signals, and the test signal lines are configured to transmit test signals and drive data in a time-sharing manner, or the address signal lines are configured to transmit drive data, and the test signal lines are configured to transmit test signals.

[0019] In another aspect, a method for testing a light emitting substrate is provided, the light emitting substrate being the light emitting substrate described in any of the above embodiments. The test method includes the steps of: inputting a test signal to a first functional pin of each driver chip, causing each driver chip to generate a test current through one of its output pins in response to the test signal; and determining the light emitting state of a device group electrically connected to one of the driver chips. If the device group emits light normally, determining that the device group and the corresponding driver chip are normally connected; and if the device group emits no light or if the light emission is abnormal, determining that the device group and the corresponding driver chip are abnormally connected.

[0020] In some embodiments, the step of inputting a test signal to a first functional pin of each of the driver chips includes the step of inputting a switch signal to a first functional pin of each of the driver chips, the switch signal being used to control the logic control module to generate a test current flowing through one of the output pins, respectively.

[0021] In some embodiments, the test method further includes a step of inputting driving data to an address pin of a first driving chip among a plurality of cascaded driving chips, the driving data including address inspection information and a plurality of driving information corresponding to the plurality of cascaded driving chips, the driving chip arranging one driving information corresponding to the current driving chip according to the address inspection information, a device group connected to the driving chip generating a corresponding driving current according to the driving information, the driving chip updating the address inspection information, generating driving data including the updated address inspection information, and outputting the driving data including the updated address inspection information to a next-level driving chip; and a step of determining whether a non-light-emitting device group exists in the device groups connected to the plurality of cascaded driving chips, and if it is determined that a non-light-emitting device group exists, determining that an abnormality exists in the driving chip connected to the first non-light-emitting device group according to the cascading order, and if it is determined that a non-light-emitting device group does not exist, determining that no abnormality exists in the plurality of cascaded driving chips.

[0022] In some embodiments, inputting a test signal to a first functional pin of each driver chip includes inputting a test signal including test data and first universal address information to a first functional pin of each driver chip, the first universal address information being matchable with initialization address information of any of the driver chips.

[0023] In some embodiments, the test method further includes inputting an address signal to an address pin of a first driver chip among the plurality of cascaded driver chips. The driver chip configures address information of the driver chip according to the address signal and generates a relay signal. The relay signal is the same as the address signal. The test method further includes inputting a test signal including test data and second general address information to a first functional pin of each driver chip, where the second general address information can match updated address information of any of the driver chips; and determining whether a non-light-emitting device group exists among device groups connected to the plurality of cascaded driver chips. If it is determined that a non-light-emitting device group exists, determining that an abnormality exists in the driver chip connected to the first non-light-emitting device group according to the cascading order; and if it is determined that a non-light-emitting device group does not exist, determining that no abnormality exists in the plurality of cascaded driver chips.

[0024] In some embodiments, the test method further includes the steps of: inputting an address signal to an address pin of a first driver chip among a plurality of cascaded driver chips, wherein the driver chip arranges address information of the driver chip according to the address signal and generates relay information; inputting drive data to a first functional pin of each driver chip among the plurality of cascaded driver chips, wherein the drive data includes a plurality of address verification information and a plurality of drive information corresponding to the plurality of address verification information; and if the address verification information matches the address information of the driver chip for any of the driver chips, the logic control module receives corresponding drive information according to the address verification information and generates a drive current corresponding to the at least one output pin according to the received drive information; and determining whether a non-light-emitting device group exists in the device groups connected to the plurality of cascaded driver chips, and if it is determined that a non-light-emitting device group exists, determining that an abnormality exists in the driver chip connected to the first non-light-emitting device group according to the cascading order; and if it is determined that a non-light-emitting device group does not exist, determining that no abnormality exists in the plurality of cascaded driver chips.

[0025] In another aspect, there is provided a display device, comprising a light emitting substrate according to any of the above examples. [Brief explanation of the drawings]

[0026] In order to more clearly explain the technical solutions according to the present disclosure, the drawings used in some embodiments of the present disclosure will be briefly described below. It is clear that the drawings in the following description are only a portion of the drawings in some embodiments of the present disclosure. Those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings in the following description can be considered as schematic diagrams and do not limit the actual dimensions of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure. [Figure 1]FIG. 1 is a diagram illustrating the configuration of a display device according to some embodiments of the present disclosure. [Figure 2] 1A and 1B are structural diagrams of a light-emitting substrate according to some embodiments of the present disclosure. [Figure 3] 1 is a structural diagram of a driver chip according to some embodiments of the present disclosure. [Figure 4] 1 is a structural diagram of a driver chip in some implementations. [Figure 5] FIG. 1 illustrates the interconnection of two driver chips according to some embodiments of the present disclosure. [Figure 6] FIG. 2 is a diagram illustrating a data format of drive data according to some embodiments of the present disclosure. [Figure 7] FIG. 10 illustrates another data format of drive data according to some embodiments of the present disclosure. [Figure 8] 10A and 10B are structural diagrams of driver chips according to some other embodiments of the present disclosure. [Figure 9] 10A and 10B are structural diagrams of driver chips according to some further embodiments of the present disclosure. [Figure 10] 10A and 10B are structural diagrams of driver chips according to some further embodiments of the present disclosure. [Figure 11] 10A to 10C are structural diagrams of light-emitting substrates according to some other embodiments of the present disclosure. [Figure 12] FIG. 12 is a partial enlarged view of the R position in FIG. [Figure 13] FIG. 10 is a circuit block diagram of a light emitting substrate according to some further embodiments of the present disclosure. [Figure 14] FIG. 14 is a circuit block diagram of the driver chip in FIG. [Figure 15] FIG. 14 is yet another circuit block diagram of the driver chip in FIG. 13. [Figure 16] 1 is a flowchart of a method for detecting a light-emitting substrate according to some embodiments of the present disclosure. [Figure 17] 10 is a flowchart of a method for detecting a light-emitting substrate according to some other embodiments of the present disclosure. [Figure 18] 10 is a flowchart of a method for detecting a light-emitting substrate according to some further embodiments of the present disclosure. [Figure 19] 10 is a flowchart of a method for detecting a light-emitting substrate according to some further embodiments of the present disclosure. [Figure 20] 10 is a flowchart of a method for detecting a light-emitting substrate according to some further embodiments of the present disclosure. [Figure 21] 10 is a flowchart of a method for detecting a light-emitting substrate according to some further embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, several embodiments of the present disclosure will be described clearly and completely with reference to the drawings. Of course, the embodiments described herein are only a part of the embodiments of the present disclosure, and are not all of the embodiments. All other embodiments that can be obtained by those skilled in the art based on the embodiments in the present disclosure shall fall within the scope of protection of the present disclosure.

[0028] Unless the context indicates otherwise, in this specification and claims, the term "comprise" and other forms thereof, such as the third-person singular "comprises" and the present participle form "comprising," should be interpreted in an open, inclusive sense, i.e., "including, but not limited to." In the description, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," "some examples," and the like, are intended to indicate that a particular feature, structure, material, or characteristic associated with this embodiment or examples is included in at least one embodiment or example of the present disclosure. General references to the above terms do not necessarily refer to the same embodiment or example. Furthermore, a described particular feature, structure, material, or characteristic may be included in any one or more embodiments or examples in any appropriate manner.

[0029] Hereinafter, the terms "first" and "second" are for descriptive purposes only and should not be understood as indicating or implying the relative importance or quantity of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In describing the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more than two.

[0030] In describing some embodiments, the term "connected" and its derivatives may be used. For example, in describing some embodiments, the term "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other.

[0031] In this specification, the use of "disposed to" is intended to be open and inclusive language and does not exclude equipment adapted or arranged to perform additional tasks or steps.

[0032] Also, the use of "based on" is meant to be open and inclusive, as a process, step, calculation, or other action performed "based on" one or more conditions or values may, in fact, be based on additional conditions or values beyond those.

[0033] As used herein, "parallel" and "perpendicular" include the described situation and situations approximating the described situation, and this range of approximations is within an acceptable deviation range, which is determined by taking into account the measurement considered by a person skilled in the art and the error associated with measuring a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes true parallel and approximately parallel, where the acceptable deviation range for approximately parallel may be, for example, a deviation within 5°. "Perpendicular" includes true perpendicular and approximately perpendicular, where the acceptable deviation range for approximately perpendicular may also be, for example, a deviation within 5°.

[0034] When a layer or element is referred to as being on another layer or substrate, it is understood that the layer or element may be directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and another layer or substrate.

[0035] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized illustrative drawings. In the drawings, thicknesses of layers and regions are exaggerated for clarity. Accordingly, variations in shape relative to the drawings due, for example, to manufacturing techniques and / or tolerances are to be expected. Thus, the exemplary embodiments are not limited to the shapes of regions illustrated herein, but should be construed to include deviations in shape due to manufacturing or otherwise. For example, an etching region shown as a rectangle typically has curved features. Thus, the regions shown in the drawings are exemplary in nature, and their shapes are not intended to represent the actual shape of the regions of the facility, nor are they intended to limit the scope of the exemplary embodiments.

[0036] 1 is a block diagram of a display device according to some embodiments of the present disclosure. Referring to FIG. 1, some embodiments of the present disclosure provide a display device 300, which includes a light-emitting substrate 200.

[0037] For example, the display device 300 may be a liquid crystal display (LCD), a mini light-emitting diode (Mini LED) display, or a micro light-emitting diode (Micro LED) display.

[0038] When the display device 300 is a liquid crystal display device, in some embodiments, the display device 300 includes a cover glass, a liquid crystal display panel, and a backlight assembly. The backlight assembly is used to provide a light source to the liquid crystal display panel. Here, the backlight assembly includes a light emitting substrate 200, which provides light to the liquid crystal display panel, allowing the liquid crystal display panel to display an image. In some examples, the backlight module in the display device 300 may further include an optical film, which is located on the side of the light emitting substrate 200 closer to the liquid crystal display panel. The optical film may include a reflective sheet, a diffusion plate, a brightness enhancement film (prism sheet), a diffusion sheet, etc., and may be used to improve the brightness and uniformity of light.

[0039] When the display device 300 is a Mini LED display device or a Micro LED display device, in some embodiments, the display device 300 includes an emission substrate 200, which may display an image. In some examples, the display device 300 may further include a reflection-reducing film layer and a protective cover, where the reflection-reducing film layer is located between the emission substrate 200 and the protective cover. The reflection-reducing film layer includes a polarizing sheet, which may be a circular polarizing sheet. Here, the polarizing sheet can reduce reflection of external light and prevent dazzling effects caused by the emission substrate 200 reflecting ambient light.

[0040] By way of example, the display device 300 described above may be any device that displays text or images, whether moving (e.g., video) or static (e.g., still images). More specifically, it is anticipated that the display device of the embodiment may be applied to or associated with multiple electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, global positioning system (GPS) receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, car displays (e.g., speedometer displays, distance meters, etc.), navigators, cockpit controllers and / or displays, camera view displays (e.g., rearview camera displays in vehicles), electronic photography, electronic signage or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of jewelry), etc.

[0041] FIG. 2 is a structural diagram of a light emitting substrate according to some embodiments of the present disclosure.

[0042] In some embodiments of the present disclosure, a light emitting substrate 200 is provided. Referring to Fig. 2, the light emitting substrate 200 includes a plurality of cascaded driver chips 100 and a plurality of device groups O respectively connected to each driver chip.

[0043] In some examples, one device group O includes at least one light-emitting unit E. Illustratively, one light-emitting unit E may include at least one light-emitting element. Here, one light-emitting unit E may include only one light-emitting element. Alternatively, one light-emitting unit E may include two or more light-emitting elements electrically connected to each other. When one light-emitting unit E includes two or more light-emitting elements, the two or more light-emitting elements may be connected in series, in parallel, or in a series-parallel connection manner.

[0044] For example, the light-emitting element may be a light-emitting diode (LED), a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), etc. In this embodiment, the light-emitting unit E may emit light under the driving of the driving chip 100, and may thus be applied to devices such as a display device and a lighting device.

[0045] When the display device 300 is a liquid crystal display device, in some examples, the light emitting substrate 200 is a backlight source for the display device 300 and is used to provide light to the liquid crystal display device. Each device group O may be controlled by a driver chip 100, and each light emitting unit E in the device group O may be controlled independently. In this way, the display device can realize local dimming, achieve a high dynamic range (HDR) effect, and improve the display quality of the display device 300. In each device group O, the number and electrical connection method of the light emitting units E are the same. In each light emitting unit E, the number and electrical connection method of the light emitting elements are the same. In this way, the uniformity of the distribution of the light emitting units E on the light emitting substrate can be ensured, which is advantageous for improving the uniformity of the light emission of the light emitting substrate and reducing the difficulty of debugging the backlight module.

[0046] When the display device is a Mini LED display device or a Micro LED display device, in some examples, the light-emitting units E (e.g., Micro LEDs, Mini LEDs, etc.) may emit light to directly display a pattern. Exemplarily, the light-emitting units E may be light-emitting elements capable of emitting light of the same color, for example, blue LEDs, red LEDs, green LEDs, or yellow LEDs. Thus, the display device may be a monochromatic display device, such as an instrument dial, a traffic light indicator screen, or the like. Exemplarily, the light-emitting units E may include a plurality of light-emitting elements of different colors, for example, at least two of red LEDs, green LEDs, blue LEDs, yellow LEDs, etc., and the light-emitting units E of different colors may be independently controlled. Thus, the display device can display colors by mixing light.

[0047] In one embodiment of the present disclosure, the device groups O on the light-emitting substrate 200 are distributed in an array at equal intervals along the row and column directions. Exemplarily, the device groups O may be arranged into a plurality of device group rows, each of which is arranged at equal intervals along the column direction and includes a plurality of light-emitting units E arranged at equal intervals along the row direction. The light-emitting units E may be arranged into a plurality of element columns, each of which is arranged at equal intervals along the row direction and includes a plurality of functional elements arranged at equal intervals along the column direction. In this way, the uniformity of the distribution of the device groups O on the light-emitting substrate 200 can be improved.

[0048] FIG. 3 is a structural diagram of a driver chip according to some embodiments of the present disclosure.

[0049] Some embodiments of the present disclosure provide a driver chip 100. Referring to Figure 3, the driver chip 100 includes a logic control module CTR, at least one output pin OUT, and a first function pin Q1.

[0050] At least one output pin OUT is electrically connected to the logic control module CTR. In one embodiment of the present disclosure, referring to FIG. 3, FIG. 3 shows an example in which the driver chip 100 has four output pins OUT. The driver chip 100 has four output pins OUT, and each output pin OUT is connected to a light-emitting unit E (as shown in FIG. 2), so that one driver chip 100 can drive at least four light-emitting units E. Compared with a solution in which one driver chip drives one light-emitting unit E, the number of driver chips 100 can be reduced to one-fourth, and the amount of driver chips 100 used can be significantly reduced, thereby reducing the cost of the light-emitting substrate 200.

[0051] Although the driver chips 100 in some embodiments of the present disclosure are slightly larger in volume than driver chips with only one output pin, these embodiments can significantly reduce the number of driver chips 100 on the light-emitting substrate 200, thereby reducing the area occupied by all driver chips 100 on the light-emitting substrate 200. This is also beneficial for improving the binding efficiency of the driver chips 100 and the yield of the light-emitting substrate 200.

[0052] For example, the driver chip 100 in some embodiments of the present disclosure has four output pins OUT, and its area is twice that of a driver chip with only one output pin OUT. However, the number of driver chips 100 in the light emitting substrate 200 of this embodiment can be reduced to 1 / 4, and therefore the area occupation rate of the driver chips 100 in the light emitting substrate 200 of this embodiment can be reduced to 1 / 2 (compared to the light emitting substrate 200 in which one driver chip drives one light emitting unit E).

[0053] It is understood that in some other embodiments, the driver chip 100 may have three, five, or six output pins OUT. Here, the design in which one driver chip 100 has four output pins OUT is more advantageous in reducing the area occupied by the driver chip 100 and saving resources than the design in which one driver chip 100 has three output pins OUT. The design in which one driver chip 100 has four output pins OUT is less advantageous in preventing the driver chip 100 from generating a large amount of heat during operation and improving the service life of the driver chip 100 compared to the design in which one driver chip 100 has five or six output pins OUT.

[0054] The first functional pin Q1 is electrically connected to the logic control module CTR, and the first functional pin Q1 is capable of receiving a test signal. The logic control module CTR is configured to generate a test current through one of the output pins OUT in response to the test signal.

[0055] In this embodiment, the driver chip 100 may use the first functional pin Q1 to provide a test signal to the logic control module CTR, which then generates a test current through one of its output pins OUT in response to the test signal. The test current may drive the light emitting units E to emit light. By providing the test signal to the first functional pin Q1 of each driver chip 100, a lighting test of the light emitting units E electrically connected to each driver chip 100 can be achieved in a single detection operation. If the light emitting units E emit light normally, it can be determined that the light emitting units E are properly connected. If the light emitting units E do not emit light, it can be determined that the light emitting units E have a problem (e.g., a short circuit, an open circuit, or other defect) and need to be repaired, thereby improving the efficiency of inspection and repair of the driver chips 100.

[0056] In some examples, the test currents flowing through any of the output pins OUT may all be the same. It will be understood that in other examples, the currents flowing through each output pin OUT may all be different, or some may be the same. This disclosure is not limited in this respect.

[0057] FIG. 4 is a structural diagram of a driver chip in some implementations.

[0058] In some possible implementations, referring to FIG. 4, it should be noted that the driver chip has an output pin OUT, an address pin Di, a relay pin Do, a data pin Data, a ground pin GND, and a power supply pin V. The address pin Di is used to receive an address signal, and address information of the driver chip is arranged according to the address signal, and a relay signal is generated. The relay signal may be the address signal of the next-level driver chip. The data pin Data is used to receive driving data, and the driving data includes driving information and address verification information. If the address verification information and the address information match, at least one light-emitting unit connected to the driver chip generates a corresponding driving current according to the driving information, and one output pin of the driver chip is controlled to form an electrical path with the corresponding light-emitting unit, and the driving current flows through the electrical path.

[0059] Because the address signal must be converted into a relay signal and sent to the next-level driver chip, if a driver chip's pins are poorly welded, the preceding driver chips drive the light-emitting units normally, but the light-emitting units electrically connected to the driver chip in question do not emit light, it can be determined that the light-emitting unit E has a problem and needs to be repaired. Because the driver chips following the driver chip with the poorly welded pins cannot receive the relay signal, that is, the driver chip in question cannot provide driving current, and the corresponding electrically connected light-emitting units cannot emit light. However, the driver chip in question cannot determine whether the light-emitting units electrically connected to the driver chip in question are normally connected. This requires repeated lighting tests one level at a time, which reduces the efficiency of driver chip inspection and repair.

[0060] Meanwhile, the driver chip 100 according to some embodiments of the present disclosure is provided with a first functional pin Q1 and a second functional pin Q2. The first functional pin Q1 may receive a test signal and transmit the test signal to the logic control module CTR. The logic control module CTR generates a test current through one of its output pins OUT in response to the test signal. The test current may drive the light emitting unit E to emit light. The second functional pin Q2 is electrically connected to the first functional pin Q1. The second functional pin Q2 may output a test signal to the next-level driver chip 100. A single detection operation can be used to test the lighting of the light emitting units E electrically connected to each driver chip 100. If the light emitting unit E does not emit light, it can be determined that there is a problem with the light emitting unit E. This eliminates the need to continuously repeat the three steps of writing addresses, inputting driving data, and repairing until it is determined whether all light emitting units require inspection or repair, thereby effectively improving the inspection and repair efficiency of the driver chip 100.

[0061] 3 , in some embodiments, the driver chip 100 has a first edge W1 and a second edge W2 that are parallel to each other. The driver chip 100 further has a fourth edge W4 located between a second end of the first edge W1 and a second end of the second edge W2. The number of output pins OUT is plural, and the plurality of output pins OUT are close to the fourth edge W4 and are arranged along the extension direction of the fourth edge W4.

[0062] In this embodiment, the driver chip 100 has a plurality of output pins OUT, which are close to the fourth edge W4 and arranged along the direction of the fourth edge W4, which facilitates electrical connection between the plurality of output pins OUT and the same second voltage line outside the driver chip 100, prevents overlapping between signal lines connected to the driver chip 100, and is advantageous for the layout of wiring on the light emitting substrate.

[0063] 3 illustrates an example in which one end of the fourth edge W4 is directly connected to the first edge W1 and the other end of the fourth edge W4 is directly connected to the second edge W2. It is understood that in some other embodiments, the fourth edge W4 and the first edge W1 are connected via other edges. In still other embodiments, the fourth edge W4 and the second edge W2 are connected via other edges.

[0064] FIG. 5 is a diagram illustrating the interconnection of two driver chips according to some embodiments of the present disclosure.

[0065] 5, in some embodiments, the driver chip 100 further includes a second functional pin Q2. The second functional pin Q2 is electrically connected to the first functional pin Q1. The second functional pin Q2 can output a test signal to the next-level driver chip 100.

[0066] With the above structure, the first functional pin Q1 is used to provide a test signal to the logic control module CTR, and the logic control module CTR generates a test current through one of the output pins OUT in response to the test signal. The test current may drive the light emitting unit E to emit light. Next, the second functional pin Q2 is used to output the test signal to the first functional pin Q1 of the next-level driver chip 100. In this way, a single detection operation can be used to test the lighting of the light emitting units E electrically connected to each driver chip 100. If the light emitting unit E emits light normally, it can be determined that the light emitting unit E is normally connected. If the light emitting unit E does not emit light, it can be determined that the light emitting unit E has a problem (e.g., a short circuit, an open circuit, or other defect) and needs to be repaired, thereby improving the efficiency of inspection and repair of the driver chips 100.

[0067] The second functional pin Q2 is electrically connected to the first functional pin Q1. The second functional pin Q2 and the first functional pin Q1 receive the same signal. Therefore, a test signal can be output to the first functional pin Q1 of the next-level driver chip 100 via the second functional pin Q2. This facilitates the wiring design between the driver chips 100 in a cascade design.

[0068] In addition, whether the second function pin Q2 needs to be set may be determined depending on the total number of pins in the driver chip 100, thereby ensuring that the total number of pins in the driver chip 100 is an even number.

[0069] 5, in some embodiments, the driver chip 100 includes a first functional pin Q1 and a second functional pin Q2, which are located on two relatively parallel sides of the driver chip 100, respectively, and which are electrically connected to each other.

[0070] The first functional pin Q1 may receive a test signal and send the test signal to the logic control module CTR, which may generate a test current through any of the output pins OUT in response to the test signal, and the test current may drive the light emitting unit E to emit light.

[0071] The second functional pin Q2 is electrically connected to the first functional pin Q1. The second functional pin Q2 can output a test signal to the next-level driver chip 100. That is, the second functional pin Q2 of the previous-level driver chip 101 can output a test signal to the first functional pin Q1 of the next-level driver chip 102, and the logic control module CTR in the next-level driver chip 102 generates a test current flowing through one of the output pins OUT in response to the test signal. As described above, the next-level driver chip 102 can continue to output the test signal to the next-level driver chip.

[0072] In this embodiment, the driver chip 100 may use the first functional pin Q1 to provide a test signal to the logic control module CTR, which then generates a test current through one of its output pins OUT in response to the test signal. The test current may drive the light emitting unit E (as shown in FIG. 2 ). The second functional pin Q2 is electrically connected to the first functional pin Q1. The second functional pin Q2 may output a test signal to the next-level driver chip 100. This structure allows for a single detection operation to test the light emitting units E electrically connected to each driver chip 100. If the light emitting unit E emits light normally, it may be determined that the light emitting unit E is properly connected. If the light emitting unit E does not emit light, it may be determined that the light emitting unit E has a problem and needs to be repaired, thereby improving the efficiency of inspection and repair of the driver chip 100. The first functional pin Q1 and the second functional pin Q2 are arranged along the first direction X, which is advantageous for wiring design.

[0073] 5, in some embodiments, the driver chip 100 further includes a second functional pin Q2 and a first connecting line L1. The second functional pin Q2 is connected to the first functional pin Q1 via the first connecting line L1. The second functional pin Q2 outputs a test signal to the next-level driver chip. The driver chip 100 has a first edge W1 and a second edge W2 that are parallel to each other. One of the first functional pin Q1 and the second functional pin Q2 is close to the first edge W1, and the other is close to the second edge W2.

[0074] In this embodiment, as shown in FIG. 5 , the first edge W1 is the upper edge of the driver chip 100, and the second edge W2 is the lower edge of the driver chip 100. The lower edge of the driver chip 101 at the previous level is close to the upper edge of the driver chip 102 at the next level. Thus, the first functional pin Q1 is located close to the first edge W1, and the second functional pin Q2 is located close to the second edge W2. That is, the second functional pin Q2 of the driver chip 101 at the previous level is close to the first functional pin Q1 of the driver chip 102 at the next level. A single external connection line K1 may be used to electrically connect the second functional pin Q2 of the driver chip 101 at the previous level to the first functional pin Q1 of the driver chip 102 at the next level. This is advantageous for making full use of the space between two adjacent cascaded driver chips 100, shortening the length of the external connection line K1, and facilitating flexible placement of the external connection line K1, thereby facilitating the subsequent wiring layout of the light-emitting substrate.

[0075] Illustratively, FIG. 5 shows that the first functional pin Q1 is close to the first edge W1 and the second functional pin Q2 is close to the second edge W2.

[0076] In some examples, the first connection line L1 may be disposed inside the driver chip 100. In other examples, the first connection line L1 is disposed on the light-emitting substrate, i.e., located outside the driver chip 100. When the first connection line L1 is disposed on the light-emitting substrate, the orthogonal projection of the first connection line L1 on the light-emitting substrate is located between the orthogonal projections of the first functional pin Q1 and the second functional pin Q2 on the light-emitting substrate. That is, the first connection line L1 is disposed between two adjacent cascaded driver chips 100, which makes full use of the space between the adjacent driver chips 100 and reduces the occupation of the left and right spaces of the driver chips 100 (as shown in FIGS. 3 and 5). The signal lines electrically connected to the driver chips 100 can be distributed, which is advantageous for the layout of the signal lines.

[0077] 5 illustrates an example in which the first connecting line L1 may be a wiring inside the driver chip 100 and is a straight line. The present disclosure does not specifically limit the shape or film layer position of the first connecting line L1, as long as it is located between the first functional pin Q1 and the second functional pin Q2 and is connected to the first functional pin Q1 and the second functional pin Q2.

[0078] In some embodiments, the driver chip 100 further includes a data pin Data (shown in FIG. 4). The data pin Data is used to receive driving data by connecting a data signal line. The driving data includes driving information and address verification information. The logic control module CTR is further configured to determine driving information corresponding to the address verification information when the address verification information matches the address information of the driver chip 100, and to control at least one light-emitting unit E (shown in FIG. 2) connected to the driver chip 100 to generate a corresponding driving current according to the driving information, and to control at least one output pin OUT of the driver chip 100 and the corresponding light-emitting unit E to form an electrical path, so that the driving current flows through the electrical path.

[0079] In some embodiments, still referring to FIG. 5 , the driver chip 100 further includes an address pin Di and a relay pin Do. The address pin Di is electrically connected to the logic control module CTR. The address pin Di is capable of receiving drive data. The drive data includes address check information and multiple pieces of drive information corresponding to multiple cascaded driver chips. The logic control module CTR is configured to obtain one piece of drive information corresponding to the current driver chip according to the address check information, update the address check information, and generate drive data including the updated address check information. The relay pin Do is electrically connected to the logic control module. The relay pin Do is capable of outputting the drive data including the updated address check information to the next-level driver chip 102.

[0080] It is understood that the address pin Di of the driver chip 101 of this level can receive driving data, and the driving data includes address checking information of the driver chip 101 of this level and multiple driving information corresponding to all cascaded driver chips. The logic control module CTR of the driver chip 101 of this level receives the driving data and obtains driving information corresponding to the address checking information of the driver chip 101 of this level according to the address checking information in the driving data. The logic control module CTR controls at least one light-emitting unit E (shown in FIG. 2 ) connected to the driver chip 100 to generate a corresponding driving current, and at least one output pin OUT of the driver chip 100 and the corresponding light-emitting unit E to form an electrical path, and the driving current may flow through the electrical path.

[0081] Then, the logic control module CTR of the driver chip 101 at this level updates the address inspection information and generates updated address inspection information. The updated address inspection information includes the updated address inspection information. The relay pin Do can output the updated address inspection information to the driver chip 102 at the next level.

[0082] For example, the logic control module CTR further updates the received driving data, i.e., updates the address check information in the driving data. The address check information in the driving data is the number of start identification bits and / or end identification bits. The logic control module CTR subtracts 1 from the number of start identification bits and / or adds 1 to the number of end identification bits in the driving data, and outputs the re-edited driving data to the address pin Di of the next-level driving chip through its relay pin. Of course, the driving chip 100 may use other different functions to generate new address check information.

[0083] In addition, the address pin Di in the driver chip 100 according to the above embodiment may be used to receive driving data. The driving data includes address verification information and multiple pieces of driving information corresponding to multiple cascaded driver chips. The logic control module CTR of the driver chip 101 at this level updates the address verification information and generates updated address verification information. The updated address verification information includes the updated address verification information. The relay pin Do can output the updated address verification information to the driver chip 102 at the next level. That is, the driving data of the address pin Di simultaneously writes the address and inputs the driving information. Compared with the method of receiving address information using the address pin Di and receiving driving data using the data pin Data, this method can reduce the number of pins in the driver chip 100, thereby reducing the area occupied by the driver chip 100 and saving resources. This method is also advantageous for the layout design of each signal wiring of the subsequent driver chip 100.

[0084] In some examples, an encoder may be provided in the external circuit (e.g., a circuit board), and a decoder may be provided in the logic control module CTR. The encoder may generate drive data by encoding it according to a 4b / 5b encoding protocol, an 8b / 10b encoding protocol, or other encoding protocol, and transmit the drive data to the address pins Di. The decoder in the logic control module CTR may obtain drive information and address check information in the drive data by decoding the drive signal.

[0085] In some embodiments, the driver chip 100 does not have a data pin, but uses an address pin Di and a relay pin Do to receive and transmit driver data, respectively.

[0086] The address pins Di of the first-level driver chips of the N driver chips 100 cascaded in sequence on the light emitting substrate 200 are connected to address signal lines. The address signal lines transmit driving data. The driving data transmitted through the address signal lines includes driving information that corresponds one-to-one with the plurality of driver chips cascaded in sequence. The driving data transmitted through the address signal lines includes driving information that corresponds one-to-one with the plurality of driver chips cascaded in sequence.

[0087] FIG. 6 is a diagram illustrating a data format of driving data according to some embodiments of the present disclosure.

[0088] In some embodiments, referring to FIG. 6, the driving data is a digital signal and is comprised of a start identification bit, address information, a register address, register byte length information, data information, and an end identification bit.

[0089] The start identification bit and the end identification bit may each occupy n bits, where n is 1 or 8. The driving data may include multiple start identification bits and multiple end identification bits, and the sum of the number of start identification bits and the number of end identification bits is a constant, for example, N+1, where N is the number of driving chips to be cascaded.

[0090] In some examples, the address information may include multiple groups, each group occupying 8 bits.

[0091] Illustratively, the address information includes the following four groups:

[0092] A command address group (dev addr) that allows different command control by assigning values to each of the eight bits of the command address.

[0093] A problem address group (vled low dev addr) capable of feeding back the location where a potential abnormality occurs in the second voltage line 10.

[0094] A fault address group (fault dev addr) that can feed back address information of the driver chip 100 in which a fault has occurred.

[0095] A fault status group (fault status) can feed back the specific status of the driver chip 100 in which a fault has occurred.

[0096] Illustratively, the address information may include only a command address.

[0097] The register address and register byte length information each occupy 8 bits. The register address corresponds to the physical address (unique) of the register unit in a driver chip, and the register byte length indicates the reserved data byte length required for the register unit, thereby making it easy to store configuration information.

[0098] The data information includes N pieces of 8-bit driving information, and the N pieces of driving information are arranged according to the cascade order of the N driving chips.

[0099] The pulse width modulation method can be used to assign a value to any bit in the driving data. For example, it can be understood that if the duty ratio of a bit is 50%, it represents the start point of the driving data, if the duty ratio of a bit is 75%, it represents logic "1", and if the duty ratio of a bit is 25%, it represents logic "0".

[0100] FIG. 7 is a diagram illustrating another data format of driving data according to some embodiments of the present disclosure.

[0101] In some examples, among N sequentially cascaded driver chips, the address pin Di of the first-level driver chip is connected to an address signal line 20. The address signal line transmits drive data. The address signal line 20 transmits drive data corresponding to the current display frame. The address pin Di of the nth-level driver chip (n is a positive integer greater than 1 and less than or equal to N) is connected to the relay pin Do of the n-1th-level driver chip, where n is a positive integer greater than 1 and less than or equal to N. Each driver chip in the sequentially cascaded N driver chips receives a fixed length of drive data, and the number of start identification bits and / or end identification bits in the drive data received by each driver chip is different. Specifically, the number of start identification bits corresponds to the order of the driver chips in the cascade sequence. For example, assuming N=3, a total of three driver chips are cascaded in sequence, where the driving data received by the first-level driver chip 100 through the address signal line 20 includes one start identification bit and three consecutive end identification bits, the driving data received by the address pin Di of the second-level driver chip 100 and output by the relay pin Do of the second-level driver chip 100 includes two consecutive start identification bits and two consecutive end identification bits, and the driving data received by the address pin Di of the third-level driver chip 100 and output by the relay pin Do of the second-level driver chip 100 includes three consecutive start identification bits and one end identification bit. The driving data received by each of the N cascaded driver chips has the same data except for the number of start identification bits and / or end identification bits, and may include address information, register address, register byte length information, and data information, i.e., the data format shown in FIG. 9. Here, the data information includes three 8-bit driving information pieces, and the three driving information pieces are arranged according to the cascading order of the three driving chips that are cascaded in order.It is understood that after the address pin Di of the driver chip 100 at each level receives the driving data, its logic control module CTR obtains only the driving information corresponding to that driver chip in the driving data, so that the driver chip provides driving current to the light-emitting unit E electrically connected to it according to the driving information, and the logic control module CTR further re-edits the received driving data, subtracts one from the number of start identification bits of the driving data and / or adds one to the number of end identification bits of the driving data, and outputs the re-edited driving data to the address pin Di of the driver chip at the next level via its relay pin Do.

[0102] In the above case, it is understood that the address check information in the driving data is the number of start identification bits and / or end identification bits.

[0103] In some embodiments, and still referring to Figure 5, the test signal includes a switch signal that is used to control the logic control module CTR to generate a test current through one of the output pins OUT, respectively.

[0104] In this case, the logic control module CTR generates a test current flowing through one of the output pins OUT in response to the switch signal. That is, the test current may be received by controlling the light-emitting unit E electrically connected to the driver chip 100 via the output pin OUT (as shown in FIG. 2). The second function pin Q2 may also output a test signal to the next-level driver chip 100. Therefore, all of the light-emitting elements E connected to the multiple cascaded driver chips 100 may receive the test current and emit light. This allows a single detection operation to test the lighting of the light-emitting units E electrically connected to each driver chip 100. If the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E, thereby effectively improving the efficiency of inspection and repair of the driver chips 100.

[0105] In some examples, the test signal may be a high-level signal or a low-level signal that controls the logic control module CTR to generate a test current through one of the output pins OUT.

[0106] In addition, in the driver chip 100, at least one output pin OUT is electrically connected to one end of the light-emitting unit E, and the other end of the light-emitting unit E is electrically connected to a second voltage line (not shown). The second voltage line is used to provide an operating voltage to the light-emitting unit E. The ground pin GND may provide a ground voltage to the driver chip 100. In this manner, the light-emitting unit E is equivalent to being connected between the second voltage line and the ground pin GND, and the logic control module CTR controls the conduction or interruption of the current path of the light-emitting unit E in response to the test signal, thereby controlling the current passing through the light-emitting unit E and the output pin OUT. In this case, when the first function pin Q1 receives the test signal and sends the test signal to the logic control module CTR, the logic control module CTR controls the conduction or interruption of the light-emitting current path of the light-emitting unit E in response to the test signal, thereby controlling the test current passing through the light-emitting unit E and the output pin OUT.

[0107] In some embodiments, if the test signal includes a switch signal, the switch signal is used to control the logic control module CTR to generate a test current flowing through one of the output pins OUT, and the drive data may be received by setting the address pin Di.

[0108] With the above structure, the driver chip 100 can perform a lighting test of the light emitting units E electrically connected to each driver chip 100 through a single detection operation, effectively improving the efficiency of inspection and repair of the driver chip 100. At the same time, the number of pins on the driver chip 100 is not increased, which is advantageous for the layout design of each signal wiring of the subsequent driver chip 100.

[0109] 5, in some other embodiments, the test signal includes test data and first general address information, the first general address information being matchable with the initialization address information of any of the driving chips, and the logic control module CTR is configured to generate a test current flowing through any of the output pins OUT in response to the test data.

[0110] Here, the driver chips 100 are set with the same initialization address before shipping. For example, the initialization address may be multiple consecutive 0s or consecutive 1s. The first general address information in the test signal is set to be the same as the initialization address of the driver chip 100. That is, if the initialization address is consecutive 0s, the general address information may be set to corresponding consecutive 0s. By matching the first general address information with the initialization address information of all driver chips 100, the logic control module CTR of each driver chip 100 obtains test data in the test signal and generates a test current through one of the output pins OUT. The light-emitting element E receives the test current and emits light. Therefore, a single detection operation can be used to perform a lighting test on the light-emitting units E electrically connected to each driver chip 100, thereby effectively improving the efficiency of inspection and repair of the driver chips 100.

[0111] In addition, in the driver chip 100, at least one output pin OUT is electrically connected to one end of the light-emitting unit E, and the other end of the light-emitting unit E is electrically connected to a second voltage line (not shown). The second voltage line is used to provide an operating voltage to the light-emitting unit E. The ground pin GND may provide a ground voltage to the driver chip 100. In this manner, the light-emitting unit E is equivalent to being connected between the second voltage line and the ground pin GND, and the logic control module CTR identifies address information and obtains test data in the test signal. The logic control module CTR controls the conduction or interruption of the current path of the light-emitting unit E according to the test data, thereby controlling the current passing through the light-emitting unit E and the output pin OUTP. In this case, when the first function pin Q1 receives the test signal and sends the test signal to the logic control module CTR, the logic control module CTR identifies first general address information and obtains test data in the test signal. The logic control module CTR controls the conduction or interruption of the light-emitting current path of the light-emitting unit E according to the test data, thereby controlling the test current passing through the light-emitting unit E and the output pin OUTP.

[0112] 5, in some embodiments, the first functional pin Q1 receives the test signal and the drive data in a time-sharing manner. For example, during one time period, the first functional pin Q1 receives the test signal. During another time period, the first functional pin Q1 receives the drive data.

[0113] When the first functional pin Q1 receives a test signal, the test signal includes test data and first general address information, and the first general address information can match the initialization address information of any of the driver chips 100. The logic control module CTR is configured to generate a test current that flows through any of the output pins OUT respectively according to the test data.

[0114] Here, after the first functional pin Q1 of the driver chip 100 of each level receives the test signal, its logic control module CTR may analyze the first general address information to obtain corresponding test data, so that the driver chip provides a test current to the light emitting unit E electrically connected thereto according to the test data. In addition, since the second functional pin Q2 and the first functional pin Q1 are directly electrically connected via the first connecting line L1, the test signal received by the first functional pin Q1 may be output to the first functional pin Q1 of the driver chip of the next level via the second functional pin Q2.

[0115] The first functional pin Q1 and the second functional pin Q2 of each level of the N driver chips 100 cascaded in sequence receive the same driving data. The driving data includes N pieces of address verification information and N pieces of driving information, where one address verification information and one driving information form an array, and the N arrays are arranged in sequence. For example, the N arrays may be arranged in sequence according to the cascading order of the N driver chips, or may be arranged in a random order. If the address verification information and the address information match, the logic control module CTR further receives corresponding driving information according to the address verification information, and controls at least one light-emitting unit E (shown in FIG. 2) connected to the driver chip 100 to generate a corresponding driving current according to the driving information, and controls at least one output pin OUT of the driver chip 100 and the corresponding light-emitting unit E to form an electrical path, so that the driving current flows through the electrical path.

[0116] Here, after the first functional pin Q1 of the driver chip 100 of each level receives the driving data, its logic control module CTR obtains only the driving information corresponding to the driver chip in the driving data, so that the driver chip provides a driving current to the light emitting unit E electrically connected thereto according to the driving information, and the logic control module CTR outputs the received driving data to the first functional pin Q1 of the driver chip of the next level via its second functional pin Q2.

[0117] After the first functional pin Q1 of the driver chip 100 at each level receives the driving data, its logic control module CTR obtains only the driving information corresponding to the driver chip in the driving data, and the driver chip provides a driving current to the light emitting unit E electrically connected thereto according to the driving information. Furthermore, since the second functional pin Q2 and the first functional pin Q1 are directly electrically connected via the first connecting line L1, the driving data received by the first functional pin Q1 can be output to the first functional pin Q1 of the driver chip at the next level via the second functional pin Q2.

[0118] As described above, in one driver chip 100, the process for the test signal after receiving it via the first functional pin Q1 is similar to the process for the drive data after receiving it via the data pin Data. Therefore, the first functional pin Q1 may be used to receive the test signal and the drive data in a time-sharing manner. When the driver chip 100 is in a test phase, the first functional pin Q1 is used to receive the test signal. When the driver chip 100 is in a normal operation phase, the first functional pin Q1 is used to receive the drive data. In this embodiment, when the first functional pin Q1 receives the test signal and the drive data in a time-sharing manner, there is no need to provide a data pin Data on the driver chip 100, which is advantageous in reducing the area occupied by the driver chip 100 and saving resources. In addition, the drive data received by the first functional pin Q1 can be output to the first functional pin Q1 of the next-level driver chip via the second functional pin Q2, which is advantageous in arranging the wiring for providing signals to the driver chip 100 on the light-emitting substrate.

[0119] In some embodiments, still referring to FIG. 5 , the driver chip 100 includes an address pin Di and a relay pin Do. The address pin Di may receive an address signal. In response to the address signal, the driver chip 100 configures address information and generates a relay signal. The relay pin Do can output the relay signal, i.e., updates the initialization address information of each driver chip 100.

[0120] In some examples, the initialization address information and the address signal may be the same type of digital signal. For example, the initialization address information is 0. After one driver chip 100 receives the address signal, it may analyze and obtain the address information stored in the address signal, increment the address signal by 1 or other non-zero amount, and modulate the incremented address signal (new address signal) into a repeat signal. The repeat signal is used as the address signal for the next-level driver chip 100. Of course, the driver chip 100 may update the address signal using other different functions.

[0121] After the address pin Di receives the address signal, the first function pin Q1 is used to receive driving data. The driving data includes a plurality of address verification information and a plurality of driving information corresponding to the plurality of address verification information. For any of the driver chips, if the address verification information matches the address information, the driver chip receives the corresponding driving information according to the address verification information, and generates a corresponding driving current for at least one output pin OUT according to the received driving information. That is, at least one light-emitting unit E connected to the driver chip 100 generates a corresponding driving current, and controls at least one output pin OUT of the driver chip 100 to form an electrical path with the corresponding light-emitting unit E, so that the driving current flows through the electrical path. The light-emitting element E receives the driving current and emits light.

[0122] In addition, the second function pin Q2 can output the driving data to the next level driving chip.

[0123] During the address configuration phase, if there is a problem with the welding between the address pin Di and the relay pin Do of a driver chip 100, the address information of that driver chip 100 cannot be updated, and the address information of all driver chips installed at a lower level of that driver chip 100 also cannot be updated. For example, assuming that the address information occupies 8 bits, the updated address information of the first four driver chips 100 is 00000001, 00000010, 00000011, and 00000100, respectively. For example, if there is a problem within the fifth driver chip 100 or in the connection between the fifth driver chip and the sixth driver chip, the address information of the subsequent driver chips 100 cascaded from the fifth driver chip will not be updated and will remain as the initialized address information 00000000. The address verification information in the driver data matches the updated address information of each driver chip one-to-one, so the first four driver chips 100 can obtain the corresponding driver information from the driver data. That is, the light-emitting elements E electrically connected to the first four driver chips 100 can emit light normally. In this case, assuming that each light-emitting element E is normally welded, none of the subsequent driver chips 100 cascaded from the fifth driver chip can obtain corresponding driving information from the driving data. That is, the address information of all subsequent driver chips 100 from the fifth driver chip cannot obtain driving current, and therefore none of the light-emitting elements E electrically connected thereto can emit light.

[0124] Based on this, it may be determined whether all the light-emitting elements E electrically connected to each driver chip 100 emit light. If none of the light-emitting elements E electrically connected from a certain driver chip 100 to the subsequent driver chip 100 emit light, it can be determined that there is a problem inside the driver chip 100 or in the connection between the driver chip 100 and the next-level driver chip 100, and it needs to be repaired.

[0125] Furthermore, the driver chip 100 according to some embodiments of the present disclosure does not require the installation of a data pin, and can receive and transmit driver data through the first functional pin Q1 and the second functional pin Q2, respectively, which is advantageous for reducing the area occupied by the driver chip 100 and saving resources, and is also advantageous for the layout of wiring for providing signals to the subsequent driver chip 100.

[0126] In some other embodiments, the address pin Di can receive an address signal. According to the address signal, the address information of the driver chip 100 is configured, and the logic control module CTR generates a relay signal according to the received address information. The relay pin Do can output the relay signal, i.e., update the initialization address information of each driver chip 100.

[0127] In some examples, the initialization address information and the address signal may be the same type of digital signal. For example, the initialization address information is 0. After one driver chip 100 receives the address signal, it may analyze and obtain the address signal stored in the address signal, and may add a certain amount to the address signal as a relay signal. The relay signal is the address signal of the next-level driver chip 100. If the certain amount is 0, that is, the address signals of all driver chips 100 are the same. Of course, the driver chip 100 may use other different functions to update the address signal.

[0128] When the first functional pin Q1 receives a test signal, the test signal includes test data and second general address information, which can match the address information of any of the driver chips 100. The logic control module CTR is configured to generate a test current flowing through any of the output pins OUT in response to the test signal.

[0129] It should be understood that, during the address configuration phase, if there is a problem within a driver chip or between the driver chip and the next-level driver chip 100, the address information of the driver chip and all subsequent cascaded driver chips cannot be updated. For example, the updated address information of the first four driver chips 100 is 11111111, while the address information of all subsequent driver chips 100 from the fifth driver chip onwards remains as 00000000. The second general address information in the test signal is preset to 11111111 and can match the updated address information of the first four driver chips 100. That is, the light-emitting elements E electrically connected to the first four driver chips 100 can emit light normally. In this case, assuming that each light-emitting element E is normally welded, the second general address information in the test signal cannot match the address information (address information after updating the initialization information) of all subsequent driver chips 100 from the fifth driver chip onwards. That is, the logic control modules of all the fifth and subsequent driver chips 100 cannot obtain the driving information from the driving data, and therefore the light emitting elements E electrically connected thereto cannot emit light.

[0130] Based on this, it may be determined whether all the light-emitting elements E electrically connected to each driver chip 100 emit light. If none of the light-emitting elements E electrically connected from a certain driver chip 100 to the subsequent driver chip 100 emit light, it can be determined that there is a problem with the welding between the address pin Di and the relay pin Do of that driver chip 100, and it needs to be repaired.

[0131] 5, in some embodiments, the driver chip 100 further includes a third edge W3 located between the first end of the first edge W1 and the first end of the second edge W2. When the driver chip 100 includes an address pin Di and a relay pin Do, one of the address pin Di and the relay pin Do is closer to the first edge W1 and the other is closer to the second edge W2. The address pin Di and the relay pin Do are closer to the third edge W3 than the first functional pin Q1 and the second functional pin Q2.

[0132] In this embodiment, one of the address pins Di and the relay pins Do is located near the first edge W1, and the other is located near the second edge W2. As shown in Figure 5, the first edge W1 is the upper edge of the driver chip 100, and the second edge W2 is the lower edge of the driver chip 100. The lower edge of the driver chip 101 on the previous level is close to the upper edge of the driver chip 102 on the next level.

[0133] Thus, the address pin Di is located close to the first edge W1, and the relay pin Do is located close to the second edge W2. That is, the relay pin Do of the previous-level driver chip 101 is close to the address pin Di of the next-level driver chip 102. An external connection line K2 may be used to electrically connect the relay pin Do of the previous-level driver chip 101 and the address pin Di of the next-level driver chip 102. Thus, the address pin Di of the previous-level driver chip 101 receives an address signal, and the logic control module CTR of the previous-level driver chip 101 configures the address information of the previous-level driver chip 101 according to the address signal and generates a relay signal. The relay signal may be the address signal of the next-level driver chip 102, and the relay pin Do of the previous-level driver chip 101 transmits the relay signal to the address pin Di of the next-level driver chip 102. This realizes dynamic address assignment for the cascaded driver chips 100.

[0134] In addition, by arranging the address pin Di close to the first edge W1 and the relay pin Do close to the second edge W2, it is advantageous to further shorten the length of the external connection line K2 and also makes it easier to flexibly arrange the position of the external connection line K2, thereby facilitating the arrangement of the wiring of the subsequent light-emitting substrate.

[0135] In addition, the address pin Di and the relay pin Do are arranged closer to the third edge W3 than the first functional pin Q1 and the second functional pin Q2. That is, the address pin Di and the relay pin Do are arranged on both the top and bottom sides closest to the third edge W3, which facilitates connection with address signal lines outside the driver chip 100 and is advantageous for the subsequent wiring layout of the light-emitting substrate.

[0136] 5 exemplarily illustrates an example in which the address pin Di is located near the first edge W1 and the relay pin Do is located near the second edge W2. It is understood that in some other embodiments, the address pin Di is located near the second edge W2 and the relay pin Do is located near the first edge W1. In some embodiments of the present disclosure, the positions of the address pin Di and the relay pin Do in the driver chip 100 may be flexibly arranged as long as the relay pin Do of the previous-level driver chip 101 is close to the address pin Di of the next-level driver chip 102.

[0137] 5 illustrates an example in which one end of the third edge W3 is directly connected to the first edge W1 and the other end of the third edge W3 is directly connected to the second edge W2. It is understood that in some other embodiments, the third edge W3 and the first edge W1 are connected via other edges. In still other embodiments, the third edge W3 and the second edge W2 are connected via other edges.

[0138] FIG. 8 is a structural diagram of a driver chip according to some other embodiments of the present disclosure.

[0139] 8, in some embodiments, the driver chip 100 further includes at least one ground pin GND. The at least one ground pin GND is electrically connected to the logic control module CTR. The ground pin GND can receive a ground signal. The ground pin GND is located between the address pin Di and the relay pin Do.

[0140] In this embodiment, the driver chip 100 further includes at least one ground pin GND for receiving a ground signal. FIG. 8 illustrates an example in which the driver chip 100 includes two ground pins GND. In some other embodiments, the driver chip 100 may include one, three, or four ground pins, which may be selected according to specific needs. By locating the ground pin GND close to the third edge W3 and between the address pin Di and the relay pin Do, the ground pin GND can be concentrated in the middle region of the third edge W3 of the driver chip 100, which is advantageous in facilitating electrical connection of the ground pin GND with subsequent ground wiring and avoiding overlapping design issues with other wiring.

[0141] 9 and 10 are structural diagrams of driver chips according to still other embodiments of the present disclosure.

[0142] 9 and 10, in some embodiments, the driver chip 100 further includes a first power supply pin V1. The first power supply pin V1 is electrically connected to the logic control module CTR. The first power supply pin V1 is capable of receiving a power supply signal. The first power supply pin V1 is close to the first edge W1 or the second edge W2. The first power supply pin V1 is farther from the third edge W3 than the address pin Di and the relay pin Do.

[0143] In this embodiment, the driver chip 100 receives a power signal through the first power pin V1, and provides the power signal required for the operation of the driver chip 100 to ensure the normal operation of the driver chip 100.

[0144] The first power pin V1 is located near the first edge W1 or the second edge W2. As shown in FIGS. 9 and 10, the first power pin V1 is located near the first edge W1 as an example. It is understood that in some other embodiments, the first power pin V1 may be located near the second edge W2. Based on the above, the first power pin V1 is located near the upper or lower edge of the driver chip 100. By locating the first power pins V1 of the multiple driver chips 100 at the upper or lower edge of the corresponding driver chip 100, the space between two adjacent driver chips 100 can be fully utilized, which is advantageous for wiring design.

[0145] Furthermore, locating the first power supply pin V1 farther away from the third edge portion W3 than the address pins Di and the relay pins Do may include the following two cases.

[0146] First Case: Referring to FIG. 9, the first power supply pin V1 is located between the first function pin Q1 and the address pin Di.

[0147] Second Case: Referring to FIG. 10, the first function pin Q1 is located between the first power supply pin V1 and the address pin Di.

[0148] It should be understood that in either the first or second case, the address pins Di and relay pins Do are located closest to the third edge W3, which facilitates connection between the address pins Di and address signal lines external to the driver chip 100 and is advantageous for the subsequent wiring layout of the light emitting substrate.

[0149] 9 and 10, in some embodiments, the driver chip 100 further includes a second power supply pin V2 and a second connecting line L2. The second power supply pin V2 is connected to the first power supply pin V1 via the second connecting line L2. Here, one of the first power supply pin V1 and the second power supply pin V2 is closer to the first edge W1, and the other is closer to the second edge W2. The first power supply pin V1 and the second power supply pin V2 are farther from the third edge W3 than the address pin Di and the relay pin Do.

[0150] In this embodiment, the first power pin V1 and the second power pin V2 of the driver chip 100 of this level are electrically connected via a second connecting line L2. The first power pin V1 and the second power pin V2 of the driver chip 100 of this level receive the same signal. Therefore, a power signal can be output to the first power pin V1 of the driver chip 100 of the next level via the second power pin V2. This facilitates the wiring design between the driver chips 100 in a cascade design.

[0151] Based on the above, one of the first power pin V1 and the second power pin V2 is positioned close to the first edge W1, and the other is positioned close to the second edge W2. As shown in Figures 7 and 8, the first edge W1 is the upper edge of the driver chip 100, and the second edge W2 is the lower edge of the driver chip 100. The lower edge of the driver chip 101 of the previous level is close to the upper edge of the driver chip 102 of the next level.

[0152] Therefore, by arranging the first power pin V1 close to the first edge W1 and the second power pin V2 close to the second edge W2, i.e., the first power pin V1 close to the upper edge of the driver chip 100 and the second power pin V2 close to the lower edge of the driver chip 100, it is possible to easily connect the second power pin V2 of two adjacent driver chips 100 with the first power pin V1, and the second power pin V2 can output a power signal to the next level driver chip 100.

[0153] In addition, whether the second functional pin Q2 needs to be installed may be determined according to the total number of pins in the driver chip 100, thereby ensuring that the total number of pins in the driver chip 100 is an even number.

[0154] In some examples, the second connecting line L2 may be a wiring inside the driver chip 100. In some other examples, the second connecting line L2 may be a wiring outside the driver chip 100 but located on the light emitting substrate. When the second connecting line L2 is located on the light emitting substrate, the orthogonal projection of the second connecting line L2 on the light emitting substrate is located between the orthogonal projections of the first power pin V1 and the second power pin V2 on the light emitting substrate.

[0155] That is, the second connection line L2 is located between two adjacent cascade-installed driver chips 100. This allows the space between the adjacent driver chips 100 to be fully utilized, and reduces the left and right spaces of the driver chip 100 (the left and right spaces of the driver chip 100 shown in FIGS. 9 and 10). This allows the signal lines electrically connected to the driver chip 100 to be installed in a dispersed manner, which is advantageous for the wiring layout of the signal lines.

[0156] 9 and 10 illustrate an example in which the second connecting line L2 may be a wiring inside the driver chip 100 and is a straight line. The present disclosure does not specifically limit the shape or film layer position of the second connecting line L2, as long as it is located between the first power pin V1 and the second power pin V2 and connects the first power pin V1 and the second power pin V2.

[0157] 9 and 10 exemplarily show the first power pin V1 close to the first edge W1 and the second power pin V2 close to the second edge W2. It is understood that in some other embodiments, the first power pin V1 may be located close to the second edge W2 and the second power pin V2 may be located close to the first edge W1. The second power pin V2 and the first power pin V1 of two adjacent driver chips 100 may be located close to each other.

[0158] Here, "the first power supply pin V1 and the second power supply pin V2 are farther away from the third edge portion W3 than the address pin Di and the relay pin Do" may include the following two cases.

[0159] 9, the first power supply pin V1 is located between the first function pin Q1 and the address pin Di. The second power supply pin V2 is located between the second function pin Q2 and the relay pin Do.

[0160] 10, the first functional pin Q1 is located between the first power supply pin V1 and the address pin Di. The second functional pin Q2 is located between the second power supply pin V2 and the relay pin Do.

[0161] It should be understood that in either the first or second case, the address pins Di and relay pins Do are located closest to the third edge W3, which facilitates connection between the address pins Di and address signal lines external to the driver chip 100 and is advantageous for the subsequent wiring layout of the light emitting substrate.

[0162] Fig. 11 is a structural diagram of a light emitting substrate according to some other embodiments of the present disclosure, and Fig. 12 is a partial enlarged view of the position R in Fig. 11 .

[0163] Some embodiments of the present disclosure provide a light emitting substrate 200. Referring to Figures 11 and 12, the light emitting substrate 200 includes a plurality of cascaded driver chips 100 and a plurality of device groups O. The driver chip 100 is the driver chip 100 of any of the above embodiments. A first end Oa of one device group O corresponds to and is electrically connected to at least one output pin OUT of one driver chip 100.

[0164] In some examples, one device group O includes at least one light-emitting unit E. Illustratively, one light-emitting unit E may include at least one light-emitting element. Here, one light-emitting unit E may include only one light-emitting element. Alternatively, one light-emitting unit E may include two or more light-emitting elements electrically connected to each other. When one light-emitting unit E includes two or more light-emitting elements, the two or more light-emitting elements may be connected in series, in parallel, or in a series-parallel connection manner.

[0165] For example, "the first end Oa of one device group O is electrically connected to at least one output pin OUT of one driver chip 100" may mean that the light-emitting units E in one device group O correspond one-to-one to the output pins OUT of one driver chip 100. The embodiments of the present disclosure do not limit the number of light-emitting units E electrically connected to each output pin OUT, and this number can be adjusted according to actual needs. For example, as shown in FIG. 12 , one driver chip 100 has four output pins OUT. One device group O includes four light-emitting units E. One output pin OUT is electrically connected to one light-emitting unit E.

[0166] In this embodiment, the first functional pin Q1 of each driver chip 100 may be used to provide a test signal to its corresponding logic control module CTR, which then generates a test current through one of its output pins OUT. The test current may drive the light emitting units E. That is, all of the light emitting units E electrically connected to all driver chips 100 can receive the test current under normal conditions. This allows a single detection operation to realize a lighting test for the light emitting units E electrically connected to each driver chip 100. If the light emitting unit E emits light normally, it can be determined that the light emitting unit E is normally connected; if the light emitting unit E does not emit light, it can be determined that the light emitting unit E has a problem and needs to be repaired, thereby improving the efficiency of inspection and repair of the driver chips 100.

[0167] 11 and 12 , in some embodiments, when the driver chip 100 further includes an address pin Di, a relay pin Do, a first power supply pin V1, and at least one ground pin GND, the relay pin Do located on the driver chip 100 at the previous level is electrically connected to the address pin Di located on the driver chip 100 at the next level. The light emitting substrate 200 further includes a conductive layer M. The conductive layer M further includes a second voltage line 10, an address signal line 20, a first voltage line 30, a test signal line 40, and a ground line 50.

[0168] The second voltage line 10 extends along the first direction X, and the light-emitting units E in one device group O are arranged along the first direction X. The second voltage line 10 is electrically connected to the second end of each device group. That is, the second voltage line 10 is electrically connected to at least one light-emitting unit E in each device group O and provides a driving voltage to the light-emitting unit E. At the same time, since the light-emitting units E in one device group O are arranged along the first direction, all the light-emitting units E in one device group O may be connected to the same second voltage line 10 using conductive lines 11 extending along the second direction Y. The non-overlapping conductive lines 11 are advantageous for realizing a single-layer wiring design of the light-emitting substrate 200. Exemplarily, the conductive lines 11 are parallel to each other. Here, the first direction X intersects with the second direction Y and is parallel to the light-emitting substrate 200. As shown in FIGS. 11 and 12 , the first direction X is perpendicular to the second direction Y. It will be appreciated that in some other embodiments, the included angle between the first direction X and the second direction Y may be an obtuse angle or an acute angle.

[0169] In some examples, multiple cascaded driving chips 100 are arranged along the first direction Y. When multiple cascaded driving chips 100 are connected to the same second voltage line 10, they may be connected to the second voltage line 10 using conductive lines 11 extending along the second direction Y. Since the conductive lines 11 do not overlap, it is advantageous to realize a single-layer wiring design of the light emitting substrate 200. Illustratively, the conductive lines 11 are parallel to each other.

[0170] Any one of the device groups O includes a plurality of light-emitting units E arranged in a row. One second voltage wire 10 may be arranged to electrically connect all of the light-emitting units E in one device group O. A plurality of device groups O forming a device group row may be arranged to simultaneously connect to the same second voltage wire 10. The second voltage wire 10 provides a first voltage to at least one light-emitting unit E.

[0171] The ground line 50 is electrically connected to at least one ground pin GND of each driver chip 100. Exemplarily, the ground line 50 is electrically connected to each ground pin GND of each driver chip 100 to provide a ground signal to the ground pin. The ground line 50 extends along the first direction X, the ground line 50 is located outside the driver chip 100, and the ground line 40 is close to the ground pin GND. Since the ground line 50 needs to be electrically connected to at least one ground pin GND of each driver chip 100, locating the ground line 40 closest to the ground pin GND facilitates the electrical connection between the ground line 40 and the ground pin GND and avoids overlap with other signal lines.

[0172] The address signal line 20 is electrically connected to the address pin Di. The address pin Di of the first driver chip among the multiple cascaded driver chips 100 is electrically connected to the address signal line 20. For other cascaded driver chips, the relay pin Do of the previous-level driver chip and the address pin Di of the next-level driver chip are electrically connected via an external connection line K2. This allows the address pin Di to receive an address signal and drive the address information of the driver chip 100 according to the address signal, and the logic control module CTR generates a relay signal according to the received address information. The relay signal may be the address signal of the next-level driver chip 100. The relay pin Do can output a relay signal.

[0173] The address signal line 20 extends along the first direction Y, and is located on the side of the ground line 40 that is farther away from the address pin Di. Because the address signal line 20 only needs to be electrically connected to the address pin Di of the first driver chip 100, locating the address signal line 20 on the side that is relatively farther away from the driver chip 100 facilitates the electrical connection between the ground line 50 and the ground pin GND and prevents the address signal line 20 and the ground line 50 from overlapping, which is advantageous for realizing a single-layer wiring design for the light emitting substrate 200.

[0174] The first voltage line 30 is electrically connected to the first power pin V1 of each driver chip 100. The first power pin V1 is located at the top edge of the driver chip. That is, the first power pins V1 of the multiple cascaded driver chips 100 are electrically connected to the first voltage line 30. The first voltage line 30 is used to provide voltage to each driver chip 100, ensuring that each driver chip 100 operates normally.

[0175] The test signal line 40 is electrically connected to the first functional pin Q1 of each first driver chip 100. The test signal line 40 is located at the top edge of the driver chip. That is, the first functional pins Q1 of multiple cascaded driver chips 100 are electrically connected to the test signal line 40. The test signal line 40 provides a test signal to each driver chip 100, and the test signal is used to test whether there is an abnormality in the light-emitting units E electrically connected to all the driver chips 100.

[0176] With the above structure, the second voltage line 10 is located on the side of the light-emitting unit E that is farther from the driving chip 100. The address signal line 20 and the ground line 50 are located on the side closer to the ground pin GND of the driving chip 100, and the ground line 50 is located between the address signal line 20 and the driving chip 100. The first voltage line 30, the test signal line 40, and the external connection line K2 are located between the second voltage line 10 and the ground line 50. As a result, the second voltage line 10, the address signal line 20, the first voltage line 30, the test signal line 40, and the ground line 50 do not overlap, which enables a single-layer wiring design of the light-emitting substrate 200, which reduces the process difficulty and costs of the light-emitting substrate 200.

[0177] 11 and 12, in some embodiments, when the driver chip 100 further includes a second functional pin Q2, the second functional pin Q2 is electrically connected to the first functional pin Q1 of the driver chip 100 at this level and the first functional pin Q1 of the driver chip at the next level, respectively. Exemplarily, the second functional pin Q2 may be electrically connected to the first functional pin Q1 of the driver chip at the next level via an external connection line K1.

[0178] The test signal line 40 is electrically connected to the first functional pin Q1 of the first driver chip 100. The second functional pin Q2 is electrically connected to the first functional pin Q1 of the driver chip 100 of this level, so that the second functional pin Q2 and the first functional pin Q1 receive the same signal. Therefore, for other cascaded driver chips, the second functional pin Q2 of the driver chip of the previous level is electrically connected to the first functional pin Q1 of the driver chip of the next level via the external connection line K1. This facilitates the wiring design between multiple cascaded driver chips 100 on the light emitting substrate 200.

[0179] The external connection line K1 is located between the second voltage line 10 and the ground line 50. As a result, the second voltage line 10, the address signal line 20, the first voltage line 30, the test signal line 40, and the ground line 50 do not overlap, which enables a single-layer wiring design of the light emitting substrate 200, which reduces the process difficulty and costs of the light emitting substrate 200.

[0180] In some embodiments, still referring to Figures 11 and 12, if the driver chip 100 further includes a second power supply pin V2, the second power supply pin V2 is electrically connected to the first power supply pin V1 of the driver chip 100 at this level and the first power supply pin V1 of the driver chip 100 at the next level, respectively.

[0181] Exemplarily, the second power pin V2 is electrically connected to the first power pin V1 of the next-level driver chip 100 via an external connection line K3.

[0182] The first voltage line 30 is electrically connected to the first power pin V1 of the first driver chip 100 among the plurality of cascaded driver chips 100. The second power pin V2 is electrically connected to the first power pin V1 of the driver chip 100 of the current level, so that the first power pin V1 and the second power pin V2 of the driver chip 100 of the current level receive the same signal. This facilitates the second power pin V2 of the driver chip of the previous level to output a power signal to the first power pin V1 of the driver chip of the next level for other cascaded driver chips. This facilitates the wiring design between the plurality of cascaded driver chips 100 on the light emitting substrate 200.

[0183] The external connection line K3 is located between the second voltage line 10 and the ground line 50. As a result, the second voltage line 10, the address signal line 20, the first voltage line 30, the test signal line 40, and the ground line 50 do not overlap, which enables a single-layer wiring design of the light emitting substrate 200, which reduces the process difficulty and costs of the light emitting substrate 200.

[0184] In some embodiments, with continued reference to FIGS. 11 and 12, address signal lines 20 are configured to transmit address signals, and test signal lines 40 are configured to transmit test signals and drive data in a time-sharing manner.

[0185] In this embodiment, the address signal line 20 transmits an address signal to the address pin Di, and the address pin Di receives the address signal. The logic control module CTR arranges address information of the driver chip 100 according to the address signal and generates a relay signal. The relay signal may be the address signal of the next-level driver chip 100. The relay pin Do is electrically connected to the logic control module CTR. The relay pin Do can output the relay signal.

[0186] For example, the address signal may be a digital signal. After receiving the address signal, one driver chip 100 may analyze and obtain address information stored in the address signal, and may increment the address signal by 1 or other fixed amount other than 0, and modulate the incremented address signal (new address signal) into a repeat signal. The repeat signal is used as the address signal for the next-level driver chip 100. Of course, the driver chip 100 may generate a new address signal using other different functions.

[0187] The test signal line 40 transmits the test signal and the driving data in a time-sharing manner, and may provide different signals to the same pin (first functional pin Q1) of the driver chip 100 in a time-sharing manner.

[0188] When the test signal line 40 provides a test signal to the first functional pin Q1, the first functional pin Q1 receives the test signal, which includes test data and first general address information. The first general address information can match the initialization address information of any of the driver chips. The logic control module of any of the driver chips 100 then generates a test current through any of the output pins OUT according to the test data. The light-emitting unit E receives the test current and emits light. A single detection operation can achieve lighting testing of the light-emitting units E electrically connected to each driver chip 100, thereby effectively improving the efficiency of inspection and repair of the driver chips 100.

[0189] When the test signal line 40 provides driving data to the first functional pin Q1, the first functional pin Q1 may also be used to receive driving data. The driving data includes driving information and address verification information. The driving data includes a plurality of address verification information and a plurality of driving information corresponding to the plurality of address verification information. For any of the driver chips, if the address verification information matches the address information, the driver chip receives the corresponding driving information according to the address verification information and generates a corresponding driving current for at least one output pin OUT according to the received driving information. That is, at least one light-emitting unit E connected to the driver chip 100 generates a corresponding driving current and controls at least one output pin OUT of the driver chip 100 to form an electrical path with the corresponding light-emitting unit E, and the driving current flows through the electrical path. If none of the light-emitting units E electrically connected to a subsequent cascaded driver chip 100 emits light from a driver chip 100, it is determined that the welding of the address pin Di of the initial driver chip 100 is faulty and needs to be repaired.

[0190] The above structure eliminates the need to provide separate signal lines and separate data pins to provide driving data to the driver chip 100, reduces the number of signal lines connected to the driver chip 100, facilitates the realization of a single-layer wiring design for the light emitting substrate 200, reduces the process difficulty of the light emitting substrate 200, and reduces costs.

[0191] 11 , in some embodiments, when the address signal line 20 is configured to be able to transmit driving data, there is no need to provide a power regulation circuit (which is used to generate a driving voltage based on the DC component of the power signal and generate driving data based on the modulation component of the power signal) within the driver chip 100, and the address signal line 20 and the second voltage line 10 use different signal lines, which can simplify the circuit structure within the driver chip 100 and thereby reduce the area of the driver chip 100. This installation method can also further simplify the external circuit structure, avoid the need for a modulation circuit for modulating the driving voltage and driving data onto power line carrier communication, and reduce the quality requirements for the driving voltage.

[0192] In some embodiments, referring to FIGS. 11 and 12, address signal lines 20 are configured to carry drive data and test signal lines 40 are configured to carry test signals.

[0193] In this embodiment, the test signal line 40 transmits a test signal to the first functional pin Q1, and the test signal received by the first functional pin Q1 of the driver chip 100 includes a switch signal. The switch signal is used to control the logic control module CTR to generate a test current through one of the output pins OUT. In this case, all of the light-emitting units E electrically connected to the driver chip 100 can be controlled to receive the test current. The second functional pin Q2 can output a test signal to the next-level driver chip 100.

[0194] This allows a single detection operation to realize a lighting test of the light-emitting units E electrically connected to each driver chip 100. If the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E, which effectively improves the efficiency of inspection and repair of the driver chip 100. In some examples, the test signal may be a high-level signal or a low-level signal. The test signal may control the logic control module CTR to generate a test current flowing through one of the output pins OUT.

[0195] The address signal line 20 transmits driving data to the address pin Di. The address pin Di receives the driving data. The driving data includes address inspection information and multiple driving information corresponding to multiple cascaded driving chips. The logic control module CTR allocates one driving information corresponding to the current driving chip according to the address inspection information, updates the address inspection information, and generates driving data including the updated address inspection information. The relay pin Do is electrically connected to the logic control module. The relay pin Do can output the driving data including the updated address inspection information to the next-level driving chip 102.

[0196] It is understood that the address pin Di of the previous-level driver chip 101 can receive driving data, which includes address check information for the previous-level driver chip 101 and multiple driving information corresponding to all cascaded driver chips. The logic control module CTR of the previous-level driver chip 101 receives the driving data and, according to the address check information in the driving data, arranges the driving information corresponding to the address check information of the previous-level driver chip 101. According to the driving information, the logic control module CTR controls at least one light-emitting unit E connected to the driver chip 100 to generate a corresponding driving current, and at least one output pin OUT of the driver chip 100 and the corresponding light-emitting unit E to form an electrical path, through which the driving current can flow. If a driver chip 100 determines that none of the light-emitting units E electrically connected to the subsequent cascaded driver chip 100 emit light, it determines that the welding of the address pin Di of the original driver chip 100 is faulty and needs to be repaired.

[0197] Then, the logic control module CTR of the previous-level driver chip 101 updates the address inspection information and generates updated address inspection information. The updated address inspection information includes the updated address inspection information. The relay pin Do can output the updated address inspection information to the next-level driver chip 102.

[0198] For example, the logic control module CTR further updates the received driving data, i.e., updates the address check information in the driving data. The address check information in the driving data is the number of start identification bits and / or end identification bits. The logic control module CTR subtracts 1 from the number of start identification bits and / or adds 1 to the number of end identification bits in the driving data, and outputs the re-edited driving data to the address pin Di of the next-level driving chip through its relay pin. Of course, the driving chip 100 may use other different functions to generate new address check information.

[0199] With the above structure, the light emitting substrate 200 can transmit driving data via the address signal lines 20. The driving data includes address inspection information and multiple pieces of driving information corresponding to the multiple cascaded driving chips. That is, the driving data provided by the address signal lines 20 can simultaneously write addresses and input driving information. Compared with a method in which data is written using the address signal lines 20 and driving information is input using the data signal lines, the number of signal lines connected to the driving chip 100 can be reduced, which facilitates the realization of a single-layer wiring design for the light emitting substrate 200, reduces the process difficulty of the light emitting substrate 200, and reduces costs.

[0200] 11 , in some embodiments, when the test signal line 40 is configured to transmit the test signal and the driving data in a time-sharing manner, there is no need to provide a power regulation circuit (which is used to generate a driving voltage based on the DC component of the power signal and generate driving data based on the modulation component of the power signal) within the driver chip 100, and the test signal line 40 and the second voltage line 10 use different signal lines, which can simplify the circuit structure within the driver chip 100 and thereby reduce the area of the driver chip 100. In addition, this configuration can further simplify the external circuit structure, avoid the need for a modulation circuit for modulating the driving voltage and driving data onto power line carrier communication, and reduce the quality requirements for the driving voltage.

[0201] 11 , in some embodiments, the light emitting substrate 200 further includes a feedback signal line 70, which is electrically connected to the relay pin Do of the last driver chip 100 in the cascade arrangement. The feedback signal line 70 is close to the ground line 50 and is located between the ground line 50 and the test signal line 40, thereby preventing the feedback signal line 70 from overlapping with other signal lines, for example, preventing the feedback signal line 70 from overlapping with the ground line 50 and the test signal line 40. This facilitates realization of a single-layer wiring design for the light emitting substrate 200, reduces the process difficulty of the light emitting substrate 200, and reduces costs.

[0202] FIG. 13 is a circuit block diagram of a light emitting substrate according to some further embodiments of the present disclosure.

[0203] In some embodiments, referring to FIG. 13, the driver chip 100 includes an address pin Di, a relay pin Do, a first function pin Q1, a second function pin Q2, a ground pin GND, a first power supply pin V1, and a second power supply pin V2.

[0204] The driver chip 100 further includes four output pins OUT, which are a first output pin OUT1, a second output pin OUT2, a third output pin OUT3, and a fourth output pin OUT4, respectively.

[0205] The logic control module CTR includes four modulation modules, namely a first modulation module PWMM1, a second modulation module PWMM2, a third modulation module PWMM3, and a fourth modulation module PWMM4. The logic control module CTR further includes a control unit CLM.

[0206] The first output pin OUT1 to the fourth output pin OUT4 are connected to the first modulation module PWMM1 to the fourth modulation module PWMM4 in a one-to-one correspondence. The control unit CLM is used to generate a first drive control signal, a second drive control signal, a third drive control signal, and a fourth drive control signal according to drive data, and transmit them to the first modulation module PWMM1, the second modulation module PWMM2, the third modulation module PWMM3, and the fourth modulation module PWMM4, respectively.

[0207] The first modulation module PWMM1 is electrically connected to the first output pin OUT1 and can be turned on or off under the control of the first drive control signal, thereby turning on or off the connection between the first output pin OUT1 and the ground line 50 electrically connected to the ground pin GND.

[0208] When the first modulation module PWMM1 is turned on, the ground line 50 (shown in FIG. 11), the first output pin OUT1, the light-emitting unit E (shown in FIG. 11) electrically connected to the first output pin OUT1, and the second voltage line 10 (shown in FIG. 11) form a signal circuit, and the light-emitting unit E operates. When the first modulation module PWMM1 is turned off, the signal circuit is turned off, and the light-emitting unit E does not operate.

[0209] In this manner, the first modulation module PWMM1 may phase-modulate the drive current flowing through the light-emitting unit E under control of the first drive control signal. The first drive control signal is a pulse-width modulation signal. The first modulation module PWMM1 may control the operating state of the light-emitting unit E by modulating the duration of the drive current flowing through the light-emitting unit E in response to the first drive control signal. If the light-emitting unit E includes an LED, increasing the duty ratio of the first drive control signal can increase the total light-emitting time of the LED within one display frame, thereby improving the total light-emitting brightness of the LED within that display frame and increasing the brightness of that region of the light-emitting substrate 200. Conversely, decreasing the duty ratio of the pulse-width modulation signal can shorten the total light-emitting time of the LED within one display frame, thereby reducing the total light-emitting brightness of the LED within that display frame and decreasing the brightness of that region of the light-emitting substrate.

[0210] Accordingly, the second modulation module PWMM2 is electrically connected to the second output pin OUT2 and can be turned on or off under the control of a second drive control signal. The second drive control signal is a pulse-width modulated signal. The third modulation module PWMM3 is electrically connected to the third output pin OUT3 and can be turned on or off under the control of a third drive control signal. The third drive control signal is a pulse-width modulated signal. The fourth modulation module PWMM4 is electrically connected to the fourth output pin OUT4 and can be turned on or off under the control of a fourth drive control signal. The fourth drive control signal is a pulse-width modulated signal.

[0211] In some embodiments, the first modulation module PWMM1 to the fourth modulation module PWMM4 may be switch elements, such as transistors such as MOS (metal-oxide semiconductor field-effect transistors) and TFT (thin film transistors). The first drive control signal to the fourth drive control signal may be pulse-width modulated signals. The switch elements are turned on or off under the control of the pulse-width modulated signals.

[0212] 13 , in some embodiments, when the address signal line 20 is configured to transmit address signals and driving data in a time-sharing manner, the first modulation module PWMM1 to the fourth modulation module PWMM4 may be electrically connected to the control unit CLM via the address signal line 20, or may be electrically connected to the control unit CLM individually via the address signal line 20, or the electrical connection with the control module CLM may be realized in other ways. When the test signal line 40 is configured to transmit test signals and driving data in a time-sharing manner, the first modulation module PWMM1 to the fourth modulation module PWMM4 may be electrically connected to the control unit CLM via the test signal line 40, or may be electrically connected to the control unit CLM individually via the test signal line 40, or the electrical connection with the control module CLM may be realized in other ways. The present disclosure is not particularly limited thereto.

[0213] 13, in some embodiments, the logic control module CTR may further include a fifth modulation module PWMM5. The fifth modulation module PWMM5 is electrically connected to the relay pin Do. When the address pin Di receives an address signal, the control unit CLM may receive the address signal from the address pin Di and generate a relay control signal in response to the address signal and transmit it to the fifth modulation module PWMM5. The fifth modulation module PWMM5 may generate a relay signal and load it into the relay pin Do in response to the relay control signal.

[0214] In this embodiment, the fifth modulation module PWMM5 may be electrically connected to the control unit CLM via the test signal line 40 or the address signal line 20, or may be electrically connected to the control module via a dedicated data line, or may be electrically connected to the control module in other ways, although the present disclosure does not impose any particular limitations thereon.

[0215] 13, in some embodiments, when the address signal line 20 is configured to be able to transmit address signals and driving data in a time-sharing manner, the first modulation module PWMM1 to the fifth modulation module PWMM5 and the control unit CLM are all connected to the address signal line 20, thereby interacting with the first modulation module PWMM1 to the fifth modulation module PWMM5. When the test signal line 40 is configured to be able to transmit test signals and driving data in a time-sharing manner, the first modulation module PWMM1 to the fifth modulation module PWMM5 and the control unit CLM are all connected to the test signal line 40, thereby interacting with the first modulation module PWMM1 to the fifth modulation module PWMM5.

[0216] In some examples, the fifth modulation module PWMM5 may include a switch element, such as a transistor such as a MOS (metal oxide semiconductor field effect transistor) or a TFT (thin film transistor). The relay control signal may be a pulse-width modulated signal. The switch element is turned on or off under the control of the pulse-width modulated signal. When the switch element is turned on, the fifth modulation module PWMM5 may output a current or a voltage, for example, the fifth modulation module PWMM5 generates a pulse-width modulated signal, which is output by the relay pin Do as a relay signal. When the switch element is turned off, the fifth modulation module PWMM5 does not output any electrical signal (current or voltage).

[0217] In some embodiments, the logic control module CTR may further include a power supply module PWRM. The first power supply pin V1 may load a power supply signal to the power supply module PWRM. The power supply module is configured to distribute power to each circuit of the driver chip 100 to ensure power supply to the driver chip 100. The second power supply pin V2 may be electrically connected to the power supply module PWRM and is used to output a power supply signal to the next-level driver chip 100.

[0218] 14 is a circuit block diagram of the driver chip in FIG. 13. In some embodiments, other modulation modules are not shown, and only the first modulation module PWMM1 is shown. Referring to FIG. 14, in this example, the driver chip 100 may include a voltage adjustment circuit 210, a low-dropout voltage regulator 230, an oscillator 240, a control unit CLM, an address driver 260, a dimming circuit 270, a transistor 275, and a brightness control circuit 280. In each embodiment, the driver chip 100 may include additional, fewer, or different components.

[0219] The voltage regulation circuit 210 receives a power signal at the first power supply pin V1 and processes it to obtain a DC component in the power signal and generate a supply voltage. In an exemplary embodiment, the voltage regulation circuit 210 includes a first-order RC filter following an active follower. The supply voltage is provided to a low-dropout voltage regulator 230. The low-dropout voltage regulator 230 converts the supply voltage into a stable DC voltage (which can be gradually reduced) for powering an oscillator 240, a control unit CLM, and other components (not shown). In an exemplary embodiment, the stable DC voltage may be 1.8 volts. The oscillator 240 provides a clock signal. The maximum frequency of the clock signal may be, for example, approximately 10 MHz.

[0220] The control unit CLM receives a test signal from the first functional pin Q1. The test signal includes test data and first general address information. The first general address information may match the initialization address information of any of the driver chips 100. This generates a test current flowing through any of the output pins OUT. The light-emitting unit E receives the test current and emits light. The control unit CLM receives the test signal through the first functional pin Q1 and provides the first general address information in the test signal to the address driver 260. The address driver 260 caches the first general address information in the second functional pin Q2 and provides the test signal to the next-level driver chip 100.

[0221] The control unit CLM receives drive data from a data pin (first functional pin Q1), a DC voltage from the low-dropout voltage regulator 230, and a clock signal from the oscillator 240. Depending on the operation stage of the light emitting board, the control unit CLM may receive digital data from an address signal received at the address pin Di. The control unit CLM may output an enable signal 252, an increment data signal 254, a PWM clock select signal 256, and a maximum current signal 258. The control unit CLM enables the address driver 260 by activating the enable signal 252. The control unit CLM receives an address signal via the address pin Di, stores the address, and provides an incremented data signal 254 representing an outgoing address to the address driver 260. When the enable signal 252 is activated during the address placement stage, the address driver 260 caches the incremented data signal 254 in the relay pin Do. The control unit CLM may control the dimming circuit 270 to turn off the transistor 275, effectively cutting off the current path from the light emitting unit.

[0222] The control unit CLM may further deactivate the enable signal 252 and tri-state the output of the address driver 260, thereby effectively decoupling it from Do. The PWM clock select signal 256 specifies the duty cycle used by the PWM dimming circuit 270 to control PWM dimming. Based on the selected duty cycle, the PWM dimming circuit 270 controls the timing of the conductive and non-conductive states of the transistor 275. During the conductive state of the transistor 275, the transistor 275 establishes a current path from the output pin OUT (coupled to the device unit and illustrated as OUT1 in FIG. 14) to the ground pin GND, and the brightness control circuit 280 aggregates the driver current through the light-emitting unit. During the non-conductive state of the transistor 275, the current path is blocked, thereby preventing current from flowing to the light-emitting unit. When the transistor 275 is in the conductive state, the brightness control circuit 280 receives the maximum current signal 258 from the control unit CLM and controls the amplitude of the current (from the output pin OUT to the ground pin GND) through the light-emitting unit. The control unit CLM controls the duty ratio of the PWM dimming circuit 270 and the maximum current 258 of the brightness control circuit 280 to set the LED of the light-emitting unit to a desired brightness.

[0223] It is understood that the driver chip 100 may further include a voltage-controlled constant current circuit (not shown), the input reference voltage and input reference current of which may be generated by the power supply signal received at the first power supply pin V1. The voltage-controlled constant current circuit may be electrically connected to the brightness control circuit 280.

[0224] 14 , in some embodiments, the modulation module is provided with a short circuit detector and an open circuit detector. Here, the open circuit detector is configured by an operational amplifier connected in a virtual open circuit manner and is used to detect whether an open circuit occurs between the device unit and the driver chip 100. Here, the Vopen terminal may be a floating signal terminal. The short circuit detector is configured by an operational amplifier connected in a virtual short circuit manner and detects whether a short circuit occurs between the device unit and the driver chip 100. Here, the potential of Vshort may be the same as the potential of the driving data transmitted by the second voltage line 10.

[0225] 14 , in some embodiments, the driver chip 100 further includes a data selector MUX and an analog-to-digital converter ADC. When the driver chip 100 uses the output pins OUT to form signal circuits between the corresponding light-emitting units and the second voltage line 10, the driver chip 100 transmits the electrical signals of the signal circuits to the data selector MUX, processes them in a time-sharing manner via the analog-to-digital converter ADC, and transmits them to the control unit CLM. The electrical signals are then transmitted level by level through the relay pins Do of the driver chip 100 (e.g., appended to the data signal 254 in order according to an encoding rule) until the final level is output by the relay pin Do of the driver chip 100, and connected to an external circuit via the feedback signal line 70. The external circuit can adjust the output signal level in response to the feedback information to reduce the power consumption of the light-emitting board.

[0226] In some embodiments, still referring to FIG. 14 , the driver chip 100 may be provided with a thermal shutdown delay sensor TSD and a thermal shutdown controller TS. The thermal shutdown delay sensor TSD is used to detect the internal temperature of the driver chip 100. When the internal temperature of the driver chip 100 reaches a preset protection temperature (typically set between 150°C and 170°C), the thermal shutdown delay controller TS operates to turn off the output of the driver chip 100, reducing the power consumption of the driver chip 100 and thereby reducing the internal temperature of the driver chip 100. When the internal temperature of the driver chip 100 drops to a preset restart temperature (restart temperature = protection temperature - delay temperature), the driver chip 100 resumes output. Here, the delay temperature is typically set within a range of 15°C to 30°C. The thermal shutdown delay controller TS may be connected to the data selector MUX and feed back abnormality information to the control unit CLM via the data selector MUX to control the operating state of the driver chip 100.

[0227] 15 is another circuit block diagram of the driver chip in FIG. 13. In some other embodiments, referring to FIG. 15, the control unit CLM receives a test signal from the first functional pin Q1, where the test signal includes a switch signal. The switch signal is used to control the control unit CLM to generate a test current flowing through any of the output pins OUT. The light-emitting unit E receives the test current and emits light. In addition, the control unit CLM receives the test signal via the first functional pin Q1 and transmits the test signal to the second functional pin Q2, which can output the test signal to the next-level driver chip 100.

[0228] The control unit CLM receives drive data from the data pin (or address pin Di), a DC voltage from the low-dropout voltage regulator 230, and a clock signal from the oscillator 240. Depending on the operation stage of the light emitting board, the control unit CLM may receive digital data from an address signal received at the address pin Di. The control unit CLM may output an enable signal 252, an increment data signal 254, a PWM clock select signal 256, and a maximum current signal 258. The control unit CLM enables the address driver 260 by activating the enable signal 252. The control unit CLM receives an address signal via the address pin Di, stores the address, and provides an incremented data signal 254 representing an outgoing address to the address driver 260. When the enable signal 252 is activated during the address placement stage, the address driver 260 caches the incremented data signal 254 in the relay pin Do. The control unit CLM may control the dimming circuit 270 to turn off the transistor 275, effectively cutting off the current path from the light emitting unit.

[0229] 16 is a flowchart of a detection method for a light-emitting substrate according to some embodiments of the present disclosure. Some embodiments of the present disclosure provide a test method for a light-emitting substrate 200. The light-emitting substrate 200 is the light-emitting substrate 200 of any of the above embodiments. The device group O includes at least one light-emitting unit E. Referring to FIG. 16, the test method includes the following steps:

[0230] S1: By inputting a test signal to the first functional pin of each driver chip, the logic control module of each driver chip generates a test current flowing through one of its output pins in response to the test signal. Determine the light-emitting status of a device group electrically connected to one of the driver chips. If light is emitting normally, determine that the device group and the corresponding driver chip are normally connected. If light is not emitting or abnormal light, determine that the device group and the corresponding driver chip are abnormally connected.

[0231] Step S1 includes the following steps.

[0232] S1a: By inputting a test signal to the first functional pin Q1 of each driver chip 100, the logic control module of each driver chip generates a test current flowing through any output pin according to the test signal.

[0233] The test current may drive the light emitting units E in the device group O to emit light.

[0234] S1b: Determine the light-emitting state of the device group O electrically connected to any one of the driver chips 100.

[0235] The connection status of the light-emitting unit E can be determined according to the light-emitting state of the light-emitting unit E in the device group O. Here, the light-emitting state may include a normal light-emitting state, an abnormal light-emitting state, and a non-light-emitting state.

[0236] If the device group O emits light normally, perform step S1c to determine that the device group O and the corresponding driver chip 100 are normally connected. If the light-emitting unit E in the device group O emits light normally, the light-emitting unit E and the corresponding driver chip 100 are normally connected. This means that the device group O / light-emitting unit E does not need to be repaired.

[0237] Here, normal light emission means that the light emission brightness of the light emitting unit E reaches the threshold brightness, which may be specifically set according to actual needs.

[0238] If the device group O is not emitting light or has an abnormal light emission, perform step S1d to determine that the device group O and the corresponding driver chip 100 are abnormally connected. If the light-emitting unit E in the device group O is not emitting light or has an abnormal light emission, determine that the light-emitting unit E and the corresponding driver chip 100 are abnormally connected.

[0239] For example, if a device group O / light-emitting unit E does not emit light, it can be determined that the device group O / light-emitting unit E and the driving chip connected thereto are disconnected and need to be inspected, repaired, and re-welded, so that the device group O / light-emitting unit E can be normally connected to the driving chip and emit light normally.

[0240] For example, if the device group O / light-emitting unit E has abnormal light emission, it can be determined that the device group O / light-emitting unit E may have a rosin connection and needs to be inspected, repaired, and re-welded, so that the device group O / light-emitting unit E can be normally connected to the driving chip and can normally emit light.

[0241] Here, the abnormal light emission means that the light emission brightness of the light emitting unit E is lower than the threshold brightness, which may be specifically set according to actual needs.

[0242] The above test method inputs a test signal to the first functional pin Q1 of each driver chip 100, thereby enabling a lighting test of the light emitting unit E electrically connected to each driver chip 100 through a single detection operation, which is advantageous in improving the inspection and repair efficiency of the driver chip 100.

[0243] FIG. 17 is a flowchart of a method for detecting a light-emitting substrate according to some other embodiments of the present disclosure.

[0244] In some embodiments, as shown in FIG. 12, with reference to FIG. 17, S1A includes the following steps:

[0245] S1Aa: Input a switch signal to the first functional pin of each driver chip, and the switch signal is used to control the logic control module to generate a test current flowing through one of the output pins, so that the logic control module of each driver chip generates a test current flowing through one of the output pins according to the test signal.

[0246] S1Ab: Determine the light-emitting state of the device group O electrically connected to any one of the driver chips 100.

[0247] If the device group O emits light normally, perform step S1Ac to determine that the device group O and the corresponding driver chip 100 are normally connected. If the light-emitting unit E in the device group O emits light normally, the light-emitting unit E and the corresponding driver chip 100 are normally connected. This means that the device group O / light-emitting unit E does not need to be repaired.

[0248] If the device group O is not emitting light or has an abnormal light emission, perform step S1Ad to determine that the device group O and the corresponding driver chip 100 are abnormally connected. If the light-emitting unit E in the device group O is not emitting light or has an abnormal light emission, determine that the light-emitting unit E and the corresponding driver chip 100 are abnormally connected.

[0249] According to the above test method, by inputting a test signal to the first functional pin Q1 of each driver chip 100, a lighting test of the light emitting unit E electrically connected to each driver chip 100 can be realized through a single detection operation, which is advantageous to improving the inspection and repair efficiency of the driver chip 100.

[0250] In this embodiment, the test signal includes a switch signal. The switch signal is used to control the logic control module CTR to generate a test current through one of the output pins OUT. That is, the light-emitting units E electrically connected to the driver chip 100 can all receive the test current. Furthermore, since the second functional pin Q2 is directly connected to the first functional pin Q1 of the driver chip at the current level and the driver chip at the next level, the driver chips 100 at each level can all receive the same test signal. Therefore, a single detection operation can be used to test the lighting of the light-emitting units E electrically connected to each driver chip 100. If a light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E, thereby effectively improving the efficiency of inspection and repair of the driver chips 100. In some examples, the test signal can be a high-level signal or a low-level signal. The test signal can be used to control the logic control module CTR to generate a test current through one of the output pins OUT.

[0251] FIG. 18 is a flowchart of a method for detecting a light-emitting substrate according to some further embodiments of the present disclosure.

[0252] In some embodiments, as shown in FIG. 12, with reference to FIG. 18, the test method further includes the following steps:

[0253] S01: Input driving data to an address pin of a first driver chip among a plurality of cascaded driver chips, the driving data including address inspection information and a plurality of driving information items corresponding to the plurality of cascaded driver chips. Here, the driver chip allocates one driving information item corresponding to the current driver chip according to the address inspection information, and generates a corresponding driving current according to the driving information item. The driver chip updates the address inspection information, generates driving data including the updated address inspection information, and outputs the driving data including the updated address inspection information to the next-level driver chip. Determine whether a non-light-emitting device group exists among the device groups connected to the plurality of cascaded driver chips. If it is determined that a non-light-emitting device group exists, determine that an abnormality exists in the driver chip connected to the first non-light-emitting device group according to the cascading order. If it is determined that a non-light-emitting device group does not exist, determine that no abnormality exists in the plurality of cascaded driver chips.

[0254] Step S01 includes the following steps.

[0255] S01a: Input driving data to the address pin Di of the first driver chip among the plurality of cascaded driver chips 100, the driving data including address inspection information and a plurality of driving information corresponding to the plurality of cascaded driver chips, wherein the driver chip 100 arranges one driving information corresponding to the current driver chip 100 according to the address inspection information, and the device group O connected to the driver chip 100 generates a corresponding driving current according to the driving information, the driver chip 100 updates the address inspection information and generates driving data including the updated address inspection information, and outputs the driving data including the updated address inspection information to the next-level driver chip 100.

[0256] S01b: Determine whether or not there is a non-light-emitting device group O among the device groups O connected to the plurality of cascaded driver chips 100.

[0257] If it is determined that there is no non-light-emitting device group O (S01b: NO), step S01c is performed to determine that there is no abnormality in the cascaded multiple driver chips 100. There is no need to inspect or repair the driver chip 100.

[0258] If it is determined that there is a non-light-emitting device group O (S01b: YES), step S01d is performed to determine that there is an abnormality in the driver chip 100 connected to the first non-light-emitting device group O according to the cascade order. The address pin Di and relay pin Do of the driver chip 100 need to be inspected and repaired to determine whether the welding is normal. After recovery, the device group O connected to the driver chip 100 can be made to emit light normally.

[0259] In some examples, step S01 may be continued until all device groups O connected to all driver chips 100 can emit light normally, and may be used to determine whether any abnormalities exist in the remaining driver chips 100.

[0260] Based on the above several embodiments, step S01a may be used to drive the light emitting substrate 200 to emit light normally.

[0261] In some embodiments, the testing method may include the above-mentioned step S1A and step S01. Step S1A is used to test the light emitting element O connected to the driver chip 100, and step S01 is used to detect the cascade state of multiple driver chips 100, which is advantageous for improving the efficiency of inspection and repair of the light emitting substrate 200.

[0262] In some examples, step S01 may be performed first, followed by step S1A, or the detection method may be performed first by step S1A, followed by step S01, although the present disclosure is not limited thereto.

[0263] FIG. 19 is a flowchart of a method for testing a light emitting substrate according to some further embodiments of the present disclosure.

[0264] In some embodiments, as shown in FIG. 19 and FIG. 12, S1B includes the following steps:

[0265] S1Ba: A test signal including test data and first general address information is input to a first functional pin of each driver chip, where the first general address information can be matched with the initialization address information of any driver chip, so that the logic control module of each driver chip generates a test current through any output pin according to the test signal.

[0266] S1Bb: Determine the light-emitting state of the device group O electrically connected to any one of the driver chips 100.

[0267] If the device group O emits light normally, perform step S1Bc to determine that the device group O and the corresponding driver chip 100 are normally connected. If the light-emitting unit E in the device group O emits light normally, the light-emitting unit E and the corresponding driver chip 100 are normally connected. This means that the device group O / light-emitting unit E does not need to be repaired.

[0268] If the device group O is not emitting light or has an abnormal light emission, perform step S1Bd to determine that the device group O and the corresponding driver chip 100 are abnormally connected. If the light-emitting unit E in the device group O is not emitting light or has an abnormal light emission, determine that the light-emitting unit E and the corresponding driver chip 100 are abnormally connected.

[0269] The above test method inputs a test signal to the first functional pin Q1 of each driver chip 100, thereby enabling a lighting test of the light emitting unit E electrically connected to each driver chip 100 through a single detection operation, which is advantageous in improving the inspection and repair efficiency of the driver chip 100.

[0270] In this embodiment, the test signal includes test data and first general address information. The first general address information may match the initialization address information of any of the driver chips 100 to generate a test current flowing through any of the output pins OUT. The light-emitting unit E receives the test current and emits light. Because the first general address information may match the initialization address information of any of the driver chips 100, the test signal can simultaneously activate the light-emitting units E electrically connected to each driver chip 100. If the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E. In this way, a single detection operation can be used to test the lighting of the light-emitting units E electrically connected to each driver chip 100, thereby effectively improving the efficiency of inspection and repair of the driver chips 100.

[0271] FIG. 20 is a flowchart of a method for detecting a light-emitting substrate according to some further embodiments of the present disclosure.

[0272] In some embodiments, as shown in FIG. 12, with reference to FIG. 20, the test method further includes the following steps:

[0273] S10A: An address signal is input to the address pin of the first driver chip among the multiple cascaded driver chips. The driver chip arranges the address information of the driver chip according to the address signal to generate a relay signal, and the relay pin outputs the relay signal to the driver chip at the next level. Here, the relay signal is the same as the address signal. That is, the address information after updating is the same (the address information after updating the initialization information is the same).

[0274] In some examples, the address signal may be a digital signal. After one driver chip 100 receives the address signal, it may analyze and obtain the address signal stored in the address signal, and then increment the address signal by 0 to obtain a new address signal, which may be modulated into a repeat signal. The repeat signal is used as the address signal for the next-level driver chip 100. The repeat signal is the same as the address signal. Of course, the driver chip 100 may use other different functions to generate a new address signal.

[0275] After step S10A, step S1B1 may be further included. In this case, step S1B1 is used to determine whether there is an abnormality in the multiple cascaded driver chips 100. S1B1 includes the following steps:

[0276] S1B1a: A test signal including test data and second general-purpose address information is input to a first functional pin of each driver chip. The second general-purpose address information can match the updated address information (the updated address information of the initialization information) of any driver chip. Thereby, the logic control module of each driver chip generates a test current flowing through one of its output pins according to the test signal.

[0277] S1B1b: Determine whether or not there is a non-light-emitting device group among the device groups connected to the plurality of cascaded driver chips.

[0278] If it is determined that there is no non-light-emitting device group (S1B1b: NO), then perform step S1B1c to determine that there is no abnormality in the cascaded driver chips. As a result, the address pin Di and the relay pin Do in the driver chip 100 connected to the light-emitting unit E are normally welded. This means that the driver chip 100 does not need to be repaired.

[0279] If it is determined that a non-light-emitting device group exists (S1B1b: YES), step S1B1d is performed to determine that an abnormality exists in the driver chip connected to the first non-light-emitting device group according to the cascade order. That is, the address pin Di and the relay pin Do in the driver chip 100 are abnormally welded. As can be seen from this, the driver chip 100 needs to be repaired.

[0280] Based on this, it may be determined whether all the light-emitting elements E electrically connected to each driver chip 100 emit light. If none of the light-emitting elements E electrically connected from a certain driver chip 100 to the subsequent driver chip 100 emit light, it can be determined that there is a problem with the welding between the address pin Di and the relay pin Do of that driver chip 100 and that repair is required.

[0281] In some embodiments, the test method includes steps S1B, S10A, and S1B1. Because each driver chip 100 is factory-installed with initialization address information, in step S1B, the first general address information in the test signal matches the initialization address information in one of the driver chips 100, causing the logic control module of each driver chip 100 to generate a test current through one of the output pins OUT. The device group O receives the test current and emits light. Whether the light-emitting unit E in the device group O emits light is used to determine whether the light-emitting unit E is properly welded. Next, in step S10A, the initialization address information is updated to obtain the updated address information, which remains the same. Next, in step S1B1, the second general address information in the test signal matches the updated address information in one of the driver chips, causing the logic control module of each driver chip 100 to generate a test current through one of the output pins OUT. The device group O receives the test current and emits light. If none of the devices in a certain device group O emits light, it is determined that the initialization address information of the driver chip 100 connected to the non-light-emitting device group O has not been updated to address information that matches the second general address information. Therefore, an abnormality exists in the driver chip 100. That is, there may be a welding problem in the address pin Di and relay pin Do for receiving the updated address information in the driver chip 100. The coordinates of the abnormal light-emitting unit E in step S1B and the coordinates of the abnormal driver chip 100 in step S1B1 are recorded, and inspection and repair are performed simultaneously. This is advantageous for improving the efficiency of inspection and repair of the light-emitting substrate 200.

[0282] FIG. 21 is a flowchart of a method for detecting a light-emitting substrate according to some further embodiments of the present disclosure.

[0283] In some embodiments, the first functional pin Q1 of the driver chip 100 receives the test signal and the driving data in a time-sharing manner. Referring to FIG. 21, as shown in FIG. 12, the test method further includes the following steps:

[0284] S10B: An address signal is input to the address pin of the first driver chip among the plurality of cascaded driver chips, and the driver chip arranges the address information of the driver chip according to the address signal to generate a relay signal, and the relay pin outputs the relay signal to the next-level driver chip, where the relay signal is different from the address signal.

[0285] In step S10B, an address signal is input to the address pins Di of the cascaded driver chips 100, and the driver chip 100 arranges the address information of the driver chip 100 according to the address signal to generate a relay signal, and the relay pin Do can output the relay signal to the next-level driver chip 100. In step S01, an address is written to each driver chip 100. Here, the relay signal is different from the address signal.

[0286] In some examples, the address signal may be a digital signal. After one driver chip 100 receives the address signal, it may analyze and obtain the address signal stored in the address signal, increment the address signal by a fixed amount such as 1 or other non-zero value, and modulate the incremented address signal (new address signal) into a repeat signal. The repeat signal is the address signal of the next-level driver chip 100. Therefore, the repeat signal is different from the address signal. Of course, the driver chip 100 may generate a new address signal using other different functions.

[0287] S11: input driving data to a first functional pin of each of the plurality of cascaded driving chips, the driving data including a plurality of address verification information and a plurality of driving information corresponding to the plurality of address verification information, and for any of the driving chips, if the address verification information matches the address information of the driving chip, the logic control module receives the corresponding driving information according to the address verification information, and generates a corresponding driving current for at least one output pin according to the received driving information; determine whether a non-light-emitting device group exists in the device groups connected to the plurality of cascaded driving chips, and if it is determined that a non-light-emitting device group exists, determine that an abnormality exists in the driving chip connected to the first non-light-emitting device group according to the cascading order; and if it is determined that a non-light-emitting device group does not exist, determine that no abnormality exists in the plurality of cascaded driving chips.

[0288] Step S11 includes the following steps.

[0289] S11a: Input driving data to a first functional pin of each of the plurality of cascaded driving chips, the driving data including a plurality of address verification information and a plurality of driving information corresponding to the plurality of address verification information, and for any of the driving chips 100, if the address verification information matches the address information of the driving chip 100, the logic control module receives the corresponding driving information according to the address verification information, and generates a driving current corresponding to at least one output pin OUT according to the received driving information.

[0290] S11b: Determine whether or not there is a non-light-emitting device group O among the device groups O connected to the plurality of cascaded driver chips 100.

[0291] If it is determined that there is no non-light-emitting device group O (S11b: NO), step S11c is performed to determine that there is no abnormality in the cascaded multiple driver chips 100. There is no need to inspect or repair the driver chip 100.

[0292] If it is determined that there is a non-light-emitting device group O (S11b: YES), step S11d is performed to determine that there is an abnormality in the driver chip 100 connected to the first non-light-emitting device group O according to the cascade order. The address pin Di and relay pin Do of the driver chip 100 need to be inspected and repaired to determine whether the welding is normal. After recovery, the device group O connected to the driver chip 100 can be made to emit light normally.

[0293] In some examples, step S11 may be continued until all device groups O connected to all driver chips 100 can emit light normally, and may be used to determine whether any abnormalities exist in the remaining driver chips 100.

[0294] Based on the above several embodiments, step S10B and step S11a may be used to drive the light emitting substrate 200 to emit light normally.

[0295] In some embodiments, the testing method may include the above-mentioned step S1B, step S10B, and step S11. Step S1B is used to test the light emitting element O connected to the driving chip 100, and steps S10B and S11 are used to detect the cascade state of multiple driving chips 100, which is advantageous for further improving the inspection and repair efficiency of the light emitting substrate 200.

[0296] In some examples, the testing method may first perform step S1B, then perform steps S10B and S11.

[0297] As described above, some embodiments of the present disclosure provide a driver chip 100, a light-emitting substrate 200, and a display device 300, and further provide a method for detecting a light-emitting substrate. The structure of the driver chip 100 is optimized, for example, to include a first functional pin Q1 and a second functional pin Q2. A test signal is input to the first functional pin Q1 of each driver chip 100. A test current is generated through one of the output pins OUT in response to the test signal. The first functional pin Q1 is electrically connected to the second functional pin Q2. The second functional pin Q2 can output a test signal to the next-level driver chip 100. This allows a single detection operation to test the lighting of the light-emitting unit E electrically connected to each driver chip 100. If the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E, thereby effectively improving the efficiency of inspection and repair of the driver chip 100. The light emitting substrate 200 having the driving chip 100, the display device 300 having the light emitting substrate 200, and the detection method of the driving chip 100 all have the beneficial effects of the driving chip 100 in any of the above embodiments, which will not be repeated here.

[0298] The above are only specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto. Any modifications or replacements that can be easily thought of by a person skilled in the art within the technical scope of the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be governed by the scope described in the claims.

Claims

1. a logic control module; at least one output pin electrically connected to said logic control module; a first functional pin electrically connected to the logic control module, the first functional pin being capable of receiving a test signal; Equipped with the logic control module is configured to generate a test current flowing through each of the output pins in response to the test signal; Driving chip.

2. the test signals include switch signals, which are used to control the logic control module to generate test currents that flow through any of the output pins, respectively; The driver chip of claim 1 .

3. The driver chip further includes an address pin and a relay pin; The address pin is electrically connected to the logic control module, and the address pin can receive driving data, and the driving data includes address inspection information and a plurality of driving information corresponding to a plurality of cascaded driving chips; The logic control module is configured to obtain one piece of driving information corresponding to the current driving chip according to the address checking information, update the address checking information, and generate driving data including the updated address checking information; the relay pin is electrically connected to the logic control module, and the relay pin is capable of outputting the driving data including updated address inspection information; 3. The driver chip according to claim 1 or 2.

4. The test signal includes test data and general address information, and the general address information can be matched with address information of any of the driving chips; the logic control module is configured to generate a test current flowing through each of the output pins in response to the test data; The driver chip of claim 1 .

5. The driver chip includes: an address pin electrically connected to the logic control module, the address pin being capable of receiving an address signal, wherein the logic control module is configured to configure address information of the driver chip and generate a relay signal according to the address signal; a relay pin electrically connected to the logic control module and capable of outputting the relay signal; Furthermore, the first functional pin is further capable of receiving driving data, the driving data including a plurality of address verification information and a plurality of driving information corresponding to the plurality of address verification information; the logic control module is configured to receive corresponding drive information according to the address verification information when the address verification information matches with the address information of the driver chip, and generate a corresponding drive current for the at least one output pin according to the received drive information; The driver chip according to claim 1 or 4.

6. The driver chip includes: a second functional pin and a first connecting line, the second functional pin being connected to the first functional pin via the first connecting line, and the second functional pin being capable of outputting a test signal; the driver tip has first and second parallel edges; one of the first functional pin and the second functional pin is near the first edge and the other is near the second edge; The driver chip according to any one of claims 1 to 5.

7. the driver tip further has a third edge located between the first end of the first edge and the first end of the second edge; When the driver chip has address pins and relay pins, one of the address pins and the relay pins is close to the first edge and the other is close to the second edge; the address pins and the relay pins are closer to the third edge than the first functional pins and the second functional pins; The driver chip of claim 6.

8. The driver chip includes: and further comprising at least one ground pin electrically connected to the logic control module and capable of receiving a ground signal, the ground pin being located between an address pin and the relay pin. The driver chip of claim 7.

9. The driver chip includes: a first power pin electrically connected to the logic control module, the first power pin capable of receiving a power signal, the first power pin being proximate to the first edge or the second edge; 9. The driver chip according to claim 7 or claim 8.

10. The driver chip includes: a second power supply pin and a second connection line, the second power supply pin being connected to the first power supply pin via the second connection line, and the second power supply pin being capable of outputting the power supply signal; one of the first power pin and the second power pin is near the first edge and the other is near the second edge; the first power supply pin and the second power supply pin are located farther from the third edge portion than the address pin and the relay pin; The driver chip of claim 9.

11. the driver tip further has a fourth edge located between the second end of the first edge and the second end of the second edge; the number of the output pins is plural, the plural output pins are close to the fourth edge portion, and the plural output pins are arranged along an extension direction of the fourth edge portion; The driver chip according to any one of claims 6 to 10.

12. a plurality of cascaded driver chips, each of which is a driver chip according to any one of claims 1 to 11; a plurality of device groups, each of which has a first end electrically connected to at least one output pin of a driver chip; Equipped with Light-emitting substrate.

13. When the driver chip further comprises an address pin, a relay pin, a first power supply pin, and at least one ground pin, The relay pins of the driver chip located on the previous level are electrically connected to the address pins of the driver chip located on the next level; the light-emitting substrate further comprises a conductive layer; The conductive layer includes: a second voltage line electrically connected to a second end of each of the device groups; an address signal line electrically connected to an address pin of the first driver chip; a first voltage line electrically connected to a first power pin of the first driver chip; a test signal line electrically connected to a first functional pin of the first driver chip; a ground line electrically connected to at least one ground pin of each of the driver chips; Contains, the second voltage line, the address signal line, the first voltage line, the test signal line, and the ground line do not overlap; The light-emitting substrate according to claim 12 .

14. If the driver chip further comprises a second functional pin, the second functional pins are electrically connected to the first functional pins of the driver chip at this level and the first functional pins of the driver chip at the next level, respectively; The light-emitting substrate according to claim 12 or 13.

15. If the driver chip further comprises a second power pin, The second power pin is electrically connected to the first power pin of the driver chip at this level and the first power pin of the driver chip at the next level, respectively; The light emitting substrate according to any one of claims 12 to 14.

16. The address signal lines are configured to transmit address signals, and the test signal lines are configured to transmit test signals and driving data in a time-sharing manner, or the address signal lines are configured to transmit driving data, and the test signal lines are configured to transmit test signals. The light emitting substrate according to any one of claims 13 to 15.

17. A method for testing a light emitting substrate, comprising: The light emitting substrate is a light emitting substrate according to any one of claims 12 to 16, The test method comprises: inputting a test signal to a first functional pin of each driver chip, so that the logic control module of each driver chip generates a test current flowing through any output pin according to the test signal; determining the light-emitting state of a device group electrically connected to any one of the driving chips, and if the light-emitting state is normal, determining that the device group and the corresponding driving chip are normally connected, and if the light-emitting state is not light-emitting or abnormal, determining that the device group and the corresponding driving chip are abnormally connected; Including, How to test a light-emitting board.

18. inputting a test signal to a first functional pin of each driver chip; inputting a switch signal to a first functional pin of each driver chip, the switch signal being used to control the logic control module to generate a test current flowing through any output pin; 18. The testing method of claim 17.

19. The test method comprises: a step of inputting driving data to an address pin of a first driving chip among a plurality of cascaded driving chips, the driving data including address inspection information and a plurality of driving information corresponding to the plurality of cascaded driving chips, the driving chip arranging one driving information corresponding to the current driving chip according to the address inspection information, and a device group connected to the driving chip generating a corresponding driving current according to the driving information, the driving chip updating the address inspection information, generating driving data including the updated address inspection information, and outputting the driving data including the updated address inspection information to a next-level driving chip; determining whether a non-light-emitting device group exists in the device groups connected to the plurality of cascaded driver chips, and if it is determined that a non-light-emitting device group exists, determining that an abnormality exists in the driver chip connected to the first non-light-emitting device group according to the cascading order, and if it is determined that a non-light-emitting device group does not exist, determining that an abnormality does not exist in the plurality of cascaded driver chips; further comprising:

19. The testing method according to claim 17 or 18.

20. inputting a test signal to a first functional pin of each driver chip; inputting a test signal including test data and first general address information to a first functional pin of each driver chip, the first general address information being matchable with initialization address information of any of the driver chips; 18. The testing method of claim 17.

21. The test method comprises: The method further includes the steps of: inputting an address signal to an address pin of a first driver chip among a plurality of cascaded driver chips, the driver chip arranging address information of the driver chip according to the address signal and generating a relay signal; the relay pin outputting the relay signal to a next-level driver chip, the relay signal being the same as the address signal; The test method comprises: inputting a test signal including test data and second general address information into a first functional pin of each driver chip, the second general address information being matched with updated address information of any of the driver chips, so that a logic control module of each of the driver chips generates a test current flowing through any of its output pins according to the test signal; determining whether a non-light-emitting device group exists in the device groups connected to the plurality of cascaded driver chips, and if it is determined that a non-light-emitting device group exists, determining that an abnormality exists in the driver chip connected to the first non-light-emitting device group according to the cascading order, and if it is determined that a non-light-emitting device group does not exist, determining that an abnormality does not exist in the plurality of cascaded driver chips; further comprising:

21. The testing method according to claim 17 or claim 20.

22. The test method comprises: inputting an address signal to an address pin of a first driver chip among a plurality of cascaded driver chips, the driver chip arranging address information of the driver chip according to the address signal and generating a relay signal, the relay pin outputting the relay signal to a next-level driver chip, the relay signal being different from the address signal; a step of inputting driving data to a first functional pin of each of a plurality of cascaded driving chips, the driving data including a plurality of address verification information and a plurality of driving information corresponding to the plurality of address verification information, and when the address verification information matches the address information of any of the driving chips, the logic control module receives the corresponding driving information according to the address verification information, and generates a driving current corresponding to the at least one output pin according to the received driving information; determining whether a non-light-emitting device group exists in the device groups connected to the plurality of cascaded driver chips, and if it is determined that a non-light-emitting device group exists, determining that an abnormality exists in the driver chip connected to the first non-light-emitting device group according to the cascading order, and if it is determined that a non-light-emitting device group does not exist, determining that an abnormality does not exist in the plurality of cascaded driver chips; further comprising:

21. The testing method according to claim 17 or claim 20.

23. A light emitting substrate according to any one of claims 12 to 16, Display device.

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