Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes an insulating layer, a protective member disposed on the insulating layer, and a plurality of posts disposed on the insulating layer along the periphery of the protective member, the protective member having an upper surface, a lower surface, and a side surface disposed between the upper surface and the lower surface, the lower surface of the protective member facing the upper surface of the insulating layer, the side surfaces of the plurality of posts facing the side surfaces of the protective member, and the side surfaces of the protective member including protrusions protruding between the plurality of posts.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] A semiconductor package has a structure in which a semiconductor chip is mounted on a circuit board. A semiconductor package can be provided by integrating multiple packages each mounting different elements into one. Such a semiconductor package has the advantage of enabling high-speed signal transmission through a short path because multiple elements are realized in one package. For this reason, semiconductor packages are widely used in mobile devices.

[0003] Meanwhile, semiconductor packaging has been achieved by using wires to attach electronic elements such as semiconductor chips to circuit boards. However, semiconductor packages with wire structures have the problem of increased volume. As a result, semiconductor packaging has recently been achieved using flip chip packaging. Flip chip packaging is a packaging method in which electronic elements such as semiconductor chips are attached to circuit boards without using additional connecting members such as wires, but by bonding the semiconductor chip to the circuit board by fusing solder bumps to the connection patterns of the semiconductor chip or circuit board.

[0004] Recently, with the demand for high-speed, large-capacity data processing and the trend toward lighter, thinner, and smaller electronic products, the bump pitch of electronic devices has been gradually decreasing. This trend has led to a decrease in the reliability of bump connections between circuit boards and semiconductor chips in flip-chip packaging. To prevent this decrease in reliability, Korean Patent Publication No. 10-2013-0027870 proposes a structure including posts with improved reliability. Summary of the Invention [Problem to be solved by the invention]

[0005] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0006] Also, the embodiments provide a circuit board and a semiconductor package including the same that can reduce the spacing or pitch between multiple posts.

[0007] Furthermore, the embodiments provide a circuit board capable of improving circuit integration and a semiconductor package including the same.

[0008] Furthermore, the embodiments provide a circuit board and a semiconductor package including the same, which have improved physical and / or electrical connection reliability between posts and pads.

[0009] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0010] A circuit board according to an embodiment includes an insulating layer, a protective member disposed on the insulating layer, and a plurality of posts disposed on the insulating layer along the periphery of the protective member, the protective member having an upper surface, a lower surface, and a side surface disposed between the upper surface and the lower surface, the lower surface of the protective member facing the upper surface of the insulating layer, the side surfaces of the plurality of posts facing the side surfaces of the protective member, and the side surfaces of the protective member including protrusions protruding between the plurality of posts.

[0011] Further, the side surfaces of the protective member include a first side surface extending in a first direction, a second side surface extending in the first direction and spaced apart from the first side surface, a third side surface extending in a second direction perpendicular to the first direction, and a fourth side surface extending in the second direction and spaced apart from the third side surface, and the protruding surfaces of the protective member are provided on the first side surface and the third side surface.

[0012] The third side surface has a first surface having a first separation distance from the plurality of posts along the first direction, a second surface having a second separation distance smaller than the first separation distance, and a third surface having a third separation distance larger than the first separation distance.

[0013] Furthermore, the distance between the fourth side surface and the plurality of posts along the first direction is uniform.

[0014] Additionally, the second side surface of the protection member includes a concave surface recessed toward the first side surface of the protection member.

[0015] The protective member also includes a plurality of through holes, and the width of the plurality of through holes is smaller than the width of the plurality of posts.

[0016] The circuit board also includes an outer protective member disposed on the insulating layer and having a through hole, and the post and protective member are disposed in the through hole of the outer protective member.

[0017] The circuit board further includes a surface treatment layer disposed on the posts.

[0018] The circuit board also includes a plurality of pads arranged between the insulating layer and the protective member, and the width of the plurality of through holes in the protective member is smaller than the width of the composite pads, and the width of the posts is smaller than the width of the pads.

[0019] The circuit board further includes a surface treatment layer disposed in each of the plurality of through holes of the protective member, and the surface treatment layer disposed in each of the plurality of through holes of the protective member and the surface treatment layer disposed on the post are made of the same material.

[0020] The protective member and the outer protective member form an upper protective layer provided on the upper surface of the insulating layer.

[0021] The outer protective member is provided along the periphery of the upper surface of the substrate.

[0022] The protective member is provided inside the outer protective member with a horizontal separation area therebetween.

[0023] Further, the separation region between the inner surface of the outer protective member and the outer surface of the protective member includes a first separation region having a first width along the horizontal direction and a second separation region having a second width different from the first width.

[0024] The separation region is formed as a closed loop along the outer surface of the protection member.

[0025] The outer surface of the protection member includes a protruding surface that protrudes toward the inner surface of the outer protection member.

[0026] Additionally, the protruding surface of the protection member is provided in the second spaced region, and the first width is greater than the second width.

[0027] The outer surface of the protection member includes a concave surface that is recessed toward the inside of the protection member.

[0028] The concave surface of the protection member is provided in the first spaced region, and the first width is greater than the second width.

[0029] Further, the protruding surface of the protective member includes a first protruding surface that protrudes toward the inner surface of the outer protective member with a first protruding width, and a second protruding surface that protrudes toward the inner surface of the outer protective member with a second protruding width that is larger than the first protruding width.

[0030] Furthermore, the inner surface of the outer protective member includes a first inner surface, a second inner surface facing the first inner surface, a third inner surface disposed between the first inner surface and the second inner surface and facing each other, and a fourth inner surface, and the outer surface of the protective member includes a first outer surface adjacent to the first inner surface, a second outer surface adjacent to the second inner surface, a third outer surface adjacent to the third inner surface, and a fourth outer surface adjacent to the fourth inner surface, and the separation region between the first inner surface of the outer protective member and the first outer surface of the protective member includes the first and second separation regions.

[0031] Furthermore, the spacing between the pads provided between the insulating layer and the posts is smaller than the width of each of the pads. [Effects of the Invention]

[0032] A circuit board according to an embodiment includes an insulating layer and a protective layer disposed on the insulating layer. The protective layer can be referred to as a protective member provided on a portion of an upper surface of the insulating layer. The circuit board includes a plurality of posts disposed on the insulating layer along the periphery of the protective member. The protective member includes an upper surface, a lower surface, and a side surface disposed between the upper and lower surfaces. The lower surface of the protective member faces the upper surface of the insulating layer. Side surfaces of the posts face side surfaces of the protective member. The side surfaces of the protective member include protrusions protruding between the posts.

[0033] Exemplarily, the outer surface of the protective member may have a horizontal step along its periphery. Specifically, the protective member may include a protruding surface or a concave surface protruding toward the post. The protruding surface and the concave surface may be designed based on the position of the post. Exemplarily, the protruding surface may protrude toward a region between a plurality of pads. This may improve design freedom for pad placement in the embodiment. This may improve the degree of integration of the pads and the posts in the embodiment.

[0034] In addition, the outer surface of the protective member of the embodiment may be positioned a certain distance further inward than the outer surface of the insulating layer. Thus, the embodiment may improve the warpage characteristics of the circuit board by using the protruding surface of the outer surface of the protective member. That is, the protective member may be the uppermost insulating layer provided on the circuit board. Furthermore, the process of forming the protective member includes processes of exposing, developing, and curing. Stress is applied to the circuit board during the processes of exposing, developing, and curing the protective member, which may cause the side edges of the circuit board to bend upward or downward. In this case, the embodiment may position the outer surface of the protective member further inward than the outer surface of the insulating layer, thereby minimizing stress due to expansion and / or contraction caused by heat cycles. Therefore, the embodiment may improve the warpage characteristics of the circuit board and a semiconductor package including the same, and further improve product reliability. Furthermore, the embodiment may minimize stress acting on interfaces between components of the circuit board, including the interface between the insulating layer and the protective member and the interface between the pad and the protective member, thereby reliably protecting the circuit board and the semiconductor package from problems such as cracks.

[0035] The circuit board further includes an outer protective member provided outside the protective member. The outer protective member is provided along the periphery of the upper surface of the insulating layer, and the protective member is provided inside the outer protective member across a separation region. The separation region between the inner surface of the outer protective member and the outer surface of the protective member includes a first separation region having a first width along the horizontal direction and a second separation region having a second width different from the first width.

[0036] In this embodiment, the first and second isolation regions may include first and second isolation regions having different widths along the inner surface of the outer protective member and the outer surface of the protective member, thereby providing different circuit integration densities in the isolation regions. For example, the first width may be greater than the second width. Thus, a pad having a relatively high integration density may be provided in the protection member adjacent to the first isolation region having the first width, and a pad having a relatively low integration density may be provided in the protection member adjacent to the second isolation region having the second width. In this manner, the embodiment may provide a first isolation region including first and second isolation regions through pad layout design, thereby improving the electrical and / or mechanical reliability of the semiconductor package. Furthermore, the embodiment may reduce the signal transmission distance by controlling the circuit integration density, thereby minimizing signal transmission loss and improving signal transmission characteristics.

[0037] Additionally, a plurality of first pads are disposed in a separation region between the protective member and the outer protective member. At this time, the first pads do not contact the protective layer (protective member and outer protective member). Exemplarily, the plurality of first pads do not contact either the first or protective member. Through this, the embodiment can solve the problem of limitations on the size of solder resistor opens (SROs) that can be formed in the protective layer in the separation region. Therefore, the embodiment can reduce the width of the first pads disposed in the separation region. Furthermore, the embodiment can improve the circuit integration of the first pads in the separation region.

[0038] Furthermore, the embodiment has a structure in which no protective layer is disposed between the plurality of first pads in the separation region. This reduces the spacing between adjacent first pads. Furthermore, the embodiment may make the spacing between adjacent first pads smaller than the width of the first pads. This increases the density of the first pads in the separation region. Therefore, the embodiment may reduce the area of a circuit board and a semiconductor package including the circuit board.

[0039] Additionally, a post is disposed on the first pad. At this time, a post seed layer is not disposed between the post and the pad. Specifically, the post in the embodiment directly contacts the first pad. More specifically, the post is electrolytically plated using the seed layer used to electrolytically plate the first pad. Therefore, the embodiment has a structure in which a chemical copper plating layer is not disposed between the first pad and the post. Therefore, in the embodiment, the first pad and the post are electrolytically plated through the same seed layer, thereby improving the physical and electrical connectivity between the first pad and the post. This is because the contact between electrolytic copper is better than the contact between chemical copper plating and electrolytic plating. Furthermore, the embodiment can solve the signal transmission loss caused by the chemical copper plating layer, thereby improving signal transmission characteristics.

[0040] In addition, the embodiment can solve the problem of the lower end of the post being recessed due to etching the chemical copper plating layer. Through this, the embodiment can make the upper and lower surfaces of the post have substantially the same width. Therefore, the embodiment can solve the problem of dendrite due to electromigration caused by the difference in width between the upper and lower surfaces of the post, thereby further improving the electrical and / or physical properties of the post.

[0041] In addition, the embodiment may omit the steps of forming a chemical copper plating layer and etching the chemical copper plating layer to form posts, thereby simplifying the manufacturing process of the circuit board and improving the process yield. [Brief explanation of the drawings]

[0042] [Figure 1] FIG. 10 is a cross-sectional view showing a circuit board according to a comparative example. [Figure 2] FIG. 1 is a cross-sectional view showing a circuit board according to a first embodiment. [Figure 3] 3 is a plan view of the circuit board with the first protective layer and posts of FIG. 2 removed. FIG. [Figure 4] FIG. 3 is a plan view of the first protective layer of FIG. 2. [Figure 5] FIG. 3 is a plan view of the circuit board of FIG. 2. [Figure 6] 3 is a cross-sectional view showing a detailed layer structure of a first through electrode, a first circuit layer, and a post in FIG. 2. FIG. [Figure 7] FIG. 10 is a cross-sectional view showing a circuit board according to a second embodiment. [Figure 8] FIG. 8 is an enlarged view of a partial area of FIG. 7. [Figure 9] FIG. 1 is a diagram illustrating a semiconductor package according to a first embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a circuit board according to a third embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing a semiconductor package according to a second embodiment. [Figure 12] FIG. 10 is a cross-sectional view showing a circuit board according to a fourth embodiment. [Figure 13] FIG. 13 is a plan view of the circuit board of FIG. 12 as seen from above. [Figure 14] 13 is an enlarged view of a region of the circuit board of FIG. 12. FIG. [Figure 15] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 16]3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 17] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 18] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 19] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 20] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 21] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 22] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 23] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 24] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 25] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 26] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 27] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 28] 3A to 3C are diagrams for explaining a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. MODE FOR CARRYING OUT THE INVENTION

[0043] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical concept of the present invention is not limited to some of the described embodiments, and may be embodied in various different forms. One or more of the components of the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0044] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as meanings that would be commonly understood by a person of ordinary skill in the art to which the present invention belongs, and commonly used terms, such as dictionary-defined terms, may be interpreted in light of the contextual meaning of the relevant art.

[0045] Furthermore, terms used in the embodiments of the present invention are intended to describe the embodiments and are not intended to limit the present invention. In this specification, the singular form can also include the plural form unless otherwise specified in the phrase, and when it is stated as "A and (and) at least one (or more) of B and C," it can include one or more of all possible combinations of A, B, and C.

[0046] Furthermore, in describing components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. are used only to distinguish the component from other components, and the term does not limit the essence, order, or sequence of the corresponding component.

[0047] Furthermore, when a component is described as being "coupled," "coupled," or "connected" to another component, it includes not only the case where the component is directly coupled, coupled, or connected to the other component, but also the case where the component is "coupled," "coupled," or "connected" by another component between the component and the other component.

[0048] Furthermore, when a component is described as being formed or positioned "above or below" a component, "above" or "below" includes not only the case where the two components are in direct contact with each other, but also the case where one or more other components are formed or positioned between the two components.

[0049] Furthermore, when expressed as "above" or "below," it can mean not only the upward direction but also the downward direction based on one component.

[0050] -Comparative Example-

[0051] FIG. 1 is a cross-sectional view showing a circuit board according to a comparative example.

[0052] Referring to FIG. 1, the circuit board includes an insulating layer 10 .

[0053] A first circuit pattern 20 is disposed on the upper surface of the insulating layer 10, and a second circuit pattern 30 is disposed on the lower surface of the insulating layer 10. The first circuit pattern 20 includes pads. The circuit board of the comparative example also includes through electrodes that penetrate the insulating layer 10. A protective layer 50 having openings that vertically overlap the upper surfaces of the pads of the first circuit pattern 20 is disposed on the upper surface of the insulating layer 10.

[0054] Posts 70 are then disposed on the pads of the first circuit pattern 20. The posts 70 have a certain height or thickness and protrude above the pads of the first circuit pattern 20. Therefore, the posts 70 have a height or thickness of at least 80 μm or more. This makes it difficult to form the posts 70 by electroless plating.

[0055] As a result, a seed layer 60 for electrolytic plating of the posts 70 is disposed between the posts 70 and the pads of the first circuit pattern 20. The seed layer 60 is a chemical copper plating layer. The seed layer 60 is disposed on the upper surfaces of the pads of the first circuit pattern 20 and on the inner walls of the protective layer 50.

[0056] That is, the comparative example has a structure in which a seed layer 60 is disposed between the post 70 and the pad of the first circuit pattern 20. As a result, the comparative example requires an additional process of forming the seed layer 60, which complicates the manufacturing process or increases the manufacturing time.

[0057] Furthermore, the circuit board of the comparative example suffers from whitening of the protective layer 50 due to a solution used in a desmear process of the seed layer 60 formed by electroless plating. The circuit board of the comparative example also has a structure in which the seed layer 60 is disposed between the pad and the post 70, resulting in a porous microstructure of the bump layer. The porous structure has low metal density, which can lead to cracks occurring in the porous seed layer 60 due to external impact or other physical forces. The cracks can then destroy the post 70, resulting in a rapid decline in product reliability and durability. Furthermore, the comparative example also suffers from a problem in which the seed layer 60 is disposed between the pad and the post 70, resulting in increased loss during signal transmission and consequent degradation of signal transmission characteristics.

[0058] -Electronic Devices-

[0059] Prior to describing the embodiments, an electronic device to which the semiconductor package of the embodiments can be applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various chips may be mounted on the semiconductor package. The semiconductor package may mainly include various elements or chips. The elements or chips may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as a central processor (e.g., CPU), graphics processor (e.g., GPU), digital signal processor, encryption processor, microprocessor, and microcontroller; and logic chips such as an analog-to-digital converter and an application-specific integrated circuit (ASIC).

[0060] The elements or chips may also include active and passive elements.

[0061] The active element refers to an element that actively utilizes the nonlinear portion of signal characteristics. The passive element refers to an element that does not utilize nonlinear signal characteristics even if both linear and nonlinear signal characteristics exist. For example, the active element may include a transistor, an IC semiconductor element, etc., and the passive element may include a capacitor, a resistor, an inductor, etc. The passive element may increase the signal processing speed of the semiconductor chip that is the active element or perform a filtering function. The chip may also be a wireless communication chip that can be used for Wi-Fi or 5G communications.

[0062] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0063] In this case, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0064] -Circuit boards and semiconductor packages-

[0065] The circuit board and semiconductor package according to the embodiment will be described below.

[0066] 2 is a cross-sectional view showing the circuit board according to Example 1. The overall structure of the circuit board of Example 1 will be described below with reference to FIG.

[0067] 2, at least one chip may be mounted on the circuit board 100. The circuit board 100 of the embodiment may be mounted on a main board of an electronic device. The main board may refer to a motherboard of the electronic device. The circuit board 100 may be coupled with at least one chip and the motherboard to form a first package.

[0068] Furthermore, a first package including the circuit board 100 of the embodiment can be coupled to a second package. The second package can be a memory package. In one embodiment, the circuit board 100 can be coupled to a memory board of the second package. In another embodiment, the circuit board can be coupled to an interposer coupled to the memory board.

[0069] The circuit board 100 includes an insulating layer 110. The insulating layer 110 may include multiple layers. In one embodiment, the insulating layer 110 may have a three-layer structure, but is not limited to this. In this case, the insulating layer 110 may serve as a support substrate that supports the circuit board 100, and thus may be referred to as a "substrate."

[0070] In one embodiment, the circuit board 100 may be a core board. For example, the circuit board 100 may include a core layer. For example, the insulating layer 110 of the circuit board 100 of the embodiment may include the third insulating layer 113 corresponding to the core layer including reinforcing fibers.

[0071] The circuit board 100 may have a structure in which at least one insulating layer is stacked on each of the upper and lower sides of the third insulating layer 113. In one embodiment, the insulating layer stacked on the upper side of the third insulating layer 113 and the insulating layer stacked on the lower side of the third insulating layer 113 may have a symmetrical structure. In another embodiment, the insulating layer stacked on the upper side of the third insulating layer 113 and the insulating layer stacked on the lower side of the third insulating layer 113 may have an asymmetrical structure.

[0072] In the following description, the circuit board 100 of the embodiment is a core board, and therefore the third insulating layer 113 is a core layer. However, the embodiment is not limited thereto. For example, the circuit board 100 of another embodiment may be a coreless board that does not include a core layer.

[0073] Meanwhile, the structural features of the circuit board of the embodiment are the openings in the protective layer and the outermost circuit layer and posts disposed in the openings in the protective layer. The protective layer, circuit layer, and posts described below can be applied to a coreless substrate. Furthermore, at least one of the outermost circuit layers of the embodiment can have an ETS (Embedded Trace Substrate) structure embedded in the surface of the insulating layer 110.

[0074] The insulating layer (or substrate) 110 of the circuit board 100 of the embodiment may include a first insulating layer 111 , a second insulating layer 112 , and a third insulating layer 113 .

[0075] The third insulating layer 113 may refer to an inner insulating layer disposed inside a plurality of insulating layers. The third insulating layer 113 may be disposed between the first insulating layer 111 and the second insulating layer 112. The third insulating layer 113 may include prepreg. The third insulating layer 113 may include reinforcing fibers.

[0076] The first insulating layer 111 may be disposed on the third insulating layer 113. For example, the first insulating layer 111 may be disposed on an upper surface of the third insulating layer 113. The first insulating layer 111 may refer to the first outermost insulating layer in the insulating layer 110 of the circuit board 100. For example, the first insulating layer 111 may refer to the insulating layer disposed on the uppermost side of the insulating layer 110 of the circuit board 100. The first insulating layer 111 may provide a mounting area on which at least one chip is mounted or a first bonding area to which a first external substrate is bonded. The first external substrate may be a main board of an electronic device.

[0077] The second insulating layer 112 may be disposed below the third insulating layer 113. The second insulating layer 112 may refer to a second outermost insulating layer in the insulating layer 110 of the circuit board 100. For example, the second insulating layer 112 may refer to an insulating layer disposed at the bottom of the insulating layer 110 of the circuit board 100. The second insulating layer 112 may provide a mounting area on which at least one chip is mounted, or a second bonding area on which a second external substrate is bonded. The second external substrate may be a memory substrate or an interposer.

[0078] The first insulating layer 111 and the second insulating layer 112 may be rigid or flexible. For example, the first insulating layer 111 and the second insulating layer 112 may include glass or plastic. Specifically, the first insulating layer 111 and the second insulating layer 112 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. Alternatively, the first insulating layer 111 and the second insulating layer 112 may include reinforced or ductile plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). Alternatively, the first insulating layer 111 and the second insulating layer 112 may include sapphire.

[0079] In addition, the first insulating layer 111 and the second insulating layer 112 may include an optical isotropic film. For example, the first insulating layer 111 and the second insulating layer 112 may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optical isotropic polycarbonate (PC), an optical isotropic polymethyl methacrylate (PMMA), or the like.

[0080] The first insulating layer 111 and the second insulating layer 112 may be formed of a material containing an inorganic filler and an insulating resin. For example, the first insulating layer 111 and the second insulating layer 112 may have a structure in which an inorganic filler such as silica or alumina is dispersed in a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. For example, the first insulating layer 111 and the second insulating layer 112 may include Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), Photo Imagable Dielectric resin (PID), BT, etc.

[0081] Each of the first insulating layer 111 and the second insulating layer 112 may have a thickness in the range of 10 μm to 60 μm. Preferably, each of the first insulating layer 111 and the second insulating layer 112 may have a thickness in the range of 12 μm to 50 μm. More preferably, each of the first insulating layer 111 and the second insulating layer 112 may have a thickness in the range of 15 μm to 40 μm.

[0082] If the thickness of the first insulating layer 111 or the second insulating layer 112 is less than 10 μm, the circuit layers included in the circuit board 100 may not be stably protected. Furthermore, if the thickness of the first insulating layer 111 or the second insulating layer 112 exceeds 60 μm, the thickness of the circuit board 100 may increase, thereby increasing the thickness of the semiconductor package. Furthermore, if the thickness of the first insulating layer 111 or the second insulating layer 112 exceeds 60 μm, the thickness of the circuit layers and the through electrodes may increase accordingly. Furthermore, if the thickness of the circuit layers and the through electrodes increases, miniaturization may become difficult and the circuit integration density may decrease. Furthermore, the signal transmission distance may increase, resulting in increased signal transmission loss.

[0083] Meanwhile, the first insulating layer 111 may be divided into a plurality of regions in the direction.

[0084] The first insulating layer 111 may include a first region R1 adjacent to a periphery 111a of the first insulating layer 111. The periphery 111a of the first insulating layer 111 may refer to the periphery of the top surface of the first insulating layer 111. The periphery 111a of the first insulating layer 111 may refer to the border of the top surface of the first insulating layer 111 adjacent to the side surface of the first insulating layer 111. The first insulating layer 111 may include a second region R2 other than the first region R1. The periphery 111a of the first insulating layer 111 may refer to the outermost portion of the top surface of the first insulating layer 111 closest to the side surface of the first insulating layer 111. In this case, the first region R1 may be a region corresponding to a first opening of a protective layer, which will be described later, or may correspond to a separation region between an outer protective member and a protective member in another embodiment.

[0085] The second region R2 may refer to a region that is farther from the periphery 111a of the first insulating layer 111 than the first region R1.

[0086] In this case, the first region R1 of the first insulating layer 111 may be formed along the circumferential direction of the first insulating layer 111. The second region R2 of the first insulating layer 111 may refer to an inner region of the first region R1 formed along the circumferential direction. For example, the first region R1 of the first insulating layer 111 may refer to an outer region of the upper surface of the first insulating layer 111, and the second region R2 may refer to an inner region of the upper surface of the first insulating layer 111 excluding the first region R1.

[0087] Meanwhile, the first region R1 and the second region R2 are described as the first region R1 and the second region R2 of the first insulating layer 111, but are not limited thereto. For example, the first region R1 and the second region R2 may refer to the first region R1 and the second region R2 of the circuit board 100.

[0088] The exemplary circuit board 100 includes a circuit layer disposed on a surface of an insulating layer 110 .

[0089] For example, the circuit board 100 may include a first circuit layer 120 disposed on an upper surface of the first insulating layer 111. For example, the circuit board 100 may include a second circuit layer 130 disposed on a lower surface of the second insulating layer 112. The circuit board 100 may also include a third circuit layer 140 disposed between the lower surface of the first insulating layer 111 and the upper surface of the third insulating layer 113. For example, the circuit board 100 may include a fourth circuit layer 150 disposed between the upper surface of the second insulating layer 112 and the lower surface of the third insulating layer 113.

[0090] The first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 can be formed using conventional circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed description thereof will be omitted here.

[0091] The first circuit layer 120 may refer to a circuit layer disposed on the first outermost layer of the circuit board 100. The second circuit layer 130 may refer to a circuit layer disposed on the second outermost layer of the circuit board 100.

[0092] The first circuit layer 120 may include a plurality of pads disposed on a first insulating layer 111 .

[0093] The first circuit layer 120 may include a first pad 121 disposed on the first region R1 of the first insulating layer 111. The first circuit layer 120 may also include a second pad 122 disposed on the second region R2 of the first insulating layer 111. The second pad 122 may be spaced farther from the periphery 111a of the first insulating layer 111 than the first pad 121.

[0094] The first pad 121 may have a first function, and the second pad 122 may have a second function different from the first function.

[0095] The first function of the first pad 121 may mean a function for connecting a first external substrate to the circuit board 100. Also, the second function of the second pad 122 may mean a function for mounting a chip on the circuit board 100.

[0096] Meanwhile, the first circuit layer 120 may further include traces. The traces of the first circuit layer 120 may be disposed on the first region R1 and the second region R2 of the first insulating layer 111. The traces of the first circuit layer 120 may connect between a plurality of first pads, a plurality of second pads, or between a first pad 121 and a second pad 122.

[0097] A planar area of the first pad 121 may be different from a planar area of the second pad 122. For example, a first horizontal diameter of the first pad 121 may be different from a first horizontal diameter of the second pad 122. For example, a width of the first pad 121 may be different from a width of the second pad 122.

[0098] That is, the first pad 121 is a pad for coupling to a first external substrate, and the second pad 122 is a pad for mounting a chip. Furthermore, the number of chip terminals is increasing, or the width or pitch of the chip terminals is becoming finer, due to factors such as 5G, Internet of Things (IOT), improved image quality, and increased communication speed. In response to this, the pads provided on the first external substrate may have a width or spacing greater than the chip terminals. Therefore, the planar area, diameter, or width in a first horizontal direction of the first pad 121 may be greater than the planar area, diameter, or width in a first horizontal direction of the second pad 122.

[0099] The first pad 121 may be disposed in the first region R1 and may not contact the protective layer of the circuit board 100. For example, the side and top surfaces of the first pad 121 may not contact the protective layer, as will be described in more detail below.

[0100] In contrast, the second pad 122 may be disposed in the second region R2 and may be in contact with the protective layer of the circuit board 100. For example, at least a portion of the side and top surfaces of the second pad 122 may be in contact with the protective layer.

[0101] Meanwhile, the second circuit layer 130 may also include a plurality of pads. The pads of the second circuit layer 130 of the circuit board 100 of the first embodiment may include, but are not limited to, pads for mounting chips.

[0102] Meanwhile, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be formed of copper (Cu), which is relatively inexpensive.

[0103] Meanwhile, the first circuit layer 120 and the second circuit layer 130 may have a thickness in the range of 5 μm to 30 μm. For example, the first circuit layer 120 and the second circuit layer 130 may have a thickness in the range of 6 μm to 25 μm. The first circuit layer 120 and the second circuit layer 130 may have a thickness in the range of 7 μm to 20 μm. If the thickness of the first circuit layer 120 and the second circuit layer 130 is less than 5 μm, resistance and signal transmission loss may increase. If the thickness of the first circuit layer 120 and the second circuit layer 130 is more than 30 μm, miniaturization may be difficult, which may result in a decrease in circuit integration density.

[0104] The circuit board 100 of the embodiment may include posts 190 .

[0105] The post 190 may be disposed on the first circuit layer 120. Preferably, the post 190 may be disposed on the first pad 121 of the first circuit layer 120.

[0106] The post 190 may have a diameter or width smaller than the diameter or width of the first pad 121. As a result, a portion of the first pad 121 may vertically overlap the post 190, and the remaining portion of the first pad 121 may not vertically overlap the post 190.

[0107] The posts 190 may not be in contact with the first protective layer 170 described below. For example, the posts 190 may be disposed within the first openings 171 of the first protective layer 170. Correspondingly, the first pads 121 of the first circuit layer 120 may also be disposed within the first openings 171 of the first protective layer 170. In this case, the first protective layer 170 in the first embodiment may have a structure including only a "protective member" in other embodiments described below. As a result, the first openings 170 of the first protective layer 170 may correspond to a separation region between an "outer protective member" described below and the protective member.

[0108] The post 190 may be disposed with a certain height on the first pad 121. The height may refer to the vertical distance from the top surface to the bottom surface of the post 190. The height of the post 190 may be greater than 100 μm, greater than 120 μm, greater than 140 μm, greater than 160 μm, or greater than 200 μm.

[0109] For example, the height of the post 190 can be in the range of 100 μm to 220 μm. Preferably, the height of the post 190 can be in the range of 110 μm to 215 μm. More preferably, the height of the post 190 can be in the range of 115 μm to 210 μm.

[0110] If the height of the post 190 is less than 100 μm, the first external substrate may not be stably coupled onto the post 190. If the height of the post 190 is less than 100 μm, the distance between the first external substrate and the circuit board 100 may be reduced, which may result in signal interference between them and degraded signal transmission characteristics. If the height of the post 190 exceeds 220 μm, the rigidity of the post 190 may be reduced. If the rigidity of the post 190 is reduced, physical reliability issues such as collapse may occur during the coupling process with the first external substrate. If the height of the post 190 exceeds 220 μm, the thickness of the circuit board 100 and the thickness of the semiconductor package may increase.

[0111] The circuit board 100 of the embodiment may include a through electrode. The through electrode may penetrate the insulating layer 110.

[0112] For example, the circuit board 100 may include a first through electrode 161 that penetrates the first insulating layer 111. The circuit board 100 may also include a second through electrode 162 that penetrates the second insulating layer 112. The circuit board 100 may also include a third through electrode 163 that penetrates the third insulating layer 113.

[0113] The first through-hole electrode 161, the second through-hole electrode 162, and the third through-hole electrode 163 may be disposed in through-holes that penetrate at least one insulating layer. For example, the first through-hole electrode 161, the second through-hole electrode 162, and the third through-hole electrode 163 may be formed by filling the through-holes with a conductive material.

[0114] The through-holes may be formed by any one of mechanical, laser, and chemical processing methods. The through-holes may be formed by milling, drilling, routing, etc. Also, the through-holes may be formed using UV or CO2 laser methods. Also, the through-holes may be formed using chemical processing methods using chemicals including silane, ketones, etc.

[0115] Meanwhile, the first through electrodes 161 may be formed in plurality in the first insulating layer 111 and spaced apart from each other in the horizontal direction.

[0116] In this case, the first through-electrodes 161 may overlap the first circuit layer 120 in the vertical direction.

[0117] The first through-hole electrode 161 may vertically overlap at least one of the first pad 121 and the second pad 122. For example, the first through-hole electrode 161 may include a first electrode part vertically overlapping the first pad 121 and a second electrode part vertically overlapping the second pad 122. The first and second electrode parts of the first through-hole electrode 161 may have different widths. In this case, each of the first and second electrode parts of the first through-hole electrode 161 may have a slope in which the width decreases from the upper surface to the lower surface. The upper surface of the first electrode part of the first through-hole electrode 161 may have a width greater than that of the upper surface of the second electrode part of the first through-hole electrode 161. That is, the first electrode part of the first through-hole electrode 161 is connected to the first pad 121, which has a width greater than that of the second pad 122 connected to the second electrode part of the first through-hole electrode 161. Therefore, the first electrode part of the first through electrode 161 may have a width greater than that of the second electrode part.

[0118] As a result, the embodiment may improve circuit integration by varying the widths of a plurality of electrode parts spaced apart horizontally within the same layer. Specifically, the second electrode part of the first through electrode 161 is connected to the second pad 122, which is connected to a chip. The second electrode part has a relatively small width, thereby reducing the width and pitch of the second pad 122. As a result, the embodiment may improve circuit integration in the second region R2 disposed on the second pad 122. Furthermore, in the embodiment, the first electrode part has a relatively large width. As a result, the embodiment may improve the transfer characteristics of heat generated in the circuit board 100 through the first electrode part. As a result, the embodiment may improve the heat dissipation characteristics of the circuit board 100 and a semiconductor package including the circuit board 100.

[0119] On the other hand, the circuit board 100 of the embodiment includes a protective layer.

[0120] Specifically, a first protective layer 170 is disposed on the upper surface of the first insulating layer 111. The first protective layer 170 includes an opening. The opening may be defined as a "through hole" penetrating the upper and lower surfaces of the first protective layer 170. The first opening 171 may also be defined as an "undisposed region" or "open region" on the upper surface of the first insulating layer 111 and / or the upper surface of the first circuit layer 120 where the first protective layer 170 is not disposed. The opening of the first protective layer 170 may also be defined as a separation region. In this case, the first protective layer 170 of the first embodiment has a structure including only the protective member of the protective layer of the other embodiments, and therefore, the separation region may refer to a separation region between the outside of the insulating layer and the outside of the first protective layer 170. Exemplarily, the first protective layer 170 of the first embodiment may be referred to as "the protective member."

[0121] The upper surface of the first insulating layer 111 and / or the upper surface of the first circuit layer 120 in the region vertically overlapping with the opening of the first protective layer 170 may be exposed to the upper side of the circuit board 100 .

[0122] The first protective layer 170 may include a first opening 171 and a second opening 172 .

[0123] The first opening 171 of the first protective layer 170 may be provided on the first region R1. The second opening 172 of the first protective layer 170 may be provided on the second region R2 of the first protective layer 170. The number of the first openings 171 and the second openings 172 may be different. There may be only one first opening 171. For example, the first protective layer 170 may include one first opening 171 that vertically overlaps with a plurality of first pads 121. The first opening 171 may also vertically overlap with a post 190 disposed on the first pad 121. Meanwhile, there may be a plurality of second openings 172. For example, the first protective layer 170 may include a plurality of second openings 172 that vertically overlap with each of a plurality of second pads 122.

[0124] In this case, the first opening 171 of the first protective layer 170 may entirely vertically overlap the first region R1. That is, the first opening 171 of the first protective layer 170 may entirely open the top surface of the first insulating layer 111 and the top and side surfaces of the first circuit layer 120 in the first region R1. Thus, the first opening 171 may essentially represent an empty region on the first insulating layer 111 and the first circuit layer 120 where the first protective layer 170 is not disposed. The first opening 171 may not be connected to the plurality of second openings 172.

[0125] The second opening 172 of the first protective layer 170 may partially overlap vertically with the second region R2. That is, the second opening 172 of the first protective layer 170 may partially overlap vertically with the top surface of the first insulating layer 111 and the top surface of the first circuit layer 120 in the second region R2.

[0126] For example, the first region R1 may include a first sub-region that vertically overlaps the first pads. The first protective layer 170 does not vertically overlap the first sub-region. For example, a first opening 171 of the first protective layer 170 vertically overlaps the first sub-region. The first region R1 may also include a second sub-region that corresponds to a region between adjacent first pads. The first protective layer 170 does not vertically overlap the second sub-region. In other words, the first opening 171 of the first protective layer 170 vertically overlaps the second sub-region.

[0127] Therefore, the first opening 171 of the first protective layer 170 of the embodiment may entirely overlap the first region R1 vertically, and the second opening 172 may partially overlap the second region R2 vertically.

[0128] Meanwhile, the circuit board 100 may further include a second protective layer 180 disposed on the lower surface of the second insulating layer 112 .

[0129] The second protective layer 180 may include at least one opening. For example, the second protective layer 180 may include an opening that vertically overlaps at least a portion of the second circuit layer 130. The opening of the second protective layer 180 may fully or partially vertically overlap a pad of the second circuit layer 130 that is connected to a chip.

[0130] The first protective layer 170 and the second protective layer 180 may include an insulating material and may include various materials that can be cured by heating after being applied to protect the surfaces of the insulating layer and the circuit layer.

[0131] The first and second protective layers 170 and 180 may be solder resist layers containing an organic polymer material. For example, the first and second protective layers 170 and 180 may include an epoxy acrylate resin. In particular, the first and second protective layers 170 and 180 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, embodiments are not limited thereto, and the first and second protective layers 170 and 180 may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0132] The first protective layer 170 and the second protective layer 180 may have a thickness of 1 μm to 20 μm. The first protective layer 170 and the second protective layer 180 may have a thickness of 1 μm to 15 μm. For example, the first protective layer 170 and the second protective layer 180 may have a thickness of 5 μm to 20 μm. If the thickness of the first protective layer 170 and the second protective layer 180 exceeds 20 μm, the overall thickness of the circuit board and the semiconductor package may increase.

[0133] The following will specifically describe the configuration of a portion of the circuit board 100 shown in FIG.

[0134] 3 is a plan view of the circuit board with the first protective layer and post of FIG. 2 removed, FIG. 4 is a plan view of the first protective layer of FIG. 2, FIG. 5 is a plan view of the circuit board of FIG. 2, and FIG. 6 is a cross-sectional view showing the detailed layer structure of the first through electrode, first circuit layer, and post of FIG. 2.

[0135] 3, the first insulating layer 111 may include a first region R1 and a second region R2. The first region R1 of the first insulating layer 111 may be a region adjacent to a periphery 111a of the first insulating layer 111. For example, the first region R1 of the first insulating layer 111 may be an outer region of the top surface of the first insulating layer 111.

[0136] The first region R1 may be provided in the circumferential direction of the first insulating layer 111 while adjacent to the periphery 111a of the first insulating layer 111. For example, the first region R1 may be provided in the circumferential direction of the first insulating layer 111 while adjacent to the periphery 111a of the first insulating layer 111 and have a closed loop shape corresponding to the periphery 111a. However, embodiments are not limited thereto. The first region R1 may also have an open loop shape including only a portion of the circumferential region in the circumferential direction.

[0137] A plurality of first pads 121 may be arranged on the first region R1 of the first insulating layer 111. The plurality of first pads 121 may be arranged along the circumferential direction of the first insulating layer 111 in the first region R1 of the first insulating layer 111.

[0138] In addition, a plurality of second pads 122 may be disposed on the second region R2 of the first insulating layer 111. The second pads 122 may be selectively disposed in the second region R2 of the first insulating layer 111 while being spaced apart from the first pads 121 in the horizontal direction.

[0139] 3, traces of the first circuit layer 120 may be disposed on the second region R2 of the first insulating layer 111. The traces of the first circuit layer 120 may electrically connect between a plurality of second pads disposed on the second region R2.

[0140] Furthermore, traces of the first circuit layer 120 may not be disposed on the first region R1 of the first insulating layer 111. Specifically, only a plurality of first pads 121 may be disposed on the first region R1 of the first insulating layer 111. The first pads 121 may be electrically connected to other circuit layers via first through electrodes 161. However, embodiments are not limited thereto. For example, traces of the first circuit layer 120 may also be disposed in the first region R1.

[0141] The first pad 121 may have a first width W1, and the second pad 122 may have a second width W2, where the first width W1 may be different from the second width W2.

[0142] Specifically, the first width W1 may correspond to a pad provided on a first external board (preferably a main board of an electronic device) coupled to the circuit board 100. The second width W2 may correspond to the width of a terminal provided on a chip.

[0143] In this case, the pads provided on the first external substrate have a width relatively larger than the width of the terminals of the chip, so that the first width W1 of the first pads 121 may be larger than the second width W2 of the second pads 122.

[0144] The first width W1 of the first pad 121 may be 25 μm to 85 μm. Preferably, the first width W1 of the first pad 121 may be 30 μm to 80 μm. More preferably, the first width W1 of the first pad 121 may be 32 μm to 75 μm.

[0145] If the first width W1 of the first pad 121 is less than 25 μm, the bonding strength with the first external substrate may be reduced. If the first width W1 of the first pad 121 is less than 25 μm, the width W3 of the post 190 disposed on the first pad 121 may be reduced accordingly. If the width W3 of the post 190 is reduced, the height H1 of the post 190 that can be formed may be reduced accordingly. Furthermore, if the first width W1 of the first pad 121 is less than 25 μm, the heat dissipation characteristics of the circuit board 100 may be reduced.

[0146] If the first width W1 of the first pads 121 exceeds 85 μm, the number of first pads 121 that can be arranged on the first region R1 may decrease. For example, if the first width W1 of the first pads 121 exceeds 85 μm, the circuit integration density of the first region R1 may decrease. Therefore, the area of the circuit board 100 may increase in order to arrange all of the first pads connected to the first external board in the first region R1.

[0147] Meanwhile, the first pad 121 may have a circular planar shape. When the first pad 121 has a circular planar shape, the first width W1 may refer to the diameter of the first pad 121.

[0148] In another embodiment, the planar shape of the first pad 121 may be square or rectangular. When the planar shape of the first pad 121 is square or rectangular, the first width W1 of the first pad 121 may refer to the smaller of the width in the width direction and the width in the longitudinal direction of the first pad 121.

[0149] In another embodiment, the planar shape of the first pad 121 may be elliptical. When the planar shape of the first pad 121 is elliptical, the first width W1 of the first pad 121 may refer to the diameter of the ellipse in the minor axis direction.

[0150] Meanwhile, the first pads in the first region R1 may be spaced apart by a first distance D1, which may refer to the minimum distance between two adjacent first pads among the first pads arranged in the first region R1.

[0151] In an embodiment, the first distance D1 may have a range corresponding to the first width W1 of one first pad 121.

[0152] In another embodiment, the first distance D1 may be smaller than the first width W1 of one first pad 121.

[0153] For example, the first distance D1 between the plurality of first pads may be in the range of 20% to 90% of the first width W1 of the first pad 121. Preferably, the first distance D1 between the plurality of first pads may be in the range of 23% to 88% of the first width W1 of the first pad 121. More preferably, the first distance D1 between the plurality of first pads may be in the range of 25% to 85% of the first width W1 of the first pad 121.

[0154] If the first distance D1 between the plurality of first pads is less than 20% of the first width W1 of the first pads 121, a short circuit connecting the plurality of first pads 121 may occur depending on the process capability in the manufacturing process of the circuit board 100, thereby reducing the electrical reliability of the circuit board 100. Furthermore, if the first distance D1 between the plurality of first pads is less than 20% of the first width W1 of the first pads 121, interference may occur between signals transmitted through the plurality of first pads 121. If such interference occurs, signal transmission loss may increase, thereby reducing signal transmission characteristics.

[0155] On the other hand, if the first distance D1 between the plurality of first pads exceeds 90% of the first width W1 of the first pad 121, the effect of improving the circuit integration density in the first region R1 may be insufficient compared to the comparative example.

[0156] In this case, in the comparative example, the spacing between the first pads exceeded 95% of the first width of the first pads. This was because the spacing between the first pads was included in the opening size of the protective layer, which is one of the factors determining the spacing between the first pads. That is, the first protective layer in the comparative example included a plurality of first openings that partially vertically overlapped the first region. Specifically, the number of first openings in the first protective layer in the comparative example corresponded to the number of the first pads. The plurality of first openings in the first protective layer in the comparative example had a structure that vertically overlapped the plurality of first pads in a 1:1 ratio. Therefore, in the comparative example, the first width of the plurality of first pads and the first spacing between the plurality of first pads were determined taking into consideration process capability and process error in the process of forming the plurality of first openings in the first protective layer.

[0157] In contrast, the first protective layer 170 of the circuit board of the embodiment includes a first opening 171 that completely opens the first region R1. Although the configuration that completely opens the first region R1 is referred to as the first opening 171 of the first protective layer 170, the first protective layer 170 may actually be disposed only in the second region R2 excluding the first region R1. That is, the first protective layer 170 may not be disposed in the first region R1 but may be selectively disposed only in the second region R2.

[0158] Therefore, the embodiment does not need to consider process capability or process error in the process of forming the plurality of first openings in the first protective layer 170. As a result, the embodiment can reduce the first width W1 of the first pad 121 and the first distance D1 between the plurality of first pads compared to the comparative example.

[0159] However, in general, the first width W1 of the first pad 121 is determined based on the width of a pad provided on a main board corresponding to the first external substrate and the width W3 of the corresponding post 190. Therefore, in the embodiment, the first width W1 of the first pad 121 can be reduced, but instead of reducing the first width W1 of the first pad 121, the first interval D1 between the plurality of first pads is reduced. As a result, the embodiment can improve the circuit integration degree while maintaining the width of the existing first pad 121.

[0160] Meanwhile, the second width W2 of the second pad 122 may be smaller than the first width W1 of the first pad 121.

[0161] The second width W2 of the second pad 122 may be 15 μm to 50 μm. Preferably, the second width W2 of the second pad 122 may be 18 μm to 45 μm. More preferably, the second width W2 of the second pad 122 may be 20 μm to 40 μm.

[0162] If the second width W2 of the second pad 122 is less than 15 μm, the resistance of the signal transmitted through the second pad 122 increases, thereby increasing signal transmission loss. If the second width W2 of the second pad 122 exceeds 50 μm, the circuit integration density may decrease. If the circuit integration density decreases, it may not be possible to arrange all the second pads connected to the chip terminals in a limited space. Furthermore, if the second width W2 of the second pad 122 exceeds 50 μm, the spacing between the second pads connected to the chip terminals may also increase. In this case, the second pad includes at least two second pads connected to each other. If the spacing increases, the signal transmission distance between the at least two second pads increases, thereby increasing signal transmission loss. This may result in degraded signal transmission characteristics.

[0163] 4, the first protective layer 170 is partially disposed on the first insulating layer 111. Specifically, the first protective layer 170 is disposed on the second region R2 of the first insulating layer 111. That is, the first protective layer 170 is not disposed on the first region R1 of the first insulating layer 111.

[0164] In other words, the first protective layer 170 may include a first opening 171 that entirely opens the first region R1 and may be selectively disposed only in the second region R2. As such, the first opening 171 may be referred to as an open region or an undisposed region of the first protective layer 170. Also, the first protective layer 170 is not disposed in regions between the plurality of first pads. That is, the first protective layer 170 entirely opens the first region R1. As a result, a structure in which the first protective layer 170 is not disposed between the plurality of first pads may be achieved.

[0165] Additionally, the first protective layer 170 may include a second opening 172 that vertically overlaps the second pad 122 in the second region R2.

[0166] In this case, the planar area of the first opening 171 of the first protective layer 170 may be different from the planar area of the second opening 172 of the first protective layer 170. Preferably, the planar area of the first opening 171 of the first protective layer 170 may be larger than the planar area of the second opening 172. In this case, a plurality of second openings 172 may be provided in the first protective layer 170 that vertically overlaps the second region R2. In this case, being provided with a plurality of second openings may mean that the plurality of openings are not connected to each other but are spaced apart in the horizontal direction.

[0167] The first opening 171 is formed as a single opening. Here, the fact that the first opening 171 is formed as a single opening may mean that the first protective layer 170 is not present in an area that vertically overlaps with the first region R1.

[0168] As a result, the outer surface of the first protective layer 170 can be located more inward than the periphery 111a of the first insulating layer 111. Specifically, the outer surface of the first protective layer 170 can be located more inward than the outer surface of the first insulating layer 111 by the width of the first region R1.

[0169] In the embodiment, the outer surface of the first protective layer 170 is located more inward than the outer surface of the first insulating layer 111, thereby improving the warpage characteristics of the circuit board. That is, the first protective layer 170 is the outermost insulating layer of the circuit board 100. The process of forming the first protective layer 170 includes the processes of exposing, developing, and curing the first protective layer 170. During the processes of exposing, developing, and curing the first protective layer 170, stress is applied to the circuit board, which may cause the side edges of the circuit board to warp upward or downward. In this case, in the embodiment, the outer surface of the first protective layer 170 is located more inward than the outer surface of the first insulating layer 111, thereby minimizing the applied stress. As a result, the embodiment can improve the warpage characteristics of the circuit board and a semiconductor package including the same, and further improve product reliability.

[0170] The outer surface of the first protective layer 170 may have a horizontal step along its periphery. Specifically, the outer surface of the first protective layer 170 may include a first portion 170a. The outer surface of the first protective layer 170 may include a second portion 170b corresponding to a concave surface recessed inward from the first portion 170a. The outer surface of the first protective layer 170 may also include a third portion 170c protruding or projecting outward from the first portion 170a. Thus, a separation region between the outer surface of the substrate and the outer surface of the first protective layer 170 may include a first separation region having a first width and a second separation region having a second width different from the first width. The first width may be greater than the second width, and the first separation region may refer to the horizontal width between the outer surface of the substrate and the second portion 170b corresponding to the concave surface of the first protective layer 170. The second separation region may also refer to the horizontal width between the outside of the substrate and the third portion 170c of the first protective layer 170 corresponding to the convex surface.

[0171] In this case, the first portion 170 a, the second portion 170 b, and the third portion 170 c of the first protective layer 170 may be designed based on the position of a first pad located adjacent to the first protective layer 170 .

[0172] For example, the second portion 170b of the first protective layer 170 may overlap in the length direction or width direction with the first pads adjacent to the first protective layer 170. The third portion 170c of the first protective layer 170 may overlap in the length direction or width direction with the regions between the first pads arranged adjacent to the first protective layer 170.

[0173] As described above, in the embodiment, the outer surface of the protective layer 170 includes not only the first portion 170a but also the second portion 170b and the third portion 170c, thereby improving the design freedom for the arrangement of the first pads in the first region R1. As a result, the embodiment can further improve the integration of the first pads in the first region R1.

[0174] That is, the posts 190 may be provided along the periphery of the outer surface of the first protective layer 170. In this case, the first protective layer 170 includes an upper surface, a lower surface, and a side surface disposed between the upper surface and the lower surface. In this case, the lower surface of the first protective layer 170 may face the upper surface of an insulating layer (e.g., the uppermost insulating layer). In addition, the plurality of posts 190 may face the side surfaces of the first protective layer 170. In addition, the side surfaces of the first protective layer 170 may include protrusions protruding between the plurality of posts.

[0175] For example, the side surfaces of the first protective layer 170 may include a first side surface extending in a first direction, a second side surface extending in the first direction and spaced apart from the first side surface, a third side surface extending in a second direction perpendicular to the first direction, and a fourth side surface extending in the second direction and spaced apart from the third side surface. In this case, protruding surfaces of the first protective layer 170 may be provided on the first side surface and the third side surface.

[0176] As a result, the third side of the first protective layer 170 may have a first surface having a first separation distance from the plurality of posts along the first direction, a second surface having a second separation distance smaller than the first separation distance, and a third surface having a third separation distance larger than the first separation distance, because the third side of the first protective layer 170 may include all of the first portion 170a, the second portion 170b, and the third portion 170c.

[0177] Furthermore, the distance between the fourth side surface of the first protective layer 170 and the plurality of posts along the first direction may be uniform, which may be a design that takes into consideration the direction in which the circuit board warps, and at least one side surface of the first protective layer 170 may be free from protrusions and recesses.

[0178] Additionally, the second side of the first protective layer 170 may include a concave surface recessed toward the first side of the first protective layer 170 .

[0179] 5, the post 190 is disposed on the first pad 121 located on the first region R1. The post 190 may have a third width W3 that is smaller than the first width W1 of the first pad 121.

[0180] Specifically, the post 190 may be disposed on the first pad 121 that is entirely opened via the first opening 171 of the first protective layer 170. Accordingly, in this embodiment, the post 190 may be formed using a separate dry film as a mask, rather than using the opening of the first protective layer 170 as a mask. In this case, the dry film may be capable of forming a smaller opening than the solder resist and may have a greater thickness. Accordingly, in this embodiment, the post 190 may have a smaller width than the first pad 121.

[0181] In addition, in the embodiment, the post 190 may be formed by directly using the seed layer used for electroplating the first pad 121. Thus, in the embodiment, there is no seed layer for electroplating the post 190 between the first pad 121 and the post 190. In the embodiment, the post 190 may be formed by removing a separate seed layer for electroplating the post 190, taking into consideration only the opening size of the dry film. Thus, in the embodiment, the third width W3 of the post 190 may be smaller than the first width W1 of the first pad 121.

[0182] The third width W3 of the post 190 may be in the range of 60% to 95% of the first width W1 of the first pad 121. Preferably, the third width W3 of the post 190 may be in the range of 65% to 92% of the first width W1 of the first pad 121. The third width W3 of the post 190 may be in the range of 70% to 90% of the first width W1 of the first pad 121.

[0183] If the third width W3 of the post 190 is less than 60% of the first width W1 of the first pad 121, the heat dissipation characteristics of the circuit board may be reduced. If the third width W3 of the post 190 is less than 60% of the first width W1 of the first pad 121, the first external board may not be stably disposed on the circuit board. If the third width W3 of the post 190 is less than 60% of the first width W1 of the first pad 121, the height H1 of the post 190 may not be formed to a certain level or more.

[0184] If the third width W3 of the post 190 is greater than 95% of the first width W1 of the first pad 121, the post 190 may have a width greater than the first pad 121 due to a process error in forming the post 190. In this case, a short circuit problem may occur when two adjacent posts 190 are connected to each other. That is, a problem with electrical reliability may occur due to a small distance between two adjacent posts 190.

[0185] 6, the post 190 is disposed on the first pad 121 with a width smaller than that of the first pad 121. The post 190 is disposed on the first pad 121 with a predetermined height H1.

[0186] The height H1 may refer to the vertical distance from the top surface to the bottom surface of the post 190. The height H1 of the post 190 may be greater than 100 μm, greater than 120 μm, greater than 140 μm, greater than 160 μm, or greater than 200 μm. For example, the height H1 of the post 190 may be in the range of 100 μm to 220 μm. Preferably, the height H1 of the post 190 may be in the range of 110 μm to 215 μm. More preferably, the height H1 of the post 190 may be in the range of 115 μm to 210 μm.

[0187] If the height H1 of the post 190 is less than 100 μm, the first external substrate may not be stably bonded onto the post 190. If the height H1 of the post 190 is less than 100 μm, the distance between the first external substrate and the circuit board 100 is reduced, which may result in signal interference between them and degraded signal transmission characteristics. If the height H1 of the post 190 exceeds 220 μm, the rigidity of the post 190 may decrease. If the rigidity of the post 190 decreases, physical reliability issues such as collapse may occur during the bonding process with the first external substrate. If the height H1 of the post 190 exceeds 220 μm, the thickness of the circuit board 100 and the semiconductor package may increase.

[0188] The post 190 is made of one metal layer. Specifically, the post 190 may include only an electrolytic plating layer without including an electroless plating layer such as a chemical copper plating layer.

[0189] The first circuit layer 120 is composed of at least two metal layers. The first pad 121 and the second pad 122 of the first circuit layer 120 may have the same layer structure. Furthermore, the first through electrode 161 may include two metal layers corresponding to the first circuit layer 120.

[0190] That is, the first pad 121 and the second pad 122 of the first circuit layer 120 may include a first metal layer 120-1 and a second metal layer 120-2, respectively.

[0191] Furthermore, the first through-electrode 161 may include a third metal layer 161-1 corresponding to the first metal layer 120-1 of the first circuit layer 120 and a fourth metal layer 161-2 corresponding to the second metal layer 120-2.

[0192] In this case, the first metal layer 120-1 and the third metal layer 161-1 may be substantially the same layer, which may be separated by their positions, and the second metal layer 120-2 and the fourth metal layer 161-2 may be substantially the same metal layer, which may be separated by their positions.

[0193] The first metal layer 120-1 may be substantially two layers, including a metal layer identical to the third metal layer 161-1 on a copper foil (Cu foil).

[0194] Also, the first metal layer 120-1 may be a layer of copper foil (Cu foil).

[0195] Therefore, only the first metal layer 120-1 and the second metal layer 120-2 will be described below.

[0196] The first metal layer 120-1 of the first circuit layer 120 may be a seed layer. The first metal layer 120-1 of the first circuit layer 120 may be a chemical copper plating layer. The first metal layer 120-1 of the first circuit layer 120 may be a copper foil layer. The first metal layer 120-1 of the first circuit layer 120 may include both a copper foil layer and a chemical copper plating layer.

[0197] The thickness of the first metal layer 120-1 of the first circuit layer 120 may be in the range of 1.0 μm to 3.0 μm. Preferably, the thickness of the first metal layer 120-1 of the first circuit layer 120 may be in the range of 1.2 μm to 2.8 μm. More preferably, the thickness of the first metal layer 120-1 of the first circuit layer 120 may be in the range of 1.5 μm to 2.5 μm.

[0198] If the thickness of the first metal layer 120-1 of the first circuit layer 120 is less than 1.0 μm, the first metal layer 120-1 of the first circuit layer 120 may not function as a seed layer. If the thickness of the first metal layer 120-1 of the first circuit layer 120 is less than 1.0 μm, it may be difficult to form the first metal layer 120-1 with a uniform thickness on the upper surface of the first insulating layer 110.

[0199] If the thickness of the first metal layer 120-1 of the first circuit layer 120 exceeds 3.0 μm, the process time for forming the first metal layer 120-1 of the first circuit layer 120 increases, which may reduce the yield. Also, if the thickness of the first metal layer 120-1 of the first circuit layer 120 exceeds 3.0 μm, the etching time for the first metal layer 120-1 in the process of forming the first circuit layer 120 may increase. Furthermore, if the thickness of the first metal layer 120-1 of the first circuit layer 120 exceeds 3.0 μm, deformation of the second metal layer 120-2 of the first circuit layer 120 may occur when etching the first metal layer 120-1 of the first circuit layer 120. Here, deformation of the second metal layer 120-2 of the first circuit pattern layer 120 may mean that the side portions of the second metal layer 120-2 are also etched when etching the first metal layer 120-1, thereby increasing the difference between the width of the top surface and the width of the bottom surface of the second metal layer 120-2. Furthermore, if the thickness of the first metal layer 120-1 of the first circuit layer 120 exceeds 3.0 μm, the etching amount of the first metal layer 120-1 increases, which may increase the depth of recesses (e.g., undercuts) formed in the side portions of the first metal layer 120-1 and the side portions of the second metal layer 120-2. For example, if the etching depth of the first metal layer 120-1 increases, or if the difference between the widths of the first metal layer 120-1 and the second metal layer 120-2 increases, signal transmission loss may increase and electrical characteristics may deteriorate. Furthermore, the difference between the widths of the first metal layer 120-1 and the second metal layer 120-2 may also increase. If the difference between the widths of the first metal layer 120-1 and the second metal layer 120-2 increases, signal transmission loss may increase and electrical characteristics may deteriorate. Furthermore, if the difference between the widths of the first metal layer 120-1 and the second metal layer 120-2 increases, dendrites may form due to electromigration, which may degrade the electrical and / or physical characteristics of the first circuit pattern layer 120.

[0200] The second metal layer 120-2 of the first circuit layer 120 may be an electroplated layer formed by electroplating using the first metal layer 120-1 as a seed layer. The second metal layer 120-2 of the first circuit layer 120 may be formed to a certain thickness on the first metal layer 120-1. The second metal layer 120-2 of the first circuit layer 120 may include, but is not limited to, the same metal as the first metal layer 120-1 of the first circuit layer 120. For example, the first metal layer 120-1 and the second metal layer 120-2 of the first circuit layer 120 may each include copper.

[0201] The thickness of the second metal layer 120-2 of the first circuit layer 120 may correspond to a value obtained by subtracting the thickness of the first metal layer 120-1 from the thickness range of the first circuit layer 120. The thickness range of the first circuit layer 120 has already been described above, so further description thereof will be omitted.

[0202] The post 190 may be formed on the second metal layer 120-2 of the first circuit layer 120 by electroplating using the first metal layer 120-1 as a seed layer. For example, the post 190 may include only a third metal layer. The third metal layer may be formed on the second metal layer 120-2 by electroplating using the first metal layer 120-1 as a seed layer, with a certain height H1. That is, the bottom surface of the third metal layer directly contacts the top surface of the second metal layer 120-2. The top surface of the third metal layer is located higher than the top surface of the first protective layer 170. This may mean that the post 190 does not include a seed layer between the second metal layer 120-2 and the third metal layer.

[0203] FIG. 7 is a cross-sectional view showing a circuit board according to the second embodiment, and FIG. 8 is an enlarged view of a partial area of FIG.

[0204] 7 and 8, the circuit board of the second embodiment may differ from the circuit board of Fig. 2 in that a surface treatment layer is disposed thereon. In the following, descriptions of parts that are substantially the same as those of the circuit board of Fig. 2 will be omitted.

[0205] The circuit board of the second embodiment may include a surface treatment layer.

[0206] Specifically, the circuit board can include a first surface treatment layer 210 .

[0207] The first surface treatment layer 210 may be disposed on the first pad 121 and the post 190 .

[0208] Specifically, the first protective layer 170 is not disposed in the area where the first pads 121 and the posts 190 are disposed. Therefore, the first surface treatment layer 210 can entirely cover the exposed surfaces of the first pads 121 and the posts 190.

[0209] The first surface treatment layer 210 may be divided into a plurality of portions.

[0210] For example, the first surface treatment layer 210 may include a first portion 210-1 arranged on the side of the first pad 121, a second portion 120-2 arranged on the top surface of the first pad 121, a third portion 210-3 arranged on the side of the post 190, and a fourth portion 210-4 arranged on the top surface of the post 190.

[0211] The circuit board may also include a second surface treatment layer 220. The second surface treatment layer 220 may be disposed on the second pad 122. Specifically, the second surface treatment layer 220 may be disposed on the upper surface of the second pad 122 exposed through the second opening 172 of the first protection layer 170.

[0212] The circuit board may also include a third surface treatment layer 230. The third surface treatment layer 230 may be disposed under the pads of the second circuit layer 130. Specifically, the third surface treatment layer 230 may be disposed on the lower surface of the pads of the second circuit layer 130 exposed through the openings in the second protective layer 180.

[0213] The first surface treatment layer 210, the second surface treatment layer 220, and the third surface treatment layer 230 may be organic solderability preservative (OSP) layers. For example, the first surface treatment layer 210, the second surface treatment layer 220, and the third surface treatment layer 230 may be organic coating layers coated with an organic substance such as benzimidazole. However, embodiments are not limited thereto. For example, the first surface treatment layer 210, the second surface treatment layer 220, and the third surface treatment layer 230 may be plating layers. For example, the first surface treatment layer 210, the second surface treatment layer 220, and the third surface treatment layer 230 may include at least one of a nickel (Ni) plating layer, a palladium (Pd) plating layer, and a gold (Au) plating layer.

[0214] FIG. 9 is a diagram showing a semiconductor package according to the first embodiment.

[0215] 9 and 10, a semiconductor package includes the circuit board 100 of FIG.

[0216] The semiconductor package of the first embodiment may have a structure in which a plurality of chips are mounted on a circuit board 100 and coupled to a first external substrate.

[0217] For this purpose, the circuit board 100 includes a first pad 121 and a second pad 122 on a first circuit layer 120. The post 190 is disposed on the first pad 121.

[0218] The semiconductor package also includes a first connection portion 310 disposed on the second pad 122. The first connection portion 310 may have a hexahedral shape. For example, the cross section of the first connection portion 310 may be a quadrilateral shape. The cross section of the first connection portion 310 may be a rectangular or square shape. For example, the first connection portion 310 may be a spherical shape. For example, the cross section of the first connection portion 310 may be a circular or semicircular shape. For example, the cross section of the first connection portion 310 may be partially or entirely rounded. The cross section of the first connection portion 310 may have a flat surface on one side and a curved surface on the other side. The first connection portion 310 may be, but is not limited to, a solder ball.

[0219] The semiconductor package may include a first chip 320 disposed on the first connection portion 310. Terminals 325 of the first chip 320 may be electrically connected to the second pads 122 via the first connection portion 310.

[0220] The semiconductor package may include a second connection portion 330 disposed under the first group of pads of the second circuit layer 130. A second chip 340 may be mounted on the second connection portion 330. The second chip 340 may include terminals 345. The terminals 345 of the second chip 340 may be electrically connected to the first group of pads via the second connection portion 330.

[0221] The semiconductor package may include a third connection portion 350 disposed under the second group of pads on the second circuit layer 130. A third chip 360 may be mounted on the third connection portion 350. The third chip 360 may include terminals 365. The terminals 365 of the third chip 360 may be electrically connected to the second group of pads via the third connection portion 350.

[0222] The semiconductor package may include a fourth connection portion 370 disposed under the third group of pads on the second circuit layer 130. A fourth chip 380 may be mounted on the fourth connection portion 370. The fourth chip 380 may include terminals 385. The terminals 385 of the fourth chip 380 may be electrically connected to the third group of pads via the fourth connection portion 370.

[0223] At least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include a logic chip. For example, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include an application processor chip. For example, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include an analog-to-digital converter or an application-specific integrated circuit (ASIC). For example, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include a memory chip. The memory chip may be a stacked memory such as an HBM. For example, the memory chip may include a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc. At least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include at least one of a drive IC chip, a diode chip, a power IC chip, a touch sensor IC chip, a multilayer ceramic condenser (MLCC) chip, a ball grid array (BGA) chip, and a chip capacitor. For example, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may be an active element, and at least one of the other may be a passive element.

[0224] The semiconductor package may include a first molding layer 390 .

[0225] The first molding layer 390 may mold the first chip 320 and the post 190. At this time, the first protective layer 170 is not disposed in the first region R1 of the first insulating layer 111. As a result, the first molding layer 390 may mold the first region R1 of the first insulating layer 111. For example, the first molding layer 390 may mold an upper surface of the first region R1 of the first insulating layer 111. For example, as a result, at least a portion of the upper surface of the first region R1 of the first insulating layer 111 may be in direct contact with the first molding layer 390. In addition, the first molding layer 390 may mold the first pad 121 disposed in the first region R1 and the post 190 disposed on the first pad 121. For example, at least a portion of the upper surface and side surface of the first pad 121 may be in direct contact with the first molding layer 390. For example, the side of the post 190 may be in direct contact with the first molding layer 390. In this case, when the first surface treatment layer 210 is included as shown in FIG. 7, the first molding layer 390 may mold the upper surface of the first region R1 of the first insulating layer 111 and the first surface treatment layer 210.

[0226] The first molding layer 390 may include an open region. For example, the first molding layer 390 may include a first open region that opens the top surface of the post 190. For example, the first molding layer 390 may include a second open region that opens the top surface of the first chip 320. The first and second open regions may be formed by grinding the top surface of the first molding layer 390 and the top surface of the post 190 so that they are flush with the top surface of the first chip 320 after the first molding layer 390 is formed.

[0227] However, the first molding layer 390 may mold the entire top surface of the first chip 320, and thus may include only a first open region that opens the top surface of the post 190.

[0228] The semiconductor package may include a second molding layer 395 .

[0229] The second molding layer 395 may be disposed on the lower surface of the second insulating layer 112. The second molding layer 395 may mold the second chip 340, the third chip 360, and the fourth chip 380.

[0230] The first molding layer 390 and the second molding layer 395 may be, but are not limited to, EMC (Epoxy Mold Compound).

[0231] In this case, the first molding layer 390 and the second molding layer 395 may have a low dielectric constant to enhance heat dissipation characteristics. For example, the dielectric constant (Dk) of the first molding layer 390 and the second molding layer 395 may be 0.2 to 10. For example, the dielectric constant (Dk) of the first molding layer 390 and the second molding layer 395 may be 0.5 to 8. For example, the dielectric constant (Dk) of the first molding layer 390 and the second molding layer 395 may be 0.8 to 5. Thus, in this embodiment, the first molding layer 390 and the second molding layer 395 have a low dielectric constant, so that heat generated in the first to fourth chips 320, 340, 360, and 380 can be efficiently dissipated to the outside.

[0232] The semiconductor package may include a fifth connection portion 410. The fifth connection portion 410 may be disposed on an upper surface of the post 190 exposed through a first open region of the first molding layer 390.

[0233] The semiconductor package may include a first external board 420 disposed on the fifth connecting portion 410. The first external board 420 may be a main board. For example, the first external board 420 may be a motherboard of an electronic device.

[0234] FIG. 10 is a cross-sectional view showing a circuit board according to the third embodiment.

[0235] 10, the circuit board 100A of the third embodiment may differ from the circuit board 100 of FIG. 2 in that the circuit board 100A has a vertically symmetrical structure. Hereinafter, descriptions of parts that are substantially the same as those of the circuit board of FIG. 2 will be omitted.

[0236] The circuit board 100A may have a first protective layer 170 including a first opening 171 and a second opening 172 disposed on a first insulating layer 111. A first post 190 may be disposed on a first pad 121 of the first circuit layer 120.

[0237] In the circuit board 100A, a second protective layer 180a and a second post 195 may be disposed on the underside of the circuit board 100A in correspondence with the first protective layer 170 and the first post 190.

[0238] Specifically, the second insulating layer 112 may also include a first region R1 and a second region R2 corresponding to the first insulating layer 111. The second protective layer 180a may include a third opening 181 that entirely opens the first region R1. The second protective layer 180a may also include a fourth opening 182 that partially opens the second region R2. That is, the second protective layer 180a may have a structure corresponding to the first protective layer 170. Here, the first and second regions of the first and second insulating layers 111 and 112 are described as overlapping each other vertically, but this is not limiting. For example, the first region of the first insulating layer and the first region of the second insulating layer may have different areas.

[0239] The second circuit layer 130 may include a third pad disposed under the first region R1 and a fourth pad disposed under the second region R2 of the second insulating layer 112. The third pad of the second circuit layer 130 may have a structure corresponding to the first pad 121 of the first circuit layer 120. The fourth pad of the second circuit layer 130 may have a structure corresponding to the second pad 122 of the first circuit layer 120.

[0240] In addition, a second post 195 is disposed under the third pad of the second circuit layer 130. The second post 195 may have a structure corresponding to the first post 190. The first post 190 has already been described in the previous embodiment, so a description thereof will be omitted.

[0241] The circuit board 100A of the third embodiment can have posts arranged on both sides of the board, and can be applied to a PoP structure.

[0242] FIG. 11 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0243] Referring to FIG. 11, the semiconductor package according to the second embodiment may have a structure in which a second external substrate 520 is further disposed in the semiconductor package of the first embodiment.

[0244] A sixth connection portion 510 may be disposed on the lower surface of the second post 195 of the circuit board 100A.

[0245] To this end, the second molding layer 395 may include a third open region that opens the lower surface of the second post 195 .

[0246] A second external board 520 may be coupled to the sixth connection portion 510. The second external board 520 may be a memory package. To this end, the second external board 520 may include a memory board 521, a memory chip 522 mounted on the memory board 521, and a connecting member 543 connecting the memory board 521 and the memory chip 522.

[0247] However, the embodiment is not limited thereto, and the second external substrate 520 may be an interposer disposed between the memory package and the second post 195 .

[0248] FIG. 12 is a cross-sectional view showing a circuit board according to the fourth embodiment, FIG. 13 is a plan view of the circuit board of FIG. 12 seen from above, and FIG. 14 is an enlarged view of a region of the circuit board of FIG. 12.

[0249] 12 to 14, the circuit board 100B of the fourth embodiment differs from the circuit board 100 of Fig. 2 in that the first protective layer of the circuit board 100B includes a reinforcing pattern. In the following, descriptions of parts that are substantially the same as those of the circuit board of Fig. 2 will be omitted.

[0250] In the circuit board of the first embodiment, the first protective layer 170 was not disposed entirely in the first region R1 including the periphery 111a of the upper surface of the first insulating layer 111. That is, the first protective layer 170 of the circuit board of the first embodiment included a first opening 171 that entirely opened the first region R1 including the periphery 111a of the upper surface of the first insulating layer 111.

[0251] Alternatively, the first protective layer 170B in the fourth embodiment may include multiple protective members.

[0252] The first protective layer 170B may include an outer protective member 170B1. The outer protective member 170B1 of the first protective layer 170B may be disposed in a peripheral or boundary region adjacent to a periphery 111a of the top surface of the first insulating layer 111.

[0253] Specifically, the first insulating layer 111 may include not only the first region R1 and the second region R2, but also a third region R3.

[0254] The third region R3 may refer to the peripheral region or frame region adjacent to the periphery 111a of the upper surface of the first insulating layer 111 in the first region R1 of the first embodiment. That is, the first protective layer 170B includes an outer protective member 170B1 disposed in the third region R3 adjacent to the periphery 111a while completely opening the first region R1. The first protective layer 170B may be disposed along the circumferential direction of the first insulating layer 111 in the frame region of the upper surface of the first insulating layer 111. That is, the outer protective member 170B1 of the first protective layer 170B may have a closed loop shape including an open region that completely opens the first region R1 and the second region R2.

[0255] The outer protective member 170B1 of the first protective layer 170B can also be considered a reinforcing member that improves the rigidity of the circuit board 100B. The outer protective member 170B1 of the first protective layer 170B can be formed by adjusting a sawing line in a sawing process that separates the board strip into units during the process of manufacturing the circuit board of the embodiment.

[0256] The protective member 170B2 of the first protective layer 170B may be disposed on the second region R2 of the first insulating layer 111. The protective member 170B2 of the first protective layer 170B corresponds to the first protective layer 170 of the first embodiment, and therefore, a detailed description thereof will be omitted.

[0257] The outer protective member 170B1 may be horizontally spaced apart from the protective member 170B2 across the first opening 171. Here, the first opening 171 can be said to be a spaced apart region between the inner surface of the outer protective member 170B1 and the outer surface of the protective member 170B2.

[0258] That is, the first opening 171 can be regarded as a separation space that separates the outer protective member 170B1 and the protective member 170B2. The outer protective member 170B1 may be disposed in a closed loop shape along the circumferential direction of the first insulating layer 111. Thus, the first opening 171 may be provided between the inner surface of the outer protective member 170B1 and the outer surface of the protective member 170B2, having a closed loop shape.

[0259] In this case, the outer surface of the protection member 170B2 includes an outwardly protruding portion and an inwardly recessed portion as described in the above embodiment, and therefore the horizontal width of the first opening 171 may include different widths along the outer surface of the protection member 170B2.

[0260] That is, the outer protective member 170B1 is provided along the periphery of the upper surface of the substrate corresponding to the insulating layer, and the protective member 170B2 is provided inside the outer protective member 170B1 with the separation region sandwiched therebetween. In this case, the separation region between the inner surface of the outer protective member 170B1 and the outer surface of the protective member 170B2 may include a first separation region having a first width along the horizontal direction and a second separation region having a second width different from the first width. This may be due to a concave and / or convex surface provided on the outer surface of the protective member 170B2. In addition, the separation region is provided in a closed loop along the outer surface of the protective member 170B2.

[0261] In this case, the outer surface of the protective member 170B2 may include a protruding surface that protrudes toward the inner surface of the outer protective member 170B1. The protruding surface of the protective member 170B2 may be provided in the second separation region, and the first width may be greater than the second width.

[0262] In this case, the protruding surface of the protective member 170B2 may include a first protruding surface protruding with a first protruding width toward the inner surface of the outer protective member 170B1, and a second protruding surface protruding with a second protruding width greater than the first protruding width toward the inner surface of the outer protective member 170B1. In this case, the first separated region may correspond to the first protruding surface, and the second separated region may correspond to the second protruding surface.

[0263] In addition, the outer surface of the protection member 170B2 may include a concave surface recessed toward the inside of the protection member 170B2. In this case, the concave surface of the protection member 170B2 may be provided in the first separation region, and the first width may be greater than the second width.

[0264] Meanwhile, the inner surface of the outer protective member 170B1 may include a first inner surface, a second inner surface facing the first inner surface, a third inner surface disposed between the first inner surface and the second inner surface and facing each other, and a fourth inner surface.

[0265] In addition, the outer surface of the second protective member 170B2 may include a first outer surface adjacent to the first inner surface, a second outer surface adjacent to the second inner surface, a third outer surface adjacent to the third inner surface, and a fourth outer surface adjacent to the fourth inner surface.

[0266] In this case, the separation area between the first inner surface of the outer protection member 170B1 and the first outer surface of the second protection member 170B2 may include the first and second separation areas.

[0267] The first circuit layer 120 includes a first pad 121 and a second pad 122, respectively.

[0268] In this case, the first circuit layer 120 may include a dummy pattern 123. The dummy pattern 123 may be disposed on the third region R3 of the first insulating layer 111. The dummy pattern 123 may be covered by the outer protection member 170B1.

[0269] The dummy pattern 123 may have a planar shape corresponding to the outer protection member 170B1. For example, the dummy pattern 123 may have a closed loop shape along the periphery 111a.

[0270] The dummy pattern 123 may be part of a seed layer used to electroplating the first pad 121, the second pad 122, and the post 190.

[0271] That is, in the fourth embodiment, the electrolytic plating process of the post 190 may be performed with the outer protective member 170B1 disposed in the third region R3. Furthermore, because the final seed layer removal is performed with the outer protective member 170B1 in place, the seed layer disposed below the outer protective member 170B1 is not removed. Thus, the first circuit layer 120 of the circuit board of the fourth embodiment may further include a dummy pattern 123 disposed below the outer protective member 170B1 in the third region R3. The dummy pattern 123 may correspond to the first metal layer 120-1 of the first circuit layer 120. That is, the dummy pattern 123 may have the same thickness as the first metal layer 120-1 of the first pad 121 and the second pad 122 of the first circuit layer 120.

[0272] In this embodiment, the dummy pattern 123 is disposed in a third region R3 on the top surface of the first insulating layer 111 of the circuit board. The dummy pattern 123 can suppress warpage of the circuit board and improve warpage characteristics. For example, the dummy pattern 123 can function as a rigid member that improves the rigidity of the circuit board. Furthermore, the outer protective member 170B1 can protect the outermost frame region on the top surface of the first insulating layer 111.

[0273] The reason why the circuit board of the fourth embodiment can have the outer protective member 170B1 and the dummy pattern 123 will be explained in more detail in the following description of the method for manufacturing the circuit board.

[0274] -Circuit board manufacturing method-

[0275] 15 to 28 are diagrams for explaining the manufacturing method of the circuit board of the first embodiment shown in Fig. 2 in the order of steps. The manufacturing method of the circuit board of the first embodiment will be explained below with reference to Fig. 15 to 28. Furthermore, in explaining the manufacturing method of the circuit board of the first embodiment, a method of forming dummy portions of the first circuit layer and the first protective layer of the fourth embodiment will also be explained.

[0276] The following description will focus on the process of forming the first circuit layer 120, the first protective layer 170, and the posts 190 on the first insulating layer 111 in the circuit board.

[0277] 15 , in an embodiment, a first insulating layer 111 is prepared. Preferably, the step of preparing the first insulating layer 111 may refer to a process of laminating the first insulating layer 111 on the third insulating layer 113 with the third circuit layer 140 disposed on the third insulating layer 113. Next, in an embodiment, a first metal layer 120-1 may be formed on the first insulating layer 111. The first metal layer 120-1 may refer to a copper foil layer disposed on the first insulating layer 111. Alternatively, the first metal layer 120-1 may be an electroless plating layer formed by electroless plating on the first insulating layer 111. For example, the first metal layer 120-1 may be a chemical copper plating layer. Alternatively, the first metal layer 120-1 may include both the copper foil layer and the chemical copper plating layer.

[0278] In this case, the circuit boards of the embodiment can be manufactured in strip units or panel units, i.e., a strip includes a plurality of circuit boards, and a panel includes a plurality of strips.

[0279] This allows the first insulating layer 111 to be divided into a plurality of regions. For example, the first insulating layer 111 includes a plurality of effective regions AR corresponding to circuit board regions and dummy regions DR disposed between the effective regions AR. Finally, a plurality of circuit boards can be separated by sawing along the lines between the effective regions AR and the dummy regions DR. The effective regions AR may include the first region R1 and the second region R2 of the circuit board 100, as described above. The first region R1 of the circuit board 100 may refer to the region adjacent to the dummy regions DR.

[0280] 16, in an embodiment, a first mask M1 is formed on the first metal layer 120-1. The first mask M1 may be disposed on the effective area AR and the dummy area DR. In this case, the first mask M1 may include an open area OR1 that is provided on the effective area AR and opens an area where the first circuit layer 120 is to be formed.

[0281] Next, referring to FIG. 17, in this embodiment, a second metal layer 120-2 is formed to fill the open area OR1 of the first mask M1 using the first metal layer 120-1 as a seed layer.

[0282] Next, referring to FIG. 18, an embodiment may perform a step of removing the first mask M1.

[0283] Next, referring to FIG. 19 , an embodiment may perform a process of forming a second mask M2. The second mask M2 may include an open region OR2. The open region OR2 of the second mask M2 may vertically overlap the first metal layer 120-1 and the second metal layer 120-2, which vertically overlap the second region R2 of the effective region AR. For example, the second mask M2 may cover the first metal layer 120-1 and the second metal layer 120-2 disposed in the first region R1 of the effective region AR. The second mask M2 may also cover the first metal layer 120-1 disposed in the dummy region DR. The first metal layer 120-1 in the first region R1 and the first metal layer 120-1 in the dummy region DR, covered by the second mask M2, may later be used as a seed layer for electroplating posts 190.

[0284] 20, in an embodiment, a process may be performed to remove the first metal layer 120-1 exposed through the open region OR2 of the second mask M2 by etching. Specifically, in an embodiment, a portion of the first metal layer 120-1 disposed in the second region R2 that does not vertically overlap the second metal layer 120-2 may be removed by etching. Through this, in an embodiment, a second pad 122 of the first circuit layer 120 including the first metal layer 120-1 and the second metal layer 120-2 in the second region R2 may be formed.

[0285] 21, the embodiment may perform a process of removing the second mask M2, thereby opening the first metal layer 120-1 disposed in the first region R1 and the first metal layer 120-1 disposed in the dummy region DR.

[0286] 22, in an embodiment, a process of forming a resist layer 170R over the entire effective area AR and the dummy area DR may be performed. The resist layer 170R may refer to the layer before the first opening 171 and the second opening 172 are formed in the first protective layer 170 in the embodiment. The resist layer 170R may cover the first metal layer 120-1 and the second metal layer 120-2 in the first area R1. The resist layer 170R may cover the first insulating layer 111 and the second pad 122 in the second area R2. The resist layer 170R may also cover the first metal layer 120-1 in the dummy area DR.

[0287] 23, in an embodiment, a process may be performed in which the resist layer 170R is exposed and developed to form a first opening 171 that completely opens the first region R1. In addition, in an embodiment, a process may be performed in which a second opening 172 that partially opens the second pad 122 arranged in the second region R2 is formed. At this time, when forming the first opening 171, the resist layer 170R on the dummy region DR may also be completely removed. However, the embodiment is not limited thereto.

[0288] For example, to manufacture the circuit board of the fourth embodiment, the third region R3 of the resist layer 170R arranged in the dummy region DR, which is adjacent to the first region R1 (e.g., the circuit board of the fourth embodiment), does not need to be removed.

[0289] 24, an embodiment may perform a process of forming a third mask M3. The third mask M3 may include an open region OR3 that is disposed entirely over the dummy region DR and the effective region AR and vertically overlaps a portion of the top surface of the second metal layer 120-2 located in the first region R1. The width of the open region OR3 may be smaller than the width of the second metal layer 120-2 in the first region R1. This allows the third mask M3 to partially open the top surface of the second metal layer 120-2 in the first region R1.

[0290] 25, in this embodiment, a process of forming posts 190 on the second metal layer 120-2 in the first region R1 exposed through the open region OR3 of the third mask M3 may be performed. In this case, the posts 190 may be formed by electrolytic plating using the first metal layer 120-1 disposed in the first region R1 and the first metal layer 120-1 disposed in the dummy region DR as seed layers.

[0291] Specifically, the first region R1 is disposed to surround the second region R2. The dummy region DR is disposed to surround the first region R1. The first metal layer 120-1 in the first region R1 and the first metal layer 120-1 in the dummy region DR remain without being removed. As a result, the first metal layer 120-1 in the dummy region DR, the first metal layer 120-1 in the first region R1, and the second metal layer 120-2 in the first region R1 are electrically connected to each other. Therefore, electrolytic plating can be performed on the second metal layer 120-2 to form posts 190 that fill the open regions OR3 of the third mask M3.

[0292] 26, the embodiment may perform a process of removing the third mask M3. Through this, the first metal layer 120-1 in the first region R1 and the first metal layer 120-1 in the dummy region DR may be opened. In this case, if the resist layer 170R is not removed in a portion of the dummy region DR adjacent to the first region R1 (i.e., the third region R3), the first metal layer 120-1 in the third region R3 may not be opened.

[0293] 27, in an embodiment, the first pad 121 of the first circuit layer 120 may be formed by etching and removing the first metal layer 120-1 that is opened in the first region R1 and the dummy region DR. At this time, as long as the resist layer 170R remains in the third region R3, the first metal layer 120-1 disposed in the third region R3 may not be removed.

[0294] 28, in this embodiment, the line between the dummy area DR and the first area R1 may be used as a sawing line to separate the effective area AR from the dummy area DR, thereby completing the manufacturing of the circuit board 100.

[0295] At this time, if the first metal layer 120-1 and the resist layer 170R remain in the third region R3, the sawing line can be located between the dummy region DR and the third region R3. Therefore, as in the fourth embodiment, a dummy pattern 123 corresponding to the first metal layer 120-1 in the third region R3 and a dummy protective layer corresponding to the resist layer 170R on the dummy pattern 123 can be formed. In this case, a portion of the dummy region DR may be included in the effective region AR of the final circuit board.

[0296] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, the content related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

[0297] Furthermore, while the above description has focused on the embodiments, these are merely illustrative and do not limit the present invention. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the present invention. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the present invention as defined in the appended claims.

Claims

1. an insulating layer; a protective member disposed on the insulating layer; a plurality of posts arranged on the insulating layer along the periphery of the protective member; the protective member includes an upper surface, a lower surface, and a side surface disposed between the upper surface and the lower surface; a lower surface of the protection member and an upper surface of the insulating layer facing each other; Side surfaces of the plurality of posts face side surfaces of the protection member, A circuit board, wherein a side surface of the protection member includes a protrusion that protrudes between the plurality of posts.

2. the side surfaces of the protection member include a first side surface extending in a first direction, a second side surface extending in the first direction and spaced apart from the first side surface, a third side surface extending in a second direction perpendicular to the first direction, and a fourth side surface extending in the second direction and spaced apart from the third side surface, The circuit board according to claim 1 , wherein the protruding surfaces of the protection member are provided on the first side surface and the third side surface.

3. 3. The circuit board of claim 2, wherein the third side has a first surface having a first distance from the plurality of posts along the first direction, a second surface having a second distance smaller than the first distance, and a third surface having a third distance larger than the first distance.

4. The circuit board according to claim 2 , wherein a distance between the fourth side surface and the plurality of posts along the first direction is uniform.

5. The circuit board according to claim 2 , wherein the second side surface of the protection member includes a concave surface recessed toward the first side surface of the protection member.

6. the protective member includes a plurality of through holes, The circuit board according to claim 1 , wherein the width of the plurality of through holes is smaller than the width of the posts.

7. an outer protective member disposed on the insulating layer and having a through hole; The circuit board of claim 1 , wherein the post and the protective member are disposed within a through hole in the outer protective member.

8. The circuit board of claim 6 , further comprising a surface treatment layer disposed on the posts.

9. a plurality of pads disposed between the insulating layer and the protective member; a width of the plurality of through holes of the protection member being smaller than a width of the plurality of pads; The circuit board of claim 8 , wherein the width of the post is smaller than the width of the pad.

10. The protective member further includes a surface treatment layer disposed in each of the plurality of through holes, The circuit board according to claim 9 , wherein the surface treatment layers disposed in the plurality of through holes of the protection member and the surface treatment layers disposed on the posts are made of the same material.

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