MEMORY SYSTEM, METHOD OF OPERATING A MEMORY SYSTEM, AND COMPUTER-READABLE STORAGE MEDIUM

Abstract

This application discloses a memory system, a method for operating a memory system, and a computer-readable storage medium related to the field of storage technology. The memory system includes a memory and a memory controller. The memory includes a memory array coupled to n word lines, the n word lines being arranged consecutively by physical word line identifiers, where n≧2. The memory controller is configured to map the n physical word line identifiers to n virtual word line identifiers, where the physical word line identifiers corresponding to m adjacent virtual word line identifiers are spaced apart from each other, where 2≦m≦n, and to generate check data based on data corresponding to the m adjacent virtual word line identifiers. The check data is generated from data corresponding to multiple adjacent virtual word line identifiers. That is, the check data is generated from data corresponding to multiple non-adjacent physical word line identifiers, which reduces the impact on the check data caused by mutual effects between adjacent physical word lines, increases the success rate of data recovery, and improves the reliability of data storage and data reading.

Description

[Technical Field]

[0001] The present application relates to the field of storage technology, and in particular to a memory system, a method of operating a memory system, and a computer-readable storage medium. [Background technology]

[0002] Memory cells in a three-dimensional (3D) memory are coupled to word lines, and data is written into the memory cells through program voltages applied by the word lines.

[0003] When data is written into a 3D memory, check data may be generated according to the written data to avoid errors in subsequent data reads. In this way, when data is read from the memory, the read data is checked according to the check data, and if the check fails, the correct data can be recovered according to the check data. Ensuring successful data recovery when the check fails has become a current research hotspot. Summary of the Invention [Means for solving the problem]

[0004] The present application provides a memory system, a method for operating the memory system, and a computer-readable storage medium, which can improve programming efficiency. The technical solutions are described as follows:

[0005] In one aspect, a memory system is provided, the memory system including: one or more memories; and a memory controller coupled to the memory and configured to control the memory, the memory including a memory array, the memory array coupled to n word lines, the n word lines arranged consecutively by physical word line identifiers, where n≧2; the memory controller is configured to obtain a plurality of data to be written into the memory array; the memory controller is configured to map the n physical word line identifiers to the n virtual word line identifiers, wherein the physical word line identifiers corresponding to the m adjacent virtual word line identifiers are spaced apart from one another, where 2≦m≦n; The memory controller is configured to generate check data based on data corresponding to the m adjacent virtual word line identifiers, and the check data is configured to check and restore the data corresponding to the m adjacent virtual word line identifiers.

[0006] In one optional implementation, the memory controller is configured to: obtain a preset mapping relationship table, where the mapping relationship table includes a mapping correspondence between physical word line identifiers and virtual word line identifiers; and obtain n virtual word line identifiers corresponding to the n physical word line identifiers by matching the n physical word line identifiers with the mapping relationship table.

[0007] In one optional implementation, the memory controller is configured to retrieve the pre-configured mapping relationship table from a static random access memory.

[0008] In one optional implementation, the reference numbers of the physical word line identifiers are distributed among the physical word line identifiers corresponding to the m adjacent virtual word line identifiers, respectively.

[0009] In one optional implementation, the memory controller is configured to obtain a preset algorithm, the preset algorithm being configured to map physical word line identifiers to virtual word line identifiers and to substitute the n physical word line identifiers into the preset algorithm to obtain n virtual word line identifiers corresponding to the n physical word line identifiers.

[0010] In one optional implementation, the memory controller is configured to process data corresponding to m adjacent virtual word line identifiers through a first operator to obtain check data, and when there is a data read failure in the data corresponding to the m adjacent virtual word line identifiers, the check data is configured to check and restore the data that failed to be read through a second operator, and the first operator and the second operator are operators whose operation logics are opposite to each other.

[0011] In one optional implementation, the memory controller is configured to send a first read command to the memory, the first read command including a first physical word line identifier corresponding to first data to be read, and receive a data read result returned by the memory; The memory controller is configured to, when the data read result indicates that the first data corresponding to the first physical word line identifier fails to be read, determine a first virtual word line identifier corresponding to the first physical word line identifier, and obtain target check data corresponding to the first virtual word line identifier for restoring the first data that failed to be read.

[0012] In one optional implementation, the memory controller is configured to obtain target check data corresponding to a first virtual word line identifier, obtain a second virtual word line identifier aligned with the first virtual word line identifier for generating the target check data, and determine a second physical word line identifier corresponding to the second virtual word line identifier; The memory controller is configured to send a second read command to the memory, the second read command including a second physical word line identifier and configured to instruct the memory to read data stored in a row of memory cells coupled to a word line corresponding to the second physical word line identifier, receive second data returned by the memory and corresponding to the second physical word line identifier, and restore the first data that failed to be read based on the target check data and the second data.

[0013] In one optional implementation, when reading first data corresponding to a first physical word line identifier, the memory controller: determines a first virtual word line identifier corresponding to the first physical word line identifier; obtains target check data corresponding to the first virtual word line identifier; obtains a second virtual word line identifier that is matched with the first virtual word line identifier for generating the target check data; and determines a second physical word line identifier that corresponds to the second virtual word line identifier; sending a read instruction to the memory, the read instruction configured to instruct reading data stored in a row of memory cells coupled to a word line corresponding to the first physical word line identifier and the second physical word line identifier; The memory controller is configured to receive a data read result returned by the memory, and when the data read result indicates that the first data fails to be read, use the target check data and second data corresponding to the second physical word line identifier to restore the first data that failed to be read.

[0014] In another aspect, a method is provided for operating a memory system, the memory system including a memory having a memory array, the memory array coupled to n word lines, the n word lines arranged consecutively by physical word line identifiers, where n≧2.

[0015] The method is: obtaining a plurality of data to be written into a memory array; writing check data into the memory, the check data being generated based on data corresponding to the spaced apart physical word line identifiers, and configured to check and restore the data; Includes.

[0016] In one optional implementation, the method includes, before writing the check data into the memory: mapping n physical word line identifiers to n virtual word line identifiers, wherein the physical word line identifiers corresponding to m adjacent virtual word line identifiers are spaced apart from one another, where 2≦m≦n; generating check data based on data corresponding to m adjacent virtual word line identifiers, the check data being configured to check and restore the data corresponding to the m adjacent virtual word line identifiers; Further includes:

[0017] In one optional implementation, mapping the n physical word line identifiers to the n virtual word line identifiers includes: obtaining a preset mapping relationship table, the mapping relationship table including a mapping correspondence between physical word line identifiers and virtual word line identifiers; obtaining n virtual word line identifiers corresponding to the n physical word line identifiers by matching the n physical word line identifiers with a mapping relationship table; Includes.

[0018] In one optional implementation, the step of obtaining the pre-configured mapping relationship table includes: The method includes retrieving a pre-configured mapping relationship table from a static random access memory.

[0019] In one optional implementation, the reference numbers of the physical word line identifiers are distributed among the physical word line identifiers corresponding to the m adjacent virtual word line identifiers, respectively.

[0020] In one optional implementation, mapping the n physical word line identifiers to the n virtual word line identifiers includes: obtaining a preset algorithm, the preset algorithm being configured to map physical word line identifiers to virtual word line identifiers; Substituting the n physical word line identifiers into a preset algorithm to obtain n virtual word line identifiers corresponding to the n physical word line identifiers; Includes.

[0021] In one optional implementation, generating check data based on data corresponding to m adjacent virtual word line identifiers includes: The method includes a step of processing data corresponding to m adjacent virtual word line identifiers through a first operator to obtain check data, and when there is a data read failure in the data corresponding to the m adjacent virtual word line identifiers, the check data is configured to check and restore the data that failed to be read through a second operator, and the first operator and the second operator are operators whose operation logics are opposite to each other.

[0022] In one optional implementation, the method, after writing the check data to the memory, includes: sending a first read command to the memory, the first read command including a first physical word line identifier corresponding to first data to be read; receiving a data read result returned by the memory; determining a first virtual word line identifier corresponding to the first physical word line identifier when the data read result indicates that reading the first data corresponding to the first physical word line identifier fails; obtaining target check data corresponding to the first virtual word line identifier for recovering the first data that failed to be read; Further includes:

[0023] In one optional implementation, obtaining target check data corresponding to the first virtual word line identifier for recovering the first data that failed to be read includes: obtaining target check data corresponding to a first virtual word line identifier; and obtaining a second virtual word line identifier that is matched with the first virtual word line identifier to generate the target check data; determining a second physical word line identifier corresponding to the second virtual word line identifier; sending a second read instruction to the memory, the second read instruction including a second physical word line identifier and configured to instruct the memory to read data stored in a row of memory cells coupled to a word line corresponding to the second physical word line identifier; receiving second data returned by the memory and corresponding to the second physical word line identifier; and recovering the first data that was unsuccessfully read based on the target check data and the second data. Includes.

[0024] In one optional implementation, the method includes, after generating check data based on data corresponding to m adjacent virtual word line identifiers: sending a first read command to the memory, the first read command including a first physical word line identifier corresponding to first data to be read; determining a first virtual word line identifier corresponding to the first physical word line identifier; and obtaining target check data corresponding to the first virtual word line identifier; obtaining a second virtual word line identifier that is matched with the first virtual word line identifier for generating target check data; and determining a second physical word line identifier that corresponds to the second virtual word line identifier; sending a second read instruction to the memory, the second read instruction including a second physical word line identifier and configured to instruct the memory to read data stored in a row of memory cells coupled to a word line corresponding to the second physical word line identifier; receiving a data read result returned by the memory; When the data read result indicates that the first data fails to be read, using the target check data and second data corresponding to the second physical word line identifier to restore the first data that failed to be read; Further includes:

[0025] In another aspect, a computer-readable storage medium is provided having instructions stored therein that, when executed on a memory controller, perform a method of operating a memory system according to any one of the implementations described above.

[0026] The technical solutions provided by the present application may include the following beneficial effects:

[0027] The virtual word line identifiers corresponding to the physical word line identifiers are generated by setting a mapping relationship between the physical word line identifiers and the virtual word line identifiers so that the physical word line identifiers corresponding to adjacent virtual word line identifiers are spaced apart, i.e., not adjacent. Check data is generated using data corresponding to a plurality of adjacent virtual word line identifiers. That is, the check data is generated using data corresponding to a plurality of non-adjacent physical word line identifiers, thereby reducing the influence on the check data caused by the mutual effect between adjacent physical word lines, increasing the success rate of data recovery, and improving the reliability of data storage and data reading.

[0028] In order to more clearly describe the technical solutions in the implementation of the present application, the drawings used in the description of the implementation are briefly introduced below.Obviously, the drawings in the following description are only some implementations of the present application.Other drawings can also be obtained for those skilled in the art based on these drawings without creative efforts. [Brief explanation of the drawings]

[0029] [Figure 1] 1 is a schematic structural diagram of a memory system according to an implementation of the present application; [Figure 2] 1 is a schematic diagram of a memory system integration scenario according to an exemplary implementation of the present application; [Figure 3] FIG. 1 is a schematic diagram of a memory system integration scenario according to another exemplary implementation of the present application. [Figure 4] 1 is a schematic diagram of a memory according to an implementation of the present application; [Figure 5] 1 is a schematic cross-sectional view of a memory array including memory strings according to one implementation of the present application. [Figure 6] FIG. 2 is a schematic diagram of a peripheral circuit according to one implementation of the present application. [Figure 7] 1 is a flowchart of a method of operating a memory system according to an exemplary implementation of the present application. [Figure 8]FIG. 2 is a schematic diagram of a mapping relationship table according to an exemplary implementation of the present application; [Figure 9] FIG. 1 is a schematic diagram of a check data generation process according to an exemplary implementation of the present application. [Figure 10] 10 is a flowchart of a method of operating a memory system according to another exemplary implementation of the present application. [Figure 11] FIG. 2 is a schematic diagram of a data checking and restoration process according to an exemplary implementation of the present application. [Figure 12] FIG. 2 is a schematic structural diagram of a memory controller according to an exemplary implementation of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0030] Implementations of the present application are further described in detail below together with the accompanying drawings.

[0031] The method for operating a memory system provided in the implementations of the present application may be applied to the memory system, which may include a 3D memory such as a 3D NAND flash.

[0032] 1 is a schematic diagram of a memory system 10 according to one implementation of the present application. As shown in FIG. 1, the memory system 10 includes one or more memories 100 and a memory controller 200 coupled to the memories 100 and configured to control the memories 100.

[0033] Memory controller 200 may be configured to control operations performed by memory 100, such as read, erase, and program operations. Memory controller 200 may further be configured to manage various functions related to data stored or to be stored in memory 100, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some examples, memory controller 200 may also be configured to process error correcting codes (ECC) on data read from or written into memory 100. Memory controller 200 may also perform any other suitable functions, such as formatting memory 100.

[0034] The memory controller 200 can also communicate with external devices according to a specific communication protocol. For example, the memory controller 200 may communicate with external devices via at least one of a variety of interface protocols. The interface protocol may be a Universal Serial Bus (USB) protocol, a Multimedia Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0035] In some implementations, memory controller 200 and one or more memories 100 may be integrated into various types of electronic devices. The electronic device may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a pointing device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. In this scenario, as shown in FIG. 1 , memory system 10 further includes a host 300. Memory controller 200 is coupled to host 300. Memory controller 200 may manage data stored in memory 100 and may communicate with host 300 to implement the functions of the electronic device as described above.

[0036] In some other implementations, the memory controller 200 and one or more memories 100 may be integrated into various types of storage devices.

[0037] As an example, the memory controller 200 and the single memory 100 may be integrated into a memory card 400 as shown in Figure 2. The memory card 400 may include a Personal Computer Memory Card International Association (PCMCIA, PC) card, a CompactFlash (CF) card, a SmartMedia (SM) card, a Memory Stick, a MultiMediaCard (MMC), a Ultra Small MMC (RS-MMC), a Micro MMC, a Secure Digital (SD) card, a Universal Flash Storage (UFS), etc. As shown in Figure 2, the memory card 400 may further include a connector 410 for coupling the memory card 400 with a host.

[0038] 3, the memory controller 200 and the plurality of memories 100 may be integrated into a solid-state disk (SSD) 500. The solid-state disk 500 may further include a connector 510 that couples the solid-state disk 500 to a host. The storage capacity and / or operating speed of the solid-state disk 500 may be greater than the storage capacity and / or operating speed of the memory card 400.

[0039] In addition, the memory 100 in Figures 1 to 3 may be any memory involved in the implementation of the present application. For example, it may be a 3D NAND (NAND gate) memory. The structure of the memory 100 is described below.

[0040] 4 is a schematic diagram of a memory 100 according to one implementation of the present application. As shown in FIG. 4, the memory 100 includes: a memory array 110 including a plurality of rows of memory cells; a plurality of word lines 120 respectively coupled to a plurality of rows of memory cells; and a peripheral circuit 130 coupled to the plurality of word lines 120 and configured to perform a verify operation or a program operation on a selected memory cell row of the plurality of memory cell rows, the selected memory cell row being a memory cell row coupled to the selected word line, the peripheral circuit 130 configured to perform a method of operating a memory provided in an implementation of the present application to perform the verify operation or the program operation.

[0041] 1, a NAND flash memory array includes a plurality of memory strings 111 arranged in an array on a substrate, with each memory string 111 extending vertically above a substrate (not shown). In some implementations, each memory string 111 includes a plurality of memory cells 112 coupled in series and stacked vertically.

[0042] 4, each memory string 111 may further include a source select gate (SSG) 113 at the bottom and a drain select gate (DSG) 114 at the top. The source select gate is also called a lower select transistor, bottom select gate (BSG), or source select transistor, and the drain select gate is also called a top select transistor, top select gate (TSG), or drain select transistor. The source select gate 113 and the drain select gate 114 may be configured to activate the selected memory string 111 during read and program operations.

[0043] In some implementations, the drain select gate 114 of each memory string 111 is coupled to a corresponding bit line 115 from which data can be read and written via an output bus (not shown).

[0044] In some implementations, each memory string 111 is configured to apply a select or deselect voltage (e.g., 0V) to a corresponding drain select gate 114 (e.g., higher than the threshold voltage of the transistor having the drain select gate 114) via one or more DSG lines 116. Additionally or alternatively, in some implementations, each memory string 111 is configured to be selected or deselected by applying a select or deselect voltage (e.g., 0V) to a corresponding source select gate 113 (e.g., higher than the threshold voltage of the transistor having the source select gate 113) via one or more SSG lines 117.

[0045] 4, the memory strings 111 may be organized into multiple blocks 140, and for any block 140 in the multiple blocks 140, the block 140 may have a source line (SL) 118. The sources of all memory strings 111 in the block 140 are coupled via the source line 118, also referred to as a common source line or array common source (ACS).

[0046] The source line 118 may be used to ground the sources of each memory cell of the memory strings in the block 140 later in some operations to achieve grounding. In some examples, the sources of each memory cell of the memory strings in the block 140 may also be connected to a high voltage via the source line 118 in some other operations.

[0047] Each block 140 is the basic data unit for an erase operation, i.e., all memory cells 112 on the same block 140 are erased simultaneously. To erase memory cells 112 in a selected block, a source line coupled to the selected block may be biased with an erase voltage (Vers), for example, a high positive voltage (20V or greater).

[0048] It should be appreciated that in other implementations, erase operations may be performed at the half block level, at the quarter block level, or at any suitable number or fraction of blocks.

[0049] 4, memory cells 112 in the same layer of adjacent memory strings 111 in the same block 140 may be coupled via word lines 120. The word lines 120 are configured to select which layer of memory cells 112 in the block 140 is affected by read and program operations.

[0050] In some implementations, each word line 120 is coupled to a page to which a memory cell 112 belongs. A page is a basic unit of data used for program operations. The size of a page may relate to the number of memory strings 111 coupled by a word line 120 in one block 140. Each word line 120 may be coupled to the control gate (i.e., gate electrode) of each memory cell 112 in the corresponding page.

[0051] Note that the same layer of memory cells in a block 140 corresponds to the same word line, but the same layer of memory cells can be divided into one or more pages. That is, one word line can be connected to one or more pages. For example, in the case of SLC, one word line is connected to one page. In the case of MLC, one word line is connected to two pages.

[0052] 5 is a schematic cross-sectional view of a memory array 110 including memory strings 111 according to one implementation of the present application. As shown in FIG. 5, the memory strings 111 may extend vertically above a substrate 101 and through a stack layer 102. The substrate 101 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0053] The stack layer 102 may include alternating gate conductive layers 103 and inter-gate dielectric layers 104. The number of memory cells 112 in the memory array 110 may be determined by the number of pairs of gate conductive layers 103 and inter-gate dielectric layers 104 in the stack layer 102.

[0054] The gate conductive layers 103 may include conductive materials, including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate conductive layer 103 includes a metal layer, such as a tungsten layer. In other implementations, each gate conductive layer 103 includes a doped polysilicon layer. In addition, each gate conductive layer 103 may include a control gate surrounding the memory cell 112 and may extend laterally at the top of the stack layer 102 as a DSG line 116 and at the bottom of the stack layer 102 as an SSG line 117, or extend laterally between the DSG line 116 and the SSG line 117 as a word line 120.

[0055] 5, the memory string 111 includes a channel structure 105 that extends vertically through the stack layers 102. In some implementations, the channel structure 105 includes a channel hole filled with semiconductor material(s) (e.g., as a semiconductor channel) and dielectric material(s) (e.g., as a memory film). The semiconductor channel includes silicon, such as polysilicon. The memory film is a composite dielectric layer that includes a tunneling layer, an accumulation layer (also called a "charge trapping / accumulation layer"), and a blocking layer.

[0056] In some implementations, the channel structure 105 has a cylindrical shape (e.g., a pillar shape), with the layers in the semiconductor channel and memory film radially arranged in that order from the center of the cylinder to the outer surface of the cylinder.

[0057] Although not shown in FIG. 5, it should be understood that memory array 110 may also include other additional components, including, but not limited to, gate line slits / source contacts, local contacts, interconnect layers, etc.

[0058] 4 , peripheral circuitry 130 may be coupled to memory array 110 via bit lines 115, word lines 120, source lines 118, SSG lines 117, and DSG lines 116. Peripheral circuitry 130 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to and sensing voltage and / or current signals from memory cells 112 via bit lines 115, word lines 120, source lines 118, SSG lines 117, and DSG lines 116 to facilitate operation of memory array 110.

[0059] The peripheral circuits 130 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 shows some exemplary peripheral circuits 130, including a page buffer / sense amplifier 131, a column decoder / bitline (BL) driver 132, a row decoder / wordline (WL) driver 133, a voltage generator 134, a control logic unit 135, a register 136, an interface 137, and a data bus 138. It should be understood that in some examples, additional peripheral circuits not shown in Figure 6 may also be included.

[0060] The page buffer / sense amplifiers 131 may be configured to read data from and program (write) data into the memory array 110 according to control signals from the control logic unit 135. For example, the page buffer / sense amplifiers 131 may store a page of program data (write data) to be programmed into one page 130 of the memory array 110. The page buffer / sense amplifiers 131 may also perform verify operations to ensure that data is correctly programmed into the memory cells 112 coupled to a selected word line 120. The page buffer / sense amplifiers 131 may also sense low-power signals from the bit lines 115 that represent data bits stored in the memory cells 112 and amplify small voltage fluctuations to recognized logic levels during a read operation.

[0061] The column decoder / bit line driver 132 is controlled by a control logic unit 135 and may be configured to select one or more memory strings 111 by applying a bit line voltage generated from a voltage generator 134 .

[0062] The row decoder / word line driver 133 may be controlled by the control logic unit 135 and configured to select / deselect blocks 140 of the memory array 110 and word lines 120 of the blocks 140. The row decoder / word line driver 133 may also be configured to drive the word lines 120 using a word line voltage (VWL) generated from a voltage generator 134. In some implementations, the row decoder / word line driver 133 may also select / deselect and drive the SSG lines 117 and the DSG lines 116. As described in more detail below, the row decoder / word line driver 133 is configured to perform an erase operation on memory cells 112 coupled to selected word lines 120.

[0063] The voltage generator 134 may be controlled by the control logic unit 135 and configured to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory array 110.

[0064] A control logic unit 135 may be coupled to each of the peripheral circuits mentioned above and may be configured to control the operation of each of the circuits.

[0065] Registers 136 may be coupled to the control logic unit 135, and may include status registers, command registers, and address registers for storing status information, command operation codes (opcodes), and command addresses for controlling the operation of each circuit in the peripheral circuits.

[0066] An interface (I / F) 137 may be coupled to control logic unit 135 and may act as a control buffer for buffering and relaying control commands received from a host (not shown) to control logic unit 135, and for buffering and relaying status information received from control logic unit 135 to the host. Interface 137 may also be coupled to column decoder / bit line drivers 132 via data bus 138 and may act as a data I / O interface and data buffer for buffering and relaying data to and from memory array 110.

[0067] The above description of the memory-related hardware implementation has similar beneficial effects to the effects of the following method implementation: By referring to the description of the method implementation in the present application, technical details not disclosed in the memory-related hardware implementation may be understood.

[0068] 1 as an example, the memory system includes one or more memories and a memory controller coupled to the memories and configured to control the memories, the memory including a memory array, the memory array coupled to n word lines, the n word lines being arranged consecutively by physical word line identifiers, where n≧2.

[0069] In this implementation, a memory controller is configured to obtain a plurality of data to be written into a memory array, and to map n physical word line identifiers to n virtual word line identifiers, wherein the physical word line identifiers corresponding to m adjacent virtual word line identifiers are spaced apart from each other, where 2≦m≦n; the memory controller is configured to generate check data based on the data corresponding to the m adjacent virtual word line identifiers, and the check data is configured to check and restore the data corresponding to the m adjacent virtual word line identifiers.

[0070] In some implementations, the memory controller is configured to: obtain a preset mapping relationship table, where the mapping relationship table includes a mapping correspondence between physical word line identifiers and virtual word line identifiers; and obtain n virtual word line identifiers corresponding to the n physical word line identifiers by matching the n physical word line identifiers with the mapping relationship table.

[0071] In some implementations, the memory controller is configured to retrieve the pre-configured mapping relationship table from a static random access memory.

[0072] In some implementations, the reference numbers of the physical word line identifiers are distributed among the physical word line identifiers corresponding to the m adjacent virtual word line identifiers, respectively.

[0073] In some implementations, the memory controller is configured to obtain a preset algorithm, the preset algorithm being configured to map physical word line identifiers to virtual word line identifiers and to substitute the n physical word line identifiers into the preset algorithm to obtain n virtual word line identifiers corresponding to the n physical word line identifiers.

[0074] In some implementations, the memory controller is configured to process data corresponding to m adjacent virtual word line identifiers through a first operator to obtain check data, and when there is a data read failure in the data corresponding to the m adjacent virtual word line identifiers, the check data is configured to check and restore the data that failed to be read through a second operator, and the first operator and the second operator are operators whose operation logics are opposite to each other.

[0075] In some implementations, the memory controller is configured to send a first read instruction to the memory, the first read instruction including a first physical word line identifier corresponding to first data to be read, and receive a data read result returned by the memory; The memory controller is configured to, when the data read result indicates that the first data corresponding to the first physical word line identifier fails to be read, determine a first virtual word line identifier corresponding to the first physical word line identifier, and obtain target check data corresponding to the first virtual word line identifier for restoring the first data that failed to be read.

[0076] In some implementations, the memory controller is configured to: obtain target check data corresponding to a first virtual word line identifier; obtain a second virtual word line identifier aligned with the first virtual word line identifier for generating the target check data; and determine a second physical word line identifier corresponding to the second virtual word line identifier; The memory controller is configured to send a second read command to the memory, the second read command including a second physical word line identifier and configured to instruct the memory to read data stored in a row of memory cells coupled to a word line corresponding to the second physical word line identifier, receive second data returned by the memory and corresponding to the second physical word line identifier, and restore the first data that failed to be read based on the target check data and the second data.

[0077] In some implementations, when reading first data corresponding to a first physical word line identifier, the memory controller: determines a first virtual word line identifier corresponding to the first physical word line identifier; obtains target check data corresponding to the first virtual word line identifier; obtains a second virtual word line identifier aligned with the first virtual word line identifier for generating the target check data; and determines a second physical word line identifier corresponding to the second virtual word line identifier; sending a read instruction to the memory, the read instruction configured to instruct reading data stored in a row of memory cells coupled to a word line corresponding to the first physical word line identifier and the second physical word line identifier; The memory controller is configured to receive a data read result returned by the memory, and when the data read result indicates that the first data fails to be read, use the target check data and second data corresponding to the second physical word line identifier to restore the first data that failed to be read.

[0078] 7 is a flowchart of a method for operating a memory system according to an exemplary implementation of the present application. Take the method as an example that the method is applied to a memory system, as shown in FIG. 7, the method includes:

[0079] Step 701 obtains a plurality of data to be written into the memory array.

[0080] The plurality of data are data to be written into a memory array of the memory. In some implementations, the memory array includes n memory cell rows, each coupled to n word lines, where the i-th memory cell row is coupled to the i-th word line, and i is less than a positive integer equal to n. The plurality of data are data to be written into the memory cell rows. The n word lines coupled to the n memory cell rows are sequentially arranged by physical word line identifiers. That is, each of the n word lines corresponds to a physical word line identifier to uniquely indicate the word line according to the order of the word line arrangement.

[0081] In some implementations, a memory controller in a memory system receives the data to be written into the memory array. Alternatively, the memory controller actively obtains the data to be written into the memory array periodically.

[0082] In some implementations, the memory controller retrieves the plurality of data and then writes the plurality of data into the memory array based on the physical word line identifier.

[0083] Step 702 writes check data into the memory, the check data being data generated based on data corresponding to the spaced apart physical word line identifiers and configured to check and restore the data.

[0084] The memory controller first determines the arrangement of multiple data to be written into memory cell rows, i.e., data corresponding to physical word line identifiers corresponding to the memory cell rows to be written, for example, data a, data b, data c, and data d, where data a is written into the memory cell row coupled to word line 1, data b is written into the memory cell row coupled to word line 2, data c is written into the memory cell row coupled to word line 3, and data d is written into the memory cell row coupled to word line 4.

[0085] The memory controller generates check data based on the arrangement of multiple data to be written in the memory cell row, and writes the check data to the memory. The check data is generated based on data corresponding to the spaced physical word line identifiers. That is, taking the above-mentioned data a, data b, data c, and data d as an example, since word line 2 is spaced between word line 1 and word line 3, and word line 3 is spaced between word line 2 and word line 4, check data is generated based on data a and data c, and check data is generated based on data b and data d.

[0086] In some implementations, when generating check data based on data corresponding to spaced-apart physical word line identifiers, first, n physical word line identifiers are mapped to n virtual word line identifiers, where the physical word line identifiers corresponding to adjacent m virtual word line identifiers are spaced apart from each other, where 2≦m≦n, and the check data is generated based on the data corresponding to the adjacent m virtual word line identifiers and is configured to check and restore the data corresponding to the adjacent m virtual word line identifiers. As an example, m, which should be 2, is taken as an example for explanation. That is, the check data is generated based on data corresponding to two adjacent virtual word line identifiers, where the physical word line identifiers corresponding to the two adjacent virtual word line identifiers are spaced apart from each other.

[0087] In some examples, the m virtual word line identifiers include adjacent first and second virtual word line identifiers, where the first virtual word line identifier is mapped to a first physical word line identifier, the second virtual word line identifier is mapped to a second physical word line identifier, and at least one physical word line identifier is distributed between the first and second physical word line identifiers.

[0088] In some implementations, the physical word line identifiers are distributed between the first physical word line identifier and the second physical word line identifier. That is, by spacing the physical word lines, check data is generated based on data corresponding to the spaced-apart physical word lines. Alternatively, multiple physical word line identifiers are distributed between the first physical word line identifier and the second physical word line identifier. For example, reference numbers of the physical word line identifiers are distributed among physical word line identifiers corresponding to m adjacent virtual word line identifiers. That is, by spacing the multiple physical word lines, check data is generated for data corresponding to the spaced-apart physical word lines. Alternatively, the number of physical word line identifiers distributed between the first physical word line identifier and the second physical word line identifier is an indeterminate number determined based on an algorithm. That is, by spacing one or more physical word lines, check data is generated for data corresponding to the spaced-apart physical word lines.

[0089] By way of example, when mapping between physical word line identifiers and virtual word line identifiers, at least one of the following approaches may be employed:

[0090] First, a preset mapping relationship table including a mapping relationship between physical word line identifiers and virtual word line identifiers is obtained, and n virtual word line identifiers corresponding to the n physical word line identifiers are obtained by matching the n physical word line identifiers with the mapping relationship table.

[0091] In some implementations, the mapping relationship table is stored in a static random access memory (SRAM), and the preset mapping relationship table is retrieved from the SRAM. Alternatively, the mapping relationship table is stored in a 3D NAND memory, and the memory controller retrieves the preset mapping relationship table from the 3D NAND.

[0092] In some implementations, the correspondence between the physical word line identifier and the virtual word line identifier is stored in the mapping relationship table in the form of a key-value pair. For example, physical word line identifier 1 is stored in the form of a key, and virtual word line identifier 1 corresponding to physical word line identifier 1 is stored in the form of a value. Physical word line identifier 2 is stored in the form of a key, and virtual word line identifier 6 corresponding to physical word line identifier 1 is stored in the form of a value. Figure 8 shows a schematic diagram of a mapping relationship table according to an exemplary implementation of the present application. As shown in FIG. 8, virtual word line identifiers 810 marked as 1-5 correspond to physical word line identifiers 820 marked as 1 / 6 / 11 / 16 / 21, respectively, and the corresponding data 830 is data 1 / data 6 / data 11 / data 16 / data 21, respectively, and the generated check data 840 is parity 1; virtual word line identifiers 810 marked as 6-10 correspond to physical word line identifiers 820 marked as 26 / 31 / 36 / 41 / 46, respectively, and the corresponding data 830 is data 26 / data 31 / data 36 / data 41 / data 46, respectively, and the generated check data 840 is parity 2, and so on.

[0093] It should be noted that in the above mapping relationship table, as an example, the physical word line identifiers corresponding to two adjacent virtual word line identifiers are spaced apart by four physical word line identifiers. However, the above number of separations is merely an illustrative example. In some implementations, taking the check data generated by five word lines as an example, virtual word line identifiers 1-5 can also correspond to physical word line identifiers 1 / 3 / 5 / 7 / 9, virtual word line identifiers 6-10 correspond to physical word line identifiers 2 / 4 / 6 / 8 / 10, and so on. That is, there is one physical word line identifier spaced apart between the physical word line identifiers corresponding to two adjacent virtual word line identifiers. Alternatively, virtual word line identifiers 1-5 can also correspond to physical word line identifiers 1 / 4 / 7 / 10 / 13, and virtual word line identifiers 6-10 correspond to physical word line identifiers 2 / 5 / 8 / 11 / 14, and so on. That is, there are two physical word line identifiers spaced apart between the physical word line identifiers corresponding to two adjacent virtual word line identifiers. Alternatively, there may be any number of physical word line identifiers spaced apart between the physical word line identifiers corresponding to two adjacent virtual word line identifiers based on ensuring a one-to-one correspondence between the virtual word line identifiers and the physical word line identifiers. Implementations of the present application do not limit the number of separations. In some implementations, the number of separations between the physical word line identifiers corresponding to two different groups of adjacent virtual word line identifiers may be different.

[0094] Second, a preset algorithm configured to map physical word line identifiers to virtual word line identifiers is obtained, and the n physical word line identifiers are substituted into the preset algorithm to obtain n virtual word line identifiers corresponding to the n physical word line identifiers.

[0095] In some implementations, the pre-stored preset algorithms are retrieved from SRAM.

[0096] In some examples, the preset algorithm includes parameter assignment bits for the physical word line identifier, and after substituting the physical word line identifier into the parameter assignment bits, a virtual word line identifier corresponding to the physical word line identifier is output through algorithmic processing of the preset algorithm.

[0097] Taking 50 physical word line identifiers as an example, the physical word line identifiers are in a series of 1 to 50, and the preset algorithm is implemented as follows: when the physical word line identifier is odd, the virtual word line identifier is equal to the physical word line identifier, and when the physical word line identifier is even, the virtual word line identifier is equal to 50 minus the value of the physical word line identifier.

[0098] It should be noted that the above method of mapping between physical word line identifiers and virtual word line identifiers is merely an illustrative example and is not limiting within this implementation of the present application.

[0099] In some implementations, when generating the check data, at least one of the following approaches is adopted:

[0100] 1. An operation is performed on data corresponding to adjacent m virtual word line identifiers through an exclusive OR algorithm to obtain check data.

[0101] In some implementations, the check data may be generated by a parity check. For example, for any data, the total number of bits that are 1 among each bit of the data under the binary code is determined, and then check data is generated to record the parity of that total number to facilitate subsequent checking of the read data by the check data.

[0102] 2. Data corresponding to adjacent m virtual word line identifiers are processed through a first operator to obtain check data, where when there is a data read failure in the data corresponding to the adjacent m virtual word line identifiers, the check data is configured to check and restore the data that failed to be read through a second operator, and the first operator and the second operator are operators whose operation logics are opposite to each other.

[0103] 9 is a schematic diagram of a check data generation process according to an exemplary implementation of the present application. As shown in FIG. 9, K pieces of data 900 to be written into a memory are first obtained, where data 1 is written into physical word lines 1-5, data 2 is written into physical word lines 6-10, and so on, and data K is written into physical word lines k-k+4. First, physical word line identifiers are mapped to virtual word line identifiers by mapping 910, where physical word line identifiers 1-5 are mapped to virtual word line identifiers 1 / 6 / 11 / 16 / 21, and physical word line identifiers 6-10 are mapped to virtual word line identifiers 2 / 7 / 12 / 17 / 22. After the mapping between the virtual word line identifiers and the physical word line identifiers, data 920 of consecutive virtual word line identifiers are obtained. For example, data of virtual word line identifiers 1-5 are obtained, and check data 1 is obtained by accumulation 930. The data for virtual word line identifiers 6-10 is obtained, and check data 2 is obtained by accumulating 930, and so on.

[0104] In some implementations, a logic analyzer performs consecutive write operations on the memory, and observes whether the NAND write addresses sent by the memory controller on the logic analyzer are non-consecutive WL numbers. If the addresses are non-consecutive WL numbers, it proves that the method of operating a memory system according to the implementation of the present application is used.

[0105] In summary, according to the method provided by the implementation of the present application, virtual word line identifiers corresponding to physical word line identifiers are generated by setting a mapping relationship between the physical word line identifiers and the virtual word line identifiers so that the physical word line identifiers corresponding to adjacent virtual word line identifiers are spaced apart, i.e., not adjacent. Check data is generated using data corresponding to a plurality of adjacent virtual word line identifiers. That is, the check data is generated using data corresponding to a plurality of non-adjacent physical word line identifiers, thereby reducing the influence on the check data caused by the mutual effect between adjacent physical word lines, increasing the success rate of data recovery, and improving the reliability of data storage and data reading.

[0106] According to the method provided in this implementation, by setting a mapping relationship table in advance, a one-to-one correspondence between physical word line identifiers and virtual word line identifiers is intuitively implemented, so that physical word line identifiers are mapped to virtual word line identifiers through the mapping relationship table, which improves the efficiency of determining virtual word line identifiers.

[0107] The method provided in this implementation matches physical word line identifiers with virtual word line identifiers according to a preset algorithm, thereby mapping physical word line identifiers to virtual word line identifiers according to a preset algorithm, which improves the efficiency of determining virtual word line identifiers.

[0108] In an exemplary implementation, after the check data is generated and stored, a process of reading the stored data is further included. Figure 10 is a flowchart of a method for operating a memory system according to another exemplary implementation of the present application. It is taken as an example that the method is applied to the memory system shown in Figure 1 and is performed after step 702 shown in Figure 7. The method includes:

[0109] Step 1001: Send a first read command to the memory, where the first read command includes a first physical word line identifier corresponding to a first data to be read.

[0110] From the memory's perspective, data is still accessed by a physical word line identifier, so when reading data, a first read command having a first physical word line identifier is sent to the memory, and the data read is performed in the row of memory cells coupled to the word line corresponding to the first physical word line identifier.

[0111] In some implementations, when a computing device on which the memory system is located receives a data read operation, a first read command is sent by the memory controller to the memory to read first data stored in a row of memory cells coupled to a word line corresponding to the first physical word line identifier.

[0112] In some implementations, the data reading process corresponding to the first read instruction includes at least one of the following situations:

[0113] First, if reading the data fails, the virtual word line identifier is determined and check data is obtained.

[0114] Step 1021 receives the data read result returned by the memory.

[0115] If the first data can be successfully read, the data read result includes the first data read from the row of memory cells coupled to the word line corresponding to the first physical word line identifier. If the first data cannot be successfully read, for example, when the row of memory cells coupled to the word line corresponding to the first physical word line identifier is damaged, the first data cannot be successfully read and the data read result includes an indicator of a failure to read the first data.

[0116] That is, the data read result includes at least one of: 1. the data obtained from the read; and 2. an indicator of a read failure.

[0117] In some implementations, the first read instruction is configured to read a plurality of first physical word lines. Then, the first data includes sub-data corresponding to the plurality of physical word lines, and the data read result may further include an indicator indicating that some of the data was not read successfully. In some implementations, the data read result includes first physical word line identifiers corresponding to the data that was not read successfully and other data that was not read successfully.

[0118] Step 1031: if the data read result indicates that reading the first data corresponding to the first physical word line identifier fails, determine a first virtual word line identifier corresponding to the first physical word line identifier.

[0119] In some examples, when generating check data, the check data is generated by mapping physical word line identifiers to virtual word line identifiers. Thus, a first physical word line identifier is mapped in the same mapping manner to determine a corresponding first virtual word line identifier. For example, when generating check data, physical word line identifiers are mapped to virtual word line identifiers through a mapping relationship table. If the first data cannot be read, a first virtual word line identifier corresponding to the first physical word line identifier is determined through the mapping relationship table. When generating check data, physical word line identifiers are mapped to virtual word line identifiers through a preset algorithm. If the first data cannot be read, a first virtual word line identifier corresponding to the first physical word line identifier is determined by the preset algorithm.

[0120] Step 1041: Obtain target check data corresponding to the first virtual word line identifier for restoring the first data that failed to be read.

[0121] In some implementations, target check data corresponding to the first virtual word line identifier is read from the memory to check the first data.

[0122] In some implementations, target check data corresponding to a first virtual word line identifier is obtained, and a second virtual word line identifier that is matched with the first virtual word line for generating the target check data is obtained. In some examples, during the check data storage process, physical word line identifiers and virtual word line identifiers corresponding to the check data and the data for generating the check data are correspondingly stored, and then the corresponding second virtual word line identifier in the target check data including the first virtual word line identifier is obtained to determine the second physical word line identifier corresponding to the second virtual word line identifier. In some examples, when generating the check data, the physical word line identifiers are mapped to the virtual word line identifiers through mapping, and the second virtual word line identifiers are mapped to the corresponding second physical word line identifiers through reverse mapping. For example, when generating the check data, the physical word line identifiers are mapped to the virtual word line identifiers through a mapping relationship table, and the second virtual word line identifiers are still mapped to the second physical word line identifiers through the mapping relationship table. When generating check data, a physical word line identifier is mapped to a virtual word line identifier through a preset algorithm, and then the second virtual word line identifier is substituted by the preset algorithm to determine a corresponding second physical word line identifier.

[0123] A second read instruction is sent to the memory, the second read instruction including a second physical word line identifier, and the second read instruction is configured to instruct the memory to read data stored in a row of memory cells coupled to a word line corresponding to the second physical word line identifier, receive second data corresponding to the second physical word line identifier returned by the memory, and recover the first data that was unsuccessfully read based on the target check data and the second data.

[0124] 11 is a schematic diagram of a data check and restore process according to an exemplary implementation of the present application. As shown in FIG. 11, when a memory controller 1101 sends a read command to a memory 1102 instructing the memory controller 1102 to read data corresponding to physical word line identifiers 1-5, the memory controller 1102 feeds back to the memory controller 1101 that the data corresponding to physical word line identifier 5 fails to be read. Then, the memory controller 1101 first determines a virtual word line identifier 21 corresponding to the physical word line identifier 5 through mapping 1110, and determines check data n corresponding to the virtual word line identifier 21 through check data lookup 1120. Another virtual word line identifier p constituting the check data n is obtained through searching data for generating check data n 1130, and a physical word line identifier q corresponding to the virtual word line identifier p is determined through mapping 1140. The memory controller 1101 sends a read command to the memory controller 1102 instructing the memory controller 1102 to read data corresponding to the physical word line identifier q. After the memory 1102 feeds back the data q to the memory controller 1101, the memory controller 1101 checks and restores the data corresponding to the physical word line identifier 5.

[0125] In the second way, the target check data and the second data are acquired in advance, and when the first data fails to be read, a check is performed through the target check data and the second data.

[0126] Step 1022: determine a first virtual word line identifier corresponding to the first physical word line identifier, and obtain target check data corresponding to the first virtual word line identifier.

[0127] In some implementations, when generating check data, physical word line identifiers are mapped to virtual word line identifiers through a mapping relationship table. If the first data cannot be read, a first virtual word line identifier corresponding to the first physical word line identifier is determined through the mapping relationship table. When generating check data, physical word line identifiers are mapped to virtual word line identifiers through a preset algorithm. If the first data cannot be read, a first virtual word line identifier corresponding to the first physical word line identifier is determined through the preset algorithm.

[0128] Step 1032: Obtain a second virtual word line identifier that is matched with the first virtual word line identifier for generating target check data, and determine a second physical word line identifier that corresponds to the second virtual word line identifier.

[0129] In some implementations, target check data corresponding to a first virtual word line identifier is obtained, and a second virtual word line identifier that is matched with the first virtual word line for generating the target check data is obtained. In some examples, during the check data storage process, physical word line identifiers and virtual word line identifiers corresponding to the check data and the data for generating the check data are correspondingly stored, and then the corresponding second virtual word line identifier in the target check data that includes the first virtual word line identifier is obtained to determine the second physical word line identifier that corresponds to the second virtual word line identifier. In some examples, when generating the check data, the physical word line identifier is mapped to the virtual word line identifier by mapping, and the second virtual word line identifier is mapped to the corresponding second physical word line identifier by reverse mapping.

[0130] Step 1042 sends a second read command to the memory, the second read command including a second physical word line identifier.

[0131] The second read command is configured to instruct the memory to read data stored in a row of memory cells coupled to a word line corresponding to the second physical word line identifier.

[0132] Step 1052 receives the data read result returned by the memory.

[0133] In some examples, the data read results include results of reading a row of memory cells coupled to a word line corresponding to the first physical word line identifier and results of reading a row of memory cells coupled to a word line corresponding to the second physical word line identifier.

[0134] In the implementation of the present application, if the first data fails to be read and the second data is successful, the first data is checked and restored.

[0135] Step 1062: If the data read result indicates that the first data fails to be read, use the target check data and second data corresponding to the second physical word line identifier to restore the first data that failed to be read.

[0136] In summary, according to the method provided by the implementation of the present application, virtual word line identifiers corresponding to physical word line identifiers are generated by setting a mapping relationship between the physical word line identifiers and the virtual word line identifiers so that the physical word line identifiers corresponding to adjacent virtual word line identifiers are spaced apart, i.e., not adjacent. Check data is generated using data corresponding to a plurality of adjacent virtual word line identifiers. That is, the check data is generated using data corresponding to a plurality of non-adjacent physical word line identifiers, thereby reducing the influence on the check data caused by the mutual effect between adjacent physical word lines, increasing the success rate of data recovery, and improving the reliability of data storage and data reading.

[0137] In the method provided by this implementation, in the case of data read failure, the data is checked and restored using check data. On the one hand, it avoids the fact that the check data cannot be checked and restored due to the mutual effect between adjacent word lines. On the other hand, it improves the security and accuracy of data storage.

[0138] 12 is a schematic structural diagram of a memory controller according to an exemplary implementation of the present application. The method for operating a memory system provided in the implementation of the present application is mainly implemented by the memory controller. As shown in FIG. 12, the memory controller 1200 includes a memory interface 1210, a memory controller 1220, a configuration register 1230, and a bus interface 1240.

[0139] The memory interface 1210 is configured to connect to the memory and convert data exchanges on the bus into data exchanges that conform to the storage timing of the storage medium.

[0140] The memory controller 1220 is configured to control the functions of the memory controller as a whole, control the memory interface to ensure correct completion of data exchange between the memory and the internal bus of the microcontroller unit (MCU), and is responsible for managing interrupt signals.

[0141] Configuration registers 1230 are configured to configure the functionality of the memory controller, such as the timing configuration of the memory interface.

[0142] The bus interface 1240 connects to the MCU's internal bus and is generally configured to: 1. transmit configuration information for the memory controller; and 2. transmit stored data that conforms to the memory controller's interface.

[0143] In some implementations, memory controller 1200 includes at least two interfaces, including at least one interface for communicating with a memory and further including at least one front-end interface for communicating with a host.

[0144] The implementations of the present application provide a control circuit, which includes a programmable logic circuit and / or program instructions and can be used to implement the methods of operating a memory system provided in the above implementations of the present application.

[0145] An implementation of the present application provides a computer-readable storage medium having stored thereon instructions that, when executed on a memory controller, perform a method for operating a memory system as provided in the above implementation of the present application.

[0146] In this application, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance. Unless expressly specified otherwise, the term "at least one" means "one or more" and the term "plurality" means "two or more."

[0147] The term "and / or" in this application is merely a conjunction of related objects, meaning that three relationships are possible. For example, A and / or B means A only, both A and B, and B only. Additionally, the character " / " in this specification generally indicates that the contextual objects form an "or" relationship.

[0148] The above description is only an exemplary implementation of the present application, and does not limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this specification shall fall within the protection scope of the present application. [Explanation of symbols]

[0149] 10 Memory System 100 memory 101 Substrate 102 stack layers 103 Gate conductive layer 104 Inter-gate dielectric layer 105 channel structure 110 Memory Array 111 Memory String 112 memory cells 113 Source Select Gate (SSG) 114 Drain Select Gate (DSG) 115 bit lines 116 DSG Line 117 SSG Line 118 Source Line (SL) 120 Word Line 130 Peripheral Circuits Page 131 Buffer / Sense Amplifier 132 Column Decoder / Bit Line (BL) Driver 133 Row decoder / word line (WL) driver 134 Voltage Generator 135 Control Logic Unit 136 registers 137 Interface 138 Data Bus 140 blocks 200 Memory Controller 300 Host 400 memory card 410 Connector 500 Solid State Disks (SSD) 510 Connector 810 Virtual Word Line Identifier 820 Physical Word Line Identifier 830 Data 840 Check Data 1101 Memory Controller 1102 memory 1200 Memory Controller 1210 memory interface 1220 memory controller 1230 Configuration Register 1240 bus interface

Claims

1. one or more memories, the memory comprising a memory array, the memory array coupled to n word lines, the n word lines arranged consecutively by physical word line identifiers, where n≧2; a memory controller coupled to the memory and configured to control the memory; wherein the memory controller obtaining a plurality of data to be written into the memory array; mapping n physical word line identifiers to n virtual word line identifiers, wherein the physical word line identifiers, each corresponding to m adjacent virtual word line identifiers, are spaced apart from one another, where 2≦m≦n; generating check data based on the data corresponding to the m adjacent virtual word line identifiers, the check data being configured to check and restore the data corresponding to the m adjacent virtual word line identifiers; a memory system configured to:

2. The memory controller acquires a preset mapping relationship table, the mapping relationship table comprising a mapping correspondence between the physical word line identifiers and the virtual word line identifiers; obtaining the n virtual word line identifiers corresponding to the n physical word line identifiers by matching the n physical word line identifiers with the mapping relationship table; The system of claim 1 , configured to:

3. The system of claim 2 , wherein the memory controller is configured to retrieve the pre-configured mapping relationship table from a static random access memory.

4. 2. The system of claim 1, wherein the reference numbers of the physical word line identifiers are distributed among the physical word line identifiers corresponding to the m adjacent virtual word line identifiers, respectively.

5. The memory controller: obtaining a preset algorithm, the preset algorithm configured to map the physical word line identifiers to the virtual word line identifiers; Substituting the n physical word line identifiers into the preset algorithm to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers; The system of claim 1 , configured to:

6. The memory controller: configured to process the data corresponding to the m adjacent virtual word line identifiers through a first operator to obtain the check data; When there is a data read failure in the data corresponding to the adjacent m virtual word line identifiers, the check data is configured to check and restore the data that has failed to be read through a second operator; The system of claim 1 , wherein the first operator and the second operator are operators whose operation logics are opposites.

7. The memory controller: sending a first read command to the memory, the first read command comprising a first physical word line identifier corresponding to first data to be read; receiving a data read result returned by said memory; configured to: The memory controller: determining a first virtual word line identifier corresponding to the first physical word line identifier when the data read result indicates that the read of the first data corresponding to the first physical word line identifier fails; obtaining target check data corresponding to the first virtual word line identifier for recovering the first data that failed to be read; 7. The system of claim 1, configured to:

8. The memory controller: obtaining the target check data corresponding to the first virtual word line identifier; obtaining a second virtual word line identifier that is matched with the first virtual word line identifier for generating the target check data; determining a second physical word line identifier corresponding to the second virtual word line identifier; configured to: The memory controller: sending a second read instruction to the memory, the second read instruction comprising the second physical word line identifier and configured to instruct the memory to read the data stored in a row of memory cells coupled to the word line corresponding to the second physical word line identifier; receiving second data returned by the memory and corresponding to the second physical word line identifier; and recovering the first data that was unsuccessfully read based on the target check data and the second data; The system of claim 7 , configured to:

9. The memory controller: determining a first virtual word line identifier corresponding to a first physical word line identifier when reading first data corresponding to the first physical word line identifier; obtaining the target check data corresponding to the first virtual word line identifier; obtaining a second virtual word line identifier that is matched with the first virtual word line identifier for generating the target check data; determining a second physical word line identifier corresponding to the second virtual word line identifier; sending a read command to the memory, the read command configured to instruct reading the data stored in a row of memory cells coupled to the word lines corresponding to the first physical word line identifier and the second physical word line identifier; configured to: The memory controller: receiving a data read result returned by the memory; When the data read result indicates that the reading of the first data fails, using the target check data and the second data corresponding to the second physical word line identifier to restore the first data that failed to be read.

7. The system of claim 1, configured to:

10. 1. A method of operating a memory system, comprising: the memory system comprises a memory having a memory array, the memory array coupled to n word lines, the n word lines arranged consecutively by physical word line identifiers, where n≧2; The method comprises: obtaining a plurality of data to be written into the memory array; writing check data into the memory, the check data being generated based on data corresponding to spaced apart physical word line identifiers, and configured to check and restore the data; A method comprising:

11. before the step of writing the check data into the memory, mapping n physical word line identifiers to n virtual word line identifiers, wherein the physical word line identifiers corresponding to m adjacent virtual word line identifiers are spaced apart from one another, where 2≦m≦n; generating the check data based on data corresponding to the m adjacent virtual word line identifiers, the check data being configured to check and restore the data corresponding to the m adjacent virtual word line identifiers; The method of claim 10 further comprising:

12. said mapping the n physical word line identifiers to the n virtual word line identifiers comprises: obtaining a preset mapping relationship table, the mapping relationship table comprising a mapping correspondence between the physical word line identifiers and the virtual word line identifiers; obtaining the n virtual word line identifiers corresponding to the n physical word line identifiers by matching the n physical word line identifiers with the mapping relationship table; The method of claim 11 , comprising:

13. 13. The method of claim 12, wherein the step of retrieving the pre-configured mapping relationship table comprises retrieving the pre-configured mapping relationship table from a static random access memory.

14. The method of claim 11 , wherein the reference numbers of the physical word line identifiers are distributed among the physical word line identifiers corresponding to the m adjacent virtual word line identifiers, respectively.

15. said mapping the n physical word line identifiers to the n virtual word line identifiers comprises: obtaining a preset algorithm, the preset algorithm configured to map the physical word line identifiers to the virtual word line identifiers; substituting the n physical word line identifiers into the preset algorithm to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers; The method of claim 11 , comprising:

16. generating the check data based on the data corresponding to the m adjacent virtual word line identifiers comprises processing the data corresponding to the m adjacent virtual word line identifiers through a first operator to obtain the check data; When there is a data read failure in the data corresponding to the adjacent m virtual word line identifiers, the check data is configured to check and restore the data that has failed to be read through a second operator; The method of claim 11 , wherein the first operator and the second operator are operators whose operation logics are opposites.

17. After writing the check data to the memory, sending a first read command to the memory, the first read command comprising a first physical word line identifier corresponding to first data to be read; receiving a data read result returned by the memory; determining a first virtual word line identifier corresponding to the first physical word line identifier when the data read result indicates that the reading of the first data corresponding to the first physical word line identifier fails; obtaining target check data corresponding to the first virtual word line identifier for recovering the first data that failed to be read; 17. The method of any one of claims 11 to 16, further comprising:

18. obtaining the target check data corresponding to the first virtual word line identifier for recovering the first data that failed to be read, obtaining the target check data corresponding to the first virtual word line identifier; obtaining a second virtual word line identifier that is matched with the first virtual word line identifier for generating the target check data; determining a second physical word line identifier corresponding to the second virtual word line identifier; sending a second read instruction to the memory, the second read instruction comprising the second physical word line identifier and configured to instruct the memory to read the data stored in a row of memory cells coupled to the word line corresponding to the second physical word line identifier; receiving second data returned by the memory and corresponding to the second physical word line identifier; recovering the first data that failed to be read based on the target check data and the second data; The method of claim 17, comprising:

19. generating the check data based on the data corresponding to the m adjacent virtual word line identifiers; sending a first read command to the memory, the first read command comprising a first physical word line identifier corresponding to the first data to be read; determining a first virtual word line identifier corresponding to the first physical word line identifier; obtaining the target check data corresponding to the first virtual word line identifier; obtaining a second virtual word line identifier that is matched with the first virtual word line identifier for generating the target check data; determining a second physical word line identifier corresponding to the second virtual word line identifier; sending a second read instruction to the memory, the second read instruction comprising the second physical word line identifier and configured to instruct the memory to read the data stored in a row of memory cells coupled to the word line corresponding to the second physical word line identifier; receiving a data read result returned by the memory; when the data read result indicates that the reading of the first data fails, using the target check data and the second data corresponding to the second physical word line identifier to restore the first data that failed to be read; 17. The method of any one of claims 11 to 16, further comprising:

20. A computer-readable storage medium having stored thereon instructions that, when executed on a memory controller, implement the method for operating the memory system of any one of claims 1 to 9.

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