Display device

Abstract

The display device includes a first substrate including first to third light-emitting regions and non-light-emitting regions surrounding the first to third light-emitting regions; first to third pixel electrodes located in the first to third light-emitting regions on the first substrate, respectively; a pixel defining film located in the non-light-emitting regions on the first substrate and defining peripheral openings that partially overlap the non-light-emitting regions; a second substrate including first to third light-projecting regions and a light-shielding region surrounding the first to third light-projecting regions; a bank layer located in the light-shielding region on one surface of the second substrate facing the pixel defining film and defining first openings that respectively overlap the first to third light-projecting regions, and second openings that overlap the light-shielding regions and each have a polygonal planar shape; and a color conversion layer located in the first openings and including color conversion particles.

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a display device that provides visual information. [Background technology]

[0002] Flat panel displays are being used as a display device to replace cathode ray tube displays due to their characteristics such as light weight and thinness. Representative examples of such flat panel displays include liquid crystal displays (LCDs) and organic light emitting displays (OLEDs).

[0003] Recently, organic light-emitting display devices have been developed that include an organic light-emitting element having an organic material and a color conversion layer having color conversion particles. The color conversion layer converts the wavelength of light emitted from the organic light-emitting element, thereby emitting light having a color different from that of the incident light.

[0004] The information disclosed in this Background is intended to enhance understanding of the background and therefore the information discussed in this Background does not constitute prior art. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device in which defects are improved.

[0006] However, the purpose of the present invention is not limited to such a purpose, and various extensions are possible without departing from the spirit and scope of the present invention. [Means for solving the problem]

[0007] In order to achieve the above object, a display device according to the present invention includes a first substrate having first to third light-emitting regions and non-light-emitting regions surrounding the first to third light-emitting regions; first to third pixel electrodes located in the first to third light-emitting regions, respectively, on the first substrate; a pixel defining film located in the non-light-emitting regions on the first substrate and defining peripheral openings that partially overlap the non-light-emitting regions; a second substrate having first to third light-transmitting regions and a light-shielding region surrounding the first to third light-transmitting regions; a bank layer located in the light-shielding region on one surface of the second substrate facing the pixel defining film and defining first openings that respectively overlap the first to third light-transmitting regions, and second openings that overlap the light-shielding regions and each have a polygonal planar shape; and a color conversion layer located in the first openings and including color conversion particles.

[0008] The pixel-defining layer may further include a planarization layer located between the first substrate and the pixel-defining layer and including an organic material, the peripheral opening exposing a portion of an upper surface of the planarization layer.

[0009] The pixel defining layer extends continuously along at least two adjacent light emitting regions among the first, second, and third light emitting regions.

[0010] The first to third light-emitting regions are repeatedly arranged along a first direction and a second direction intersecting the first direction, and the pixel defining layer includes a first pattern portion covering an edge of the first pixel electrode, a second pattern portion covering an edge of the second pixel electrode, a third pattern portion covering an edge of the third pixel electrode, a first connecting portion overlapping a portion of the first pixel electrode and connecting the first to third pattern portions, and a second connecting portion connecting two adjacent pattern portions of the first to third pattern portions and including a portion extending in the first direction and a portion extending in the second direction.

[0011] The pixel defining layer further defines a central opening exposing a portion of the top surface of each of the first to third pixel electrodes.

[0012] The pixel defining layer may include an inorganic material or an organic material.

[0013] The pixel defining layer includes an organic material containing at least one selected from the group consisting of a black pigment, a black dye, and carbon black.

[0014] Each of the second openings has a rectangular planar shape.

[0015] The bank layer includes a first partition located in at least one of the second openings, and a second partition formed integrally with the first partition and constituting the remaining portion excluding the first partition.

[0016] The second opening where the first partition wall is located is divided into two openings by the first partition wall.

[0017] The bank layer further defines a third opening extending in a first direction and a fourth opening extending in a second direction intersecting the first direction.

[0018] The first to third light projection areas are repeatedly arranged along the first direction and the second direction, the third opening is located adjacent to the first opening that overlaps the second light projection area, and the fourth opening is located between the first openings that overlap the first and third light projection areas, respectively.

[0019] The first light-projected area overlaps the first light-emitting area, the second light-projected area overlaps the second light-emitting area, and the third light-projected area overlaps the third light-emitting area.

[0020] The area of the first light-emitting region is larger than the area of the first light-projecting region, the area of the second light-emitting region is larger than the area of the second light-projecting region, and the area of the third light-emitting region is larger than the area of the third light-projecting region.

[0021] The first to third light-emitting regions emit light of a first color, the first light-projecting region transmits light of a second color different from the first color, the second light-projecting region transmits light of a third color different from the first color and the second color, and the third light-projecting region transmits light of the first color.

[0022] The second substrate further includes a color filter layer located on one side thereof, and a protective layer including an inorganic material located on the one side of the color filter layer facing the bank layer.

[0023] The bank layer is located on one surface of the protective layer facing the bank layer, and the second opening exposes the upper surface of the protective layer.

[0024] The pixel defining layer may further include a filling layer containing a light-transmitting material, the filling layer being located between the pixel defining layer and the bank layer, and the second opening may be partially filled with the filling layer.

[0025] In order to achieve the object of the present invention, a display device according to the present invention includes: a first substrate having a light-emitting region, a contact region adjacent to the light-emitting region, and a non-light-emitting region surrounding the light-emitting region and the contact region; a pixel electrode located in the light-emitting region on the first substrate; a pixel defining film located on the first substrate, the pixel defining film defining a central opening in the light-emitting region that exposes a portion of an upper surface of the pixel electrode and a peripheral opening in the non-light-emitting region that is spaced apart from the pixel electrode in a planar manner; a second substrate having a light-projecting region and a light-shielding region surrounding the light-projecting region and overlapping the contact region; a bank layer located on one surface of the second substrate facing the pixel defining film, the bank layer defining a first opening overlapping the light-projecting region and a second opening overlapping the contact region, each of which has a polygonal planar shape; and a color conversion layer located in the first opening and including color conversion particles.

[0026] The contact area is subjected to a laser drilling process.

[0027] The pixel defining layer further includes an insulating pattern located on the first substrate, adjacent to the contact region, and including the same material as the pixel defining layer.

[0028] The insulating pattern is spaced apart from the pixel defining layer in a plan view.

[0029] The insulating pattern entirely overlaps the second opening.

[0030] The insulating pattern is spaced apart from the bank layer on a plane. [Effects of the Invention]

[0031] A display device according to the present invention includes an array substrate and a color conversion substrate disposed on the array substrate. According to one embodiment, the array substrate includes a pixel defining layer having a peripheral opening defined therein that partially overlaps the non-light-emitting region. According to another embodiment, the color conversion substrate includes a bank layer having a second opening defined therein that overlaps the light-shielding region and has a polygonal planar shape. This can improve defects in the display device due to the penetration of foreign matter.

[0032] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawings]

[0033] [Figure 1] FIG. 1 is a perspective view showing a display device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II' of FIG. 1 according to one embodiment. [Figure 3] FIG. 3 is a plan view illustrating an array substrate of the display device of FIGS. 1 and 2 according to an embodiment. [Figure 4] FIG. 4 is an enlarged plan view of area A of FIG. 3 according to one embodiment. [Figure 5] FIG. 5 is a cross-sectional view taken along line II-II' of FIG. 4 according to one embodiment. [Figure 6]FIG. 6 is a cross-sectional view taken along line III-III' of FIG. 4 according to one embodiment. [Figure 7] FIG. 7 is a plan view showing a color conversion substrate of the display device of FIGS. 1 and 2 according to one embodiment. [Figure 8] FIG. 8 is an enlarged plan view of area B of FIG. 7 according to one embodiment. [Figure 9] FIG. 9 is a cross-sectional view taken along line IV-IV' of FIG. 8 according to one embodiment. [Figure 10] FIG. 10 is a plan view showing both area A of FIG. 4 and area B of FIG. 8 according to one embodiment. [Figure 11] FIG. 11 is a cross-sectional view taken along line VV' of FIG. 10 according to one embodiment. [Figure 12] FIG. 12 is a cross-sectional view illustrating a method for manufacturing the array substrate in FIG. 5 according to an embodiment. [Figure 13] FIG. 13 is a cross-sectional view illustrating a method for manufacturing the array substrate in FIG. 5 according to an embodiment. [Figure 14] FIG. 14 is a cross-sectional view illustrating a method for manufacturing the array substrate in FIG. 5 according to an embodiment. [Figure 15] FIG. 15 is a cross-sectional view illustrating a method for manufacturing the array substrate in FIG. 5 according to an embodiment. [Figure 16] 16A to 16C are cross-sectional views showing a method for manufacturing the color conversion substrate in FIG. 9 according to one embodiment. [Figure 17] 17A to 17C are cross-sectional views showing a method for manufacturing the color conversion substrate in FIG. 9 according to one embodiment. [Figure 18] 18A to 18C are cross-sectional views showing a method for manufacturing the color conversion substrate in FIG. 9 according to one embodiment. [Figure 19] 19A to 19C are cross-sectional views showing a method for manufacturing the color conversion substrate in FIG. 9 according to one embodiment. [Figure 20] FIG. 20 is a block diagram showing an electronic device including the display device of FIG. 1 according to one embodiment. [Figure 21] FIG. 21 is a diagram illustrating an example in which the electronic device of FIG. 20 is implemented as a television according to an embodiment. [Figure 22] FIG. 22 is a diagram illustrating an example in which the electronic device of FIG. 20 is implemented as a smartphone according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0034] Hereinafter, a display device according to an embodiment of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements in the drawings, and redundant description of the same elements will be omitted.

[0035] Fig. 1 is a perspective view showing a display device according to an embodiment, and Fig. 2 is a cross-sectional view taken along line II' of Fig. 1 according to an embodiment.

[0036] As shown in FIGS. 1 and 2, a display device 1000 according to an embodiment of the present invention includes an array substrate 100 , a sealing part 350 , a filling layer 300 , and a color conversion substrate 200 .

[0037] The display device 1000 has a rectangular shape on a plane (for example, when viewed perpendicularly to the plane of the display surface of the display device 1000). For example, the display device 1000 includes two first sides extending in a first direction (D1) and two second sides extending in a second direction (D2). The corners where the first sides intersect with the second sides form right angles. However, one embodiment of the present invention is not limited to this, and the corners where the first sides intersect with the second sides of the display device 1000 may form curved surfaces.

[0038] The display device 1000 includes a display area (DA) and a non-display area (NDA). The display area (DA) generates light or adjusts the transmittance of light provided from an external light source to display an image. The non-display area (NDA) does not display an image. The non-display area (NDA) is located on the periphery of the display area (DA). For example, the non-display area (NDA) surrounds the display area (DA) and is located on the periphery (or outside the footprint) of the display area (DA).

[0039] The array substrate 100 includes a substrate, an insulating layer, and elements for displaying images. For example, the elements include semiconductor elements (e.g., transistors), light emitting elements, etc. The array substrate 100 will be described in detail later.

[0040] The color conversion substrate 200 is located on the array substrate 100. The color conversion substrate 200 faces the array substrate 100. The color conversion substrate 200 includes a color conversion layer that converts the wavelength of light emitted from the light emitting elements. The color conversion substrate 200 will be described in detail later.

[0041] The sealing unit 350 is located between the array substrate 100 and the color conversion substrate 200 in the non-display area (NDA). For example, the sealing unit 350 is arranged along the edges of the array substrate 100 and the color conversion substrate 200 in the non-display area (NDA) and surrounds the display area (DA) in a planar manner. Thus, the array substrate 100 and the color conversion substrate 200 are coupled together through the sealing unit 350. The sealing unit 350 includes an organic material. For example, the sealing unit 350 includes an organic material such as an epoxy resin. However, the present invention is not limited thereto, and the sealing unit 350 may include other types of organic materials.

[0042] The filling layer 300 is located between the array substrate 100 and the color conversion substrate 200 in the display area (DA). For example, the filling layer 300 fills the space between the array substrate 100 and the color conversion substrate 200 in the display area (DA). The filling layer 300 includes a light-transmitting material that transmits light. For example, the filling layer 300 includes an organic material. Examples of organic materials used for the filling layer 300 include silicone-based resins and epoxy-based resins. These may be used alone or in combination with each other. In other embodiments, the filling layer 300 may be omitted.

[0043] In this specification, a plane is defined by a first direction (D1) and a second direction (D2) intersecting the first direction (D1). For example, the first direction (D1) is perpendicular to the second direction (D2). Furthermore, a third direction (D3) is perpendicular to both the first direction (D1) and the second direction (D2).

[0044] FIG. 3 is a plan view showing the array substrate of the display device in FIGS.

[0045] As shown in FIGS. 3 and 4, the array substrate 100 includes a plurality of light-emitting areas (EA), a plurality of contact areas (CA), and a non-light-emitting area (NEA).

[0046] Each of the light emitting areas (EA) includes a first light emitting area (EA1), a second light emitting area (EA2), and a third light emitting area (EA3). Each of the first light emitting area (EA1), the second light emitting area (EA2), and the third light emitting area (EA3) is an area where light emitted from the light emitting element is emitted to the outside of the array substrate 100.

[0047] The first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) emit light of the same color. For example, the first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) emit light of a first color. In another embodiment, the first color is blue.

[0048] The first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) each have a triangular planar shape, a rectangular planar shape, a circular planar shape, a track-shaped planar shape, an elliptical planar shape, etc. In other embodiments, the first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) each have a rectangular planar shape. However, the configuration according to one embodiment of the present invention is not limited thereto.

[0049] On a plane, the light emitting areas (EA) are repeatedly arranged along the row and column directions. For example, the light emitting areas (EA) are repeatedly arranged along the first direction (D1) and the second direction (D2). For example, the second light emitting areas (EA2) are repeatedly arranged along the first direction (D1) in odd-numbered rows (e.g., the first row). Furthermore, the first light emitting areas (EA1) and the third light emitting areas (EA3) are alternately arranged along the first direction (D1) in even-numbered rows (e.g., the second row) adjacent to the odd-numbered rows.

[0050] In a plan view, the contact areas (CA) are repeatedly arranged between the light-emitting areas (EA) along the first direction (D1) and the second direction (D2). For example, the contact areas (CA) are repeatedly arranged along the first direction (D1) in the odd-numbered rows. That is, each contact area (CA) is located between the second light-emitting areas (EA2). Each contact area (CA) is an area where a laser drilling process is performed to connect an auxiliary electrode (e.g., the auxiliary electrode (AE) in FIG. 4) to a common electrode (e.g., the common electrode (CE) in FIG. 3) to reduce the resistance of the common electrode.

[0051] The non-emissive area (NEA) is located between the emissive area (EA) and the contact area (CA). For example, the non-emissive area (NEA) surrounds the emissive area (EA) and the contact area (CA) on a plane. The non-emissive area (NEA) is the remaining area of the display area (DA) excluding the emissive area (EA) and the contact area (CA). In other words, no light-emitting element that emits light is located in the non-emissive area (NEA). In other words, the non-emissive area (NEA) does not emit light.

[0052] FIG. 4 is an enlarged plan view of region A in FIG.

[0053] Hereinafter, some of the components included in the array substrate 100 of FIGS. 1 to 3 will be described in plan view with reference to FIG.

[0054] As shown in Figures 3 and 4, the array substrate 100 includes a first light-emitting element (e.g., the first light-emitting element (EE1) in Figure 5) including a first pixel electrode (PE1) overlapping the first light-emitting area (EA1), a second light-emitting element (e.g., the second light-emitting element (EE2) in Figure 5) including a second pixel electrode (PE2) overlapping the second light-emitting area (EA2), a third light-emitting element (e.g., the third light-emitting element (EE3) in Figure 5) including a third pixel electrode (PE3) overlapping the third light-emitting area (EA3), an auxiliary electrode (AE), a pixel defining layer (PDL), and an insulating pattern (IP).

[0055] The first pixel electrode (PE1) is electrically connected to the first transistor through a first contact hole (CNT1). The second pixel electrode (PE2) is electrically connected to the second transistor through a second contact hole (CNT2). The third pixel electrode (PE3) is electrically connected to the third transistor through a third contact hole (CNT3). The first to third contact holes (CNT1, CNT2, CNT3) are arranged spaced apart from one another.

[0056] The pixel defining layer (PDL) covers the edges of the first to third pixel electrodes (PE1, PE2, PE3), and is defined with a first central opening (COP1) overlapping the first light emitting area (EA1) and exposing a portion of the upper surface of the first pixel electrode (PE1), a second central opening (COP2) overlapping the second light emitting area (EA2) and exposing a portion of the upper surface of the second pixel electrode (PE2), and a third central opening (COP3) overlapping the third light emitting area (EA3) and exposing a portion of the upper surface of the third pixel electrode (PE3).

[0057] In another embodiment, the pixel defining layer (PDL) defines a peripheral opening (POP) overlapping the non-emitting area (NEA). Specifically, the peripheral opening (POP) partially overlaps the non-emitting area (NEA). Here, the peripheral opening (POP) does not overlap the first to third pixel electrodes (PE1, PE2, PE3). That is, the peripheral opening (POP) is spaced apart from the first to third pixel electrodes (PE1, PE2, PE3) in a plan view.

[0058] The pixel defining layer (PDL) extends continuously along the first to third light emitting regions (EA1, EA2, EA3). However, the present invention is not limited thereto. Optionally, the pixel defining layer (PDL) extends continuously along at least two of the first to third light emitting regions (EA1, EA2, EA3). For example, the pixel defining layer (PDL) extends continuously along the first and second light emitting regions (EA1, EA2). In this case, a portion of the pixel defining layer (PDL) is independently disposed in the third light emitting region (EA3).

[0059] The insulating pattern (IP) overlaps the contact area (CA) and covers the edges of the auxiliary electrodes (AE). In another embodiment, the insulating pattern (IP) is located only on the edges of the auxiliary electrodes (AE). For example, the insulating pattern (IP) has an island shape on a plane. Also, a fourth central opening (COP4) overlapping the contact area (CA) is defined in the insulating pattern (IP).

[0060] In another embodiment, the insulating pattern (IP) is arranged separately from the pixel defining layer (PDL), i.e., the insulating pattern (IP) is arranged independently from the pixel defining layer (PDL), i.e., the insulating pattern (IP) is not connected to the pixel defining layer (PDL).

[0061] A peripheral opening (POP) is defined in the insulating pattern (IP) and partially overlaps the non-emitting area (NEA). That is, the pixel defining layer (PDL) and the insulating pattern (IP) share the peripheral opening (POP). The pixel defining layer (PDL) and the insulating pattern (IP) are separated from each other by the peripheral opening (POP).

[0062] In another embodiment, the pixel defining layer (PDL) is located only on the edges of each of the first to third pixel electrodes (PE1, PE2, PE3). For example, the pixel defining layer (PDL) includes a first pattern portion (PP1), a second pattern portion (PP2), a third pattern portion (PP3), a first connecting portion (CP1), and a second connecting portion (CP2).

[0063] In another embodiment, the first pattern portion (PP1) covers the edge of the first pixel electrode (PE1), the second pattern portion (PP2) covers the edge of the second pixel electrode (PE2), and the third pattern portion (PP3) covers the edge of the third pixel electrode (PE3).

[0064] The first connecting portion (CP1) overlaps a portion protruding from the first pixel electrode (PE1). For example, the first connecting portion (CP1) overlaps a portion of the first pixel electrode (PE1) where the first contact hole (CNT1) is located. In another embodiment, the first connecting portion (CP1) connects the first to third pattern portions (PP1, PP2, PP3) located in one light-emitting area (EA). That is, the first connecting portion (CP1) causes the first to third pattern portions (PP1, PP2, PP3) located in one light-emitting area (EA) to extend continuously.

[0065] The second connecting portion (CP2) connects two pattern portions among the first to third pattern portions (PP1, PP2, PP3). In another embodiment, the second connecting portion (CP2) includes a second connecting portion (CP2) extending in a first direction (D1) and a second connecting portion (CP2) extending in a second direction (D2). For example, the second connecting portion (CP2) extending in the first direction (D1) connects the first pattern portion (PP1) and a third pattern portion (PP3) adjacent to the first pattern portion (PP1) in the direction opposite to the first direction (D1). The second connecting portion (CP2) extending in the second direction (D2) connects the second pattern portion (PP2) and a third pattern portion (PP3) adjacent to the second pattern portion (PP2) in the second direction (D2). That is, two adjacent pattern portions are connected by the second connecting portion (CP2).

[0066] In another embodiment, the second connecting portion (CP2) does not overlap the first to third light-emitting areas (EA1, EA2, EA3) but overlaps the non-pixel area (NEA), i.e., the first to third pixel electrodes (PE1, PE2, PE3) are not located below the second connecting portion (CP2).

[0067] The width of the second connecting portion (CP2) is different from the width of each of the first to third pattern portions (PP1, PP2, PP3). In another embodiment, the width of the second connecting portion (CP2) is smaller than the width of each of the first to third pattern portions (PP1, PP2, PP3).

[0068] Fig. 5 is a cross-sectional view taken along line II-II' in Fig. 4. Fig. 6 is a cross-sectional view taken along line III-III' in Fig. 4.

[0069] The components included in the array substrate 100 will be described in more detail below with reference to a stacked structure.

[0070] As shown in Figures 5 and 6, the array substrate 100 includes a first substrate 110, a buffer layer 120, a gate insulating layer 130, first to third transistors (TR1, TR2, TR3), an interlayer insulating layer 140, a conductive pattern 145, a planarization layer 150, a pixel defining layer (PDL), an insulating pattern (IP), first to third light-emitting elements (EE1, EE2, EE3), a common layer (CL), and an encapsulation layer 160.

[0071] Here, the first transistor (TR1) includes a first active layer (ACT1), a first gate electrode (GAT1), a first source electrode (SE1), and a first drain electrode (DE1). The second transistor (TR2) includes a second active layer (ACT2), a second gate electrode (GAT2), a second source electrode (SE2), and a second drain electrode (DE2). The third transistor (TR3) includes a third active layer (ACT3), a third gate electrode (GAT3), a third source electrode (SE3), and a third drain electrode (DE3).

[0072] The first light-emitting element (EE1) includes a first pixel electrode (PE1), a first light-emitting layer (EL1), and a common electrode (CE). The second light-emitting element (EE2) includes a second pixel electrode (PE2), a second light-emitting layer (EL2), and a common electrode (CE). The third light-emitting element (EE3) includes a third pixel electrode (PE3), a third light-emitting layer (EL3), and a common electrode (CE).

[0073] As described above, the array substrate 100 includes an emitting area (EA), a contact area (CA), and a non-emitting area (NEA). Since the array substrate 100 includes the emitting area (EA), the contact area (CA), and the non-emitting area (NEA), the components included in the array substrate 100 (such as the first substrate 110) also include the emitting area (EA), the contact area (CA), and the non-emitting area (NEA).

[0074] The first substrate 110 includes a transparent material or an opaque material. The first substrate 110 is made of a transparent resin substrate. Examples of the transparent resin substrate include a polyimide substrate. In this case, the polyimide substrate includes a first organic layer, a first barrier layer, and a second organic layer. Alternatively, the first substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, a non-alkali glass substrate, or the like. These may be used alone or in combination with each other.

[0075] The buffer layer 120 is positioned on the first substrate 110. The buffer layer 120 prevents or reduces the diffusion of metal atoms or impurities from the first substrate 110 into the transistors (TR1, TR2, TR3). In addition, the buffer layer 120 improves the flatness of the surface of the first substrate 110 if the surface of the first substrate 110 is not uniform. For example, the buffer layer 120 may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination.

[0076] First to third active layers (ACT1, ACT2, ACT3) are located on the buffer layer 120. Each of the first to third active layers (ACT1, ACT2, ACT3) includes a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon, polysilicon), or an organic semiconductor. The first to third active layers (ACT1, ACT2, ACT3) include the same material. For example, each of the first to third active layers (ACT1, ACT2, ACT3) includes a source region, a drain region, and a channel region located between the source region and the drain region.

[0077] The metal oxide semiconductor is a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ), quaternary compounds (AB x C y D z For example, the metal oxide semiconductor includes zinc oxide (ZnO x ), gallium oxide (GaO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), etc. These can be used alone or in combination with each other.

[0078] A gate insulating layer 130 is located on the buffer layer 120. The gate insulating layer 130 fully covers the first to third active layers (ACT1, ACT2, ACT3), does not create steps around the first to third active layers (ACT1, ACT2, ACT3), and has a substantially flat upper surface. Optionally, the gate insulating layer 130 may cover the first to third active layers (ACT1, ACT2, ACT3) and be arranged along the respective profiles of the first to third active layers (ACT1, ACT2, ACT3) with a uniform thickness. For example, the gate insulating layer 130 may be made of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon carbide (SiC x ), silicon oxynitride (SiO x N y ), silicon oxide carbide (SiO x C y ) which can be used alone or in combination with each other.

[0079] First, second, and third gate electrodes (GAT1, GAT2, and GAT3) are positioned on the gate insulating layer 130. The first gate electrode (GAT1) overlaps the channel region of the first active layer (ACT1), the second gate electrode (GAT2) overlaps the channel region of the second active layer (ACT2), and the third gate electrode (GAT3) overlaps the channel region of the third active layer (ACT3). For example, each of the first, second, and third gate electrodes (GAT1, GAT2, and GAT3) may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination with each other. The first, second, and third gate electrodes (GAT1, GAT2, and GAT3) may include the same material.

[0080] An interlayer insulating layer 140 is positioned on the gate insulating layer 130. The interlayer insulating layer 140 fully covers the first to third gate electrodes (GAT1, GAT2, GAT3) and has a substantially flat upper surface without creating steps around the first to third gate electrodes (GAT1, GAT2, GAT3). Optionally, the interlayer insulating layer 140 may cover the first to third gate electrodes (GAT1, GAT2, GAT3) and be arranged with a uniform thickness along the respective profiles of the first to third gate electrodes (GAT1, GAT2, GAT3). For example, the interlayer insulating layer 140 may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, etc. These may be used alone or in combination with each other.

[0081] First to third source electrodes (SE1, SE2, SE3) are located on the interlayer insulating layer 140. The first source electrode (SE1) is connected to the source region of the first active layer (ACT1) through a contact hole that penetrates the gate insulating layer 130 and the interlayer insulating layer 140. The second source electrode (SE2) is connected to the source region of the second active layer (ACT2) through a contact hole that penetrates the gate insulating layer 130 and the interlayer insulating layer 140. The third source electrode (SE3) is connected to the source region of the third active layer (ACT3) through a contact hole that penetrates the gate insulating layer 130 and the interlayer insulating layer 140.

[0082] First, second, and third drain electrodes (DE1, DE2, DE3) are located on the interlayer insulating layer 140. The first drain electrode (DE1) is connected to the drain region of the first active layer (ACT1) through a contact hole that penetrates the gate insulating layer 130 and the interlayer insulating layer 140. The second drain electrode (DE2) is connected to the drain region of the second active layer (ACT2) through a contact hole that penetrates the gate insulating layer 130 and the interlayer insulating layer 140. The third drain electrode (DE3) is connected to the drain region of the third active layer (ACT3) through a contact hole that penetrates the gate insulating layer 130 and the interlayer insulating layer 140.

[0083] For example, each of the first to third source electrodes (SE1, SE2, SE3) includes a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. The first to third drain electrodes (DE1, DE2, DE3) include the same material as the first to third source electrodes (SE1, SE2, SE3).

[0084] As a result, a first transistor (TR1) including a first active layer (ACT1), a first gate electrode (GAT1), a first source electrode (SE1), and a first drain electrode (DE1) is located on the first substrate 110, a second transistor (TR2) including a second active layer (ACT2), a second gate electrode (GAT2), a second source electrode (SE2), and a second drain electrode (DE2) is located on the first substrate 110, and a third transistor (TR3) including a third active layer (ACT3), a third gate electrode (GAT3), a third source electrode (SE3), and a third drain electrode (DE3) is located on the first substrate 110.

[0085] The conductive pattern 145 is located in the contact area (CA) on the interlayer insulating layer 140. For example, the conductive pattern 145 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0086] In another embodiment, the conductive pattern 145 includes the same material as the first to third source electrodes (SE1, SE2, SE3) (or the first to third drain electrodes (DE1, DE2, DE3)). That is, the conductive pattern 145 is located on the same layer as the first to third source electrodes (SE1, SE2, SE3) (or the first to third drain electrodes (DE1, DE2, DE3)).

[0087] The planarization layer 150 is positioned on the interlayer insulating layer 140. The planarization layer 150 fully covers the first to third source electrodes (SE1, SE2, SE3), the first to third drain electrodes (DE1, DE2, DE3), and the conductive pattern 145. The planarization layer 150 includes an organic material. For example, the planarization layer 150 includes an organic material such as a phenolic resin, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, or an epoxy resin. These materials may be used alone or in combination with each other.

[0088] First to third pixel electrodes (PE1, PE2, PE3) are respectively located in first to third light-emitting regions (EA1, EA2, EA3) on the planarization layer 150. For example, the first pixel electrode (PE1) is located in the first light-emitting region (EA1), the second pixel electrode (PE2) is located in the second light-emitting region (EA2), and the third pixel electrode (PE3) is located in the third light-emitting region (EA3). The first pixel electrode (PE1) is connected to the first drain electrode (DE1) via a first contact hole (CNT1) that penetrates the planarization layer 150, the second pixel electrode (PE2) is connected to the second drain electrode (DE2) via a second contact hole (CNT2) that penetrates the planarization layer 150, and the third pixel electrode (PE3) is connected to the third drain electrode (DE3) via a third contact hole (CNT3) that penetrates the planarization layer 150.

[0089] For example, each of the first to third pixel electrodes (PE1, PE2, PE3) may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination with each other. In another embodiment, each of the first to third pixel electrodes (PE1, PE2, PE3) may have a stacked structure including ITO / Ag / ITO. The first to third pixel electrodes (PE1, PE2, PE3) may include the same material. For example, each of the first to third pixel electrodes (PE1, PE2, PE3) may function as an anode.

[0090] An auxiliary electrode (AE) is located in the contact area (CA) on the planarization layer 150. The auxiliary electrode (AE) is connected to the conductive pattern 145 via a fourth contact hole (CNT4) that penetrates the planarization layer 150. For example, the auxiliary electrode (AE) includes a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other.

[0091] In another embodiment, the auxiliary electrode (AE) includes the same material as the first to third pixel electrodes (PE1, PE2, PE3), i.e., the auxiliary electrode (AE) is located on the same layer as the first to third pixel electrodes (PE1, PE2, PE3).

[0092] A pixel defining layer (PDL) is positioned on the planarization layer 150. The pixel defining layer (PDL) covers the edges of the first to third pixel electrodes (PE1, PE2, PE3), and is defined in the pixel defining layer (PDL) with a first central opening (COP1) exposing a portion of the top surface of the first pixel electrode (PE1), a second central opening (COP2) exposing a portion of the top surface of the second pixel electrode (PE2), and a third central opening (COP3) exposing a portion of the top surface of the third pixel electrode (PE3).

[0093] The pixel defining layer (PDL) may include an inorganic material or an organic material. In another embodiment, the pixel defining layer (PDL) may include an organic material. For example, the pixel defining layer (PDL) may include an organic material such as polyimide (PI). However, the organic material used for the pixel defining layer (PDL) is not limited thereto.

[0094] The pixel defining layer (PDL) may further include a black light-blocking material, such as a black pigment, a black dye, or carbon black, which may be used alone or in combination with each other.

[0095] An insulating pattern (IP) is located on the planarization layer 150. The insulating pattern (IP) partially overlaps the contact area (CA). The insulating pattern (IP) covers the edges of the auxiliary electrodes (AE). The insulating pattern (IP) also defines a fourth central opening (COP4) that exposes a portion of the top surface of the auxiliary electrodes (AE).

[0096] In another embodiment, the insulating pattern (IP) comprises the same material as the pixel defining layer (PDL), i.e., the insulating pattern (IP) is located on the same layer as the pixel defining layer (PDL).

[0097] In another embodiment, a peripheral opening (POP) is defined in the pixel defining layer (PDL) and the insulating pattern (IP) in the non-emitting area (NEA) to expose the top surface of the planarization layer 150. In other words, the peripheral opening (POP) is formed between the pixel defining layer (PDL) and the insulating pattern (IP).

[0098] First, second, and third light-emitting layers (EL1, EL2, EL3) are located on the first, second, and third pixel electrodes (PE1, PE2, PE3). For example, the first, second, and third light-emitting layers (EL1, EL2, EL3) are located within the first, second, and third central openings (COP1, COP2, COP3), respectively. Each of the first, second, and third light-emitting layers (EL1, EL2, EL3) is formed using at least one of light-emitting materials that emit red light, green light, and blue light. In another embodiment, the first, second, and third light-emitting layers (EL1, EL2, EL3) emit blue light. For example, each of the first, second, and third light-emitting layers (EL1, EL2, EL3) includes a small molecule organic compound or a polymer organic compound.

[0099] A common layer (CL) is located on the planarization layer 150, the auxiliary electrode (AE), the first light-emitting layer (EL1), the second light-emitting layer (EL2), and the third light-emitting layer (EL3). The common layer (CL) includes a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc. In another embodiment, the first to third light-emitting layers (EL1, EL2, EL3) are disposed between the hole transport layer and the electron transport layer.

[0100] In the contact region (CA), a fifth contact hole (CNT5) is formed that penetrates the common layer (CL) and exposes a portion of the upper surface of the auxiliary electrode (AE). In another embodiment, the fifth contact hole (CNT5) is formed by removing a portion of the common layer (CL) using a laser drilling process. In another embodiment, the fifth contact hole (CNT5) can also be formed by removing a portion of the common layer (CL) using an organic film taper adjustment process or an organic film reverse taper adjustment process.

[0101] The common electrode (CE) is located on the common layer (CL). The common electrode (CE) may be made of a metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, or the like. These may be used alone or in combination with each other. In another embodiment, the common electrode (CE) has a laminated structure including Mg and Ag. For example, the common electrode (CE) may function as a cathode.

[0102] In another embodiment, the common electrode (CE) is connected to the auxiliary electrode (AE) in the contact region (CA) through the fifth contact hole (CNT5) in the common layer (CL). That is, the common electrode (CE) is electrically connected to the auxiliary electrode (AE) in the contact region (CA) through the fifth contact hole (CNT5) in the common layer (CL). This reduces the resistance of the common electrode (CE).

[0103] As a result, a first light-emitting element (EE1) including a first pixel electrode (PE1), a first light-emitting layer (EL1), and a common electrode (CE) is located in a first light-emitting region (EA1) on the first substrate 110, a second light-emitting element (EE2) including a second pixel electrode (PE2), a second light-emitting layer (EL2), and a common electrode (CE) is located in a second light-emitting region (EA2) on the first substrate 110, and a third light-emitting element (EE3) including a third pixel electrode (PE3), a third light-emitting layer (EL3), and a common electrode (CE) is located in a third light-emitting region (EA3) on the first substrate 110.

[0104] The encapsulation layer 160 is positioned on the common electrode (CE). The encapsulation layer 160 prevents or reduces the penetration of impurities, moisture, external air, or other contaminants from the outside into the first to third light emitting elements (EE1, EE2, EE3). The encapsulation layer 160 includes at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the inorganic encapsulation layer includes silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination. The organic encapsulation layer includes a polymeric cured material such as polyacrylate.

[0105] FIG. 7 is a plan view showing a color conversion substrate of the display device in FIGS.

[0106] 7 and 8, color conversion substrate 200 includes a first light-emitting region (TA1), a second light-emitting region (TA2), a third light-emitting region (TA3), and a light-shielding region (BA). Each of the first light-emitting region (TA1), the second light-emitting region (TA2), and the third light-emitting region (TA3) is a region where light emitted from array substrate 100 passes through color conversion substrate 200 and is provided to the outside of display device 1000.

[0107] Light of different colors is transmitted through the first light projection area (TA1), the second light projection area (TA2), and the third light projection area (TA3) and provided to the outside of the display device 1000. For example, light of a first color is transmitted through the first light projection area (TA1), light of a second color is transmitted through the second light projection area (TA2), and light of a third color is transmitted through the third light projection area (TA3). In another embodiment, the first color is red, the second color is green, and the third color is blue. However, the present invention is not limited thereto.

[0108] On a plane, the light projection areas (TA1, TA2, TA3) are repeatedly arranged along the row and column directions. For example, the light projection areas (TA1, TA2, TA3) are repeatedly arranged along the first direction (D1) and the second direction (D2). For example, the second light projection area (TA2) is repeatedly arranged along the first direction (D1) in odd-numbered rows (e.g., the first row). Furthermore, the first light projection area (TA1) and the third light projection area (TA3) are alternately arranged along the first direction (D1) in even-numbered rows (e.g., the second row) adjacent to the odd-numbered rows.

[0109] The light-shielding area (BA) is located between the first light-projection area (TA1), the second light-projection area (TA2), and the third light-projection area (TA3). For example, the light-shielding area (BA) surrounds the first light-projection area (TA1), the second light-projection area (TA2), and the third light-projection area (TA3) on a plane. The light-shielding area (BA) is the remaining area excluding the first light-projection area (TA1), the second light-projection area (TA2), and the third light-projection area (TA3). In other words, the light-shielding area (BA) is an area through which light emitted from the array substrate 100 does not pass.

[0110] Fig. 8 is an enlarged plan view of region B in Fig. 7. Fig. 9 is a cross-sectional view taken along line IV-IV' in Fig. 8.

[0111] As shown in Figures 7, 8 and 9, the color conversion substrate 200 includes a second substrate 170, a color filter layer (CF), a low refractive index layer 180, a protective layer 190, a color conversion layer (CCL), and a bank layer (BL).

[0112] As described above, color conversion substrate 200 includes a light-transmitting area (TA) and a light-blocking area (BA). Because color conversion substrate 200 includes a light-transmitting area (TA) and a light-blocking area (BA), components included in color conversion substrate 200 (e.g., second substrate 170, etc.) also include a light-transmitting area (TA) and a light-blocking area (BA).

[0113] The second substrate 170 transmits light emitted from the light emitting elements (e.g., the first to third light emitting elements (EE1, EE2, and EE3) in FIG. 5). For example, the second substrate 170 is made of a transparent resin substrate. The second substrate 170 includes an insulating material such as glass or plastic. Alternatively, the second substrate 170 may include an organic polymer material such as polycarbonate (PC), polyethylene (PE), or polypropylene (PP). These may be used alone or in combination with each other.

[0114] A color filter layer (CF) is located under the second substrate 170. The color filter layer (CF) can selectively transmit light having a specific wavelength. For example, the color filter layer (CF) includes a first color filter layer (CF1), a second color filter layer (CF2), and a third color filter layer (CF3). The first color filter layer (CF1) overlaps the first transmission area (TA1) and the light-blocking area (BA), the second color filter layer (CF2) overlaps the second light-transmitting area (TA2) and the light-blocking area (BA), and the third color filter layer (CF3) overlaps the third light-transmitting area (TA3) and the light-blocking area (BA).

[0115] The first color filter layer (CF1) selectively transmits light having a first wavelength (e.g., red light), the second color filter layer (CF2) selectively transmits light having a second wavelength (e.g., green light), and the third color filter layer (CF3) selectively transmits light having a third wavelength (e.g., blue light).

[0116] A light-shielding layer is located under the second substrate 170. The light-shielding layer overlaps the light-shielding area (BA). Light emitted from the light-emitting elements (e.g., the first to third light-emitting elements (EE1, EE2, EE3) in FIG. 5) can only pass through a portion of the color conversion substrate 200. That is, the light emitted from the light-emitting elements passes only through the areas of the color conversion substrate 200 that overlap the first to third light-emitting areas (TA1, TA2, TA3), and does not pass through the areas of the color conversion substrate 200 that overlap the light-shielding area (BA). In another embodiment, the light-shielding layer is formed by stacking first to third color filter layers (CF1, CF2, CF3).

[0117] In another embodiment, the light-blocking layer includes a light-blocking material, for example, the light-blocking material has a particular color.

[0118] The low refractive index layer 180 is located below the color filter layer (CF). The low refractive index layer 180 covers the color filter layer (CF). The low refractive index layer 180 has a relatively low refractive index. For example, the refractive index of the low refractive index layer 180 is lower than the refractive index of the color conversion layer 260. The low refractive index layer 180 includes an organic material. For example, the low refractive index layer 180 includes an organic polymer material containing silicon.

[0119] A protective layer 190 is positioned below the low refractive index layer 180. The protective layer 190 covers the low refractive index layer 180. The protective layer 190 blocks external impurities to prevent or reduce contamination of the color filter layer (CF). The protective layer 190 includes an inorganic material. For example, the protective layer 190 includes silicon oxide, silicon nitride, aluminum nitride, etc. These may be used alone or in combination with each other.

[0120] The bank layer (BL) is located under the protective layer 190. The bank layer (BL) overlaps the light-shielding area (BA). For example, the bank layer (BL) includes an organic material such as polyimide. Alternatively, the bank layer (BL) may include an organic material containing a light-shielding material.

[0121] The bank layer (BL) can block light emitted from the first color conversion pattern (CCP1) from being irradiated onto the second color conversion pattern (CCP2) or the transmission pattern (TP), light emitted from the second color conversion pattern (CCP2) from being irradiated onto the first color conversion pattern (CCP1) or the transmission pattern (TP), or light emitted from the transmission pattern (TP) from being irradiated onto the first color conversion pattern (CCP1) or the second color conversion pattern (CCP2).

[0122] In another embodiment, a first opening (OP1) and a second opening (OP2) are defined in the bank layer (BL).

[0123] The first opening (OP1) overlaps with the first light projection area (TA1), the second light projection area (TA2), and the third light projection area (TA3). The first opening (OP1) exposes a portion of the bottom surface of the protective layer 190. The color conversion layer (CCL) is formed in the first opening (OP1) by an inkjet method.

[0124] The second opening (OP2) overlaps the light-shielding area (BA). In one embodiment, the second opening (OP2) exposes a portion of the bottom surface of the protective layer 190. The second opening (OP2) accommodates the remaining ink ejected by the inkjet method in the process of forming the color conversion layer (CCL).

[0125] The first openings (OP1) are repeatedly arranged along the first direction (D1) and the second direction (D2). The second openings (OP2) are also repeatedly arranged along the first direction (D1) and the second direction (D2). For example, the first openings (OP1) overlapping the second light-projection area (TA2) are repeatedly arranged in odd-numbered rows (e.g., the first row), and the second openings (OP2) are repeatedly arranged in the odd-numbered rows, sandwiching the first openings (OP1) overlapping the second transmission area (TA2). The first openings (OP1) overlapping the first and third light-projection areas (TA1, TA3) are repeatedly arranged in the even-numbered rows (e.g., the second row) adjacent to the odd-numbered rows.

[0126] The second opening (OP2) has a polygonal planar shape, a circular planar shape, a track-shaped planar shape, an elliptical planar shape, etc. In other embodiments, the second opening (OP2) has a rectangular planar shape. However, the planar shape of the second opening (OP2) is not limited thereto.

[0127] The area of the second opening (OP2) is different from the area of the first opening (OP1). In another embodiment, the area of the second opening (OP2) is greater than the area of the first opening (OP1).

[0128] Here, the first opening (OP1) refers to a portion of the bank layer (BL) that is filled with the material of the color conversion layer (CCL), and the second opening (OP2) refers to a portion of the bank layer (BL) that is filled with the material of the filling layer 300. In other words, each of the first opening (OP1) and the second opening (OP2) refers to a portion where a part of the protective layer 190 contacts not the bank layer (BL) but another component (e.g., the color conversion layer (CCL), the filling layer 300, etc.).

[0129] In another embodiment, the bank layer (BL) further defines a third opening (OP3) and a fourth opening (OP4), the third opening (OP3) extending in the first direction (D1) and the fourth opening (OP4) extending in the second direction (D2).

[0130] The third openings (OP3) are repeatedly arranged along the second direction (D2) with the first openings (OP1) overlapping the second light projection area (TA2) sandwiched between them. The fourth openings (OP4) are repeatedly arranged along the first direction (D1) with the first openings (OP1) overlapping the first and third light projection areas (TA1, TA3) sandwiched between them. The third openings (OP3) and fourth openings (OP4) contain the remaining ink ejected by the inkjet method in the process of forming the color conversion layer (CCL).

[0131] Here, the third opening (OP3) and the fourth opening (OP4) each refer to a portion of the bank layer (BL) that is filled with the material of the filling layer 300. In other words, the third opening (OP3) and the fourth opening (OP4) each refer to a portion of a part of the protective layer 190 that is in contact with another component (such as the filling layer 300) rather than the bank layer (BL).

[0132] In another embodiment, the bank layer (BL) includes a first partition wall (PT1) and a second partition wall (PT2) that is integrally formed with the first partition wall (PT1) and is the remaining portion excluding the first partition wall (PT1). The first partition wall (PT1) is located in at least one second opening (OP2) of the bank layer (BL).

[0133] In another embodiment, in the case of the second opening (OP2) where the first partition (PT1) is located, the second opening (OP2) is divided into two openings by the first partition (PT1). However, in the case of the second opening (OP2) where the first partition (PT1) is not located, the second opening (OP2) has a rectangular planar shape.

[0134] Spacers are positioned on the first partition walls (PT1) of the bank layer (BL). The spacers serve to maintain a gap between the color conversion substrate 200 and the array substrate (e.g., the array substrate 100 of FIG. 5). For example, the spacers include an organic material.

[0135] A color conversion layer (CCL) is located under the protective layer 190. The color conversion layer (CCL) converts light emitted from the light emitting elements (e.g., the first to third light emitting elements (EE1, EE2, and EE3) in FIG. 5) into light having a specific wavelength. For example, the color conversion layer (CCL) includes color conversion particles.

[0136] The color conversion layer (CCL) includes a first color conversion pattern (CCP1), a second color conversion pattern (CCP2), and a transmission pattern (TP). For example, the first color conversion pattern (CCP1) overlaps the first light-projecting area (TA1), the second color conversion pattern (CCP2) overlaps the second light-projecting area (TA2), and the transmission pattern (TP) overlaps the third light-projecting area (TA3).

[0137] The first color conversion pattern (CCP1) converts light emitted from a first light-emitting element (e.g., the first light-emitting element (EE1) in FIG. 5) into light of a first color (e.g., red light). The second color conversion pattern (CCP2) converts light emitted from a second light-emitting element (e.g., the second light-emitting element (EE2) in FIG. 5) into light of a second color (e.g., green light). The transmission pattern (TP) transmits light emitted from a third light-emitting element (e.g., the third light-emitting element (EE3) in FIG. 5). In another embodiment, the light is blue light. However, the configuration of the present invention is not limited thereto, and the light may also mean light of another color, such as white light.

[0138] The first color conversion pattern (CCP1) includes first color conversion particles that are excited by light generated from the first light emitting element and emit light of a first color, and further includes a first photosensitive polymer having first scattering particles dispersed therein.

[0139] The second color conversion pattern (CCP2) includes second color conversion particles that are excited by light generated from the second light-emitting element and emit light of a second color. The second color conversion pattern (CCP2) further includes a second photosensitive polymer in which second scattering particles are dispersed. Each of the first color conversion particles and the second color conversion particles represents a quantum dot.

[0140] The transmission pattern (TP) transmits light generated from the third light emitting element and emits the light in a direction toward the second substrate 170. The transmission pattern (TP) includes a third photosensitive polymer in which third scattering particles are dispersed. For example, each of the first to third photosensitive polymers includes an organic material having optical transparency, such as a silicone resin or an epoxy resin. These may be used alone or in combination with each other.

[0141] The first to third photosensitive polymers contain the same material. The first to third scattering particles scatter and emit light generated from the first to third light emitting elements, and the first to third scattering particles contain the same material.

[0142] Fig. 10 is a plan view showing both area A in Fig. 4 and area B in Fig. 8. Fig. 11 is a cross-sectional view taken along line VV' in Fig. 10.

[0143] As shown in FIGS. 4, 5, 8, 9, 10 and 11, a display device 1000 according to an embodiment of the present invention includes an array substrate 100, a filler layer 300, and a color conversion substrate 200.

[0144] Here, the array substrate 100 includes a first substrate 110, a buffer layer 120, a gate insulating layer 130, first to third transistors (TR1, TR2, TR3), an interlayer insulating layer 140, a conductive pattern 145, a planarization layer 150, a pixel defining layer (PDL), an insulating pattern (IP), first to third light emitting elements (EE1, EE2, EE3), a common layer (CL), and an encapsulation layer 160. The color conversion substrate 200 includes a second substrate 170, a color filter layer (CF), a low refractive index layer 180, a protective layer 190, a color conversion layer (CCL), and a bank layer (BL).

[0145] In the following, descriptions that overlap with the array substrate 100 and color conversion substrate 200 of the display device 1000 described with reference to FIGS. 1 to 9 will be omitted or simplified.

[0146] The array substrate 100 and the color conversion substrate 200 are bonded together. For example, the filler layer 300 is located on the array substrate 100, and the color conversion substrate 200 is located on the filler layer 300.

[0147] As described above, the array substrate 100 includes a first light-emitting area (EA1), a second light-emitting area (EA2), a third light-emitting area (EA3), and a non-light-emitting area (NEA), and the color conversion substrate 200 includes a first light-emitting area (TA1), a second light-emitting area (TA2), a third light-emitting area (TA3), and a light-shielding area (BA).

[0148] The first light-emitting area (EA1) overlaps (or corresponds to) the first light-projecting area (TA1), the second light-emitting area (EA2) overlaps (or corresponds to) the second light-projecting area (TA2), the third light-emitting area (EA3) overlaps (or corresponds to) the third light-projecting area (TA3), the non-light-emitting area (NEA) overlaps (or corresponds to) the light-blocking area (BA), and the light-blocking area (BA) overlaps (or corresponds to) the contact area (CA).

[0149] In another embodiment, the area of the first light-projected area (TA1) is larger than the area of the first light-emitting area (EA1), the area of the second light-projected area (TA2) is larger than the area of the second light-emitting area (EA2), and the area of the third light-projected area (TA3) is larger than the area of the third light-emitting area (EA3). In another embodiment, the area of the first light-projected area (TA1) is the same as the area of the first light-emitting area (EA1), the area of the second light-projected area (TA2) is the same as the area of the second light-emitting area (EA2), and the area of the third light-projected area (TA3) is the same as the area of the third light-emitting area (EA3).

[0150] The second opening (OP2) overlaps the contact area (CA). In another embodiment, the entire insulating pattern (IP) located adjacent to the contact area (CA) overlaps the second opening (OP2) of the bank layer (BL). That is, the insulating pattern (IP) is separated from the bank layer (BL) in a plan view.

[0151] The third opening (OP3) of the bank layer (BL) partially overlaps with the pixel defining layer (PDL). For example, the third opening (OP3) partially overlaps with the first connecting portion (CP1) of the pixel defining layer (PDL). Also, the fourth opening (OP4) of the bank layer (BL) partially overlaps with the pixel defining layer (PDL). For example, the fourth opening (OP4) partially overlaps with the second connecting portion (CP2) of the pixel defining layer (PDL).

[0152] However, the display device 1000 according to an embodiment of the present invention is described as being limited to an organic light emitting display (OLED), but the configuration of the present invention is not limited thereto. In other embodiments, the display device 1000 may include a liquid crystal display (LCD), a field emission display device (FED), a plasma display device (PDP), an electrophoretic display device (EPD), or an inorganic light emitting display device (ILED).

[0153] As described above, the display device 1000 according to one embodiment of the present invention has a structure in which the color conversion substrate 200 including the color conversion layer (CCL) and the array substrate 100 including the light emitting elements (EE1, EE2, EE3) are combined (i.e., a structure including two substrates). However, other embodiments according to the present invention are not limited thereto, and the display device 1000 may have a structure in which the array substrate 100 including the light emitting elements (EE1, EE2, EE3) and the color conversion layer (CCL) are sequentially stacked on the array substrate 100 (i.e., a single substrate structure).

[0154] In a pixel defining layer that has a central opening that exposes a portion of an upper surface of a pixel electrode and that extends continuously in a region other than the central opening, a thickness of a sealing layer that overlaps the pixel defining layer is relatively smaller than a thickness of the sealing layer that overlaps an emission layer, and in this case, if foreign matter penetrates onto the pixel defining layer, defects in the display device may occur.

[0155] Furthermore, in the process of forming the color conversion layer, foreign matter (such as ink) is dropped onto the bank layer, which can cause gap defects between the array substrate and the color conversion substrate included in the display device.

[0156] A display device 1000 according to an embodiment of the present invention includes an array substrate 100 and a color conversion substrate 200 disposed on the array substrate 100. The array substrate 100 includes a pixel defining layer (PDL) in which a peripheral opening (POP) partially overlapping a non-emissive area (NEA) is defined. The color conversion substrate 200 includes a bank layer (BL) in which a second opening (OP2) having a polygonal planar shape is defined and overlapping a light-blocking area (BA). This can improve defects in the display device 1000 due to the penetration of foreign matter.

[0157] 12 to 15 are cross-sectional views showing a method for manufacturing the array substrate in FIG.

[0158] 12, a buffer layer 120 is formed on a first substrate 110, which may include a transparent or opaque material. For example, the buffer layer 120 may be formed using an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0159] First to third active layers (ACT1, ACT2, ACT3) are formed on the buffer layer 120. Each of the first to third active layers (ACT1, ACT2, ACT3) includes a metal oxide semiconductor, an inorganic semiconductor, or an organic semiconductor. The first to third active layers (ACT1, ACT2, ACT3) may be formed simultaneously using the same material. For example, each of the first to third active layers (ACT1, ACT2, ACT3) includes a source region, a drain region, and a channel region located between the source region and the drain region.

[0160] A gate insulating layer 130 is formed on the buffer layer 120. The gate insulating layer 130 covers the first to third active layers ACT1, ACT2, and ACT3. For example, the gate insulating layer 130 is formed using an inorganic material such as silicon oxide or silicon nitride.

[0161] First to third gate electrodes (GAT1, GAT2, GAT3) are formed on the gate insulating layer 130. Each of the first to third gate electrodes (GAT1, GAT2, GAT3) is formed to overlap the channel region of each of the first to third active layers (ACT1, ACT2, ACT3). For example, each of the first to third gate electrodes (GAT1, GAT2, GAT3) is formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The first to third gate electrodes (GAT1, GAT2, GAT3) are simultaneously formed using the same material.

[0162] An interlayer insulating layer 140 is formed on the gate insulating layer 130. The interlayer insulating layer 140 covers the first to third gate electrodes GAT1, GAT2, and GAT3. For example, the interlayer insulating layer 140 is formed using an inorganic material such as silicon oxide or silicon nitride.

[0163] First to third source electrodes (SE1, SE2, SE3) are formed on the interlayer insulating layer 140. Each of the first to third source electrodes is connected to the source region of each of the first to third active layers (ACT1, ACT2, ACT3) through a contact hole formed by removing a portion of the gate insulating layer 130 and the interlayer insulating layer 140. Also, first to third drain electrodes (DE1, DE2, DE3) are formed on the interlayer insulating layer 140. Each of the first to third drain electrodes (DE1, DE2, DE3) is connected to the drain region of each of the first to third active layers (ACT1, ACT2, ACT3) through a contact hole formed by removing a portion of the gate insulating layer 130 and the interlayer insulating layer 140.

[0164] The first to third source electrodes (SE1, SE2, SE3) and the first to third drain electrodes (DE1, DE2, DE3) are each formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The first to third source electrodes (SE1, SE2, SE3) and the first to third drain electrodes (DE1, DE2, DE3) are simultaneously formed using the same material.

[0165] A planarization layer 150 is formed on the interlayer insulating layer 140. The planarization layer 150 is formed to sufficiently cover the first to third source electrodes (SE1, SE2, SE3) and the first to third drain electrodes (DE1, DE2, DE3). For example, the planarization layer 150 is formed using an organic material such as a phenolic resin, a polyimide resin, a polyamide resin, etc.

[0166] 13, first to third pixel electrodes (PE1, PE2, PE3) are formed on the planarization layer 150. The first to third pixel electrodes (PE1, PE2, PE3) are formed in the first to third light-emitting areas (EA1, EA2, EA3), respectively. The first to third pixel electrodes (PE1, PE2, PE3) are simultaneously formed using the same material.

[0167] An insulating film 400 is formed on the planarization layer 150. The insulating film 400 is formed over the first to third light-emitting areas (EA1, EA2, EA3) and the non-light-emitting area (NEA). For example, the insulating film 400 is formed using an organic material. Alternatively, the insulating film 400 may be formed using an organic material containing a light-blocking material such as a black pigment or a black dye.

[0168] 14, an etching process is performed on the insulating film 400 to form a pixel defining layer (PDL) overlapping the non-emitting area (NEA). Here, the etching process forms a first central opening (COP1) exposing a portion of the top surface of the first pixel electrode (PE1), a second central opening (COP2) exposing a portion of the top surface of the second pixel electrode (PE2), and a third central opening (COP3) exposing a portion of the top surface of the third pixel electrode (PE3) in the pixel defining layer (PDL). In addition, the etching process forms a peripheral opening (POP) exposing the top surface of the planarization layer 150 in the pixel defining layer (PDL) in the non-emitting area (NEA).

[0169] 15, a first light-emitting layer (EL1) is formed on a first pixel electrode (PE1), a second light-emitting layer (EL2) is formed on a second pixel electrode (PE2), and a third light-emitting layer (EL3) is formed on a third pixel electrode (PE3). For example, each of the first to third light-emitting layers (EL1, EL2, EL3) is formed using a low-molecular organic compound or a high-molecular organic compound.

[0170] A common layer (CL) is formed on the planarization layer 150, the pixel defining layer (PDL), the first light-emitting layer (EL1), the second light-emitting layer (EL2), and the third light-emitting layer (EL3). The common layer (CL) extends continuously through the first to third light-emitting regions (EA1, EA2, EA3) and the non-light-emitting region (NEA). For example, the common layer (CL) may include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc.

[0171] A common electrode (CE) is formed on the common layer (CL). The common electrode (CE) extends continuously in the first to third light-emitting areas (EA1, EA2, EA3) and the non-light-emitting area (NEA). For example, the common electrode (CE) may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like.

[0172] 5, the encapsulation layer 160 is formed on the common electrode (CE). The encapsulation layer 160 extends continuously over the first to third light-emitting areas (EA1, EA2, EA3) and the non-light-emitting area (NEA). For example, the encapsulation layer 160 includes at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0173] In this way, the array substrate 100 in FIG. 5 is manufactured.

[0174] 16 to 19 are cross-sectional views showing a method for manufacturing the color-changing substrate in FIG.

[0175] As shown in Figure 16, a first color filter layer (CF1) is formed on a second substrate 170 made of a transparent resin substrate. The first color filter layer (CF1) overlaps the first light-transmitting area (TA1) and the light-blocking area (BA). The first color filter layer (CF1) is a red color filter that transmits red light. For example, the first color filter layer (CF1) is formed from a red pigment and / or a color filter composition containing a red pigment.

[0176] A second color filter layer (CF2) is formed on the first color filter layer (CF1) and the second substrate 170. The second color filter layer (CF2) overlaps the second light-transmitting area (TA2) and the light-blocking area (BA). The second color filter layer (CF2) is a green color filter that transmits green light. For example, the second color filter layer (CF2) is formed from a green pigment and / or a color filter composition containing a green pigment.

[0177] A third color filter layer (CF3) is formed on the second color filter layer (CF2) and the second substrate 170. The third color filter layer (CF3) overlaps the third light-transmitting area (TA3) and the light-blocking area (BA). The third color filter layer (CF3) is formed from a blue pigment and / or a color filter composition containing a blue pigment.

[0178] A low refractive index layer 180 is formed on the color filter layer (CF). The low refractive index layer 180 covers the color filter layer (CF). The low refractive index layer 180 has a relatively low refractive index. For example, the low refractive index layer 180 is formed using an organic material.

[0179] A protective layer 190 is formed on the low refractive index layer 180. The protective layer 190 is formed using an inorganic material. For example, the protective layer 190 is formed using silicon oxide, silicon nitride, aluminum nitride, or the like.

[0180] 17, a preliminary bank layer (BL') is formed on the protective layer 190. That is, a material for forming the preliminary bank layer (BL') is applied entirely onto the protective layer 190. For example, the preliminary bank layer (BL') is formed using an organic material such as polyimide.

[0181] 18, the bank layer (BL) is formed by performing an etching process on the preliminary bank layer (BL'). Here, the etching process forms in the bank layer (BL) first openings (OP1) that overlap the first to third light-transmitting areas (TA1, TA2, TA3) and expose the upper surface of the protective layer 190, and second openings (OP2) that overlap the light-shielding areas (BA).

[0182] An inkjet device 500 drops ink 10 into a first opening (OP1). Here, the ink 10 is a substance that forms a color conversion layer (for example, the color conversion layer (CCL) in FIG. 8). In this case, an ink layer 11 used to manufacture a first color conversion pattern (CCP1) is formed in the first opening (OP1).

[0183] As shown in Fig. 19, the inkjet device 500 repeatedly dispenses droplets of ink 10 onto the first opening (OP1) that overlaps the first light projection area (TA1), thereby forming a first color conversion pattern (CCP1). Referring again to Fig. 9, the inkjet device 500 repeatedly dispenses droplets of ink 10 onto the first openings (OP1) that overlap the second light projection area (TA2) and the third light projection area (TA3), thereby forming a second color conversion pattern (CCP2) and a transmission pattern (TP).

[0184] In this way, the color conversion substrate 200 in FIG. 9 is manufactured.

[0185] 11 again, color conversion substrate 200 is bonded onto array substrate 100 with filling layer 300 sandwiched therebetween, thereby manufacturing display device 1000 in FIG.

[0186] Fig. 20 is a block diagram showing an electronic device including the display device of Fig. 1. Fig. 21 is a diagram showing an example in which the electronic device of Fig. 19 is implemented as a television. Fig. 22 is a diagram showing an example in which the electronic device of Fig. 19 is implemented as a smartphone.

[0187] 20, 21, and 22, in another embodiment, electronic device 900 includes a processor 910, a memory device 920, a storage device 930, an input / output device 940, a power supply 950, and a display device 960. In this case, display device 960 corresponds to display device 1000 described in Figures 1-11. Electronic device 900 further includes a number of ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc.

[0188] In another embodiment, the electronic device 900 is embodied as a television, as shown in Fig. 21. In another embodiment, the electronic device 900 is embodied as a smartphone, as shown in Fig. 22. However, the electronic device 900 is not limited thereto, and may be embodied as a mobile phone, a video phone, a smart pad, a smart watch, a tablet PC, a vehicle navigation system, a computer monitor, a laptop computer, a head-mounted display (HMD), or the like.

[0189] The processor 910 performs specific calculations or tasks. In other embodiments, the processor 910 is a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 910 is connected to other components via an address bus, a control bus, a data bus, etc. The processor 910 is also connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0190] The memory device 920 stores data necessary for the operation of the electronic device 900. In other embodiments, the memory device 920 includes a non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM) device, etc., and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.

[0191] The storage device 930 includes a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, and the like.

[0192] The input / output device 940 includes input means such as a keyboard, keypad, touchpad, touchscreen, mouse, etc., and output means such as a speaker, printer, etc.

[0193] A power supply 950 provides the power necessary for operation of the electronic device 900. A display device 960 is connected to the other components through a bus or other communication link. In other embodiments, the display device 960 can be included in the input / output device 940.

[0194] While the present invention has been described with reference to exemplary embodiments thereof, those skilled in the art will appreciate that various modifications and variations can be made thereto without departing from the spirit and scope of the present invention as set forth in the following claims. [Industrial Applicability]

[0195] The present invention can be applied to the manufacturing process of various display devices including a display device, such as high-resolution smartphones, mobile phones, smart pads, smart watches, tablet PCs, vehicle navigation systems, televisions, computer monitors, and notebook computers. [Explanation of symbols]

[0196] 1000:Display device EA1, EA2, EA3: first to third light-emitting regions CA:Contact area NEA: Non-Emitting Area TA1, TA2, TA3: First to third projection areas BA: Light blocking area PDL: Pixel-defined membrane IP: Insulation pattern PE1, PE2, PE3: first to third pixel electrodes PP1, PP2, PP3: first to third pattern portions CP1, CP2: first and second connecting portions COP1, COP2, COP3, COP4: First to fourth central openings POP: Peripheral opening OP1, OP2, OP3, OP4: first to fourth openings BL: Bank layer CCL: Color conversion layer 110: First substrate 170: Second substrate

Claims

1. a first substrate including first to third light-emitting regions and a non-light-emitting region surrounding the first to third light-emitting regions; first to third pixel electrodes located in the first to third light-emitting regions on the first substrate, respectively; a pixel defining film positioned in the non-light emitting region on the first substrate, the pixel defining film defining a peripheral opening that partially overlaps the non-light emitting region; a second substrate including first to third light-projecting regions and a light-shielding region surrounding the first to third light-projecting regions; a bank layer positioned in the light-shielding region on one surface of the second substrate facing the pixel defining layer, the bank layer defining first openings overlapping the first to third light-transmitting regions, respectively, and second openings overlapping the light-shielding region, each having a polygonal planar shape; a color conversion layer located in the first opening and including color conversion particles.

2. a planarization layer located between the first substrate and the pixel defining layer, the planarization layer comprising an organic material; The display device according to claim 1 , wherein the peripheral opening exposes a portion of the upper surface of the planarization layer.

3. The display device of claim 1 , wherein the pixel defining layer extends continuously along at least two adjacent light emitting regions among the first, second, and third light emitting regions.

4. The first to third light-emitting regions are repeatedly arranged along a first direction and a second direction intersecting the first direction, The pixel defining film is a first pattern portion covering an edge of the first pixel electrode; a second pattern portion covering an edge of the second pixel electrode; a third pattern portion covering an edge of the third pixel electrode; a first connecting portion overlapping a portion of the first pixel electrode and connecting the first to third pattern portions; 2. The display device according to claim 1, further comprising a second connecting portion that connects two adjacent pattern portions among the first to third pattern portions and includes a portion extending in the first direction and a portion extending in the second direction.

5. 2. The display device of claim 1, wherein the pixel defining layer further defines a central opening that exposes a portion of an upper surface of each of the first, second, and third pixel electrodes.

6. The display device of claim 1 , wherein the pixel defining layer comprises an inorganic material or an organic material.

7. 7. The display device of claim 6, wherein the pixel defining layer includes an organic material containing at least one selected from the group consisting of a black pigment, a black dye, and carbon black.

8. 2. The display device according to claim 1, wherein each of the second openings has a rectangular planar shape.

9. The bank layer is a first partition wall located in at least one of the second openings; 2. The display device according to claim 1, further comprising a second partition wall that is formed integrally with the first partition wall and is a remaining portion excluding the first partition wall.

10. 10. The display device according to claim 9, wherein the second opening where the first partition is located is divided into two openings by the first partition.

11. The bank layer includes: a third opening extending in the first direction; 2. The display device according to claim 1, further comprising a fourth opening extending in a second direction intersecting the first direction.

12. the first to third light projection regions are repeatedly arranged along the first direction and the second direction, 12. The display device according to claim 11, wherein the third opening is located adjacent to the first opening that overlaps the second light projection area, and the fourth opening is located between the first openings that overlap the first and third light projection areas, respectively.

13. 2. The display device according to claim 1, wherein the first light-projecting region overlaps the first light-emitting region, the second light-projecting region overlaps the second light-emitting region, and the third light-projecting region overlaps the third light-emitting region.

14. 14. The display device according to claim 13, wherein an area of the first light-emitting region is smaller than an area of the first light-projecting region, an area of the second light-emitting region is smaller than an area of the second light-projecting region, and an area of the third light-emitting region is smaller than an area of the third light-projecting region.

15. the first to third light-emitting regions emit light of a first color; 14. The display device of claim 13, wherein the first light projection area transmits light of a second color different from the first color, the second light projection area transmits light of a third color different from the first color and the second color, and the third light projection area transmits light of the first color.

16. a color filter layer located on one surface of the second substrate; 2. The display device of claim 1, further comprising a protective layer including an inorganic material, the protective layer being located on one surface of the color filter layer facing the bank layer.

17. 17. The display device according to claim 16, wherein the bank layer is located on one surface of the protective layer facing the bank layer, and the second opening exposes an upper surface of the protective layer.

18. a filling layer disposed between the pixel defining layer and the bank layer, the filling layer including a light-transmitting material; 2. The display device according to claim 1, wherein the second opening is filled with a part of the filling layer.

19. a first substrate having a light emitting region, a contact region adjacent to the light emitting region, and a non-light emitting region surrounding the light emitting region and the contact region; a pixel electrode located in the light-emitting region on the first substrate; a pixel defining layer positioned on the first substrate, the pixel defining layer defining a central opening in the light emitting region that exposes a portion of an upper surface of the pixel electrode, and a peripheral opening in the non-light emitting region that is spaced apart from the pixel electrode in a plane; a second substrate including a light-emitting region and a light-shielding region surrounding the light-emitting region and overlapping the contact region; a bank layer positioned on one surface of the second substrate facing the pixel definition layer, the bank layer defining a first opening overlapping the light projection area and a second opening overlapping the contact area, each having a polygonal planar shape; a color conversion layer located in the first opening and including color conversion particles.

20. The display device of claim 19, wherein the contact area is subjected to a laser drilling process.

21. 20. The display device of claim 19, further comprising an insulating pattern located on the first substrate, adjacent to the contact region, and including the same material as the pixel defining layer.

22. The display device of claim 21, wherein the insulating pattern is spaced apart from the pixel defining layer in a plan view.

23. 22. The display device of claim 21, wherein the insulating pattern entirely overlaps the second opening.

24. The display device of claim 21, wherein the insulating pattern is spaced apart from the bank layer in a plan view.

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