Display substrate and manufacturing method thereof, display device

Abstract

The display substrate, its manufacturing method, and display device include a display substrate including a base 101, a driving circuit layer 102, and a light-emitting structure layer 103. The driving circuit layer 102 includes a plurality of circuit units, each including a pixel driving circuit, each including at least a storage capacitor 40 and a compensation transistor T2, a first electrode of the compensation transistor T2 connected to a first electrode of the storage capacitor 40 via a first connecting electrode 41. The light-emitting structure layer 103 includes a plurality of light-emitting units, each including at least an anode 50, the anode 50 connected to the pixel driving circuit, an orthogonal projection of the anode 50 of at least one light-emitting unit on the base 101 at least partially overlaps with an orthogonal projection of the first connecting electrode 41 of at least one circuit unit on the base, and the shapes of the first connecting electrodes 41 of at least two circuit units are different.

Description

[Technical Field]

[0001] The present specification relates to the field of display technology, but is not limited thereto, and specifically to a display substrate and a manufacturing method thereof, and a display device. [Background technology]

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as autonomous light emission, wide viewing angle, high contrast, low power consumption, extremely fast response speed, light weight, thin profile, bendability, and low cost. With the development of display technology, flexible displays that use OLEDs or QLEDs as light-emitting devices and thin film transistors (TFTs) for signal control have become mainstream products in the current display field. Summary of the Invention

[0003] The following is a summary of the subject matter described herein, which does not limit the scope of protection of the claims.

[0004] In one aspect, the present disclosure provides a display substrate, comprising: a driving circuit layer disposed on a base; and a light-emitting structure layer disposed on a side of the driving circuit layer remote from the base, the driving circuit layer comprising a plurality of circuit units, the circuit units including at least a pixel driving circuit, the pixel driving circuit including at least a storage capacitor and a compensation transistor, a first electrode of the compensation transistor connected to a first electrode plate of the storage capacitor via a first connecting electrode; the light-emitting structure layer comprising a plurality of light-emitting units, the light-emitting units including at least an anode, the anode connected to the pixel driving circuit, an orthogonal projection of the anode of at least one light-emitting unit on the base at least partially overlaps with an orthogonal projection of the first connecting electrode of at least one circuit unit on the base, and shapes of the first connecting electrodes of at least two circuit units are different.

[0005] In an exemplary embodiment, the first connection electrode includes an electrode body portion and an electrode compensation portion, the electrode body portion includes a first end connected to a first plate of the storage capacitor and a second end connected to a first pole of the compensation transistor, the electrode compensation portion is provided on a side of the first end away from the second end, the electrode body portions of at least two circuit units have the same shape, and the electrode compensation portions of at least two circuit units have different shapes.

[0006] In an exemplary embodiment, the plurality of circuit units form a plurality of unit rows and a plurality of unit columns, the unit rows including a plurality of circuit units arranged sequentially along a first direction, the unit columns including a plurality of circuit units arranged sequentially along a second direction, the first direction intersecting the second direction, and in at least one unit column, the shapes of the first connection electrodes of at least two circuit units are the same.

[0007] In an exemplary embodiment, in at least one unit row, the plurality of circuit units includes at least a first circuit unit, a second circuit unit, and a third circuit unit, wherein the pixel driving circuit of the first circuit unit is connected to a red light-emitting unit that emits red light, the pixel driving circuit of the second circuit unit is connected to a blue light-emitting unit that emits blue light, and the pixel driving circuit of the third circuit unit is connected to a green light-emitting unit that emits green light, and the shapes of the first connection electrodes in the first circuit unit, the second circuit unit, and the third circuit unit are different.

[0008] In an exemplary embodiment, the shapes of the electrode main body portions in the first circuit unit, the second circuit unit, and the third circuit unit are the same, and the shapes of the electrode compensation portions in the first circuit unit, the second circuit unit, and the third circuit unit are different.

[0009] In an exemplary embodiment, the first connection electrode of the first circuit unit has a first length, the first connection electrode of the second circuit unit has a second length, and the first connection electrode of the third circuit unit has a third length, the first length, the second length, and the third length are different, and the first length, the second length, and the third length are the sizes of the first connection electrodes in the second direction.

[0010] In an exemplary embodiment, the second length is greater than the first length, and the second length is greater than the third length.

[0011] In an exemplary embodiment, the third length is greater than the first length.

[0012] In an exemplary embodiment, the anode of at least one light-emitting unit includes an anode body portion, an anode connection portion, and an anode compensation portion, the anode connection portion being configured to be connected to the pixel driving circuit, and the anode compensation portion being provided on a side of the anode connection portion remote from the anode body portion.

[0013] In an exemplary embodiment, in at least one circuit unit, an orthogonal projection of the anode compensation portion on the base at least partially overlaps with an orthogonal projection of the electrode compensation portion of the first connection electrode on the base.

[0014] In an exemplary embodiment, in at least one circuit unit, an orthogonal projection of the anode compensation portion on the base at least partially overlaps with an orthogonal projection of the electrode body portion of the first connection electrode on the base.

[0015] In an exemplary embodiment, in at least one circuit unit, an orthogonal projection of the anode body portion on the base at least partially overlaps with an orthogonal projection of the first connection electrode on the base.

[0016] In an exemplary embodiment, in at least one circuit unit, an orthogonal projection of the anode body portion on the base does not overlap with an orthogonal projection of the first connection electrode on the base.

[0017] In an exemplary embodiment, in at least one circuit unit, a compensation notch is provided in the anode, and the compensation notch is configured to reduce an overlapping area between the anode and the first connection electrode.

[0018] In an exemplary embodiment, the anode further includes a protrusion, the protrusion being provided on a side of the anode body portion away from the anode connection portion, the orthogonal projection of the protrusion on the base at least partially overlapping with the orthogonal projection of the first connection electrode on the base, and the compensation notch being provided on the protrusion.

[0019] In an exemplary embodiment, the compensation notch comprises a groove provided in an edge of the protrusion, the orthogonal projection of the groove on the base at least partially overlapping the orthogonal projection of the first connection electrode on the base.

[0020] In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on the base, the semiconductor layer including at least an active layer of the compensation transistor, the first conductive layer including at least a first electrode plate of the storage capacitor and a gate electrode of the compensation transistor, the second conductive layer including at least a second electrode plate of the storage capacitor, and the third conductive layer including at least the first connection electrode.

[0021] In another aspect, the present disclosure also provides a display device including the above-described display substrate.

[0022] In yet another aspect, the present disclosure further provides a method for manufacturing a display substrate, the method including: forming a driving circuit layer on a base, the driving circuit layer including a plurality of circuit units, the circuit unit including at least a pixel driving circuit, the pixel driving circuit including at least a storage capacitor and a compensation transistor, a first electrode of the compensation transistor connected to a first electrode plate of the storage capacitor through a first connecting electrode, the first connecting electrode of at least two circuit units having different shapes; and forming a light-emitting structure layer on the driving circuit layer, the light-emitting structure layer including a plurality of light-emitting units, the light-emitting units including at least an anode, the anode connected to the pixel driving circuit, an orthogonal projection of the anode of at least one light-emitting unit on the base at least partially overlaps with an orthogonal projection of the first connecting electrode of at least one circuit unit on the base.

[0023] Other aspects will be understood after reading and understanding the drawings and detailed description. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a structural schematic diagram of a display device. [Figure 2] FIG. 2 is a schematic plan view of the structure of a display substrate. [Figure 3] FIG. 2 is a schematic cross-sectional view of a display substrate. [Figure 4] FIG. 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit. [Figure 5] FIG. 2 is a schematic diagram illustrating the layout of a circuit unit according to an exemplary embodiment of the present disclosure. [Figure 6] FIG. 2 is a schematic diagram illustrating the layout of a light-emitting unit according to an exemplary embodiment of the present disclosure. [Figure 7] 1 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure; [Figure 8] 3 is a schematic diagram of a display substrate according to the present disclosure after a semiconductor layer pattern is formed on the display substrate. FIG. [Figure 9A] 3 is a schematic diagram of a display substrate according to the present disclosure after a first conductive layer pattern has been formed. FIG. [Figure 9B] 3 is a schematic diagram of a display substrate according to the present disclosure after a first conductive layer pattern has been formed. FIG. [Figure 10A] 3 is a schematic diagram of a display substrate according to the present disclosure after a second conductive layer pattern has been formed. FIG. [Figure 10B] 3 is a schematic diagram of a display substrate according to the present disclosure after a second conductive layer pattern has been formed. FIG. [Figure 11] 10 is a schematic diagram of the display substrate of the present disclosure after a fourth insulating layer pattern has been formed. FIG. [Figure 12A] 10 is a schematic diagram of a display substrate according to the present disclosure after a third conductive layer pattern has been formed. FIG. [Figure 12B] 10 is a schematic diagram of a display substrate according to the present disclosure after a third conductive layer pattern has been formed. FIG. [Figure 13] FIG. 2 is a schematic diagram of a display substrate according to the present disclosure after a flat layer pattern is formed on the substrate. [Figure 14A] 3 is a schematic diagram of a display substrate according to the present disclosure after an anode conductive layer pattern is formed on the display substrate. FIG. [Figure 14B] 3 is a schematic diagram of a display substrate according to the present disclosure after an anode conductive layer pattern is formed on the display substrate. FIG. [Figure 15A] FIG. 1 is a schematic plan view of an anode according to the present disclosure. [Figure 15B] FIG. 1 is a schematic plan view of an anode according to the present disclosure. [Figure 15C] FIG. 1 is a schematic plan view of an anode according to the present disclosure. [Figure 16A] FIG. 10 is a structural schematic diagram of another display substrate according to an embodiment of the present disclosure. [Figure 16B]FIG. 10 is a structural schematic diagram of another display substrate according to an embodiment of the present disclosure. [Figure 16C] FIG. 10 is a structural schematic diagram of another display substrate according to an embodiment of the present disclosure. [Figure 17A] FIG. 10 is a structural schematic diagram of yet another display substrate according to an embodiment of the present disclosure. [Figure 17B] FIG. 10 is a structural schematic diagram of yet another display substrate according to an embodiment of the present disclosure. [Figure 17C] FIG. 10 is a structural schematic diagram of yet another display substrate according to an embodiment of the present disclosure. [Figure 18A] FIG. 10 is a structural schematic diagram of yet another display substrate according to an embodiment of the present disclosure. [Figure 18B] FIG. 10 is a structural schematic diagram of yet another display substrate according to an embodiment of the present disclosure. [Explanation of symbols]

[0025] 11-first active layer, 12-second active layer, 13-third active layer, 14-4th active layer, 15-5th active layer, 16-6th active layer, 17—seventh active layer; 21—first scanning signal line; 22—second scanning signal line; 23 - light emission control signal line, 24 - first electrode plate, 31 - initial signal line, 32 - second electrode plate, 33 - electrode plate connecting wire, 34 - shield electrode, 35 - opening, 40 - storage capacitor, 41 - first connection electrode, 41-1 electrode main body part, 41-2 electrode compensation part, 42—second connection electrode, 43—third connection electrode; 44—data signal line; 45—first power line; 50-anode, 50-1 anode body, 50-2 anode compensation part, 51-first anode, 52-second anode, 53-third anode, 54—fourth anode, 55—fifth anode, 71—first convex portion, 72—second convex portion, 73—third convex portion, 74—fourth convex portion, 75—fifth convex portion, 76—sixth convex portion, 81—first anode compensation portion, 82—second anode compensation part, 83—third anode compensation part, 90—compensation notch, 101 - base, 102 - driving circuit layer, 103 - light emitting structure layer, 104 - Package structure layer. DETAILED DESCRIPTION OF THE INVENTION

[0026] The drawings are intended to facilitate understanding of the technical solutions of the present disclosure, constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present application, but are not intended to limit the technical solutions of the present disclosure.

[0027] To clarify the objectives, technical solutions, and advantages of the present disclosure, the following detailed description of the embodiments of the present disclosure will be given with reference to the accompanying drawings. It should be noted that the embodiments can be implemented in many different forms. As those skilled in the art can easily understand, the manner and content of the present disclosure can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the following embodiments. Where there is no conflict, the embodiments and features of the embodiments of the present disclosure can be combined with each other.

[0028] The proportions in the drawings in this disclosure may be used as a reference for actual processes, but are not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual needs. The number of pixels on the display substrate and the number of subpixels in each pixel are also not limited to the numbers shown in the drawings. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0029] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components and are not intended to limit the number of components.

[0030] For convenience, the positions of components in this specification are described with reference to the drawings using terms indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer." However, this is intended to simplify and explain the specification, and is not intended to indicate or suggest that the described devices or elements have a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit the present disclosure. The positional relationships of components may be appropriately changed depending on the direction in which each component is described. Therefore, the terms described in the specification may not be limited and may be appropriately changed as the case may be.

[0031] In this specification, unless otherwise clearly specified and limited, the terms "attach," "couple," and "connect" should be understood in a broad sense. For example, they may be fixedly connected, detachably connected, or integrally connected. They may be mechanically connected or electrically connected. They may be directly connected, indirectly connected via a linker, or internally connected between two elements. Those skilled in the art can understand the specific meanings of the above terms in the present disclosure according to the specific circumstances.

[0032] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and a current can flow through the drain electrode, channel region, and source electrode. In this specification, the channel region refers to a region through which a current mainly flows.

[0033] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. When using a transistor with opposite polarity, or when the current direction during operation in a circuit changes, the functions of "source electrode" and "drain electrode" may be interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" may be interchangeable, and "source terminal" and "drain terminal" may be interchangeable.

[0034] In this specification, "electrically connected" includes cases where components are connected via an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected components. Examples of "elements having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0035] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is between -10° and 10°, and includes a state in which the angle is between -5° and 5°. "Perpendicular" refers to a state in which the angle formed by two straight lines is between 80° and 100°, and includes a state in which the angle is between 85° and 95°.

[0036] In this specification, the terms "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0037] The triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not intended to be exact, and may be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc., and may have small variations due to tolerances, chamfers, arc edges, and variations.

[0038] In this disclosure, "about" refers to a case where the boundary is not precisely defined, but rather allows for a numerical value within the tolerances of process and measurement.

[0039] FIG. 1 is a schematic diagram of a display device. As shown in FIG. 1, the display device includes a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data drivers are connected to a plurality of data signal lines (D1-Dn), the scan drivers are connected to a plurality of scan signal lines (S1-Sm), and the light-emitting drivers are connected to a plurality of light-emitting signal lines (E1-Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit is connected to the scan signal lines, data signal lines, and light-emitting signal lines, respectively. In an exemplary embodiment, the timing controller provides gray values ​​and control signals conforming to the specifications of the data driver to the data driver, provides clock signals, scan start signals, etc. conforming to the specifications of the scan driver to the scan driver, and provides clock signals, firing stop signals, etc. conforming to the specifications of the light-emitting driver to the light-emitting driver. The data driver generates data voltages to be provided to the data signal lines D1, D2, D3, ..., Dn using gray values ​​and control signals received from the timing controller. For example, the data driver may sample gray values ​​using a clock signal and apply data voltages corresponding to the gray values ​​to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver receives a clock signal, a scan start signal, etc. from the timing controller and generates scan signals to be provided to the scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver may sequentially provide scan signals having turn-on level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and generate scan signals by sequentially transferring the scan start signal, provided in the form of a turn-on level pulse, to the next stage circuit under the control of a clock signal, where m may be a natural number.The light emitting driver receives a clock signal, a firing stop signal, etc. from the timing controller to generate firing signals to be provided to the light emitting signal lines E1, E2, E3, ..., Eo. For example, the light emitting driver may sequentially provide firing signals having cutoff level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate firing signals by sequentially transferring the firing stop signal provided in the form of a cutoff level pulse to the next stage circuit under the control of the clock signal, where o may be a natural number.

[0040] 2 is a schematic planar diagram of a display substrate. In an exemplary embodiment, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, each of the three sub-pixels including a circuit unit and a light-emitting unit, the circuit unit may include a pixel driving circuit, and the light-emitting unit may include a light-emitting unit, the pixel driving circuit being connected to scanning signal lines, data signal lines, and emission signal lines, respectively, the pixel driving circuit being configured to receive data voltages transmitted by the data signal lines under the control of the scanning signal lines and emission signal lines, and output corresponding currents to the light-emitting units, and the light-emitting units being configured to emit light with corresponding luminance in response to the currents output by the connected pixel driving circuits.

[0041] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the shape of the subpixel may be rectangular, rhombic, pentagonal, or hexagonal, and the three subpixels may be arranged in a horizontal parallelepiped, vertical parallelepiped, or square shape, etc.

[0042] In another exemplary embodiment, the pixel unit P may include four sub-pixels, and the four sub-pixels may be arranged in a manner such as horizontally parallel, vertically parallel, diamond-shaped, or square-shaped, but the present disclosure is not limited thereto.

[0043] 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three subpixels on the display substrate. As shown in FIG. 3, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a base 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the base, and a packaging structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the base. In some possible implementations, the display substrate may include other film layers, such as spacer columns, and the present disclosure is not limited thereto.

[0044] In an exemplary embodiment, the base 101 may be a flexible base or a rigid base. The driving circuit layer 102 of each subpixel may include multiple circuit units, which may include a pixel driving circuit consisting of multiple transistors and a storage capacitor. However, FIG. 3 only shows an example in which the pixel driving circuit includes one driving transistor and one storage capacitor. The light-emitting structure layer 103 of each subpixel may include multiple light-emitting units, which may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the drain electrode of the driving transistor through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color when driven by the anode and the cathode. The package structure layer 104 may include a first package layer, a second package layer, and a third package layer stacked together, the first package layer and the third package layer being made of inorganic materials, the second package layer being made of organic materials, and the second package layer being disposed between the first package layer and the third package layer, which can ensure that external water vapor does not penetrate into the light emitting structure layer 103.

[0045] In exemplary embodiments, the organic light-emitting layer may include an emissive layer (EML) and any one or more of a hole-injection layer (HIL), a hole-transport layer (HTL), an electron-blocking layer (EBL), a hole-blocking layer (HBL), an electron-transport layer (ETL), and an electron-injection layer (EIL). In exemplary embodiments, the hole-injection layer, electron-injection layer, hole-transport layer, electron-transport layer, hole-blocking layer, and electron-blocking layer of all the light-emitting units may be common layers connected to each other, or the light-emitting layers of adjacent light-emitting units may have a small amount of overlap or may be separated.

[0046] 4 is a schematic equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 4, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) connected to seven signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light-emitting signal line E, initial signal line INIT, first power supply line VDD, and second power supply line VSS), respectively, and one storage capacitor C.

[0047] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to a first pole of the third transistor T3, a second pole of the fourth transistor T4, and a second pole of the fifth transistor T5, respectively. The second node N2 is connected to a second pole of the first transistor T3, a first pole of the second transistor T2, a control pole of the third transistor T3, and a second end of the storage capacitor C, respectively. The third node N3 is connected to a second pole of the second transistor T2, a second pole of the third transistor T3, and a first pole of the sixth transistor T6, respectively. The fourth node N4 is connected to a second pole of the sixth transistor T6 and a second pole of the seventh transistor T7, respectively.

[0048] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, i.e., the second end of the storage capacitor C is connected to the control pole of the third transistor T3.

[0049] The control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor T1 is connected to the second node N2. When an on-level scanning signal is applied to the second scanning signal line S2, the first transistor T1 transmits an initial voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.

[0050] The control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When an on-level scanning signal is applied to the first scanning signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0051] The third transistor T3 has a control electrode connected to the second node N2, a control electrode connected to the second end of the storage capacitor C, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 may be referred to as a drive transistor, and determines the amount of drive current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and first electrode.

[0052] The control electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 may also be called a switching transistor, a scanning transistor, etc., and when an on-level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0053] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 may be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting element EL to emit light.

[0054] The seventh transistor T7 has a control electrode connected to the first scanning signal line S1, a first electrode connected to the initial signal line INIT, and a second electrode connected to the first electrode of the light-emitting element EL. When an on-level scanning signal is applied to the first scanning signal line S1, the seventh transistor T7 transmits an initial voltage to the first electrode of the light-emitting element EL to initialize or release the charge accumulated in the first electrode of the light-emitting element EL.

[0055] In an exemplary embodiment, the light-emitting element EL may be an OLED in which a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) are stacked, or may be a QLED in which a first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode) are stacked.

[0056] In an exemplary embodiment, the second electrode of the light-emitting element EL is connected to a second power supply line VSS, the signal of the second power supply line VSS is a continuously supplied low-level signal, and the signal of the first power supply line VDD is a continuously supplied high-level signal.

[0057] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit simplifies the process flow, reduces the process difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0058] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, oxide thin-film transistors, or a combination of low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistors uses low-temperature polysilicon (abbreviated as LTPS), and the active layer of the oxide thin-film transistors uses an oxide semiconductor (oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. By integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a single display substrate to form a low-temperature polycrystalline oxide (abbreviated as LTPO) display substrate, the advantages of both can be utilized, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0059] In an exemplary embodiment, taking the seven transistors in the pixel driving circuit of FIG. 4 as an example, all are P-type transistor OLED, the operation process of the pixel driving circuit may include the following steps:

[0060] The first stage A1 is called the reset stage, in which the signal on the second scanning signal line S2 is low, and the signals on the first scanning signal line S1 and the light-emitting signal line E are high. The signal on the second scanning signal line S2 is low, turning on the first transistor T1. The signal on the initialization signal line INIT is supplied to the second node N2, initializing the storage capacitor C and clearing the original data voltage in the storage capacitor. The signals on the first scanning signal line S1 and the light-emitting signal line E are high, turning off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. In this stage, the OLED does not emit light.

[0061] The second stage A2 is called the data writing stage or threshold compensation stage. The signal on the first scanning signal line S1 is low, the signals on the second scanning signal line S2 and the light-emitting signal line E are high, and the data signal line D outputs a data voltage. In this stage, the second end of the storage capacitor C is low, so the third transistor T3 is turned on. The signal on the first scanning signal line S1 is low, so the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on. By turning on the second transistor T2 and the fourth transistor T4, the data voltage output by the data signal line D is supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second end (second node N2) of the storage capacitor C is Vd-|Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. By turning on the seventh transistor T7, the initial voltage of the initial signal line INIT is supplied to the first terminal of the OLED, initializing (resetting) the first terminal of the OLED and clearing the internal pre-stored voltage. The initialization is completed, ensuring that the OLED does not emit light. The signal of the second scan signal line S2 is a high-level signal, turning off the first transistor T1. The signal on the light-emitting signal line E is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0062] The third stage A3 is called the light-emitting stage, in which the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD supplies a driving voltage to the first electrode of the OLED through the fifth transistor T5, the third transistor T3 and the sixth transistor T6 that are turned on, thereby driving the OLED to emit light.

[0063] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage at the second node N2 is Vd-|Vth|, the driving current of the third transistor T3 is given by the following equation:

[0064] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0065] where I is the driving current flowing through the third transistor T3, i.e., the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0066] An exemplary embodiment of the present disclosure provides a display substrate. In a plane perpendicular to the display substrate, a display region may include a driving circuit layer disposed on a base, a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, and a packaging structure layer disposed on a side of the light-emitting structure layer away from the base. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each including at least a pixel driving circuit configured to output a corresponding current under control of a corresponding signal line. The light-emitting structure layer is connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting unit is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0067] In an exemplary embodiment, the circuit unit referred to in the present disclosure refers to an area divided for each pixel driving circuit, and the light-emitting unit referred to in the present disclosure refers to an area divided for each light-emitting element. In an exemplary embodiment, the position and shape of the orthogonal projection on the base of the light-emitting unit may correspond to the position and shape of the orthogonal projection on the base of the circuit unit, or the position and shape of the orthogonal projection on the base of the light-emitting unit may not correspond to the position and shape of the orthogonal projection on the base of the circuit unit.

[0068] 5 is a schematic diagram of the layout of circuit units in an exemplary embodiment of the present disclosure. As shown in FIG. 5, in the exemplary embodiment, in a plane parallel to the display substrate, the driving circuit layer in the display area may include a plurality of circuit units PA, which may form a plurality of unit rows and unit columns, where each unit row may include a plurality of circuit units PA arranged sequentially along a first direction X, and each unit column may include a plurality of circuit units PA arranged sequentially along a second direction Y, where the first direction X and the second direction Y may intersect.

[0069] In an exemplary embodiment, the shape of the circuit unit PA may be rectangular, and the long sides of the rectangular circuit unit PA may extend along the second direction Y (column direction), and the short sides of the rectangular circuit unit PA may extend along the first direction X (row direction), forming a horizontal parallel unit arrangement.

[0070] In an exemplary embodiment, the circuit unit PA may include at least a pixel driving circuit, which is respectively connected to the scanning signal lines, the data signal lines, and the light-emitting signal lines, and which is configured to receive the data voltage transmitted from the data signal lines under the control of the scanning signal lines and the light-emitting signal lines, and output a current corresponding to the connected light-emitting units.

[0071] 6 is a schematic diagram of the arrangement of light-emitting units in an exemplary embodiment of the present disclosure. As shown in FIG. 6, in an exemplary embodiment, in a plane parallel to the display substrate, the light-emitting structure layer of the display substrate may include a plurality of light-emitting units PB regularly arranged, and the plurality of light-emitting units PB may form a plurality of pixel rows and a plurality of pixel columns, where each pixel row may include a plurality of light-emitting units PB sequentially arranged along a first direction X, and each pixel column may include a plurality of light-emitting units PB sequentially arranged along a second direction Y.

[0072] In an exemplary embodiment, the plurality of light emitting units PB may include a red light emitting unit that emits red light, a blue light emitting unit that emits blue light, and a green light emitting unit that emits green light, and the red light emitting units, blue light emitting units, and green light emitting units in each pixel row may be periodically arranged in the first direction X, and the red light emitting units, blue light emitting units, and green light emitting units in odd-numbered pixel rows and even-numbered pixel rows may be staggered, and six light emitting units share one surrounding light emitting unit, forming a Delta pixel arrangement, which is characterized by a large pixel aperture ratio.

[0073] In an exemplary embodiment, the light-emitting unit is connected to a pixel driving circuit of a corresponding circuit unit, and the light-emitting unit is configured to emit light at a corresponding brightness in response to a current output by the connected pixel driving circuit.

[0074] In an exemplary embodiment, the shape of the light emitting unit PB may include any one or more of a triangle, a rectangle, a rhombus, a pentagon, and a hexagon.

[0075] An exemplary embodiment of the present disclosure provides a display substrate, including: a driving circuit layer disposed on a base; and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, the driving circuit layer including a plurality of circuit units, the circuit unit including at least a pixel driving circuit, the pixel driving circuit including at least a storage capacitor and a compensation transistor, a first electrode of the compensation transistor connected to a first electrode plate of the storage capacitor through a first connecting electrode; the light-emitting structure layer including a plurality of light-emitting units, the light-emitting units including at least an anode, the anode connected to the pixel driving circuit, an orthogonal projection of the anode of at least one light-emitting unit on the base at least partially overlaps with an orthogonal projection of the first connecting electrode of at least one circuit unit on the base, and shapes of the first connecting electrodes of at least two circuit units are different.

[0076] In an exemplary embodiment, the first connection electrode includes an electrode body portion and an electrode compensation portion, the electrode body portion includes a first end connected to a first plate of the storage capacitor and a second end connected to a first pole of the compensation transistor, the electrode compensation portion is provided on a side of the first end away from the second end, the electrode body portions of at least two circuit units have the same shape, and the electrode compensation portions of at least two circuit units have different shapes.

[0077] In an exemplary embodiment, the plurality of circuit units form a plurality of unit rows and a plurality of unit columns, the unit rows including a plurality of circuit units arranged sequentially along a first direction, the unit columns including a plurality of circuit units arranged sequentially along a second direction, the first direction intersecting the second direction, and in at least one unit column, the shapes of the first connection electrodes of at least two circuit units are the same.

[0078] In an exemplary embodiment, in at least one unit row, the plurality of circuit units includes at least a first circuit unit, a second circuit unit, and a third circuit unit, wherein the pixel driving circuit of the first circuit unit is connected to a red light-emitting unit that emits red light, the pixel driving circuit of the second circuit unit is connected to a blue light-emitting unit that emits blue light, and the pixel driving circuit of the third circuit unit is connected to a green light-emitting unit that emits green light, and the shapes of the first connection electrodes in the first circuit unit, the second circuit unit, and the third circuit unit are different.

[0079] In an exemplary embodiment, the anode of at least one light-emitting unit includes an anode body portion, an anode connection portion, and an anode compensation portion, the anode connection portion being configured to be connected to the pixel driving circuit, and the anode compensation portion being provided on a side of the anode connection portion remote from the anode body portion.

[0080] In an exemplary embodiment, in at least one circuit unit, an orthogonal projection of the anode compensation portion on the base at least partially overlaps with an orthogonal projection of the electrode compensation portion of the first connection electrode on the base.

[0081] In an exemplary embodiment, in at least one circuit unit, an orthogonal projection of the anode compensation portion on the base at least partially overlaps with an orthogonal projection of the electrode body portion of the first connection electrode on the base.

[0082] In an exemplary embodiment, in at least one circuit unit, a compensation notch is provided in the anode, and the compensation notch is configured to reduce an overlapping area between the anode and the first connection electrode.

[0083] In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on the base, the semiconductor layer including at least an active layer of the compensation transistor, the first conductive layer including at least a first electrode plate of the storage capacitor and a gate electrode of the compensation transistor, the second conductive layer including at least a second electrode plate of the storage capacitor, and the third conductive layer including at least the first connection electrode.

[0084] 7 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate may include a driving circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. As shown in FIG. 7, in a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and the light-emitting structure layer may include a plurality of light-emitting units forming a plurality of pixel rows and a plurality of pixel columns, at least one circuit unit may include at least a pixel driving circuit, and at least one light-emitting unit may include at least one anode connected to a corresponding pixel driving circuit.

[0085] In an exemplary embodiment, the plurality of unit columns may include a first unit column and a second unit column, and the plurality of pixel columns may include a first pixel column and a second pixel column. In an exemplary embodiment, the first unit column and the first pixel column may be odd unit columns and odd pixel columns, respectively, and the second unit column and the second pixel column may be even unit columns and even pixel columns, respectively. In another exemplary embodiment, the first unit column and the first pixel column may be even unit columns and even pixel columns, respectively, and the second unit column and the second pixel column may be odd unit columns and odd pixel columns, respectively. In the following description of the present disclosure, the first unit column and the first pixel column are respectively odd-numbered unit columns and odd-numbered pixel columns, and the second unit column and the second pixel column are respectively even-numbered unit columns and even-numbered pixel columns. The odd unit column and odd-numbered pixel column may include the Nth column, the N+2th column, the N+4th column, the N+6th column, and the N+8th column, and the even unit column and even pixel column may include the N+1th column, the N+3th column, the N+5th column, and the N+7th column.

[0086] In an exemplary embodiment, the pixel driving circuit of the circuit unit may include at least a compensation transistor and a storage capacitor 40, and a first pole of the compensation transistor is connected to a first plate of the storage capacitor 40 via a first connection electrode 41.

[0087] In an exemplary embodiment, the orthogonal projection of the anode 50 of at least one light-emitting unit in the first pixel column at the base thereof has a first overlapping area with the orthogonal projection of the first connection electrode 41 of at least one circuit unit in the first unit column at the base thereof, and the orthogonal projection of the anode 50 of at least one light-emitting unit in the second pixel column at the base thereof has a second overlapping area with the orthogonal projection of the first connection electrode 41 of at least one circuit unit in the second unit column at the base thereof, and the ratio of the first overlapping area to the second overlapping area may be approximately 0.8 to 1.2.

[0088] In an exemplary embodiment, the first connection electrode 41 of at least one circuit unit in the first unit row may include an electrode body portion 41-1 and an electrode compensation portion 41-2, and the electrode compensation portion 41-2 may be located on the second direction Y side of the electrode body portion 41-1.

[0089] In an exemplary embodiment, the electrode body portion 41-1 may include a first end connected to a first plate of the storage capacitor 40 and a second end connected to a first pole of the compensation transistor, and the electrode compensation portion 41-2 may be provided on a side of the electrode body portion 41-1 where the first end is away from the second end, and the electrode compensation portion 41-2 extends in a direction away from the electrode body portion 41-1.

[0090] In an exemplary embodiment, the anode of at least one light-emitting unit in the first pixel column may include an anode body portion 50-1 and an anode compensation portion 50-2, and the anode compensation portion 50-2 may be located on the opposite side of the anode body portion 50-1 in the second direction Y.

[0091] In an exemplary embodiment, the anode 50 may further include an anode connection portion, which may be provided on the opposite side of the anode body portion 50-1 in the second direction Y, the anode connection portion being configured to be connected to the pixel driving circuit, and the anode compensation portion 50-2 may be provided on the side of the anode connection portion away from the anode body portion 50-1, the anode compensation portion 50-2 extending in a direction away from the anode body portion 50-1.

[0092] In the exemplary embodiment, the orthogonal projection of the anode compensation portion 50-2 on the base at least partially overlaps with the orthogonal projection of the electrode compensation portion 41-2 of the first connecting electrode 41 on the base.

[0093] In the exemplary embodiment, the orthogonal projection of the anode compensation portion 50-2 on the base at least partially overlaps with the orthogonal projection of the electrode body portion 41-1 of the first connection electrode 41 on the base.

[0094] In an exemplary embodiment, the orthogonal projection of at least one light-emitting unit in the first pixel column at the base of the anode body portion 50-1 does not overlap with the orthogonal projection of at least one light-emitting unit in the second pixel column at the base of the anode body portion 50-1 at least partially overlaps with the orthogonal projection of at least one light-emitting unit in the second pixel column at the base of the anode body portion 50-1 at least partially overlaps with the orthogonal projection of at least one light-emitting unit in the second pixel column at the base of the first connection electrode 41.

[0095] In an exemplary embodiment, the first overlap area may include the overlap area between the orthogonal projection at the base of the anode compensation portion 50-2 and the orthogonal projection at the bases of the electrode main body portion 41-1 and the electrode compensation portion 41-2, and the second overlap area may include the overlap area between the orthogonal projection at the base of the anode 50 and the orthogonal projection at the base of the first connection electrode 41, and the ratio of the first overlap area to the second overlap area may be approximately 0.9 to 1.1.

[0096] In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially disposed on a base, wherein the semiconductor layer includes at least active layers of a plurality of transistors in the pixel driving circuit, the first conductive layer includes at least a first plate of the storage capacitor and gate electrodes of the plurality of transistors, the second conductive layer includes at least a second plate of the storage capacitor, and the third conductive layer includes at least a first connection electrode 41.

[0097] In an exemplary embodiment, the drive circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a planar layer, wherein the first insulating layer is disposed between the base and the semiconductor layer, the second insulating layer is disposed between the semiconductor layer and the first conductive layer, the third insulating layer is disposed between the first conductive layer and the second conductive layer, the fourth insulating layer is disposed between the second conductive layer and the third conductive layer, and the planar layer is disposed between the third conductive layer and the anode.

[0098] The manufacturing process of a display substrate is described below by way of example. The "patterning process" described in this disclosure includes processes such as photoresist application, mask exposure, development, etching, and photoresist stripping for metal materials, inorganic materials, and transparent conductive materials, and organic material application, mask exposure, and development for organic materials. Deposition may include one or more of sputtering, evaporation, and chemical vapor deposition. Coating may include one or more of spraying, spin coating, and inkjet printing. Etching may include one or more of dry etching and wet etching, but the present disclosure is not limited to these processes. A "thin film" refers to a thin film layer fabricated on a base material by deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be referred to as a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern." In the present disclosure, "A and B are disposed on the same layer" means that A and B are formed simultaneously by the same patterning process. The "thickness" of a film layer is the size of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of the present disclosure, "the orthogonal projection of B is within the range of the orthogonal projection of A" or "the orthogonal projection of A includes the orthogonal projection of B" means that the boundary of the orthogonal projection of B is within the boundary range of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps the boundary of the orthogonal projection of B.

[0099] In an exemplary embodiment, manufacturing the display substrate may include manufacturing at least a driving circuit layer and a light emitting structure layer.

[0100] In an exemplary embodiment, taking 18 circuit units (2 unit rows and 9 unit columns) as an example, the manufacturing process of the driving circuit layer may include the following operations.

[0101] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, as shown in Figure 8, forming a semiconductor layer pattern may include sequentially depositing a first insulating thin film and a semiconductor thin film on a base, patterning the semiconductor thin film by a patterning process, and forming a first insulating layer covering the base and a semiconductor layer disposed on the first insulating layer.

[0102] In an exemplary embodiment, the semiconductor layer of each circuit unit may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, where the first active layer 11 to the seventh active layer 17 are connected to each other and form an integral structure, and the sixth active layer 16 of the circuit unit in the Mth row and the seventh active layer 17 of the circuit unit in the (M+1)th row of each unit column are connected to each other, i.e., the semiconductor layers of adjacent circuit units in each unit column are connected to each other and form an integral structure.

[0103] In an exemplary embodiment, in the first direction X, the fourth active layer 14 and the fifth active layer 15 of the circuit unit in the Nth row may be located on a side closer to the circuit unit in the N+1th row of the third active layer 13 of this circuit unit, and the second active layer 12 and the sixth active layer 16 may be located on a side farther from the circuit unit in the N+1th row of this circuit unit.

[0104] In an exemplary embodiment, in the second direction Y, the first active layer 11, the second active layer 12, the fourth active layer 14, and the seventh active layer 17 of the circuit unit in the Mth row may be located on the side of the third active layer 13 of the circuit unit away from the circuit unit in the M+1th row, the first active layer 11 and the seventh active layer 17 may be located on the side of the second active layer 12 and the fourth active layer 14 away from the third active layer 13, and the fifth active layer 15 and the sixth active layer 16 of the circuit unit in the Mth row may be located on the side of the third active layer 13 closer to the circuit unit in the M+1th row.

[0105] In an exemplary embodiment, the first active layer 11 may have an "n" shape, the third active layer 13 may have an "S" shape, the second active layer 12 may have an "L" shape, and the fourth active layer 14, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may have an "I" shape.

[0106] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 11-1 of the first active layer 11 may be the first region 17-1 of the seventh active layer 17, the second region 11-2 of the first active layer 11 may be the first region 12-1 of the second active layer 12, the first region 13-1 of the third active layer 13 may simultaneously be the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, the second region 13-2 of the third active layer 13 may simultaneously be the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16, the second region 16-2 of the sixth active layer 16 may simultaneously be the second region 17-2 of the seventh active layer 17, and the first region 14-1 of the fourth active layer 14 and the first region 15-1 of the fifth active layer 15 are provided separately.

[0107] (2) Forming a first conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 9A and 9B, forming the first conductive layer pattern may include sequentially depositing a second insulating thin film and a first conductive thin film on the patterned base, patterning the first conductive thin film using a patterning process, and forming a second insulating layer covering the semiconductor layer pattern and the first conductive layer pattern disposed on the second insulating layer. FIG. 9B is a schematic plan view of the first conductive layer in FIG. 9A. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0108] In an exemplary embodiment, the first conductive layer pattern of each circuit unit may include at least a first scanning signal line 21 , a second scanning signal line 22 , a light emission control signal line 23 and a first electrode plate 24 .

[0109] In an exemplary embodiment, the first plate 24 of the storage capacitor may be rectangular in shape, with chamfered corners, and the orthogonal projection of the base of the first plate 24 at least partially overlaps the orthogonal projection of the base of the third active layer of the third transistor T3. In an exemplary embodiment, the first plate 24 may simultaneously be one plate of the storage capacitor and the gate electrode of the third transistor T3.

[0110] In an exemplary embodiment, the first scanning signal line 21, the second scanning signal line 22, and the light-emitting control signal line 23 may have linear shapes whose main bodies extend along the first direction X, and the first scanning signal line 21 in the circuit unit in the Mth row may be located on a side of the first electrode plate 24 of the circuit unit that is far from the circuit unit in the (M+1)th row, the second scanning signal line 22 may be located on a side of the first scanning signal line 21 that is far from the first electrode plate 24, and the light-emitting control signal line 23 may be located on a side of the first electrode plate 24 of the circuit unit that is close to the circuit unit in the (M+1)th row.

[0111] In an exemplary embodiment, a gate block 21-1 is provided on the side of the first scanning signal line 21 away from the first electrode plate 24, and the region where the first scanning signal line 21 and the gate block 21-1 overlap with the second active layer 12 serves as the gate electrode of the second transistor T2 having a dual gate structure, and the region where the first scanning signal line 21 overlaps with the fourth active layer 14 serves as the gate electrode of the fourth transistor T4.

[0112] In an exemplary embodiment, the overlapping area between the second scanning signal line 22 and the first active layer 11 is the gate electrode of the first transistor T1 of the dual gate structure, the overlapping area between the second scanning signal line 22 and the seventh active layer 17 is the gate electrode of the seventh transistor T7, the overlapping area between the light emission control signal line 23 and the fifth active layer 15 is the gate electrode of the fifth transistor T5, and the overlapping area between the light emission control signal line 23 and the sixth active layer 16 is the gate electrode of the sixth transistor T6.

[0113] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer is made conductive using the first conductive layer as a shield, and the semiconductor layer in the area shielded by the first conductive layer forms the channel regions of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is made conductive, that is, the first and second areas of the first to seventh active layers are all made conductive.

[0114] (3) Forming a second conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 10A and 10B, forming the second conductive layer pattern may include sequentially depositing a third insulating thin film and a second conductive thin film on the patterned base, patterning the second conductive thin film by a patterning process, and forming a third insulating layer covering the first conductive layer and a second conductive layer pattern disposed on the third insulating layer. FIG. 10B is a schematic plan view of the second conductive layer in FIG. 10A. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0115] In an exemplary embodiment, the second conductive layer pattern of each circuit unit may include at least an initial signal line 31, a second electrode plate 32, an electrode plate connection line 33, and a shield electrode .

[0116] In an exemplary embodiment, the shape of the initial signal line 31 may be a line whose main body extends along the first direction X, and the initial signal line 31 in the circuit unit of the Mth row may be located on the side of the second scanning signal line 22 away from the first scanning signal line 21, and the initial signal line 31 is configured to supply an initial voltage signal to the first transistor T1 and the seventh transistor T7.

[0117] In an exemplary embodiment, the outline of the second plate 32 of the storage capacitor may be rectangular, with chamfered corners of the rectangle, the orthogonal projection of the second plate 32 at the base at least partially overlaps the orthogonal projection of the first plate 24 at the base, and the first plate 24 and the second plate 32 form the storage capacitor of the pixel drive circuit.

[0118] In an exemplary embodiment, the plate connecting wire 33 may be provided on one side of the second plate 32 in the first direction X or on the opposite side of the second plate 32 in the first direction X, with a first end of the plate connecting wire 33 connected to the second plate 32 of the present circuit unit, and a second end of the plate connecting wire 33 extending along the first direction X or the opposite direction to the first direction X to connect to the second plate 32 of an adjacent circuit unit in the circuit row, such that the second plates 32 of adjacent circuit units in the unit row are connected to each other via the plate connecting wire 33. In an exemplary embodiment, the second plate 32 is connected to a subsequently formed first voltage line, and the second plates of multiple circuit units in one unit row are connected to each other by the plate connecting wire 33 to form an integral structure, allowing the integral second plate to be multiplexed as a power signal line, ensuring that the multiple second plates in one unit row have the same potential, which is beneficial to improving panel uniformity, avoiding display defects, and ensuring the display effect of the display substrate.

[0119] In an exemplary embodiment, second plate 32 is provided with an opening 35, which may be located in the center of second plate 32 and may be rectangular in shape, causing second plate 32 to be formed in an annular structure. Opening 35 exposes the third insulating layer covering first plate 24, and the orthogonal projection of first plate 24 at its base includes the orthogonal projection of opening 35 at its base. In an exemplary embodiment, opening 35 is configured to accommodate a subsequently formed first via, which is located within opening 35 to expose first plate 24 and connect the second pole of a subsequently formed first transistor T1 to first plate 24.

[0120] In an exemplary embodiment, the shield electrode 34 may be located between the first scanning signal line 21 (excluding the main body portion of the gate block 21-1) and the second scanning signal line 22 of the circuit unit, the shape of the shield electrode 34 may be "L"-shaped, the orthogonal projection at the base of the shield electrode 34 at least partially overlaps with the orthogonal projection at the base of the second region of the first active layer, and the orthogonal projection at the base of the shield electrode 34 at least partially overlaps with the orthogonal projection at the base of the first region of the second active layer, and the shield electrode 34 is configured to shield the key nodes from being affected by data voltage jumps, prevent the data voltage jumps from affecting the potential of the key nodes of the pixel driving circuit, and improve the display effect.

[0121] (4) Forming a fourth insulating layer pattern. In an exemplary embodiment, as shown in Figure 11, forming the fourth insulating layer pattern may include depositing a fourth insulating thin film on the base on which the pattern is formed, and patterning the fourth insulating thin film by a patterning process to form a fourth insulating layer covering the second conductive layer, and each circuit unit is provided with a plurality of vias.

[0122] In an exemplary embodiment, the multiple vias of each circuit unit may include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9.

[0123] In an exemplary embodiment, the orthogonal projection at the base of the first via V1 is within the range of the orthogonal projection at the base of the opening 35 on the second electrode plate 32, the fourth insulating layer and the third insulating layer within the first via V1 are etched away to expose the surface of the first electrode plate 24, and the first via V1 is configured to connect the second pole of the first transistor T1, which is formed subsequently, to the first electrode plate 24 through the via.

[0124] In an exemplary embodiment, the orthogonal projection of the base of the second via V2 is within the range of the orthogonal projection of the base of the second electrode plate 32, the fourth insulating layer in the second via V2 is removed by etching to expose the surface of the second electrode plate 32, and the second via V2 is configured to connect a first power line to be formed later to the second electrode plate 32 through the via. In an exemplary embodiment, there may be multiple second vias V2. The multiple second vias V2 may be sequentially arranged along the second direction Y to improve the connection reliability between the first power line and the second electrode plate 32.

[0125] In an exemplary embodiment, the orthogonal projection at the base of the third via V3 is within the range of the orthogonal projection at the base of the first region of the fifth active layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the third via V3 are removed by etching to expose the surface of the first region of the fifth active layer, and the third via V3 is configured to connect a subsequently formed first power line to the first region of the fifth active layer through the via.

[0126] In an exemplary embodiment, the orthogonal projection at the base of the fourth via V4 is within the range of the orthogonal projection at the base of the second region of the sixth active layer (which is also the second region of the seventh active layer), the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via V4 are removed by etching to expose the surface of the second region of the sixth active layer, and the fourth via V4 is configured to connect the second pole of the sixth transistor T6 (which is also the second pole of the seventh transistor T7) to be formed subsequently to the second region of the sixth active layer (which is also the second region of the seventh active layer).

[0127] In an exemplary embodiment, the orthogonal projection at the base of the fifth via V5 is within the range of the orthogonal projection at the base of the first region of the fourth active layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifth via V5 are removed by etching to expose the surface of the first region of the fourth active layer, and the fifth via V5 is configured to connect a subsequently formed data signal line to the first region of the fourth active layer through the via.

[0128] In an exemplary embodiment, the orthogonal projection at the base of the sixth via V6 is within the range of the orthogonal projection at the base of the second region of the first active layer (which is also the first region of the second active layer), the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via V6 are removed by etching to expose the surface of the second region of the first active layer, and the sixth via V6 is configured to connect the second pole of the first transistor T1 (which is also the first pole of the second transistor T2) to be formed subsequently to the second region of the first active layer (which is also the first region of the second active layer).

[0129] In an exemplary embodiment, the orthogonal projection at the base of the seventh via V7 is within the range of the orthogonal projection at the base of the first region of the first active layer (which is also the first region of the seventh active layer), the fourth insulating layer, the third insulating layer, and the second insulating layer in the seventh via V7 are removed by etching to expose the surface of the first region of the first active layer, and the seventh via V7 is configured to connect the first pole of the first transistor T1 (which is also the first pole of the seventh transistor T7) to be formed subsequently to the first region of the first active layer (which is also the first region of the seventh active layer).

[0130] In an exemplary embodiment, the orthogonal projection at the base of the eighth via V8 is within the range of the orthogonal projection at the base of the shield electrode 34, the fourth insulating layer within the eighth via V8 is etched away to expose the surface of the shield electrode 34, and the eighth via V8 is configured to connect a subsequently formed first power line to the shield electrode 34 through the via.

[0131] In an exemplary embodiment, the orthogonal projection at the base of the ninth via V9 is within the range of the orthogonal projection at the base of the initial signal line 31, the fourth insulating layer in the ninth via V9 is etched away to expose the surface of the initial signal line 31, and the ninth via V9 is configured to connect the first pole of the subsequently formed first transistor T1 (which is also the first pole of the seventh transistor T7) to the initial signal line 31.

[0132] (5) Forming a third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 12A and 12B, forming the third conductive layer may include depositing a third conductive thin film on the patterned base, patterning the third conductive thin film by a patterning process, and forming a third conductive layer disposed on the fourth insulating layer. FIG. 12B is a schematic plan view of the third conductive layer in FIG. 12A. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0133] In the exemplary embodiment, the third conductive layer of each circuit unit includes at least a first connection electrode 41 , a second connection electrode 42 , a third connection electrode 43 , a data signal line 44 , and a first power supply line 45 .

[0134] In an exemplary embodiment, the first connection electrode 41 may have a stripe shape extending along the second direction Y, and is connected to the first plate 24 and the second region of the first active layer (which is also the first region of the second active layer) via the first via V1 and the sixth via V6, respectively, so that the first plate 24, the second pole of the first transistor T1, and the first pole of the second transistor T2 have the same potential. In an exemplary embodiment, the first connection electrode 41 simultaneously serves as the second pole of the first transistor T1 and the first pole of the second transistor T2 (the second node N2 in the pixel driving circuit).

[0135] In an exemplary embodiment, the second connection electrode 42 may have a stripe shape extending along the second direction Y, with a first end of the second connection electrode 42 connected to the first region of the first active layer (which is also the first region of the seventh active layer) through a seventh via V7, and a second end of the second connection electrode 42 connected to the initial signal line 31 through a ninth via V9, which writes an initial voltage signal to the first transistor T1 and the seventh transistor T7. In an exemplary embodiment, the second connection electrode 42 simultaneously serves as the first pole of the first transistor T1 and the first pole of the seventh transistor T7.

[0136] In an exemplary embodiment, the third connection electrode 43 may have a polygonal shape and is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the fourth via V4 so that the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 have the same potential. In an exemplary embodiment, the third connection electrode 43 simultaneously serves as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, and is configured as an anode connection electrode to be connected to an anode that will be formed later.

[0137] In an exemplary embodiment, the shape of the data signal line 44 may be a line whose main body extends along the second direction Y, and the data signal line 44 is connected to the first region of the fourth active layer through the fifth via V5, thereby realizing the data signal line 44 writing a data signal to the fourth transistor T4.

[0138] In an exemplary embodiment, the shape of the first power line 45 may be a broken line whose main body extends along the second direction Y. On the one hand, the first power line 45 is connected to the second electrode plate 32 through the second via V2; on the other hand, the first power line 45 is connected to the first region of the fifth active layer through the third via V3; and on the other hand, the first power line 45 is connected to the shield electrode 34 through the eighth via V8, so that the first power line 45 can write a first power signal to the fifth transistor T5, and the second electrode plate 32 and the shield electrode 34 have the same potential as the first power line 45.

[0139] In the exemplary embodiment, the orthogonal projection of the base of the stripe portion of the shield electrode 34 at least partially overlaps with the orthogonal projection of the base of the first region of the second active layer, and the stripe portion of the shield electrode 34 extending along the second direction Y is located between the first connecting electrode 41 and the data signal line 44. Therefore, the shield electrode 34 is connected to the first power supply line 45 and is a constant voltage signal. Therefore, the shield electrode 34 can effectively shield the second node N2 of the pixel driving circuit from being affected by the data voltage jump of the data signal line 44, thereby avoiding the data voltage jump from being affected by the potential of the key node of the pixel driving circuit and improving the display effect.

[0140] In the exemplary embodiment, the first connecting electrode 41 and the data signal line 44 are respectively located on both sides of the first power supply line 45 in the first direction X. Since the first power supply line 45 is a constant voltage signal, the first power supply line 45 can effectively shield the second node N2 of the pixel driving circuit from being affected by a data voltage jump, thereby preventing the data voltage jump from being affected by the potential of the key node of the pixel driving circuit and improving the display effect.

[0141] In an exemplary embodiment, the first power line 45 of at least one circuit unit may be a polygonal line with non-uniform width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.

[0142] In an exemplary embodiment, the first connection electrode 41 of at least one circuit unit in the first unit row may have a different shape from the first connection electrode 41 of at least one circuit unit in the second unit row.

[0143] In an exemplary embodiment, in multiple first unit columns, the first connection electrode 41 of the circuit unit in at least one first unit column may have a different shape from the first connection electrode 41 of the circuit unit in at least one other first unit column.

[0144] In an exemplary embodiment, the first connection electrode 41 in at least one circuit unit may include an electrode body portion 41-1 and an electrode compensation portion 41-2, and the electrode compensation portion 41-2 is configured to compensate for the parasitic capacitance between the second node N2 and the fourth node N4 in the pixel driving circuit, thereby eliminating the difference between the parasitic capacitance of the pixel driving circuit in the odd unit column and the parasitic capacitance of the pixel driving circuit in the even unit column.

[0145] In an exemplary embodiment, in at least one circuit unit, the electrode body portion 41-1 may include a first end connected to a first plate of the storage capacitor and a second end connected to a first pole of the compensation transistor, and the electrode compensation portion 41-2 may be located on the side of the first end away from the second end, i.e., the electrode compensation portion 41-2 may be located on the second direction Y side of the electrode body portion 41-1.

[0146] In an exemplary embodiment, the electrode body portion 41-1 of at least one circuit unit in the first unit column may have the same shape as the electrode body portion 41-1 of at least one circuit unit in the second unit column, and the electrode compensation portion 41-1 of at least one circuit unit in the first unit column may have a different shape from the electrode compensation portion 41-1 of at least one circuit unit in the second unit column.

[0147] In an exemplary embodiment, the first connection electrodes 41 of at least two circuit units in at least one unit column may have the same shape.

[0148] In an exemplary embodiment, in at least one unit row, the multiple circuit units may include at least a first circuit unit, a second circuit unit and a third circuit unit, wherein the pixel driving circuit of the first circuit unit is connected to the red light-emitting unit that emits red light, the pixel driving circuit of the second circuit unit is connected to the blue light-emitting unit that emits blue light, and the pixel driving circuit of the third circuit unit is connected to the green light-emitting unit that emits green light, and the shapes of the first connection electrode 41 in the first circuit unit, the first connection electrode 41 in the second circuit unit, and the first connection electrode 41 in the third circuit unit may be different.

[0149] In an exemplary embodiment, the shapes of the electrode main body portion 41-1 in the first circuit unit, the electrode main body portion 41-1 in the second circuit unit, and the electrode main body portion 41-1 in the third circuit unit may be the same, and the shapes of the electrode compensation portion 41-2 in the first circuit unit, the electrode compensation portion 41-2 in the second circuit unit, and the electrode compensation portion 41-2 in the third circuit unit may be different.

[0150] In an exemplary embodiment, the first connection electrode 41 of the first circuit unit has a first length L1, the first connection electrode 41 of the second circuit unit has a second length L2, and the first connection electrode 41 of the third circuit unit has a third length L3, and the first length L1, the second length L2, and the third length L3 are different, and the first length L1, the second length L2, and the third length L3 are the sizes of the first connection electrode 41 in the second direction Y.

[0151] In an exemplary embodiment, the second length L2 may be longer than the first length L1, and the second length L2 may be longer than the third length L3.

[0152] In an exemplary embodiment, the third length L3 may be greater than the first length L1.

[0153] In an exemplary embodiment, the first connection electrode 41 of the circuit unit in the first unit row may include an electrode body portion and an electrode compensation portion, the first connection electrode 41 of the circuit unit in the second unit row may include only the electrode body portion, and the first connection electrode 41 with the electrode compensation portion 41-2 may be installed in the circuit unit of the spaced unit row.

[0154] In an exemplary embodiment, the shape of the electrode compensating portion 41-2 may be a stripe extending along the second direction Y, with a first end of the electrode compensating portion 41-2 connected to the electrode body portion 41-1 and a second end of the electrode compensating portion 41-2 extending away from the electrode body portion 41-1 along the second direction Y. Since the first connecting electrode 41 has the potential of the second node N2 in the pixel driving circuit, the electrode compensating portion 41-2 has the potential of the second node N2 in the pixel driving circuit, and the electrode compensating portion 41-2 is configured to increase the overlapping area between the second node N2 in the first pixel column and the anode (fourth node N4) to be formed later, and further increase the parasitic capacitance between the second node N2 and the fourth node N4, so that the parasitic capacitance of the odd-numbered columns and the parasitic capacitance of the even-numbered columns are essentially the same.

[0155] In the exemplary embodiment, the electrode compensation unit 41-2 is intended to adjust the overlapping area between the first connection electrode and the anode, but since the position and shape of the anode located in different pixel columns may differ, the electrode compensation unit 41-2 may be provided in one first unit column and the electrode compensation unit 41-2 may not be provided in another first unit column, and the position and shape of the electrode compensation unit 41-2 may be the same in one first unit column or may be different in another first unit column, but the present disclosure is not limited thereto.

[0156] (6) Forming a flat layer pattern. In an exemplary embodiment, as shown in Figure 13, forming a flat layer pattern may include applying a flat thin film to the base on which the pattern is formed, patterning the flat thin film by a patterning process, forming a flat layer covering the third conductive layer, and providing a plurality of vias in the flat layer.

[0157] In one exemplary embodiment, the vias of each circuit unit include at least an eleventh via V11. The orthogonal projection at the base of the eleventh via V11 is within the range of the orthogonal projection at the base of the third connecting electrode 43, the planar layer within the eleventh via V11 is removed to expose the surface of the third connecting electrode 43, and the eleventh via V11 is configured so that a subsequently formed anode is connected to the third connecting electrode 43 through the via.

[0158] At this stage, a driving circuit layer is fabricated on the base to complete the process. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each of which may include a pixel driving circuit, a first scanning signal line, a second scanning signal line, a light-emitting control signal line, a primary signal line, a data signal line, and a first power supply line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, and a planar layer, which are sequentially stacked on the base.

[0159] In an exemplary embodiment, the base may be a flexible base or a rigid base. The rigid base may be made of one or more of, but not limited to, glass and quartz. The flexible base may be made of, but not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and woven fabric. In an exemplary embodiment, the flexible base may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymeric flexible film. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the water and oxygen resistance of the substrate. The semiconductor layer may be made of amorphous silicon (a-Si).

[0160] In an exemplary embodiment, the first, second, and third conductive layers may be made of one or more metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of these metals, such as aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb). They may have a single-layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first, second, third, and fourth insulating layers may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multilayer, or composite. The first insulating layer may be called a buffer layer, the second and third insulating layers may be called gate insulating (GI) layers, and the fourth insulating layer may be called an interlayer dielectric (ILD) layer. The planarization layer may be made of an organic material, such as a resin. The active layer can be made of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc nitride oxide (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene or polythiophene, i.e., the present disclosure is suitable for transistors fabricated based on oxide technology, silicon technology or organic technology.

[0161] In an exemplary embodiment, after the fabrication of the driving circuit layer is completed, a light emitting structure layer is fabricated on the driving circuit layer, and the fabrication process of the light emitting structure layer may include the following operations:

[0162] (9) Forming an anode conductive layer pattern. In an exemplary embodiment, as shown in Figures 14A and 14B, forming an anode conductive layer pattern may include depositing an anode conductive thin film on the patterned base, patterning the anode conductive thin film by a patterning process, and forming an anode conductive layer pattern disposed on a flat layer. Figure 14B is a schematic plan view of the anode conductive layer in Figure 14A.

[0163] In an exemplary embodiment, the anode conductive layer pattern may include at least a plurality of anodes, which may include a first anode 51 for a red light-emitting unit, a second anode 52 for a blue light-emitting unit, and a third anode 53 for a green light-emitting unit, where the region where the first anode 51 is located may form a red light-emitting unit that emits red light, the region where the second anode 52 is located may form a blue light-emitting unit that emits blue light, and the region where the third anode 53 is located may form a green light-emitting unit that emits green light.

[0164] In an exemplary embodiment, the first anode 51, the second anode 52, and the third anode 53 may be connected to the third connection electrode 43 of the corresponding circuit unit through the eleventh via V11. The third connection electrode 43 of the circuit unit is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through a via, so that the first anode 51, the second anode 52, and the third anode 53 can be connected to the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 through the third connection electrode 43, respectively, so that the pixel driving circuit can drive the light emitting element to emit light.

[0165] In an exemplary embodiment, the plurality of light-emitting units may form a plurality of pixel rows and a plurality of pixel columns, and the pixel rows may include a plurality of light-emitting units arranged sequentially along a first direction X, and the pixel columns may include a plurality of light-emitting units arranged sequentially along a second direction Y.

[0166] In an exemplary embodiment, the positions of the light-emitting units in two pixel rows correspond to the positions of the pixel driving circuits in one unit row, i.e., the area of ​​one unit row corresponds to the area of ​​two pixel rows, and the first anodes 51, second anodes 52 and third anodes 53 in each pixel row can be periodically arranged in the first direction X, and the first anodes 51, second anodes 52 and third anodes 53 of adjacent pixel rows are arranged with their positions staggered.

[0167] In an exemplary embodiment, the light-emitting units in one pixel column correspond to the positions of the pixel driving circuits in one unit column, i.e., the area of ​​one unit column corresponds to the area of ​​one pixel column, and each pixel column includes a plurality of anodes arranged sequentially in the second direction Y, with the anodes in adjacent pixel columns being staggered. The anodes in one pixel column may be a plurality of first anodes 51, the anodes in another pixel column may be a plurality of second anodes 52, and the anodes in one pixel column may be a plurality of third anodes 53.

[0168] In an exemplary embodiment, in the first direction X, the first anode 51 of one pixel row may be located between the second anode 52 and the third anode 53 of the adjacent pixel row, and the three anodes form a triangular pixel unit. In the first direction X, the second anode 52 of one pixel row may be located between the first anode 51 and the third anode 53 of the adjacent pixel row, and the three anodes form a triangular pixel unit. In the first direction X, the third anode 53 of one pixel row may be located between the first anode 51 and the second anode 52 of the adjacent pixel row, and the three anodes form a triangular pixel unit. In this way, the plurality of first anodes 51, the plurality of second anodes 52, and the plurality of third anodes 53 form a Delta pixel arrangement.

[0169] In an exemplary embodiment, in the second direction Y, a first anode 51 in one pixel column may be located between two second anodes 52 in an adjacent pixel column, and a first anode 51 in one pixel column may be located between two third anodes 53 in another adjacent pixel column, and the one first anode 51, the two second anodes 52, and the two third anodes 53 may constitute four pixel units arranged in a triangle. In the second direction Y, a second anode 52 in one pixel column may be located between two first anodes 51 in an adjacent pixel column, and the second anode 52 in one pixel column may be located between two third anodes 53 in another adjacent pixel column, and the two first anodes 51, the one second anode 52, and the two third anodes 53 may constitute four pixel units arranged in a triangle. In the second direction Y, the third anode 53 of one pixel column may be located between two second anodes 52 of an adjacent pixel column, and the third anode 53 of one pixel column may be located between two first anodes 51 of another adjacent pixel column, and the two first anodes 51, two second anodes 52, and one third anode 53 may form four pixel units arranged in a triangle.

[0170] In an exemplary embodiment, the first anode 51, the second anode 52, and the third anode 53 may have different shapes and areas.

[0171] In an exemplary embodiment, the plurality of pixel rows may include a first pixel row and a second pixel row, wherein the shape and area of ​​the first anode 51 in the first pixel row may be different from the shape and area of ​​the first anode 51 in the second pixel row, the shape and area of ​​the second anode 52 in the first pixel row may be different from the shape and area of ​​the second anode 52 in the second pixel row, and the shape and area of ​​the third anode 53 in the first pixel row may be different from the shape and area of ​​the third anode 53 in the second pixel row.

[0172] In an exemplary embodiment, the anode conductive layer may employ a single layer structure such as indium tin oxide ITO or indium zinc oxide IZO, or a multi-layer composite structure such as ITO / Ag / ITO.

[0173] 15A is a schematic plan view of a first anode of the present disclosure, FIG. 15B is a schematic plan view of a second anode of the present disclosure, and FIG. 15C is a schematic plan view of a third anode of the present disclosure. In an exemplary embodiment, the anode of the first pixel column may include an anode compensation portion 50-2.

[0174] As shown in Figure 15A, the first anode 51 may include a first anode main body portion 51-1 and a first anode connection portion 51-2, and the shape of the first anode main body portion 51-1 may be similar to a diamond, and the shape of the first anode connection portion 51-2 may be a stripe extending along the second direction Y, and is configured to be connected to the first anode main body portion 51-1, and to be connected to the corresponding third connection electrode 43 through the 11th via V11.

[0175] In an exemplary embodiment, the first anode connection portion 51-2 of the odd-numbered pixel columns may be arranged on the opposite side of the first anode body portion 51-1 in the second direction Y, and the first anode connection portion 51-2 of the even-numbered pixel columns may be arranged on the second direction Y side of the first anode body portion 51-1.

[0176] In an exemplary embodiment, the first anode 51 may further include a first protrusion 71, and the shape of the first protrusion 71 may be a stripe extending along the second direction Y, with a first end of the first protrusion 71 connected to the first anode main body portion 51-1 and a second end of the first protrusion 71 extending in a direction away from the first anode main body portion 51-1.

[0177] In an exemplary embodiment, the first protrusions 71 may be provided on a side of the first anode body portion 51-1 that is away from the first anode connection portion 51-2. For example, the first protrusions 71 of odd-numbered pixel columns may be provided on the second direction Y side of the first anode body portion 51-1, and the first protrusions 71 of even-numbered pixel columns may be provided on the side of the first anode body portion 51-1 that is opposite to the second direction Y.

[0178] In the exemplary embodiment, the orthogonal projection at the base of the first convex portion 71 at least partially overlaps with the orthogonal projection at the base of the first scanning signal line 21 and the gate block 21-1, and the first convex portion 71 is configured to shield the second transistor T2, thereby improving the electrical performance of the second transistor T2 and improving the display quality and display effect.

[0179] In an exemplary embodiment, the first anodes 51 in the odd-numbered pixel columns may further include second protrusions 72. The second protrusions 72 may have a stripe shape extending along the first direction X, with a first end of the second protrusion 72 connected to the first anode body portion 51-1 and a second end of the second protrusion 72 extending in a direction away from the first anode body portion 51-1.

[0180] In an exemplary embodiment, the second protrusion 72 may be provided on the side of the first anode body portion 51-1 opposite to the first direction X, and the orthogonal projection at the base of the second protrusion 72 at least partially overlaps with the orthogonal projection at the base of the second connection electrode 42 and the first power line 45 in the previous column circuit unit, and the second protrusion 72 is configured to adjust the flatness of the first anode 51 in the odd-numbered pixel columns, thereby making the wiring of the third conductive layer on the anode side as symmetrical as possible, reducing the brightness difference, and improving the display quality and display effect.

[0181] In an exemplary embodiment, the first anodes 51 in the even-numbered pixel columns may not have the second protrusions 72 .

[0182] In an exemplary embodiment, the first anodes 51 in the odd pixel columns may include first anode compensation portions 81, where the orthogonal projection of the anode body portion of the first anodes 51 in the odd pixel columns at the base does not overlap with the orthogonal projection of the first connection electrode at the base, and the first anode compensation portions 81 are configured to make the parasitic capacitance of the odd pixel columns essentially the same as the parasitic capacitance of the even pixel columns.

[0183] In an exemplary embodiment, the shape of the first anode compensation portion 81 may be a broken line extending along the second direction Y, with a first end of the first anode compensation portion 81 connected to the first anode connection portion 51-2 and a second end of the first anode compensation portion 81 extending in a direction away from the first anode main body portion 51-1 (the opposite direction to the second direction Y).

[0184] In an exemplary embodiment, the orthogonal projection at the base of the first anode compensation portion 81 at least partially overlaps with the orthogonal projection at the base of the electrode body portion 41-1 and the electrode compensation portion 41-2 of the first connecting electrode 41, or the orthogonal projection at the base of the first anode compensation portion 81 at least partially overlaps with the orthogonal projection at the base of the electrode compensation portion 41-2 of the first connecting electrode 41. Because the first connecting electrode 41 has the potential of the second node N2 in the pixel driving circuit and the first anode compensation portion 81 has the potential of the fourth node N4 in the pixel driving circuit, the first anode compensation portion 81 and the first connecting electrode 41 can form a parasitic capacitance.

[0185] In an exemplary embodiment, the first anodes in the even pixel columns may not include the first anode compensation portion, and the orthogonal projection of the anode body portion of the first anodes in the even pixel columns at the base at least partially overlaps with the orthogonal projection of the first connection electrode at the base.

[0186] In an exemplary embodiment, the first anode body portion 51-1, the first anode connection portion 51-2, the first convex portion 71, the second convex portion 72, and the first anode compensation portion 81 of the odd-numbered pixel columns may be an integral structure connected to each other, and the first anode body portion 51-1, the first anode connection portion 51-2, and the first convex portion 71 of the even-numbered pixel columns may be an integral structure connected to each other.

[0187] In an exemplary embodiment, the first overlapping area may include an overlapping area between an orthogonal projection of the first anode compensation portion at the base and an orthogonal projection of the first connecting electrode at the base, and the second overlapping area may include an overlapping area between an orthogonal projection of the first anode body portion at the base and an orthogonal projection of the first connecting electrode at the base, wherein the orthogonal projection of the first anode compensation portion at the base of at least one light-emitting unit in an odd-numbered pixel column has a first overlapping area with the orthogonal projection of the first connecting electrode at the base, and the orthogonal projection of the first anode body portion at least one light-emitting unit in an even-numbered pixel column has a second overlapping area with the orthogonal projection of the first connecting electrode at the base, and the ratio of the first overlapping area to the second overlapping area may be approximately 0.8 to 1.2.

[0188] As shown in Figure 15B, the second anode 52 may include a second anode main body portion 52-1 and a second anode connection portion 52-2, where the shape of the second anode main body portion 52-1 may be similar to a hexagon and the shape of the second anode connection portion 52-2 may be a stripe extending along the second direction Y, and is connected to the second anode main body portion 52-1, and the second anode connection portion 52-2 is configured to be connected to the corresponding third connection electrode 43 through the 11th via V11.

[0189] In an exemplary embodiment, the second anode connection portion 52-2 of the odd-numbered pixel columns may be positioned on the opposite side of the second anode body portion 52-1 in the second direction Y, and the second anode connection portion 52-2 of the even-numbered pixel columns may be positioned on the side of the second anode body portion 52-1 in the second direction Y.

[0190] In an exemplary embodiment, the second anode 52 may further include a third protrusion 73, and the shape of the third protrusion 73 may be a stripe extending along the second direction Y, with a first end of the third protrusion 73 connected to the second anode body portion 52-1 and a second end of the third protrusion 73 extending in a direction away from the second anode body portion 52-1.

[0191] In an exemplary embodiment, the third protrusions 73 may be provided on a side of the second anode body portion 52-1 that is away from the second anode connection portion 52-2. For example, the third protrusions 73 of the odd-numbered pixel columns may be provided on the second direction Y side of the second anode body portion 52-1, and the third protrusions 73 of the even-numbered pixel columns may be provided on the side of the second anode body portion 52-1 that is opposite to the second direction Y.

[0192] In the exemplary embodiment, the orthogonal projection at the base of the third convex portion 73 at least partially overlaps with the orthogonal projection at the base of the first scanning signal line 21 and the gate block 21-1, and the third convex portion 73 is configured to shield the second transistor T2, thereby improving the electrical performance of the second transistor T2 and enhancing the display quality and display effect.

[0193] In an exemplary embodiment, the second anodes 52 in the odd-numbered pixel columns may further include fourth protrusions 74. The fourth protrusions 74 may have a stripe shape extending along the first direction X, with a first end of the fourth protrusion 74 connected to the second anode body portion 52-1 and a second end of the fourth protrusion 74 extending in a direction away from the second anode body portion 52-1.

[0194] In an exemplary embodiment, the fourth protrusion 74 may be provided on the side of the second anode body portion 52-1 opposite to the first direction X, and the orthogonal projection of the base of the fourth protrusion 74 at least partially overlaps with the orthogonal projection of the base of the second connection electrode 42 and the first power line 45 in the previous row circuit unit, and the fourth protrusion 74 is configured to adjust the flatness of the second anode 52, thereby making the wiring of the third conductive layer below the anode as symmetrical as possible, reducing brightness differences, and improving display quality and display effect.

[0195] In an exemplary embodiment, the second anodes 52 in the even-numbered pixel columns may not have the fourth protrusions 74 .

[0196] In an exemplary embodiment, the second anodes 52 in the odd pixel columns may include second anode compensation portions 82, wherein the orthogonal projection of the anode body portion of the second anodes 52 in the odd pixel columns at the base does not overlap with the orthogonal projection of the first connection electrode at the base, and the second anode compensation portions 82 are configured to make the parasitic capacitance of the odd pixel columns essentially the same as the parasitic capacitance of the even pixel columns.

[0197] In an exemplary embodiment, the shape of the second anode compensation portion 82 may be a broken line extending along the second direction Y, with a first end of the second anode compensation portion 82 connected to the second anode connection portion 52-2 and a second end of the second anode compensation portion 82 extending in a direction away from the second anode main body portion 52-1 (the opposite direction to the second direction Y).

[0198] In the exemplary embodiment, the orthogonal projection at the base of the second anode compensation portion 82 at least partially overlaps with the orthogonal projection at the base of the electrode body portion 41-1 and the electrode compensation portion 41-2 of the first connecting electrode 41, or the orthogonal projection at the base of the second anode compensation portion 82 at least partially overlaps with the orthogonal projection at the base of the electrode compensation portion 41-2 of the first connecting electrode 41. Because the first connecting electrode 41 has the potential of the second node N2 in the pixel driving circuit and the second anode compensation portion 82 has the potential of the fourth node N4 in the pixel driving circuit, the second anode compensation portion 82 and the first connecting electrode 41 can form a parasitic capacitance.

[0199] In an exemplary embodiment, the second anodes in the even pixel columns may not include second anode compensation portions, and the orthogonal projection of the anode body portion of the second anodes in the even pixel columns at the base at least partially overlaps with the orthogonal projection of the first connection electrode at the base.

[0200] In an exemplary embodiment, the second anode body portion 52-1, the second anode connection portion 52-2, the third convex portion 73, the fourth convex portion 74, and the second anode compensation portion 82 of the odd-numbered pixel columns may be an integral structure connected to each other, and the second anode body portion 52-1, the second anode connection portion 52-2, and the third convex portion 73 of the even-numbered pixel columns may be an integral structure connected to each other.

[0201] In an exemplary embodiment, the first overlapping area may include an overlapping area between an orthogonal projection at the base of the second anode compensation portion and an orthogonal projection at the base of the first connecting electrode, the second overlapping area may include an overlapping area between an orthogonal projection at the base of the second anode body portion and an orthogonal projection at the base of the first connecting electrode, the orthogonal projection at the base of the second anode compensation portion of at least one light-emitting unit in an odd-numbered pixel column has a first overlapping area with the orthogonal projection at the base of the first connecting electrode, and the orthogonal projection at the base of the second anode body portion of at least one light-emitting unit in an even-numbered pixel column has a second overlapping area with the orthogonal projection at the base of the first connecting electrode, and the ratio of the first overlapping area to the second overlapping area may be approximately 0.8 to 1.2.

[0202] As shown in Figure 15C, the third anode 53 may include a third anode main body portion 53-1 and a third anode connection portion 53-2, and the shape of the third anode main body portion 53-1 may be similar to a hexagon, and the shape of the third anode connection portion 53-2 may be a stripe shape extending along the second direction Y, and is configured to be connected to the third anode main body portion 53-1 and connected to the corresponding third connection electrode 43 through the 11th via V11.

[0203] In an exemplary embodiment, the third anode connection portion 53-2 of the odd-numbered pixel columns may be arranged on the opposite side of the third anode body portion 53-1 in the second direction Y, and the third anode connection portion 53-2 of the even-numbered pixel columns may be arranged on the second direction Y side of the third anode body portion 53-1.

[0204] In an exemplary embodiment, the third anode 53 may further include a fifth protrusion 75, and the shape of the fifth protrusion 75 may be a stripe extending along the second direction Y, with a first end of the fifth protrusion 75 connected to the third anode body portion 53-1 and a second end of the fifth protrusion 75 extending in a direction away from the third anode body portion 53-1.

[0205] In an exemplary embodiment, the fifth protrusions 75 may be provided on a side of the third anode body portion 53-1 that is away from the third anode connection portion 53-2. For example, the fifth protrusions 75 of the odd-numbered pixel columns may be provided on the second direction Y side of the third anode body portion 53-1, and the fifth protrusions 75 of the even-numbered pixel columns may be provided on the side of the third anode body portion 53-1 that is opposite to the second direction Y.

[0206] In the exemplary embodiment, the orthogonal projection at the base of the fifth convex portion 75 at least partially overlaps with the orthogonal projection at the base of the first scanning signal line 21 and the gate block 21-1, and the fifth convex portion 75 is configured to shield the second transistor T2, thereby improving the electrical performance of the second transistor T2 and improving the display quality and display effect.

[0207] In an exemplary embodiment, the third anodes 53 in the odd-numbered pixel columns may further include sixth protrusions 76. The sixth protrusions 76 may have a stripe shape extending along the first direction X, with a first end of the sixth protrusions 76 connected to the third anode body portion 53-1 and a second end of the sixth protrusions 76 extending in a direction away from the third anode body portion 53-1.

[0208] In an exemplary embodiment, the sixth protrusion 76 may be provided on the side of the third anode body portion 53-1 opposite to the first direction X, and the orthogonal projection of the base of the sixth protrusion 76 at least partially overlaps with the orthogonal projection of the base of the second connection electrode 42 and the first power line 45 in the previous row circuit unit, and the sixth protrusion 76 is configured to adjust the flatness of the third anode 53, thereby making the wiring of the third conductive layer below the anode as symmetrical as possible, reducing brightness differences, and improving display quality and display effect.

[0209] In an exemplary embodiment, the third anode 53 in the even-numbered pixel columns may not have the sixth protrusion 76 .

[0210] In an exemplary embodiment, the third anodes 53 in the odd pixel columns may include third anode compensation portions 83, wherein the orthogonal projection of the anode body portions of the third anodes 53 in the odd pixel columns at the base does not overlap with the orthogonal projection of the first connection electrode at the base, and the third anode compensation portions 83 are configured to make the parasitic capacitance of the odd pixel columns essentially the same as the parasitic capacitance of the even pixel columns.

[0211] In an exemplary embodiment, the shape of the third anode compensation portion 83 may be a broken line extending along the second direction Y, with a first end of the third anode compensation portion 83 connected to the third anode connection portion 53-2 and a second end of the third anode compensation portion 83 extending in a direction away from the third anode main body portion 53-1 (the opposite direction to the second direction Y).

[0212] In an exemplary embodiment, the orthogonal projection at the base of the third anode compensator 83 at least partially overlaps with the orthogonal projection at the base of the electrode body portion 41-1 and the electrode compensator 41-2 of the first connecting electrode 41, or the orthogonal projection at the base of the third anode compensator 83 at least partially overlaps with the orthogonal projection at the base of the electrode compensator 41-2 of the first connecting electrode 41. Because the first connecting electrode 41 has the potential of the second node N2 in the pixel driving circuit and the third anode compensator 83 has the potential of the fourth node N4 in the pixel driving circuit, the third anode compensator 83 and the first connecting electrode 41 can form a parasitic capacitance.

[0213] In an exemplary embodiment, the third anode in the even pixel column may not include a third anode compensation portion, and the orthogonal projection of the anode body portion in the third anode in the even pixel column at the base at least partially overlaps with the orthogonal projection of the first connection electrode at the base.

[0214] In an exemplary embodiment, the third anode body portion 53-1, the third anode connection portion 53-2, the fifth convex portion 75, the sixth convex portion 76, and the third anode compensation portion 83 of the odd-numbered pixel columns may be an integral structure connected to each other, and the third anode body portion 53-1, the third anode connection portion 53-2, and the fifth convex portion 75 of the even-numbered pixel columns may be an integral structure connected to each other.

[0215] In an exemplary embodiment, the first overlapping area may include an overlapping area between an orthogonal projection at the base of the third anode compensation portion and an orthogonal projection at the base of the first connecting electrode, the second overlapping area may include an overlapping area between an orthogonal projection at the base of the third anode body portion and an orthogonal projection at the base of the first connecting electrode, the orthogonal projection at the base of the third anode compensation portion of at least one light-emitting unit in an odd-numbered pixel column has a first overlapping area with the orthogonal projection at the base of the first connecting electrode, and the orthogonal projection at the base of the third anode body portion of at least one light-emitting unit in an even-numbered pixel column has a second overlapping area with the orthogonal projection at the base of the first connecting electrode, and the ratio of the first overlapping area to the second overlapping area may be approximately 0.8 to 1.2.

[0216] Due to the characteristics of the Delta pixel arrangement, the first anodes of odd-numbered pixel columns are not on the same horizontal line as the first anodes of even-numbered pixel columns, and the pixel drive circuits of odd-numbered unit columns are on the same horizontal line as the pixel drive circuits of even-numbered unit columns, so that the corresponding areas of the first anodes of odd-numbered pixel columns and the pixel drive circuits are different from those of even-numbered pixel columns, so that the orthogonal projections of the bases of the first anodes of odd-numbered pixel columns at least partially overlap with the orthogonal projections of the bases of the first transistor T1 and the seventh transistor T7 in the pixel drive circuits, and the orthogonal projections of the bases of the first anodes of even-numbered pixel columns at least partially overlap with the orthogonal projections of the bases of the second transistor T2, the third transistor T3, and the storage capacitor in the pixel drive circuits. Furthermore, because the second anodes of odd-numbered pixel columns are not on the same horizontal line as the second anodes of even-numbered pixel columns, the corresponding areas of the second anodes of odd-numbered pixel columns and the pixel drive circuits are different from those of even-numbered pixel columns. Since the third anodes of the odd-numbered pixel columns are not on the same horizontal line as the third anodes of the even-numbered pixel columns, the corresponding areas of the third anodes of the odd-numbered pixel columns and the pixel driving circuits are different from the corresponding areas of the third anodes of the even-numbered pixel columns and the pixel driving circuits.

[0217] In an exemplary embodiment, the anode bodies of the even pixel columns are located in the region where the storage capacitor is located, and the orthogonal projections of the anode bodies of the even pixel columns at their bases at least partially overlap with the orthogonal projections of the anode bodies of the odd pixel columns at their bases, while the anode bodies of the odd pixel columns are farther away from the storage capacitor, and the orthogonal projections of the anode bodies of the odd pixel columns at their bases do not overlap with the orthogonal projections of the first connection electrode 41. Therefore, the parasitic capacitance formed by the second node N2 and the fourth node N4 of the even pixel columns is larger than that of the odd pixel columns. Research has revealed that, in the initial stage of pixel emission, the potential of the fourth node N4 increases as the brightness increases, thereby increasing the potential of the second node N2. If the parasitic capacitance of the odd pixel columns is different from the parasitic capacitance of the even pixel columns, the degree of increase in the potential of the second node N2 of the odd pixel columns will be different from the degree of increase in the potential of the second node N2 of the even pixel columns, and the brightness of the light-emitting units of the odd pixel columns will be different from the brightness of the light-emitting units of the even pixel columns, resulting in a vertical streak defect on the display.

[0218] In a display substrate according to an exemplary embodiment of the present disclosure, a first connecting electrode includes an electrode compensator, thereby effectively reducing the difference between the parasitic capacitance of a first pixel column and the parasitic capacitance of a second pixel column. In one aspect, the present disclosure provides a display substrate in which an anode of the first pixel column includes an anode compensator, the anode compensator extending in the direction of the first connecting electrode, and an orthogonal projection of the anode compensator at a base at least partially overlapping with an orthogonal projection of the first connecting electrode at a base, thereby increasing the parasitic capacitance of the first pixel column and reducing the difference between the parasitic capacitance of the first pixel column and the parasitic capacitance of the second pixel column. In another aspect, the present disclosure provides a display substrate in which a first connecting electrode of the first pixel column includes an electrode compensator, the electrode compensator extending in the direction of the anode, and an orthogonal projection of the electrode compensator at a base at least partially overlapping with an orthogonal projection of the anode compensator at a base, thereby further increasing the parasitic capacitance of the first pixel column and further reducing the difference between the parasitic capacitance of the first pixel column and the parasitic capacitance of the second pixel column. The present disclosure provides an electrode compensation unit and an anode compensation unit to effectively reduce the difference between the parasitic capacitance of the first pixel column and the parasitic capacitance of the second pixel column, making the parasitic capacitance of the first pixel column and the parasitic capacitance of the second pixel column essentially the same, effectively eliminating vertical stripe defects on the display, and improving display quality and display effect. The manufacturing process of the present disclosure has good compatibility with existing manufacturing processes, is simple to realize, is easy to implement, has high production efficiency, low manufacturing cost, and a high yield rate.

[0219] In an exemplary embodiment, subsequent manufacturing processes may include forming a pixel defining layer pattern, the pixel defining layer pattern including at least a plurality of pixel openings exposing the anodes; forming an organic light-emitting layer using a vapor deposition or inkjet printing process, the organic light-emitting layer connected to the anodes through the pixel openings; forming a cathode in the organic light-emitting layer, the cathode connected to the organic light-emitting layer; and forming a package structure layer, the package structure layer including stacked first, second, and third package layers, the first and third package layers may be made of inorganic materials, the second package layer may be made of organic material, and the second package layer may be disposed between the first and third package layers to prevent external water vapor from entering the light-emitting structure layer.

[0220] The above-mentioned structure and its manufacturing process of the present disclosure are only exemplary descriptions, and in the exemplary embodiments, the corresponding structure can be modified and patterning processes can be added or removed according to actual needs, and the present disclosure is not limited thereto.

[0221] Fig. 16A is a structural schematic diagram of another display substrate in an embodiment of the present disclosure, Fig. 16B is a plan view of the third conductive layer in Fig. 16A, and Fig. 16C is a plan view of the anode conductive layer in Fig. 16A. In an exemplary embodiment, the structure of the display substrate in this embodiment is basically the same as the structure of the display substrate shown in Fig. 7, except that the first connection electrode part in the driving circuit layer does not have an electrode compensation part, and the anode in the light-emitting structure layer is respectively provided with an anode compensation part and a compensation notch.

[0222] 16A, 16B, and 16C, the structure of the driving circuit layer of this embodiment is basically the same as that of the driving circuit layer of the previous embodiment, except that the first connection electrode 41 includes only an electrode main body portion and does not include an electrode compensation portion. The structure of the light-emitting structure layer of this embodiment is basically the same as that of the light-emitting structure layer of the previous embodiment, except that the anode 50 not only includes an anode main body portion 50-1 and an anode compensation portion 50-2, but also includes a compensation notch 90.

[0223] In an exemplary embodiment, the orthogonal projection of the base of the anode body portion of at least one light-emitting unit in the first pixel column does not overlap with the orthogonal projection of the base of the first connecting electrode 41, and the orthogonal projection of the base of the anode body portion of at least one light-emitting unit in the second pixel column at least partially overlaps with the orthogonal projection of the base of the first connecting electrode 41.

[0224] In an exemplary embodiment, the anode of at least one light-emitting unit in the first pixel column may include an anode body portion 50-1 and an anode compensation portion 50-2, the structures of the anode body portion 50-1 and the anode compensation portion 50-2 being basically the same as those in the above-described embodiment, and the orthogonal projection at the base of the anode compensation portion 50-2 at least partially overlaps with the orthogonal projection at the base of the first connection electrode 41.

[0225] In an exemplary embodiment, the anode of at least one light-emitting unit in the second pixel column may have a compensation notch 90 configured to compensate for the parasitic capacitance between the second node N2 and the fourth node N4 in the pixel driving circuit, thereby eliminating the difference between the parasitic capacitance of the pixel driving circuit in the odd-numbered unit column and the parasitic capacitance of the pixel driving circuit in the even-numbered unit column. In an exemplary embodiment, the compensation notch 90 is configured to reduce the overlapping area between the first connecting electrode (second node N2) and the first connecting electrode (fourth node N4) of the second pixel column, thereby reducing the parasitic capacitance between the second node N2 and the fourth node N4, so that the parasitic capacitance of the odd-numbered column is essentially the same as the parasitic capacitance of the even-numbered column.

[0226] In an exemplary embodiment, the compensation notch 90 in the second pixel column may be provided in the anode body portion 50-1, and the compensation notch 90 may be a groove provided in the anode body portion 50-1, wherein the orthogonal projection at the base of the groove at least partially overlaps with the orthogonal projection at the base of the first connection electrode.

[0227] In another exemplary embodiment, the compensation notch 90 in the second pixel column may be located in the protrusion. The anode of at least one light-emitting unit in the second pixel column may include an anode body portion 50-1, an anode connection portion, and a protrusion, the protrusion may be located on a side of the anode body portion 50-1 away from the anode connection portion, a first end of the protrusion connected to the anode body portion, and a second end of the protrusion extending in a direction away from the anode body portion, the orthogonal projection of the base of the protrusion at least partially overlapping with the orthogonal projection of the base of the first connecting electrode, the compensation notch 90 may be a groove provided in the protrusion, the orthogonal projection of the groove at the base at least partially overlapping with the orthogonal projection of the base of the first connecting electrode.

[0228] In yet another exemplary embodiment, the compensation notch 90 in the second pixel column may be a region where a portion of the anode (e.g., a protrusion or extension) is narrowed relative to its neighbors, where the narrowed region is free of the anode conductive film but is directly adjacent to the anode.

[0229] In yet another exemplary embodiment, the compensation notches 90 in the second pixel column may be recessed areas inside the anode boundary, the recessed areas being free of the anode conductive film but directly adjacent to the anode.

[0230] In the display substrate according to the exemplary embodiment of the present disclosure, on one side, an anode compensation portion is provided on the anode of the first pixel column, thereby increasing the parasitic capacitance of the first pixel column; and on the other side, a compensation notch is provided on the anode of the second pixel column, which corresponds to reducing the area of ​​a portion of the anode, thereby reducing the parasitic capacitance of the second pixel column. As a result, the difference between the parasitic capacitance of the first pixel column and the parasitic capacitance of the second pixel column is reduced, and the parasitic capacitance of the first pixel column and the parasitic capacitance of the second pixel column can be basically made the same, which effectively eliminates vertical stripe defects on the display and improves the display quality and display effect.

[0231] In an exemplary embodiment, the present disclosure also provides another display substrate, the structure of which is basically the same as that of the aforementioned display substrate, except that the first connection electrode is provided with an electrode compensation portion, and the anode is provided with an anode compensation portion and a compensation notch, respectively. The electrode compensation portion, anode compensation portion and compensation notch are basically the same as those in the aforementioned embodiment, and will not be described again here.

[0232] In a display substrate according to an exemplary embodiment of the present disclosure, on one side, an anode compensating portion is provided on the anode of the first pixel column to increase the parasitic capacitance of the first pixel column; on the other side, an electrode compensating portion is provided on the first connecting electrode of the first pixel column to increase the parasitic capacitance of the first pixel column; and on the other side, a compensation notch is provided on the anode of the second pixel column to reduce the parasitic capacitance of the second pixel column. As a result, by minimizing the difference between the parasitic capacitance of the first pixel column and the parasitic capacitance of the second pixel column, the difference between the parasitic capacitance of the first pixel column and the parasitic capacitance of the second pixel column can be minimized, and the parasitic capacitance of the first pixel column and the parasitic capacitance of the second pixel column can be basically made the same. This can eliminate vertical stripe defects across all grayscales, and maximize the display quality and display effect.

[0233] 17A is a structural schematic diagram of another display substrate in an exemplary embodiment of the present disclosure, FIG. 17B is a plan view of the third conductive layer in FIG. 17A, and FIG. 17C is a plan view of the anode conductive layer in FIG. 17A, showing a GGRB pixel layout. As shown in FIG. 17A, FIG. 17B, and FIG. 17C, the driving circuit layer may include at least a first connection electrode 41 and a third connection electrode 43, and the light-emitting structure layer may include a plurality of anodes 50.

[0234] In an exemplary embodiment, the shape of the first connection electrode 41 may be a stripe extending along the second direction Y, a first end of the first connection electrode 41 is connected to a first plate of the storage capacitor through a via, a second end of the first connection electrode 41 is connected to a first region of the second active layer through a via, and the first connection electrode 41 may be a second node N2 in the pixel driving circuit.

[0235] In an exemplary embodiment, the shape of the third connecting electrode 43 may be a polygon, the third connecting electrode 43 is connected to the second pole of the sixth transistor and the second pole of the seventh transistor through a via, and the third connecting electrode 43 may be the fourth node N4 in the pixel driving circuit.

[0236] In an exemplary embodiment, the plurality of anodes 50 may include at least a first anode 51 of a red light-emitting unit, a second anode 52 of a blue light-emitting unit, a fourth anode 54 of a first green light-emitting unit, and a fifth anode 55 of a second green light-emitting unit. A red light-emitting unit R emitting red light may be formed in the region where the first anode 51 is located, a blue light-emitting unit B emitting blue light may be formed in the region where the second anode 52 is located, a first green light-emitting unit G1 emitting green light may be formed in the region where the fourth anode 54 is located, and a second green light-emitting unit G2 emitting green light may be formed in the region where the fifth anode 55 is located. The red light-emitting unit R and the blue light-emitting unit B may be arranged sequentially along the first direction X, and the first green light-emitting unit G1 and the second green light-emitting unit G2 may be arranged sequentially along the second direction Y. In the first direction X, the first green light-emitting unit G1 and the second green light-emitting unit G2 may be arranged between the red light-emitting unit R and the blue light-emitting unit B, forming a GGRB configuration.

[0237] In the exemplary embodiment, the positional relationship between the four anodes and the circuit units may be different, with the body of the fourth anode 54 located on the second direction Y side of the corresponding connected circuit unit, and the body of the fifth anode 55 located on the circuit unit in the next row of the corresponding connected circuit unit. Because the corresponding circuit units of the fourth anode 54 and the fifth anode 55 are not on the same horizontal line, the parasitic capacitance formed between the anodes and the first connecting electrodes is significantly different between the parasitic capacitance of the first green light-emitting unit G1 and the parasitic capacitance of the second green light-emitting unit G2.

[0238] In an exemplary embodiment, the anode may include an anode body portion and an anode connection portion, the anode connection portion is configured to be connected to the third connection electrode 43 in the corresponding circuit unit through a via, and the orthogonal projection of the base of the anode body portion of the fourth anode 54 of the first green light-emitting unit G1 at least partially overlaps with the orthogonal projection of the base of the first connection electrode 41, and the orthogonal projection of the base of the anode body portion of the fifth anode 55 of the second green light-emitting unit G2 does not overlap with the orthogonal projection of the base of the first connection electrode 41.

[0239] In an illustrative embodiment, the fifth anode 55 of the second green light-emitting unit G2 may further include an anode compensator 50-2, a first end of the anode compensator 50-2 connected to the anode connection portion of the fifth anode 55, a second end of the anode compensator 50-2 extending away from the anode body portion, an orthogonal projection of the anode compensator 50-2 at a base at least partially overlapping with an orthogonal projection of the first connecting electrode 41 at a base, an orthogonal projection of the fourth anode 54 at a base and an orthogonal projection of the first connecting electrode 41 at a base have a first overlapping area, and an orthogonal projection of the fifth anode 55 at a base of the anode compensator 50-2 at a base and an orthogonal projection of the first connecting electrode 41 at a base have a second overlapping area, and the ratio of the first overlapping area to the second overlapping area may be approximately 0.8 to 1.2.

[0240] In another exemplary embodiment, the fifth anode of the second green light-emitting unit G2 may further include an anode compensator, and the first connecting electrode in the circuit unit connected to the fifth anode may further include an electrode compensator, wherein the orthogonal projection at the base of the electrode compensator at least partially overlaps with the orthogonal projection at the base of the anode compensator, the orthogonal projection at the base of the fourth anode has a first overlapping area with the orthogonal projection at the base of the first connecting electrode, and the orthogonal projection at the base of the anode compensator of the fifth anode has a second overlapping area with the orthogonal projection at the base of the electrode compensator of the first connecting electrode, and the ratio of the first overlapping area to the second overlapping area may be approximately 0.9 to 1.1.

[0241] In yet another exemplary embodiment, the fifth anode of the second green light-emitting unit G2 may further include an anode compensator, and the fourth anode of the first green light-emitting unit G1 may further include a compensator, wherein an orthogonal projection at a base of the compensator at least partially overlaps with an orthogonal projection at a base of the first connecting electrode, the compensator is configured to reduce an overlapping area between the fourth anode and the first connecting electrode, wherein the orthogonal projection at the base of the fourth anode has a first overlapping area with an orthogonal projection at the base of the first connecting electrode, and the orthogonal projection at the base of the anode compensator of the fifth anode has a second overlapping area with an orthogonal projection at the base of the first connecting electrode, and the ratio of the first overlapping area to the second overlapping area may be approximately 0.9 to 1.1.

[0242] In yet another exemplary embodiment, the fifth anode of the second green light-emitting unit G2 may further include an anode compensator, the fourth anode of the first green light-emitting unit G1 may further include a compensation notch, wherein an orthogonal projection of the compensation notch at a base thereof at least partially overlaps with an orthogonal projection of the first connecting electrode at a base thereof, the circuit unit connected to the fifth anode may further include an electrode compensator, wherein an orthogonal projection of the electrode compensator at the base thereof at least partially overlaps with an orthogonal projection of the anode compensator at the base thereof, the orthogonal projection of the fourth anode at the base thereof has a first overlapping area with an orthogonal projection of the first connecting electrode at the base thereof, and the orthogonal projection of the anode compensator of the fifth anode at the base thereof has a second overlapping area with an orthogonal projection of the electrode compensator of the first connecting electrode at the base thereof, wherein a ratio of the first overlapping area to the second overlapping area may be approximately 0.9 to 1.1.

[0243] The display substrate according to the exemplary embodiment of the present disclosure can effectively reduce the difference in parasitic capacitance between the first green light-emitting unit and the second green light-emitting unit, and can basically make the parasitic capacitance of the first green light-emitting unit and the parasitic capacitance of the second green light-emitting unit the same, thereby not only ensuring the consistency of green brightness but also eliminating vertical stripe defects across all grayscales, thereby improving display quality and display effect.

[0244] 18A is a structural schematic diagram of another display substrate in an exemplary embodiment of the present disclosure, and FIG. 18B is a plan view of the third conductive layer in FIG. 18A , showing the Magic pixel arrangement. As shown in FIGS. 18A and 18B , the driving circuit layer may include at least a first connection electrode 41, and the light-emitting structure layer may include a plurality of anodes 50.

[0245] In an exemplary embodiment, the shape of the first connection electrode 41 may be a stripe extending along the second direction Y, a first end of the first connection electrode 41 may be connected to a first plate of the storage capacitor through a via, a second end of the first connection electrode 41 may be connected to a first region of the second active layer through a via, and the first connection electrode 41 may be a second node N2 in the pixel driving circuit.

[0246] In an exemplary embodiment, the plurality of anodes 50 may include at least a first anode 51 for a red light-emitting unit, a second anode 52 for a blue light-emitting unit, a fourth anode 54 for a first green light-emitting unit, and a fifth anode 55 for a second green light-emitting unit. A red light-emitting unit R that emits red light may be formed in a region where the first anode 51 is located, a blue light-emitting unit B that emits blue light may be formed in a region where the second anode 52 is located, a first green light-emitting unit G1 that emits green light may be formed in a region where the fourth anode 54 is located, and a second green light-emitting unit G2 that emits green light may be formed in a region where the fifth anode 55 is located. The red light-emitting unit R, the first green light-emitting unit G1, the blue light-emitting unit B, and the second green light-emitting unit G2 may be sequentially arranged along a first direction X, with the red light-emitting unit R and the blue light-emitting unit B positioned on a first horizontal line, and the first green light-emitting unit G1 and the second green light-emitting unit G2 positioned on a second horizontal line, which is positioned on a side of the first horizontal line in the second direction Y, and the red light-emitting unit R, the blue light-emitting unit B, the first green light-emitting unit G1, and the second green light-emitting unit G2 form a Magic pixel configuration.

[0247] In an exemplary embodiment, the anode may include an anode body portion and an anode connection portion, and the anode connection portion is configured to be connected to a third connection electrode in a corresponding circuit unit through a via. Thus, the anode may serve as a fourth node N4 in a pixel driving circuit. The anode body portions of the fourth anode 54 and the fifth anode 55 may have a rectangular shape, with the long side of the rectangle deflected at an angle with respect to the second direction Y, and the deflection direction of the fourth anode 54 is opposite to that of the fifth anode 55. Therefore, although the corresponding circuit units of the fourth anode 54 and the fifth anode 55 are on the same horizontal line, the deflection directions of the fourth anode 54 and the fifth anode 55 are different. Therefore, with regard to the parasitic capacitance formed by the anode and the first connection electrode, the parasitic capacitance of the first green light-emitting unit G1 is significantly different from the parasitic capacitance of the second green light-emitting unit G2.

[0248] In an exemplary embodiment, at least one of the fourth anode 54 or the fifth anode 55 may include an anode compensator, and an orthogonal projection of the anode compensator at the base at least partially overlaps with an orthogonal projection of the anode compensator at the base of the first connection electrode 41. In another exemplary embodiment, the corresponding circuit unit may include an electrode compensator, and an orthogonal projection of the electrode compensator at the base at least partially overlaps with an orthogonal projection of the anode compensator at the base. In yet another exemplary embodiment, one anode may include an anode compensator, and the other anode may have a compensation notch. In yet another exemplary embodiment, the corresponding circuit unit may include an electrode compensator, and one anode may include an anode compensator, and the other anode may have a compensation notch.

[0249] The display substrate according to the exemplary embodiment of the present disclosure can effectively reduce the difference in parasitic capacitance between the first green light-emitting unit and the second green light-emitting unit, and can basically make the parasitic capacitance of the first green light-emitting unit and the parasitic capacitance of the second green light-emitting unit the same, thereby not only ensuring the consistency of green brightness but also eliminating vertical stripe defects across all grayscales, thereby improving display quality and display effect.

[0250] The present disclosure further provides a method for manufacturing a display substrate according to the above embodiments. In an exemplary embodiment, the method may include forming a driving circuit layer on a base, the driving circuit layer including a plurality of circuit units, the circuit units including at least a pixel driving circuit, the pixel driving circuit including at least a storage capacitor and a compensation transistor, a first electrode of the compensation transistor connected to a first electrode of the storage capacitor through a first connecting electrode, the first connecting electrodes of at least two circuit units having different shapes; and forming a light-emitting structure layer on the driving circuit layer, the light-emitting structure layer including a plurality of light-emitting units, the light-emitting units including at least an anode, the anode connected to the pixel driving circuit, an orthogonal projection of the anode of at least one light-emitting unit on the base at least partially overlapping an orthogonal projection of the first connecting electrode of at least one circuit unit on the base.

[0251] The present disclosure further provides a display device including the display substrate, which may be any product or component with a display function, such as a mobile phone, a tablet, a television, a display, a laptop, a digital photo frame, or a navigation system, and the embodiments of the present disclosure are not limited thereto.

[0252] Although the embodiments disclosed in the present disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the present disclosure and are not used to limit the present disclosure. Those skilled in the art can make any modifications and changes in the embodiments and details without departing from the spirit and scope of the present disclosure. However, the scope of patent protection of the present disclosure must comply with the scope defined by the appended claims.

Claims

1. A display substrate, a driving circuit layer disposed on a base; and a light-emitting structure layer disposed on a side of the driving circuit layer remote from the base, the driving circuit layer including a plurality of circuit units, the circuit units including at least a pixel driving circuit, the pixel driving circuit including at least a storage capacitor and a compensation transistor, a first electrode of the compensation transistor connected to a first electrode plate of the storage capacitor via a first connecting electrode; the light-emitting structure layer including a plurality of light-emitting units, the light-emitting units including at least an anode, the anode connected to the pixel driving circuit, an orthogonal projection of the anode of at least one light-emitting unit on the base at least partially overlaps with an orthogonal projection of the first connecting electrode of at least one circuit unit on the base, and shapes of the first connecting electrodes of at least two circuit units are different.

2. 2. The display substrate of claim 1, wherein the first connection electrode includes an electrode main body portion and an electrode compensation portion, the electrode main body portion includes a first end connected to a first electrode plate of the storage capacitor and a second end connected to a first electrode of the compensation transistor, the electrode compensation portion is provided on the side of the first end away from the second end, the electrode main body portions of at least two circuit units have the same shape, and the electrode compensation portions of at least two circuit units have different shapes.

3. 3. The display substrate of claim 2, wherein the plurality of circuit units form a plurality of unit rows and a plurality of unit columns, the unit rows include a plurality of circuit units arranged sequentially along a first direction, the unit columns include a plurality of circuit units arranged sequentially along a second direction, the first direction intersects with the second direction, and in at least one unit column, the shapes of the first connection electrodes of at least two circuit units are the same.

4. 4. The display substrate of claim 3, wherein in at least one unit row, the plurality of circuit units include at least a first circuit unit, a second circuit unit, and a third circuit unit, wherein the pixel driving circuit of the first circuit unit is connected to a red light-emitting unit that emits red light, the pixel driving circuit of the second circuit unit is connected to a blue light-emitting unit that emits blue light, and the pixel driving circuit of the third circuit unit is connected to a green light-emitting unit that emits green light, and the shapes of the first connection electrodes of the first circuit unit, the second circuit unit, and the third circuit unit are different.

5. The display substrate according to claim 4 , wherein the electrode main body portions in the first circuit unit, the second circuit unit, and the third circuit unit have the same shape, and the electrode compensation portions in the first circuit unit, the second circuit unit, and the third circuit unit have different shapes.

6. 5. The display substrate of claim 4, wherein the first connection electrode of the first circuit unit has a first length, the first connection electrode of the second circuit unit has a second length, and the first connection electrode of the third circuit unit has a third length, the first length, the second length, and the third length are different, and the first length, the second length, and the third length are the sizes of the first connection electrodes in the second direction.

7. The display substrate of claim 6 , wherein the second length is longer than the first length, and the second length is longer than the third length.

8. The display substrate of claim 6 , wherein the third length is longer than the first length.

9. 9. The display substrate of claim 1, wherein the anode of at least one light-emitting unit includes an anode body portion, an anode connection portion, and an anode compensation portion, the anode connection portion is configured to be connected to the pixel driving circuit, and the anode compensation portion is provided on a side of the anode connection portion away from the anode body portion.

10. The display substrate of claim 9 , wherein, in at least one circuit unit, an orthogonal projection of the anode compensation portion on the base at least partially overlaps an orthogonal projection of the electrode compensation portion of the first connection electrode on the base.

11. The display substrate of claim 9 , wherein in at least one circuit unit, an orthogonal projection of the anode compensation portion on the base at least partially overlaps an orthogonal projection of the electrode body portion of the first connection electrode on the base.

12. The display substrate according to claim 9 , wherein in at least one circuit unit, an orthogonal projection of the anode body portion on the base at least partially overlaps an orthogonal projection of the first connection electrode on the base.

13. The display substrate according to claim 9 , wherein in at least one circuit unit, an orthogonal projection of the anode body on the base does not overlap an orthogonal projection of the first connection electrode on the base.

14. 10. The display substrate of claim 9, wherein in at least one circuit unit, the anode is provided with a compensation notch, the compensation notch being configured to reduce an overlapping area between the anode and the first connection electrode.

15. 15. The display substrate of claim 14, wherein the anode further includes a protrusion, the protrusion being provided on a side of the anode body portion away from the anode connection portion, the orthogonal projection of the protrusion on the base at least partially overlapping with the orthogonal projection of the first connection electrode on the base, and the compensation notch being provided on the protrusion.

16. 16. The display substrate of claim 15, wherein the compensation notch comprises a groove provided on an edge of the protrusion, and an orthogonal projection of the groove on the base at least partially overlaps an orthogonal projection of the first connection electrode on the base.

17. The display substrate of any one of claims 1 to 8, wherein in a plane perpendicular to the display substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on the base, the semiconductor layer including at least an active layer of the compensation transistor, the first conductive layer including at least a first electrode plate of the storage capacitor and a gate electrode of the compensation transistor, the second conductive layer including at least a second electrode plate of the storage capacitor, and the third conductive layer including at least the first connection electrode.

18. A display device comprising the display substrate according to any one of claims 1 to 17.

19. A method for manufacturing a display substrate, forming a driving circuit layer on the base, the driving circuit layer including a plurality of circuit units, the circuit units including at least a pixel driving circuit, the pixel driving circuit including at least a storage capacitor and a compensation transistor, a first pole of the compensation transistor being connected to a first electrode plate of the storage capacitor through a first connection electrode, and shapes of the first connection electrodes of at least two circuit units being different; forming a light-emitting structure layer on the driving circuit layer, the light-emitting structure layer including a plurality of light-emitting units, the light-emitting units including at least an anode, the anode connected to the pixel driving circuit, and a positive projection of the anode of at least one light-emitting unit on the base at least partially overlapping with a positive projection of the first connection electrode of at least one circuit unit on the base.

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