Light-emitting pixel structure system for improving light-emitting efficiency and manufacturing method thereof

Abstract

The present invention discloses a pixel structure for improving light-emitting efficiency. The pixel structure includes, from top to bottom, a pixel lens, a negative electrode pad layer, a conductive semiconductor layer, a quantum well, an isolation layer, a positive electrode layer, a dielectric layer, and an integrated circuit (IC) chip layer. The quantum well is disposed within the conductive semiconductor layer. A three-sided covering reflective layer is disposed between the bottom surface of the conductive semiconductor layer and the top surface of the positive electrode layer. The conductive semiconductor layer includes an inverted trapezoidal semiconductor portion and a continuous planarization layer. The slopes on both sides of the inverted trapezoidal semiconductor portion concentrate and reflect light emitted from the quantum well toward the pixel lens. The negative electrode pad layer is disposed on the continuous planarization layer.

Description

[Technical Field]

[0001] The present invention generally relates to the technical field of displays, and more particularly to a light-emitting pixel structure and its manufacturing process that reduces the light blocking effect and improves light reflection efficiency. [Background technology]

[0002] Display technology is becoming increasingly important in modern commercial electronic devices. These display panels are widely used in fixed large screens such as liquid crystal display televisions (LCD TVs) and organic light emitting diode televisions (OLED TVs), as well as portable electronic devices such as laptop personal computers, smartphones, tablet computers, and wearable electronic devices.

[0003] Light-emitting diode (LED) chips generally include organic light-emitting diode (OLED) chips, mini light-emitting diode (submillimeter light-emitting diode) chips, and micro LED (micro light-emitting diode) chips. LEDs are widely used in the lighting field. As LED display screens gradually penetrate the high-end market, the requirements for luminous efficiency of LED display screen devices are becoming increasingly higher.

[0004] Pixels consist of small squares in an image that have a definite location and are assigned a color value; the color and location of the square determine the pixel's appearance. Pixels can be thought of as indivisible units or elements of the overall image. Indivisible means that a pixel cannot be further divided into smaller units or elements that exist in a single color unit. Each dot matrix image contains a certain number of pixels, and these pixels determine the size of the image displayed on a screen.

[0005] Some embodiments disclose a light-emitting diode unit including a plurality of pixels for a display, and a display device including the light-emitting diode unit. The embodiments disclose the following: (1) in the plurality of pixels, each pixel includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit, each including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; (2) the third light-emitting unit is electrically connected to the first light-emitting unit, thereby independently driving the first light-emitting unit; (3) the second wavelength converter converts the wavelength of light emitted from the second light-emitting unit; (4) the third wavelength converter converts the wavelength of light emitted from the third light-emitting unit, the third wavelength converter converting the wavelength of light to a longer wavelength than that of the second wavelength converter; the second light-emitting unit has a light-emitting area larger than that of the first light-emitting unit; and the third light-emitting unit has a light-emitting area larger than that of the second light-emitting unit. Because a light-emitting diode unit including a plurality of pixels is used, the light-emitting units can be easily attached to a substrate.

[0006] However, the pixel structures in these embodiments have the following technical problems: Because the light emitted from the light-emitting unit is emitted around the light-emitting unit, the light emitted from the display device or near-sighted augmented reality (AR) device may be limited to only the light emitted from the light-emitting unit toward the lens. Furthermore, because of the light-blocking situation between the light-emitting unit and the lens, the brightness of the light emitted from the light-emitting unit and received by the lens is only 50% or less of the light emitted from the light-emitting unit of the pixel. Therefore, the operating efficiency of the light-emitting unit is low and needs to be improved.

[0007] It would therefore be desirable to provide a light emitting structure for a display panel that overcomes the above drawbacks and others. Summary of the Invention

[0008] There is a need for improved display device designs that help address the above-mentioned problems and shortcomings of conventional display systems. In particular, there is a need for display panels that provide improved light efficiency and better images.

[0009] The present invention relates to the technical field of displays, and discloses a pixel structure and its manufacturing process that can reduce the light blocking effect and improve the light reflection efficiency, thereby solving the technical problem of the low light conversion efficiency of the current pixel light-emitting unit.

[0010] The present invention includes, but is not limited to, the following illustrative examples.

[0011] Some example embodiments of the present invention include a micro-luminescence pixel structure, which includes: a conductive semiconductor layer having an inverted trapezoid shape and including a continuous planarization layer located on the top of the inverted trapezoid; a quantum well layer that emits light and is located within the conductive semiconductor layer; a three-sided coated reflective layer located below the conductive semiconductor layer and made of Ag; a negative electrode pad layer electrically connected to the conductive semiconductor layer; a positive electrode layer electrically connected to the conductive semiconductor layer; and an integrated circuit (IC) chip layer electrically connected to the positive electrode layer.

[0012] Some exemplary embodiments of the present invention include a micro-luminescence pixel structure, which includes: a conductive semiconductor layer having an inverted trapezoid shape; a quantum well layer that emits light and is located in the conductive semiconductor layer; a three-sided coated reflective layer that is located below the conductive semiconductor layer and is made of Ag; an isolation layer that is located between the conductive semiconductor layer and the three-sided coated reflective layer and is made of Al2O3 or Si3N4; a negative electrode pad layer that is electrically connected to the conductive semiconductor layer; a positive electrode layer that is electrically connected to the conductive semiconductor layer; and an integrated circuit (IC) chip layer that is electrically connected to the positive electrode layer.

[0013] In some exemplary embodiments or any combination of exemplary embodiments of the micro-luminescent pixel structure, the three-sided coated reflective layer includes an intermediate conductive portion in contact with the positive electrode layer and the conductive semiconductor layer, two side reflective portions in contact with the isolation layer, and two edge reflective portions in contact with the isolation layer, and the three-sided coated reflective layer surrounds the quantum well layer to form an inverted trapezoid.

[0014] In some exemplary embodiments of the micro-emissive pixel structure or any combination of exemplary embodiments, the quantum well layer is confined within an inverted trapezoid of the conductive semiconductor layer such that light from the quantum well is concentrated toward the top of the emissive pixel structure.

[0015] In some exemplary embodiments or any combination of exemplary embodiments of the micro-emissive pixel structure, the isolation layer forms an inverted trapezoid around the quantum well layer.

[0016] In some exemplary embodiments or any combination of exemplary embodiments of the micro-emissive pixel structure, the conductive semiconductor layer includes a continuous planarization layer located on top of the inverted trapezoid.

[0017] In some exemplary embodiments of the micro-emitting pixel structure or any combination of exemplary embodiments, the continuous planarization layer covers the entire surface of the micro-emitting pixel structure and extends to adjacent micro-emitting pixel structures.

[0018] In some exemplary embodiments of the micro-luminescent pixel structure or any combination of the exemplary embodiments, the micro-luminescent pixel structure further includes an isolation layer located between the conductive semiconductor layer and the three-sided coated reflective layer, the isolation layer being made of Al2O3 or Si3N4.

[0019] In some exemplary embodiments or any combination of exemplary embodiments of the micro-light-emitting pixel structure, the negative electrode pad layer is formed above the continuous planarization layer, and the area above the quantum well is hollowed out so that the light emitted from the quantum well is not blocked by the negative electrode pad layer.

[0020] In some exemplary embodiments of the micro-luminescent pixel structure or any combination of the exemplary embodiments, the micro-luminescent pixel structure further includes a dielectric layer located between the three-sided coated reflective layer and the IC chip layer, where the dielectric layer covers the surface of the three-sided coated reflective layer and includes a top dielectric layer made of Si3N4 and a bottom dielectric layer made of SiO2.

[0021] In some exemplary embodiments or any combination of exemplary embodiments of the micro-luminescent pixel structure, the positive electrode layer includes a top epitaxial positive electrode located in the dielectric layer and a bottom chip positive electrode located in the IC chip layer.

[0022] In some exemplary embodiments or any combination of exemplary embodiments of the micro-luminescent pixel structure, the IC chip layer includes a top chip dielectric layer and a bottom chip electrical plate.

[0023] In some exemplary embodiments or any combination of exemplary embodiments of the micro-luminescent pixel structure, the IC chip layer including the bottom chip positive electrode contacts the dielectric layer including the top epitaxial positive electrode.

[0024] In some exemplary embodiments of the micro-luminescent pixel structure or any combination of exemplary embodiments, the micro-luminescent pixel structure further includes a pixel lens located above the conductive semiconductor layer.

[0025] Some example embodiments of the present invention include a method for manufacturing a micro-light-emitting pixel structure, the method including: providing an epitaxial wafer including a conductive semiconductor layer and a quantum well layer that emits light and is located in the conductive semiconductor layer; etching the conductive semiconductor layer having the quantum well layer into an inverted trapezoid; forming an isolation layer made of Al2O3 or Si3N4 on a bottom surface of the conductive semiconductor layer; forming a three-sided coated reflective layer made of Ag on the bottom surface of the isolation layer; forming a first positive electrode layer on a bottom surface of an intermediate conductive portion of the three-sided coated reflective layer; bonding an integrated circuit (IC) chip layer to the first positive electrode layer; and forming a negative electrode pad layer on an upper surface of the conductive semiconductor layer.

[0026] In some exemplary embodiments or any combination of exemplary embodiments of the method for manufacturing a micro-light-emitting pixel structure, the method further includes, after forming the three-sided coated reflective layer and before forming the first positive electrode layer, forming a dielectric layer between the three-sided coated reflective layer and the IC chip layer, where the dielectric layer covers the surface of the three-sided coated reflective layer and includes a top dielectric layer made of Si3N4 and a bottom dielectric layer made of SiO2.

[0027] In some exemplary embodiments or any combination of exemplary embodiments of the method for manufacturing a micro-emissive pixel structure, etching the conductive semiconductor layer having the quantum well layer further includes leaving a continuous planarization layer on top of the inverted trapezoid of the conductive semiconductor layer.

[0028] In some exemplary embodiments or any combination of exemplary embodiments of the method for manufacturing a micro-light-emitting pixel structure, the epitaxial wafer includes a sapphire substrate layer, and after bonding the IC chip layer and before forming the negative electrode pad layer, the method further includes removing the sapphire substrate layer.

[0029] In some exemplary embodiments or any combination of exemplary embodiments of the method for manufacturing a micro-luminescent pixel structure, forming the isolation layer includes etching the isolation layer to form an opening for depositing an intermediate conductive portion of the three-sided coated reflective layer on the bottom surface of the conductive semiconductor layer.

[0030] In some example embodiments or any combination of example embodiments of the method for manufacturing a micro-emission pixel structure, forming the dielectric layer includes etching the dielectric layer to form an opening for depositing the first positive electrode layer.

[0031] In some exemplary embodiments or any combination of exemplary embodiments of the method for manufacturing a micro-luminescent pixel structure, the bonding includes aligning and bonding an IC chip layer having an embedded second positive electrode layer to a bottom surface of the dielectric layer having an embedded first positive electrode layer, where the first positive electrode layer is a top epitaxial positive electrode and the second positive electrode layer is a bottom chip positive electrode.

[0032] In some exemplary embodiments or any combination of the exemplary embodiments of the method for manufacturing a micro-light-emitting pixel structure, forming the negative electrode pad layer includes forming a hollow shape in the negative electrode pad layer in a region above the quantum well by a lift-off process, so that the light emitted from the quantum well is not blocked by the negative electrode pad layer.

[0033] In some exemplary embodiments or any combination of exemplary embodiments of the method for manufacturing a micro-light-emitting pixel structure, after forming the negative electrode pad layer, the method further includes: forming a pixel lens above the conductive semiconductor layer and aligning it with the hollow shape of the negative electrode pad layer.

[0034] In order to solve the problem of low light conversion efficiency of the conventional light emitting unit, the present invention achieves the purpose of improving the light conversion efficiency through the internal design of the pixel structure.

[0035] In some exemplary embodiments, the present invention provides the following technical aspects:

[0036] In some embodiments, a pixel structure that reduces the light blocking effect and improves light reflection efficiency includes, from top to bottom or from outside to inside, a pixel lens, a negative electrode pad layer, a conductive semiconductor layer, a quantum well, an isolation layer, a positive electrode layer, a dielectric layer, and an integrated circuit (IC) chip layer, and the quantum well is disposed in the conductive semiconductor layer.

[0037] In some embodiments, the three-sided coated reflective layer is disposed between the bottom surface of the conductive semiconductor layer and the top of the positive electrode layer, and covers and conforms to the shape of the bottom, side and top surfaces of the conductive semiconductor layer, respectively.

[0038] In some embodiments, the conductive semiconductor layer includes an inverted trapezoidal semiconductor portion and a continuous planarization layer. The quantum well is located inside the inverted trapezoidal semiconductor portion. The inverted trapezoidal semiconductor portion is divided horizontally into a bottom P-GaN portion and a top N-GaN portion of the quantum well. The slopes on both sides of the inverted trapezoidal semiconductor portion (the sloping sides of the inverted trapezoid) concentrate light emitted from the quantum well and reflect it toward the pixel lenses. The continuous planarization layer between the multiple pixels is configured to be entirely continuous. A negative electrode pad layer is provided on the top surface of the continuous planarization layer, so that the negative electrode pad layer and the conductive semiconductor layer are not on the same planar layer. The positive electrode layer is disposed on the dielectric layer, and the dielectric layer and the IC chip layer are connected together.

[0039] According to the structure disclosed herein, light emitted from the quantum well is reflected by the three-sided coated reflective layer, and light from the side of the quantum well away from the surface of the pixel lens is reflected toward the pixel lens, thereby significantly improving the utilization efficiency of the light emitted from the quantum well. Furthermore, by reflecting the light emitted from the quantum well to both sides of the pixel lens using the slopes of the inverted trapezoidal semiconductor portion, the light emitted from the quantum well to both sides of the pixel lens is concentrated and collected in the direction toward the pixel lens, thereby further improving the utilization efficiency of the light emitted from the quantum well. Furthermore, by using the structural design of the continuous planarization layer, the negative electrode pad layer may be positioned at any position on the continuous planarization layer. In some embodiments, the negative electrode pad layer may be positioned at an unobstructed position of the quantum well so that the light is emitted toward the pixel lens, thereby not obstructing the light and further improving the light collection efficiency of the pixel lens.

[0040] In some embodiments, the three-sided coated reflective layer includes a conductive portion, a side reflector, and an edge reflector. The conductive portion has a top surface attached to the conductive semiconductor layer and a bottom surface attached to the positive electrode layer. Both the top surface of the side reflector and the top surface of the edge reflector are attached to the isolation layer, and the bottom surface of the side reflector is attached to the dielectric layer.

[0041] In some embodiments, the conductive portion has a primary reflection effect, the side reflection portion has a residual light reflection effect, and the isolation layer is a transparent layer.

[0042] In some embodiments, the three-sided coated reflective layer is or includes an Ag layer formed by electron beam evaporation or thermal evaporation.

[0043] In some embodiments, a high reflection effect is achieved by using an Ag layer, and the reflectivity of Ag is the highest among reflective materials.

[0044] In some embodiments, the isolation layer is configured as Al2O3 or Si3N4.

[0045] In some embodiments, the negative electrode pad layer is hollow, a pixel lens is provided in the hollow portion of the negative electrode pad layer, and the main portion of the negative electrode pad layer is positioned on top of the continuous planarization layer, rather than in a position that blocks light toward the pixel lens.

[0046] According to the structure disclosed in this specification, the light traveling from the quantum well toward the pixel lens is not blocked by the placement of the negative electrode pad layer.

[0047] In some embodiments, the dielectric layer includes a top SiN layer structure and a bottom SiO layer structure, the SiN layer structure covering and attached to the surface of the three-sided coated reflective layer, the positive electrode includes an epitaxial positive electrode and a chip positive electrode, the epitaxial positive electrode is disposed continuously on the SiN layer structure and the SiO layer structure in a through configuration, and the chip positive electrode is disposed on the IC chip layer.

[0048] In some embodiments, the IC chip layer includes a chip dielectric layer located at the top and a chip electrical plate located at the bottom, and the chip positive electrode is disposed in the chip dielectric layer in a through configuration, the top is connected to the epitaxial positive electrode by aligned bonding, and the bottom is electrically connected to the chip electrical plate.

[0049] Due to the fact that a three-sided Ag coated reflective layer is disposed on the pixel structure and a conventional pixel process is used to fabricate the pixel structure, loss of the Ag layer may occur, which further causes an internal short circuit of the pixel structure. In some embodiments, a non-short circuit attachment of the IC chip layer is achieved by using a chip dielectric layer-to-dielectric layer alignment bonding connection structure and process.

[0050] In some embodiments, the positive electrode layer is configured as a Cu pillar.

[0051] In some exemplary embodiments, the present specification discloses the following technical aspects:

[0052] In some embodiments, a manufacturing process of a pixel structure is provided that reduces the light blocking effect and improves the light reflection efficiency based on the internal structure of the pixel. The manufacturing process of the pixel structure includes the following process steps 1 to 10.

[0053] Step 1 involves selecting an epitaxial wafer. In some embodiments, the epitaxial wafer includes a sapphire layer on top and a conductive semiconductor layer on the bottom, with a quantum well in between the conductive semiconductor layers.

[0054] In step 2, the semiconductor is etched.

[0055] In sub-step 2-1 of step 2, a conductive semiconductor layer is etched inside the epitaxial wafer to form an inverted trapezoidal semiconductor portion having an inverted trapezoidal shape, and the quantum well is located inside the inverted trapezoidal semiconductor portion.

[0056] In step 3, an isolation layer is deposited, patterned, and etched.

[0057] In sub-step 3-1 of step 3, an isolation layer is formed on the bottom surface of the conductive semiconductor layer.

[0058] In sub-step 3-2 of step 3, after depositing the isolation layer, the isolation layer is etched to form an opening at the bottom of the inverted trapezoid semiconductor portion for depositing the conductive portion of the three-sided coated reflective layer.

[0059] In step 4, a three-sided coated reflective layer is deposited, patterned, and etched.

[0060] In sub-step 4-1 of step 4, a three-sided coated reflective layer is formed by deposition on the bottom surface of the isolation layer.

[0061] In sub-step 4-2 of step 4, trimming is performed to form the shape of the three-sided coated reflective layer.

[0062] In step 5, a dielectric layer is deposited, patterned, and etched.

[0063] In sub-step 5-1 of step 5, a dielectric layer is formed by deposition on the lower surface of the three-sided coated reflective layer.

[0064] Sub-step 5-2 of step 5 involves etching and trimming to define the shape of the dielectric layer.

[0065] In step 6, the positive electrode is deposited and polished.

[0066] In step 6, substep 6-1, a positive electrode layer is formed by deposition. In sub-step 6-2 of step 6, a polishing operation is performed on the positive electrode layer.

[0067] Step 7 is alignment and bonding.

[0068] Sub-step 7-1 of step 7 involves connecting the IC chip layer to the bottom surface of the dielectric layer by an aligned bonding process.

[0069] In step 8, the sapphire layer is removed.

[0070] In step 9, a negative electrode pad layer is deposited and patterned.

[0071] In sub-step 9-1 of step 9, a negative electrode pad layer is formed by deposition.

[0072] In sub-step 9-2 of step 9, the negative electrode pad layer is patterned to form a hollow shape.

[0073] In step 10, the lenses are deposited and patterned.

[0074] In sub-step 10-1 of step 10, deposition is performed to form a layer structure of a pixel lens.

[0075] In sub-step 10-2 of step 10, the layer structure of the pixel lens is patterned to form the lens shape.

[0076] By means of this technology, novel pixel structures can be fabricated using this technology.

[0077] In some embodiments, the epitaxial wafer in step 1 includes a sapphire layer, a conductive semiconductor layer, and quantum wells as starting materials to be processed by the pixel structure process, and the conductive semiconductor layer includes a P-type material, such as a P-GaN material layer, at the bottom of the quantum wells, and an N-type material, such as an N-GaN material layer, at the top of the quantum wells.

[0078] In some embodiments, the process of etching the conductive semiconductor layer on the epitaxial wafer in step 2 is an inductively coupled plasma (ICP) semiconductor etching process, which etches to form an inverted trapezoid or bowl-shaped pattern.

[0079] In some embodiments, the process of forming the isolation layer in step 3 is an atomic layer deposition (ALD) process, and the process of etching the deposited isolation layer is an ICP etching process.

[0080] In some embodiments, the process of forming the three-sided coated reflective layer in step 4 is a physical vapor deposition (PVD) process such as electron beam evaporation or thermal evaporation, and the process of etching the three-sided coated reflective layer is performed by a peeling process, followed by etching and trimming to form a shape.

[0081] In some embodiments, the process of forming the dielectric layer in step 5 is carried out by a chemical vapor deposition (CVD) process method, followed by etching and trimming to form the shape of the dielectric layer by an ICP semiconductor etching process.

[0082] In some embodiments, step 6 involves forming a positive electrode layer by performing an electroplating deposition process, and polishing the positive electrode layer by a chemical mechanical polishing (CMP) process.

[0083] In some embodiments, step 8 involves delaminating the sapphire layer on top of the epitaxial wafer using a laser delamination process.

[0084] In some embodiments, in step 9, the negative electrode pad layer is formed by PVD deposition, which is a physical vapor deposition process such as electron beam evaporation or thermal evaporation, and a peeling process is performed to peel off the negative electrode pad layer to form a hollow shape.

[0085] In some embodiments, the process in step 10 is a CVD deposition process to form a layer structure of a pixel lens, and then an ICP semiconductor etching process is performed on the layer structure of the pixel lens to form a pixel lens having a lens shape.

[0086] In summary, the systems and methods disclosed herein have the following advantages and improvements:

[0087] (1) The light emitted from the quantum well is reflected by the three-sided coated reflective layer, and the light from the side of the quantum well away from the pixel lens is reflected toward the pixel lens, thereby significantly improving the utilization efficiency of the light emitted from the quantum well.

[0088] (2) The slopes of the inverted trapezoidal semiconductor section reflect the light emitted from the quantum well to both sides of the pixel lens, so that the light emitted from the quantum well to both sides of the pixel lens is concentrated and collected in the direction toward the pixel lens, further improving the utilization efficiency of the light emitted from the quantum well.

[0089] (3) By using the structural design of the continuous planarization layer, the negative electrode pad layer can be positioned at any position on the continuous planarization layer. Therefore, the negative electrode pad layer is positioned at an unobstructed position of the quantum well so that light is emitted to the pixel lens. This allows the negative electrode pad layer to not block light, further improving the light collection efficiency of the pixel lens. Furthermore, because the negative electrode pad layer and the mesa (i.e., the epitaxial wafer including a conductive semiconductor layer with a quantum well as an intermediate layer) are not on the same planar layer, short circuits between the negative electrode pad layer and the three-sided coated reflective layer are unlikely to occur. The placement of the negative electrode pad layer allows current diffusion from the top of the pixel structure to the mesa. The placement of the negative electrode pad layer further prevents interference between adjacent pixels.

[0090] (4) The three-sided coated Ag reflective layer is processed to form a three-sided coated pattern. When connecting the three-sided coated reflective layer to the IC chip layer, an alignment bonding process is carried out to align the epitaxial positive electrode with the chip positive electrode one-to-one and bond and connect them.

[0091] (5) The continuous planarization layer between multiple pixels realizes a continuous design, plays a role in protecting the Ag, and makes it easier to spread current.

[0092] (6) An isolation layer made of Al2O3 or Si3N4 is provided to separate the three-sided coated reflective layer from the conductive semiconductor layer containing the quantum well. Compared to other conventional materials, Al2O3 has fewer lattice defects, so selecting Al2O3 as the isolation layer can prevent Ag diffusion. Compared to other conventional materials, Si3N4 has fewer lattice defects, so selecting Si3N4 as the isolation layer can prevent Ag diffusion.

[0093] (7) A novel structural design was used in which the dielectric layer was divided into a top Si3N4 layer structure and a bottom SiO2 layer structure, and the Si3N4 layer structure was attached to and covered the surface of the Ag reflective layer.

[0094] It should be noted that each of the above-described embodiments can be combined with any other embodiment described in this specification. The features and advantages described in the specification are not all-inclusive, and in particular, many additional features and advantages will be apparent to those skilled in the art upon consideration of the drawings, specification, and claims. It should also be noted that the language used in this specification has been selected primarily for readability and instructional purposes, and is not intended to describe or limit the subject matter of the present invention. [Brief explanation of the drawings]

[0095] In order that the present invention may be more fully understood, a more particular description may be made by reference to the features of various embodiments, some of which are illustrated in the drawings. However, the drawings are merely for the purpose of illustrating the relevant features of the invention, and the description should not be considered limiting, as other advantageous features may be enabled.

[0096] For convenience, "upward" refers to facing away from the substrate of the light emitting structure or circuit board, "downward" refers to facing toward the substrate, and other directional terms such as "top," "bottom," "above," "below," "beneath," "underside," etc. should be interpreted accordingly.

[0097] [Figure 1] 1 is a schematic cross-sectional view illustrating an example of the overall structure of a pixel structure according to some examples of this embodiment. [Figure 2] 1A and 1B are schematic plan views illustrating pixel structures according to some implementations of the present embodiment. [Figure 3] 1 is an exemplary schematic diagram of step 1 in a manufacturing process of a pixel structure according to some examples of the present embodiment. [Figure 4]FIG. 10 is an exemplary schematic diagram of step 2 in the manufacturing process of a pixel structure according to some examples of the present embodiment. [Figure 5] FIG. 10 is an exemplary schematic diagram of step 3 in the manufacturing process of a pixel structure according to some examples of the present embodiment. [Figure 6] FIG. 10 is an exemplary schematic diagram of step 4 in the manufacturing process of a pixel structure according to some examples of this embodiment. [Figure 7] FIG. 10 is an exemplary schematic diagram of step 5 in the manufacturing process of a pixel structure according to some examples of this embodiment. [Figure 8] FIG. 10 is an exemplary schematic diagram of step 6 in the manufacturing process of a pixel structure according to some examples of the present embodiment. [Figure 9] FIG. 10 is an exemplary schematic diagram of step 7 in the manufacturing process of a pixel structure according to some examples of this embodiment. [Figure 10] FIG. 10 is an exemplary schematic diagram of step 8 in the manufacturing process of a pixel structure according to some examples of this embodiment. [Figure 11] FIG. 10 is an exemplary schematic diagram of step 9 in the manufacturing process of a pixel structure according to some examples of the present embodiment. [Figure 12] 1 is an exemplary schematic block diagram of step 10 in a manufacturing process of a pixel structure according to some implementations of the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0098] According to common practice, the various features illustrated in the figures may not be drawn to scale. Accordingly, dimensions of various features have been arbitrarily increased or decreased for clarity. Also, some drawings may not show all of the components of a particular system, method, or apparatus. Finally, like reference numerals refer to like features throughout the specification and drawings.

[0099] Numerous details are described herein to provide a thorough understanding of the exemplary embodiments shown in the drawings. However, some embodiments may be practiced without many of the specific details, and the claims are limited only by the features and aspects specifically recited in the claims. Additionally, well-known processes, components, and materials are not described in detail to avoid unnecessarily obscuring relevant aspects of the embodiments described herein.

[0100] FIG. 1 is a schematic cross-sectional view showing an example of the overall structure of a pixel structure according to some examples of this embodiment.

[0101] FIG. 2 is a schematic plan view illustrating an example of a pixel structure according to some examples of this embodiment.

[0102] In some embodiments, Figures 1 and 2 show pixel structures configured to reduce light blocking effects and improve reflection efficiency. Pitch refers to the distance between the centers of adjacent pixels of a display panel. In some embodiments, the pitch may vary from about 40 microns to about 20 microns, to about 10 microns, and / or preferably to about 5 microns or less. Much effort has been made to reduce the pitch. When the pitch specification is determined, the single pixel area is fixed.

[0103] The structure includes, from the outside (top) to the inside (bottom), a pixel lens 1, a negative electrode pad layer 2, a conductive semiconductor layer 3, a quantum well 4, an isolation layer 5, a positive electrode layer 6, a dielectric layer 7, and an IC chip layer 8. The quantum well 4 is disposed inside the conductive semiconductor layer 3. The conductive semiconductor layer 3 is made of GaN semiconductor material, and the positive electrode layer 6 is configured as a Cu pillar. The overall operating principle is as follows: The quantum well 4 is used as a light-emitting unit. The negative electrode pad layer 2 and the positive electrode layer 6 are grounded and connected to an electrical signal from the IC chip layer 8, respectively. The electrical signal is transmitted inside the pixel via the negative electrode pad layer 2 and the positive electrode layer 6 to provide a driving signal to the quantum well 4 and control whether the quantum well 4 emits light. Therefore, the signal control command from the IC chip layer 8 enters the inside of the pixel structure via the positive electrode layer 6.

[0104] Compared with conventional pixel structures, the present invention provides improved internal details of the pixel structure, and the processing techniques for fabricating the pixel structure are also different, aiming to improve the collection efficiency of light emitted from the quantum wells 4 in the pixel structure. In some embodiments, specifically, a three-sided coated reflective layer 9 is disposed between the lower surface of the conductive semiconductor layer 3 and the top of the positive electrode layer 6, and the three-sided coated reflective layer 9 includes a conductive portion 9-1, a side reflector 9-2, and an edge reflector 9-3. The upper surface of the conductive portion 9-1 contacts the conductive semiconductor layer 3, and the lower surface of the conductive portion 9-1 contacts the positive electrode layer 6. Both the upper surface of the side reflector 9-2 and the upper surface of the edge reflector 9-3 contact the isolation layer 5, and both the lower surfaces of the side reflector 9-2 and the edge reflector 9-3 contact the dielectric layer 7. In some embodiments, as shown in FIG. 1 , the three-sided coated reflective layer 9 has symmetrical side reflectors 9-2 and edge reflectors 9-3 on both sides of the three-sided coated reflective layer 9. In this embodiment, the three-sided coated reflective layer 9 is or includes an Ag layer formed by electron beam evaporation or thermal evaporation, but other reflective material layers may also be used. Ag is used as the reflective layer material because it has the highest reflective effect. However, Ag is a material that is highly diffusive during etching, so it is not usually used as a reflective layer in the internal structure of a pixel device. In this invention, this specification describes an Ag reflective layer structure and its pixel processing technology.

[0105] In some embodiments, the light emitted from the quantum well 4 is reflected by the three-sided coated reflective layer 9, and the light from the side of the quantum well 4 away from the pixel lens 1 is reflected towards the pixel lens 1, thereby significantly improving the utilization efficiency of the light emitted from the quantum well 4.

[0106] In some embodiments, the conductive semiconductor layer 3 includes two portions: an inverted trapezoidal semiconductor portion 3-1 and a continuous planarization layer 3-2. Because the quantum well 4 is located inside the inverted trapezoidal semiconductor portion 3-1, the slope 3-1B of the inverted trapezoidal semiconductor portion 3-1 collects light emitted from the quantum well 4 and reflects it toward the pixel lens 1. Therefore, by reflecting the light emitted from the quantum well 4 on both sides of the pixel lens 1 by the slope of the inverted trapezoidal semiconductor portion 3-1, the light emitted from both sides of the pixel lens 1 is concentrated and collected in the direction of the pixel lens 1, further improving the utilization efficiency of the light emitted from the quantum well 4. The inverted trapezoidal semiconductor portion 3-1 is divided into a bottom portion 3-11 and a top portion 3-12 along the horizontal direction of the quantum well 4, and the bottom portion 3-11 and the top portion 3-12 are separated by the quantum well 4. In some embodiments, the bottom portion 3-11 is a layer including a P-type conductive semiconductor material such as P-GaN or P-InGaP, and the top portion 3-12 is a layer including an N-type conductive semiconductor material such as N-GaN or N-InGaP. In some embodiments, a transparent conductive thin film, an indium tin oxide (ITO) thin film, is deposited on top of the conductive semiconductor layer 3. In other embodiments, the P-type and N-type materials may be interchanged, and the positive and negative electrode layers may be interchanged.

[0107] In some embodiments, the negative electrode pad layer 2 is configured to have a hollow shape as shown in FIGS. 1 and 2. The hollow portion of the negative electrode pad layer 2 is aligned with the pixel lens 1, and the main portion of the negative electrode pad layer 2 is positioned on the top surface of the continuous planarization layer 3-2, rather than blocking light toward the pixel lens 1. The main portion of the negative electrode pad layer 2 protrudes from the top surface of the continuous planarization layer 3-2. Therefore, due to the design of the continuous planarization layer 3-2, the negative electrode pad layer 2 is positioned to emit light toward the pixel lens 1 through the quantum well 4, so that the negative electrode pad layer 2 does not block light, further improving the light collection efficiency of the pixel lens 1. In some embodiments, as shown in FIG. 1, the mesa is formed by an epitaxial wafer, and the epitaxial wafer is (or includes) a conductive semiconductor layer 3 having a quantum well 4 therebetween. The mesa is a light-emitting PN junction. Furthermore, since the negative electrode pad layer and the mesa are not on the same plane layer, a short circuit between the negative electrode pad layer and the three-face coated reflective layer 9 is unlikely to occur.

[0108] In some exemplary embodiments, the isolation layer 5 between the mesa and the three-sided coated reflective layer 9 and dielectric layer 7 is configured as an Al2O3 or Si3N4 material layer fabricated by deposition and etching.

[0109] Because the pixel structure includes a three-sided Ag reflective layer 9, fabricating the pixel structure using a conventional pixel fabrication process can result in loss of the Ag layer and even internal short circuits in the pixel structure. In some embodiments, the dielectric layer 7 includes a two-layer structure: a top SiN layer structure 7-1 and a bottom SiO layer structure 7-2. The SiN layer structure 7-1 covers and is attached to the surface of the three-sided reflective layer 9. The positive electrode layer 6 includes an epitaxial positive electrode 6-1 and a chip positive electrode 6-2. The epitaxial positive electrode 6-1 is disposed continuously on the SiN layer structure 7-1 and the SiO layer structure 7-2. The chip positive electrode 6-2 is disposed on an IC chip layer 8. The IC chip layer 8 includes a top chip dielectric layer 8-1 and a bottom chip electrical plate 8-2. When the chip positive electrode 6-2 penetrates the chip dielectric layer 8-1, its top is connected to the epitaxial positive electrode 6-1 by aligned bonding, and its bottom is electrically connected to the chip electrical plate 8-2. The two electrodes, the epitaxial positive electrode 6-1 and the chip positive electrode 6-2, are positioned on the two wafers before bonding and form a bond after bonding. The positive electrode layer 6 is configured as a Cu pillar. In some embodiments, the above structural arrangement and connection mode can be used to fabricate a pixel structure, i.e., a three-sided coating pattern is formed on the reflective layer during the manufacturing process, and then connected by an aligned bonding process in a subsequent stage.

[0110] Based on the above-mentioned internal pixel structure design, this embodiment provides a manufacturing process for a pixel structure that reduces the light blocking effect and improves the light reflection efficiency, which includes the following processing steps:

[0111] In step 1, an epitaxial wafer is selected. FIG. 3 is an exemplary schematic diagram of step 1 in the manufacturing process of a pixel structure according to some examples of this embodiment. As shown in FIG. 3, in the manufacturing process of a pixel structure, an epitaxial wafer including a sapphire layer 10, a conductive semiconductor layer 3, and a quantum well 4′ is selected as a starting material. In some examples, the conductive semiconductor layer 3′ includes a P-GaN material layer at the bottom of the quantum well 4′ and an N-GaN material layer at the top of the quantum well 4′.

[0112] In step 2, the semiconductor is etched. FIG. 4 is an exemplary schematic diagram of step 2 in the manufacturing process of a pixel structure according to some examples of this embodiment. As shown in FIG. 4, the conductive semiconductor layer 3′ in FIG. 3 is etched inside the epitaxial wafer using an ICP semiconductor etching process to form an inverted trapezoidal semiconductor portion 3-1 and a continuous planarization layer 3-2. The etched quantum well 4 is located inside the inverted trapezoidal semiconductor portion 3-1. In the horizontal direction of the quantum well 4, the inverted trapezoidal semiconductor portion 3-1 is etched so as to form a P-GaN portion 3-11 at the bottom and an N-GaN portion 3-12 at the top.

[0113] In step 3, an isolation layer is deposited, patterned, and etched. FIG. 5 is an exemplary schematic diagram of step 3 in the manufacturing process of a pixel structure according to some implementations of this embodiment. As shown in FIG. 5, the method includes the following two substeps: (A) depositing an ALD layer on the bottom surface of the conductive semiconductor layer 3 through a deposition process to form the isolation layer 5 (the original shape of the isolation layer 5 after deposition is not shown in FIG. 5), depositing the isolation layer 5 using Al2O3 or Si3N4 material, (B) etching the deposited isolation layer 5 to form the isolation layer 5 with the opening shown in FIG. 5, and etching the bottom of the inverted trapezoidal semiconductor portion 3-1 through an ICP etching process to form an opening (not completely shown in FIG. 5) for depositing the conductive portion 9-1 of the three-sided coated reflective layer 9.

[0114] In step 4, a three-sided coated reflective layer is deposited, patterned, and etched. FIG. 6 is an exemplary schematic diagram of step 4 in the manufacturing process of a pixel structure according to some implementations of this embodiment. As shown in FIG. 6, the method includes the following two substeps: (A) forming a three-sided coated reflective layer 9 on the bottom surface of the isolation layer 5 by a PVD process such as electron beam evaporation or thermal evaporation (the original shape of the reflective layer 9 after deposition is not shown in FIG. 6). In this implementation, an Ag material is used as the reflective layer 9; and (B) etching and trimming the three-sided coated reflective layer 9 to a predetermined shape by a peeling process.

[0115] In step 5, a dielectric layer is deposited, patterned, and etched. FIG. 7 is an exemplary schematic diagram of step 5 in the manufacturing process of a pixel structure according to some implementations of this embodiment. As shown in FIG. 7, the method includes the following two substeps: (A) forming a dielectric layer 7 (the original shape of the dielectric layer 7 after deposition is not shown in FIG. 7) on the underside of the three-sided coated reflective layer 9 by a CVD deposition process, and dividing the dielectric layer 7 into a two-layer structure consisting of a top SiN layer structure 7-1 and a bottom SiO layer structure 7-2, as shown in FIG. 1; and (B) etching and trimming the dielectric layer 7 to a predetermined shape by an ICP semiconductor etching process, leaving a space for the positive electrode layer 6.

[0116] In step 6, a positive electrode is deposited and polished. Figure 8 is an exemplary schematic diagram of step 6 in the manufacturing process of a pixel structure according to some implementations of this embodiment. As shown in Figure 8, the method includes the following two substeps: (A) depositing a positive electrode layer 6 by an electroplating process deposition method, i.e., depositing to form an epitaxial positive electrode 6-1; and (B) polishing the epitaxial positive electrode 6-1 by a CMP polishing process.

[0117] Step 7 involves aligned bonding. FIG. 9 is an exemplary schematic diagram of step 7 in the manufacturing process of a pixel structure according to some implementations of this embodiment. As shown in FIG. 9, the bottom surface of the dielectric layer 7 is connected to the IC chip layer 8 through an aligned bonding process, and the epitaxial positive electrode 6-1 and the chip positive electrode 6-2 are aligned and bonded to each other. Aligned bonding is typically performed between wafers with patterns on each side. In some implementations, the sapphire layer 10 and the IC chip layer 8 have patterned electrodes (copper) and SiO2 on their surfaces. To align and bond them, the electrodes of the two wafers are properly aligned face-to-face. The two wafers are then brought into contact to form an initial bond. The bonding is completed by the following annealing process, which improves the bonding strength of the copper-to-copper contact and the SiO2-to-SiO2 contact.

[0118] In step 8, the sapphire layer 10 is removed. Fig. 10 is an exemplary schematic diagram of step 8 in the manufacturing process of a pixel structure according to some examples of this embodiment. As shown in Fig. 10, the sapphire layer 10 on the top surface of the epitaxial wafer is peeled off by a laser peeling process.

[0119] In step 9, a negative electrode pad layer is deposited and patterned. Figure 11 is an exemplary schematic structural diagram of step 9 in the manufacturing process of a pixel structure according to some implementations of this embodiment. As shown in Figure 11, the method includes the following two substeps: (A) forming the negative electrode pad layer 2 using a PVD process of electron beam evaporation or thermal evaporation (the original shape of the negative electrode pad layer 2 after PVD is not shown in Figure 11), and (B) peeling off the negative electrode pad layer 2 through a peeling process to form a hollow shape.

[0120] In step 10, a lens is deposited and patterned. FIG. 12 is an exemplary schematic diagram of step 10 in a manufacturing process of a pixel structure according to some implementations of this embodiment. As shown in FIG. 12, the method includes the following two substeps: (A) forming a layer structure of the pixel lens 1 by a CVD deposition process (the original shape of the pixel lens 1 after deposition is not shown in FIG. 12); and (B) etching the layer structure of the pixel lens 1 by an ICP semiconductor etching process to form a lens-shaped pixel lens 1. In another example, the lens 1 is formed by self-assembly in the CVD deposition process by directly forming the lens shape on the underlying structure without etching. In some examples, the lens 1 is aligned with the hollow shape. For example, the edge of the lens 1 and the edge of the hollow shape are approximately aligned when viewed vertically.

[0121] The dimensions used in the manufacturing process are determined according to the pixel structure design of the micro LED product. In some embodiments, the following dimensional designs are implemented. For example, the diameter of the circular portion of the pixel lens 1 is 3.2±0.8 μm, the thickness of the bottom of the pixel lens 1 (e.g., excluding the focal lens portion) is 1±1 μm, the width of the top of the inverted trapezoidal semiconductor portion 3-1 is 2.05 μm to 3.8 μm, the thickness of the continuous planarization layer 3-2 is 0.01 μm to 0.2 μm, the diameter of the epitaxial positive electrode 6-1 and the chip positive electrode 6-2 is 1 μm, the height of the negative electrode pad layer 2 is 100 nm to 1 μm, and the thickness of the isolation layer 5 is 10 nm to 200 nm. Other dimensions are designed according to the design requirements of the product.

[0122] In the manufacturing process of pixel structure, the present invention relates to some special processing methods, including ICP semiconductor etching process, ALD process, PVD process, LIFT-OFF process, CVD process, electroplating deposition process, CMP polishing process, alignment bonding process and laser delamination process. Those skilled in the art can understand these technical methods.

[0123] Those skilled in the art will appreciate that pixel structures are not limited to those described above and may include more or fewer components than those shown, may combine some components, or may use different components.

[0124] The above description is only an embodiment of the present invention, and the present invention is not limited thereto. Any modifications, equivalent replacements, and improvements made without departing from the concept and principle of the present invention are included in the protection scope of the present invention.

[0125] Further embodiments further include various subsets of the embodiments described above, combining the embodiments shown in Figures 1-12 into various other embodiments, or rearranging them in other ways.

[0126] Although the detailed description contains many details, these details should not be understood to limit the scope of the present invention, but should be construed merely as illustrating different examples and aspects of the present invention. It should be understood that the scope of the present invention includes other embodiments not discussed in detail above. For example, the methods described above can be applied to the integration of functional devices other than LEDs and OLEDs with control circuit systems other than pixel drivers. Examples of non-LED devices include vertical-cavity surface-emitting lasers (VCSELs), photodetectors, microelectromechanical systems (MEMS), silicon photonics devices, power electronics, and distributed feedback lasers (DFBs). Examples of other control circuit systems include current drivers, voltage drivers, transimpedance amplifiers, and logic circuits.

[0127] The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the embodiments described herein and variations thereof. Various modifications to these embodiments will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the subject matter disclosed herein. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.

[0128] Features of the present invention may be implemented in or with the aid of a computer program product, such as a storage medium or computer-readable storage medium, having stored thereon instructions usable to program a processing system to perform any of the features presented herein. The storage medium may include high-speed random access memory, such as DRAM, SRAM, DDR RAM, or other random access solid-state memory devices, but may also include non-volatile memory, such as one or more disk storage devices, optical disk storage devices, flash memory, or other non-volatile solid-state memory devices. The memory optionally includes one or more storage devices remote from the CPU. The memory or non-volatile memory devices within the memory include non-transitory computer-readable storage media.

[0129] Features of the present invention stored on any machine-readable medium may be embodied in software and / or firmware to control the hardware of a processing system and to enable the processing system to interact with other mechanisms to utilize the results of the present invention. Such software or firmware may include, but is not limited to, application code, device drivers, operating systems, and execution environments / containers.

[0130] Although various elements or steps may be described herein using the terms "first," "second," etc., it should be understood that these elements or steps are not limited to these terms; these terms merely distinguish one element or step from another.

[0131] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the claims. As used in the embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly dictates otherwise. The term "and / or," as used herein, should be understood to include any and all combinations of one or more of the associated listed items. It should also be further understood that the terms "comprising" and / or "including," as used herein, indicate the presence of said features, integers, steps, operations, elements, and / or assemblies, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, assemblies, and / or combinations thereof.

[0132] Depending on the context, the term "if" may be understood to mean "if said precondition is true" or "when said precondition is true" or "in response to determining that said precondition is true" or "based on determining that said precondition is true" or "in response to detecting that said precondition is true." Similarly, the phrase "if [said precondition is true]" or "if [said precondition is true]" or "when [said precondition is true]" may be understood to mean "when said precondition is determined to be true" or "in response to determining that said precondition is true" or "based on determining that said precondition is true" or "upon detecting that said precondition is true" or "in response to detecting that said precondition is true," depending on the context.

[0133] The above description has been written with reference to specific embodiments for purposes of interpretation. However, the above illustrative discussion is not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments have been selected and described to enable those skilled in the art to best utilize the invention and its various embodiments by best understanding the principles of operation and practical applications. [Explanation of symbols]

[0134] 1 pixel lens 2 Negative electrode pad layer 3. Conductive semiconductor layer 3-1 Inverted trapezoid semiconductor part 3-11 P-GaN part 3-12 N-GaN part 3-2 Continuous planarization layer 4. Quantum wells 5 isolation layer 6 Positive electrode layer 6-1 Epitaxial positive electrode 6-2 Tip positive electrode 7 Dielectric Layer 7-1 Si3N4 layer structure 7-2 SiO2 layer structure 8 IC chip layer 8-1 Chip dielectric layer 8-2 Chip electrical board 9 Three-sided reflective layer 9-1 Conductive part 9-2 Side reflector 9-3 Edge reflection section

Claims

1. a conductive semiconductor layer having an inverted trapezoid shape and including a continuous planarizing layer located at the apex of the inverted trapezoid; a quantum well layer that emits light and is located within the conductive semiconductor layer; a three-sided coated reflective layer located below the conductive semiconductor layer and made of Ag; a negative electrode pad layer electrically connected to the conductive semiconductor layer; a positive electrode layer electrically connected to the conductive semiconductor layer; an integrated circuit (IC) chip layer electrically connected to the positive electrode layer; Micro-luminescent pixel structure.

2. a conductive semiconductor layer having an inverted trapezoid shape; a quantum well layer that emits light and is located within the conductive semiconductor layer; a three-sided coated reflective layer located below the conductive semiconductor layer and made of Ag; a conductive semiconductor layer and a three-sided coated reflective layer, the conductive semiconductor layer being located between the conductive semiconductor layer and the three-sided coated reflective layer, the material of which is Al ２ O ３ or Si ３ N ４ an isolation layer, a negative electrode pad layer electrically connected to the conductive semiconductor layer; a positive electrode layer electrically connected to the conductive semiconductor layer; an integrated circuit (IC) chip layer electrically connected to the positive electrode layer; Micro-luminescent pixel structure.

3. The three-sided reflective layer is an intermediate conductive portion in contact with the positive electrode layer and the conductive semiconductor layer; two side reflectors in contact with the isolation layer; two edge reflectors in contact with the isolation layer; the three-sided coated reflective layer surrounds the quantum well layer to form an inverted trapezoid; 3. The micro-luminescent pixel structure according to claim 1 or 2.

4. the quantum well layer is confined within the inverted trapezoid of the conductive semiconductor layer such that light from the quantum well is concentrated toward the top of the light-emitting pixel structure.

3. The micro-luminescent pixel structure according to claim 1 or 2.

5. the isolation layer surrounds the quantum well layer to form an inverted trapezoid; 3. The micro-luminescent pixel structure according to claim 1 or 2.

6. the conductive semiconductor layer includes a continuous planarization layer located at the top of the inverted trapezoid; The micro-luminescent pixel structure according to claim 2 .

7. the continuous planarization layer covers the entire surface of the micro-emissive pixel structure and extends to an adjacent micro-emissive pixel structure; 10. The micro-luminescent pixel structure of claim 1 or 6.

8. a conductive semiconductor layer and a three-sided coated reflective layer, the conductive semiconductor layer being located between the conductive semiconductor layer and the three-sided coated reflective layer, the material of which is Al ２ O ３ or Si ３ N ４ further comprising an isolation layer which is The micro-luminescent pixel structure of claim 1 .

9. the negative electrode pad layer is formed above the continuous planarization layer, and a region above the quantum well is hollowed out so that light emitted from the quantum well is not blocked by the negative electrode pad layer; 10. The micro-luminescent pixel structure according to claim 1 or 6.

10. The semiconductor device further includes a dielectric layer located between the three-sided coated reflective layer and the IC chip layer; The dielectric layer covers the surface of the three-sided coated reflective layer, and is made of Si ３ N ４ a top dielectric layer composed of SiO ２ and a bottom dielectric layer comprising 3. The micro-luminescent pixel structure according to claim 1 or 2.

11. the positive electrode layer includes a top epitaxial positive electrode located in the dielectric layer and a bottom chip positive electrode located in the IC chip layer; 11. The micro-luminescent pixel structure according to claim 10.

12. The IC chip layer includes a top chip dielectric layer and a bottom chip electrical plate; 3. The micro-luminescent pixel structure according to claim 1 or 2.

13. the IC chip layer containing the bottom chip positive electrode contacts the dielectric layer containing the top epitaxial positive electrode; 11. The micro-luminescent pixel structure according to claim 10.

14. further comprising a pixel lens positioned above the conductive semiconductor layer; 3. The micro-luminescent pixel structure according to claim 1 or 2.

15. providing an epitaxial wafer including a conductive semiconductor layer and a quantum well layer that emits light and is located within the conductive semiconductor layer; etching the conductive semiconductor layer having the quantum well layer into an inverted trapezoid; The bottom surface of the conductive semiconductor layer is made of Al ２ O ３ or Si ３ N ４ forming an isolation layer which is forming a three-sided coated reflective layer made of Ag on the bottom surface of the isolation layer; forming a first positive electrode layer on a bottom surface of the intermediate conductive portion of the three-sided coated reflective layer; bonding an integrated circuit (IC) chip layer to the first positive electrode layer; forming a negative electrode pad layer on the upper surface of the conductive semiconductor layer; A method for manufacturing a micro-luminescent pixel structure.

16. After forming the three-sided coated reflective layer and before forming the first positive electrode layer, a dielectric layer is formed between the three-sided coated reflective layer and the IC chip layer; The dielectric layer covers the surface of the three-sided coated reflective layer, and is made of Si ３ N ４ a top dielectric layer composed of SiO ２ and a bottom dielectric layer comprising 16. The method of claim 15.

17. and etching the conductive semiconductor layer with the quantum well layer further comprises leaving a continuous planarizing layer on top of the inverted trapezoid of the conductive semiconductor layer.

16. The method of claim 15.

18. the epitaxial wafer includes a sapphire substrate layer; the method further includes removing the sapphire substrate layer after bonding the IC chip layer and before forming the negative electrode pad layer.

16. The method of claim 15.

19. Forming the isolation layer comprises: etching the isolation layer to form an opening on a bottom surface of the conductive semiconductor layer for depositing the intermediate conductive portion of the three-sided coated reflective layer; 16. The method of claim 15.

20. forming the dielectric layer etching the dielectric layer to form an opening for depositing the first positive electrode layer; 17. The method of claim 16.

21. Bonding is a aligning and bonding the IC chip layer having the second positive electrode layer embedded therein to the bottom surface of the dielectric layer having the first positive electrode layer embedded therein; the first positive electrode layer is an upper epitaxial positive electrode; the second positive electrode layer is the bottom tip positive electrode; 17. The method of claim 16.

22. forming the negative electrode pad layer forming a hollow shape in the negative electrode pad layer in a region above the quantum well by a lift-off process so that light emitted from the quantum well is not blocked by the negative electrode pad layer; 16. The method of claim 15.

23. After forming the negative electrode pad layer, forming a pixel lens above the conductive semiconductor layer and aligning it with the hollow shape of the negative electrode pad layer.

23. The method of claim 22.

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