Rate matching method and communication device

Abstract

This application provides a rate matching method and a communication device. A transmitting end punctures an LDPC codeword based on the priority of check bits of a mother code of the LDPC code. The priority of the check bits of the mother code indicates the priority of puncturing the check bits in the rate matching process, and the priority is related to the reliability of the check bits. The reliability of the check bits indicates the degree to which the check bits are affected by noise in the channel transmission process. Furthermore, puncturing the check bits can ensure the recoverability of system variable nodes, and check bits with higher reliability are more likely to be correctly recovered, thereby providing more useful information to other system variable nodes during decoding iterations. Therefore, this application proposes that check bits with higher reliability are preferentially punctured to provide more useful information to other system variable nodes in the iterative decoding process, thereby improving the decoding performance of the receiving end.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to Chinese Patent Application No. 202211026138.X, entitled "RATE MATCHING METHOD AND COMMUNICATION APPARATUS," filed with the State Intellectual Property Office of the People's Republic of China on August 25, 2022, which is incorporated herein by reference in its entirety.

[0002] [Technical field] This application relates to the field of channel coding, and more particularly to an LDPC rate matching method and a communication device. [Background technology]

[0003] In the field of channel coding, low-density parity-check (LDPC) codes are the most mature and widely applied channel coding scheme. LDPC codes have performance close to the Shannon limit and offer many advantages. Therefore, protocols such as IEEE 802.11n, 802.11ac, and 802.11ax propose that LDPC codes be used as the standard channel coding scheme for wireless local area networks (WLANs). Currently, the 802.11ac / ax standard uses a total of 12 check matrices for LDPC codes. There are three code lengths, and each code length supports four code rates. The transmitting device selects a corresponding check matrix from the 12 check matrices based on the target code length and code rate to perform LDPC coding.

[0004] To further improve the throughput of communication systems, the next-generation WLAN 802.11be standard, based on the 802.11ax standard, is proposed to introduce the incremental redundancy-hybrid automatic repeat request (IR-HARQ) mechanism. The IR-HARQ mechanism increases redundant bits through retransmissions, reducing the channel coding rate and improving the decoding performance at the receiving end.

[0005] However, the above coding schemes used in current WLAN standards cannot meet the requirement of continuously increasing redundant bits through retransmission in the IR-HARQ mechanism to reduce the channel coding rate and improve decoding performance. Summary of the Invention

[0006] This application provides a rate matching method and a communication device that can improve decoding performance.

[0007] According to a first aspect, this application provides a rate matching method, including: a transmitting end performs rate matching on a first LDPC codeword having a first code rate based on the priority of check bits of a mother code of an LDPC code to obtain a second LDPC codeword having a second code rate; the priority indicates the priority of puncturing the check bits of the mother code during rate matching, and the priority is related to the reliability of the check bits, which indicates the degree to which the check bits are affected by noise in the channel transmission process; and the transmitting end transmits the second LDPC codeword.

[0008] In the technical solution of this application, the transmitting end performs rate matching on an LDPC codeword based on a priority for puncturing check bits of a mother code of the LDPC code during rate matching. The priority of the check bits indicates the priority for puncturing the check bits in the rate matching process, and the priority is related to the reliability of the check bits, which indicates the degree to which the check bits are affected by noise in the channel transmission process. The reliability of the check bits reflects the reliability of the check bits. Furthermore, puncturing the check bits can ensure the recoverability of the system variable nodes, and check bits with higher reliability are more likely to be correctly recovered, thereby providing more useful information to other system variable nodes during decoding iterations. Therefore, when the priority of the check bits in the rate matching process (specifically, the priority of the puncturing bits) is designed, it can be considered that check bits with higher reliability are preferentially punctured to provide more useful information to other system variable nodes in the iterative decoding process, thereby improving decoding performance.

[0009] Furthermore, the transmitting end punctures an LDPC codeword having a low code rate based on the priority of check bits of the mother code of the LDPC code to obtain an LDPC codeword having a higher code rate that is compatible with the low code rate. Alternatively, the transmitting end may obtain an LDPC codeword having a low code rate based on the priority of check bits of the mother code and the puncture position of an LDPC codeword having a high code rate. Therefore, the technical solution of this application is also applicable to an enhanced link adaptation scenario. Two communicating parties may select an appropriate code rate for communication based on the link status to select a code rate with finer granularity.

[0010] Referring to the first aspect, in some implementations of the first aspect, the transmitting end performing rate matching on a first LDPC codeword having a first code rate based on the priorities of check bits of a mother code includes: the transmitting end selecting L check bits in the first LDPC codeword for puncturing based on the number L of bits to be punctured and the priorities of the check bits of the mother code, the priorities being in descending order of the reliability of the check bits, and the L check bits being the first L check bits in the priorities, where L≧1 and L is an integer;

[0011] It should be understood that the priority of all L check bits is higher than the priority of other check bits contained in the mother code.

[0012] Referring to the first aspect, in some implementations of the first aspect, the check matrix of the mother code includes a check part, the check part includes columns corresponding to check bits and in the check matrix of the mother code, and the priority indicates the priority of the columns included in the check part, where each column included in the check part corresponds to z check bits of the mother code, z=N / n, N is the code length of the mother code, and n is the total number of columns included in the check matrix of the mother code.

[0013] Referring to the first aspect, in some implementations of the first aspect, the code length of the mother code is 1944, the code rate is 1 / 2, the check part is the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priority of the 13th column to the 24th column is as follows: 13,14,24,15,23,16,22,17,21,18,20,19 is.

[0014] Referring to the first aspect, in some implementations of the first aspect, the code length of the mother code is 1296, the code rate is 1 / 2, the check part is the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priority of the 13th column to the 24th column is as follows: 13,17,22,18,24,16,23,19,14,21,15,20 is.

[0015] Referring to the first aspect, in some implementations of the first aspect, the code length of the mother code is 648, the code rate is 1 / 2, the check part is the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priority of the 13th column to the 24th column is as follows: 13,17,16,20,24,14,19,18,23,22,15,21 is.

[0016] In the above embodiment, the column indexes of the check matrix of the mother code are numbered sequentially starting from 1. For example, for a mother code with a code rate of 1 / 2 and a code length of 1944, 1296, or 648, the column index range of the check matrix of the mother code is [1, 24].

[0017] Optionally, in some embodiments, the column indexes of the check matrix of the mother code may alternatively be numbered sequentially starting from 0. In this case, for a mother code with a code rate of ½ and a code length of 1944, 1296, or 648 in this embodiment of this application, the column index range of the check matrix of the mother code is [0, 23].

[0018] It should be understood that the technical solutions represented by the above two different index ranges, i.e., [1,24] and [0,23], are essentially the same.

[0019] Referring to the first aspect, in some implementations of the first aspect, the z check bits corresponding to any one of the columns included in the check part of the check matrix of the mother code have the same priority.

[0020] Referring to the first aspect, in some implementations of the first aspect, the L check bits in the first LDPC codeword have the following characteristics: When L ≤ z, the L check bits in the first LDPC codeword are L of the z check bits corresponding to the column with the highest priority among the columns included in the check part, where z is a positive integer, or When L > z, the L check bits in the first LDPC codeword are L of the tz check bits corresponding to t columns among the columns included in the check part. The L check bits include z(t - 1) check bits corresponding to the first t - 1 of the t columns and p check bits in the t-th column. The p check bits are any p of the z check bits corresponding to the t-th column, where both t and p are positive integers and p ≤ z, or When L = mz, the L check bits in the first LDPC codeword are mz check bits corresponding to m columns among the columns included in the check part. The m columns are the first m columns among the columns included in the check part sorted in descending order of priority, where m ≥ 1 and m is an integer satisfies one of the following.

[0021] In some descriptions of this embodiment of this application, it should be noted that "the Q columns corresponding to the highest priority in the parity-check matrix of the mother code" means that among all the columns of the parity-check matrix of the mother code, the priority of the column with the lowest priority among the Q columns is higher than the priority of the column with the highest priority among the remaining columns other than the Q columns in the parity-check matrix.

[0022] For example, assuming that the code rate of the mother code is 1 / 2 and the code length is 1944, the parity-check matrix of the mother code contains 24 columns (refer to the specification). The columns corresponding to the check bits are the 13th to 24th columns (i.e., the check part). Assuming that the priorities of the 13th to 24th columns are 13, 14, 24, 15, 23, 16, 22, 17, 21, 18, 20, 19 in descending order of priority, the 4 columns with the highest priority (e.g., Q = 4) are the 13th, 14th, 24th, and 15th columns.

[0023] Referring to the first aspect, in some implementations of the first aspect, after the transmitting end transmits the second LDPC codeword, the method further includes: the transmitting end receives retransmission instruction information; the transmitting end performs rate matching on the codeword to be retransmitted based on the priority of the check bits of the mother code to obtain a third LDPC codeword having a third code rate; the codeword to be retransmitted is obtained by performing LDPC encoding on the bits to be retransmitted, and a puncture position set of the check bits of the third LDPC codeword is a proper subset of the puncture position set of the check bits of the second LDPC codeword; and the transmitting end transmits the third LDPC codeword.

[0024] According to a second aspect, this application provides a decoding method, including: a receiving end receives a first channel received sequence; the receiving end zero-pads a corresponding position of a first LLR sequence corresponding to the first channel received sequence based on the priority of check bits of a mother code of an LDPC code; and decodes the zero-padded first LLR sequence; the corresponding position of the first LLR sequence is a position of a check bit to be punctured in a rate matching process of an LDPC codeword corresponding to the first channel received sequence, and the priority of the check bit is related to the reliability of the check bit, which indicates the degree to which the check bit is affected by noise in the channel transmission process; and if the system bits of the LDPC codeword are not obtained through decoding, the receiving end requests the transmitting end to perform retransmission.

[0025] It can be understood that when the receiving end successfully decodes the system bits of the LDPC codeword, the receiving end outputs the decoding result.

[0026] Referring to the second aspect, in some implementations of the second aspect, the check bits to be punctured in the rate matching process of the LDPC code word are the first L check bits in the check bits of the mother code corresponding to the LDPC code word and sorted in descending order of priority, where L is the number of check bits to be punctured, and L is an integer.

[0027] Referring to the second aspect, in some implementations of the second aspect, the check matrix of the mother code includes a check part, the check part includes columns corresponding to check bits and in the check matrix, and the priority indicates the priority of the columns included in the check part, where each column included in the check part corresponds to z codeword bits of the mother code, z=N / n, N represents the code length of the mother code, n represents the total number of columns included in the check matrix of the mother code, and N and n are integers.

[0028] Referring to the second aspect, in some implementations of the second aspect, the length of the mother code is 1944, the code rate is 1 / 2, the check part is the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priority of the 13th column to the 24th column is as follows: 13,14,24,15,23,16,22,17,21,18,20,19 is.

[0029] Referring to the second aspect, in some implementations of the second aspect, the length of the mother code is 1296, the code rate is 1 / 2, the check part is the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priority of the 13th column to the 24th column is as follows: 13,17,22,18,24,16,23,19,14,21,15,20 is.

[0030] Referring to the second aspect, in some implementation manners of the second aspect, the length of the mother code is 648, the code rate is 1 / 2, the check part is from the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priorities of the 13th column to the 24th column is as follows, that is, 13, 17, 16, 20, 24, 14, 19, 18, 23, 22, 15, 21 is.

[0031] Referring to the second aspect, in some implementation manners of the second aspect, the priorities of the z codeword bits corresponding to any column included in the check part are the same.

[0032] Referring to the second aspect, in some implementation manners of the second aspect, in the rate matching process of the LDPC codeword corresponding to the first channel reception sequence, the L check bits punctured are in the following cases, that is, when L < z, the L punctured check bits are any L of the z check bits corresponding to the column with the highest priority among the columns included in the check part, or when L > z, the L punctured check bits are L of the tz check bits corresponding to t columns among the columns included in the check part, the t columns are the first t columns among the columns included in the check part sorted in descending order of priority, the L check bits include z(t - 1) check bits corresponding to the first t - 1 columns among the t columns and p check bits in the tth column, the p check bits are any p of the z check bits corresponding to the tth column, and both t and p are positive integers and p ≤ z, or when L = mz, the L punctured check bits are the mz check bits corresponding to m columns included in the check part, and the m columns are the first m columns among the columns included in the check part sorted in descending order of priority satisfies one of them.

[0033] Referring to the second aspect, in some implementation manners of the second aspect, when the system bits of the LDPC code word corresponding to the first channel receiving sequence are not obtained through decoding, the receiving end requests the transmitting end to perform retransmission: The receiving end sends retransmission instruction information to the transmitting end; a receiving end receiving the second channel receive sequence; The receiving end pads corresponding positions of the second LLR sequence corresponding to the second channel received sequence with zeros based on the priority of the check bits of the LDPC code, and decodes a combined sequence of the zero-padded second LLR sequence and the zero-padded first LLR sequence. The set including positions that need to be padded with zeros in the second LLR sequence is a proper subset of the set including positions that need to be padded with zeros in the first LLR sequence. The positions that need to be padded with zeros in the second LLR sequence are the first several positions among the positions that need to be padded with zeros in the first LLR sequence and are sorted in descending order of priority.

[0034] It should be noted that the fact that the positions that need to be padded with zeros in the second LLR sequence are the first few positions of the positions that need to be padded with zeros in the first LLR sequence and that are sorted in descending order of priority indicates that the set of positions that need to be padded with zeros in the first LLR sequence completely includes the set of positions that need to be padded with zeros in the second LLR sequence, and that the positions that need to be padded with zeros in the second LLR sequence are the first few positions of the positions that need to be padded with zeros in the first LLR sequence and that are sorted in descending order.

[0035] For example, the set 1 of positions that need to be padded with zeros in the first LLR sequence is {n1, n2,..., n TAssuming that the positions in set 1 are arranged in decreasing order of priority, the positions that need to be padded with zeros in the second LLR sequence are arranged in front-to-back order from set 1 {n1, n2,..., n T} may be some positions within n1 and n2. For example, if there are two positions in the second LLR sequence that need to be padded with zeros, the positions in the second LLR sequence that need to be padded with zeros are n1 and n2. In another example, if there are four positions in the second LLR sequence that need to be padded with zeros, the positions in the second LLR sequence that need to be padded with zeros are n1, n2, n3, and n4.

[0036] According to a third aspect, the present application provides a communication device. The communication device has a function for implementing the method according to the first aspect or any possible implementation manner of the first aspect. The function may be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

[0037] According to a fourth aspect, the present application provides a communication device. The communication device has a function for implementing the method according to the second aspect or any possible implementation manner of the second aspect. The function may be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

[0038] According to a fifth aspect, the present application provides a communications device including an interface circuit and a processor, the interface circuit configured to receive computer code or instructions and transmit the computer code or instructions to the processor, the processor executing the computer code or instructions to implement a method according to the first aspect or any implementation manner of the first aspect.

[0039] According to a sixth aspect, the present application provides a communications device including an interface circuit and a processor, the interface circuit configured to receive computer code or instructions and transmit the computer code or instructions to the processor, the processor executing the computer code or instructions to implement a method according to the second aspect or any implementation manner of the second aspect.

[0040] According to a seventh aspect, the present application provides a communications device including at least one processor. The at least one processor is coupled to at least one memory. The at least one memory is configured to store computer programs or instructions. The at least one processor is configured to retrieve and execute the computer programs or instructions from the at least one memory to enable the communications device to perform a method according to the first aspect or any possible implementation manner of the first aspect.

[0041] In one example, the communication device may be an encoder.

[0042] According to an eighth aspect, the present application provides a communications device including at least one processor. The at least one processor is coupled to at least one memory. The at least one memory is configured to store computer programs or instructions. The at least one processor is configured to retrieve and execute the computer programs or instructions from the at least one memory to enable the communications device to perform a method according to the second aspect or any possible implementation manner of the second aspect.

[0043] In one example, the communication device may be a decoder (also called a decryptor).

[0044] According to a ninth aspect, the present application provides a computer-readable storage medium, the computer-readable storage medium storing computer instructions, which, when executed on a computer, effectuate a method according to the first aspect, the second aspect, or a possible implementation of either the first or second aspect.

[0045] According to a tenth aspect, the present application provides a computer program product, the computer program product comprising computer program code which, when executed on a computer, implements a method according to the first aspect, the second aspect, or a possible implementation of either the first or second aspect.

[0046] According to an eleventh aspect, the present application provides a wireless communication system including a communication device according to the third aspect and a communication device according to the fourth aspect, for example, a transmitting end and a receiving end (i.e., an encoder and a decoder) in an embodiment of the present application. [Brief explanation of the drawings]

[0047] [Figure 1] FIG. 1 is a diagram of a check matrix H of an LDPC code. [Figure 2] 1 is a Tanner graph of a check matrix H of an LDPC code. [Figure 3] 1(a) and 1(b) are diagrams of a system architecture applicable to embodiments of this application. [Figure 4] 1 is a schematic flow chart of a rate matching method according to the present application; [Figure 5] 1 is a diagram of a rate matching process for an LDPC code according to the present application. [Figure 6] FIG. 2 is a diagram of the decoding process at the receiving end according to the present application. [Figure 7] 1 is a flowchart for obtaining the reliability order of check bits according to this application; [Figure 8]1 shows an image of the function φ(x) used to determine the reliability order of check bits according to an embodiment of this application. [Figure 9] An example of application of the rate matching method according to this application is given below. [Figure 10] A comparison is shown between the BER performance curves of the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme for different numbers of check bits to be punctured. [Figure 11] A comparison is shown between the BER performance curves of the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme for different numbers of check bits to be punctured. [Figure 12] A comparison is shown between the BER performance curves of the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme for different numbers of check bits to be punctured. [Figure 13] A comparison is shown between the BER performance curves of the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme for different numbers of check bits to be punctured. [Figure 14] A comparison is shown between the BER performance curves of the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme for different numbers of check bits to be punctured. [Figure 15] A comparison is shown between the BER performance curves of the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme for different numbers of check bits to be punctured. [Figure 16] A comparison is shown between the BER performance curves of the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme for different numbers of check bits to be punctured. [Figure 17] A comparison is shown between the BER performance curves of the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme for different numbers of check bits to be punctured. [Figure 18]A comparison is shown between the BER performance curves of the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme for different numbers of check bits to be punctured. [Figure 19] A comparison is shown between the BER performance curves of the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme for different numbers of check bits to be punctured. [Figure 20] 1 is a block diagram of a communication device 1000 according to the present application. [Figure 21] 1 is a diagram of the structure of a communication device 10 according to the present application. DETAILED DESCRIPTION OF THE INVENTION

[0048] Below, the technical solutions of the embodiments in this application are described with reference to the accompanying drawings.

[0049] In the field of channel coding, low-density parity-check (LDPC) codes are the most mature and widely applied channel coding scheme. LDPC codes have performance close to the Shannon limit and offer many advantages, such as good bit error performance without deep interleaving, good frame error rate performance, and low decoding delay due to support for parallel decoding. Therefore, protocols such as IEEE 802.11n, 802.11ac, and 802.11ax propose that LDPC codes be used as the standard channel coding scheme for wireless local area networks (WLANs).

[0050] The 802.11be standard for next-generation wireless local area networks (WLANs) of the 802.11ax standard proposes hybrid automatic repeat request (HARQ) to further improve the system throughput rate. HARQ is mainly used for storing, requesting retransmission, and combining and demodulation. When data decoding (or decoding) fails, the receiving end stores the received data and requests the transmitting end to retransmit the data. The receiving end combines the retransmitted data with previously received and stored data and performs decoding. By using diversity gain, the success rate of data decoding can be improved.

[0051] HARQ may generally include two types: chase combining (CC) and incremental redundancy (IR), which may be referred to as CC HARQ and IR HARQ, respectively.

[0052] HARQ mechanisms may include two types: chase combining (CC) and incremental redundancy (IR-HARQ). In a dedicated HARQ mechanism, the receiving end directly discards incorrectly received data packets. However, although an incorrectly received data packet cannot be accurately decoded independently, the data packet still contains some useful information. In CC HARQ, this information is used to store the incorrectly received data packet in memory and combine it with a retransmitted data packet for decoding. This improves transmission efficiency. In an IR HARQ mechanism, the transmitting end transmits information bits and some redundant bits during initial transmission and transmits additional redundant bits during retransmission. If accurate decoding fails during the initial transmission, the transmitting end retransmits more redundant bits to reduce the channel's code rate, thereby increasing the decoding success rate. If the receiving end still cannot accurately perform decoding based on the redundant bits in the first retransmission, the transmitting end performs another retransmission. As the number of retransmissions increases, the redundant bits continuously increase and the channel coding rate continuously decreases, thereby achieving a better decoding effect.

[0053] If IR HARQ mechanisms are introduced in next generation WLAN standards, LDPC coding schemes that support compatibility with multiple rates will be required to support them, so that new incremental redundancy bits can be introduced during retransmissions.

[0054] To facilitate understanding of the solution of this application, concepts related to LDPC codes are first described.

[0055] The LDPC code is a linear block code, and the check matrix of the LDPC code is a sparse matrix. In the check matrix of the LDPC code, the number of zero elements is much greater than the number of non-zero elements. Alternatively, the row weight and column weight of the check matrix are sufficiently smaller than the code length of the LDPC code. An LDPC code whose information bit sequence length is equal to k and whose code length is equal to n may be uniquely determined based on the check matrix of the LDPC code.

[0056] In 1981, Tanner expressed the codeword of an LDPC code as a graph. This graph is now called a Tanner graph, and there is a one-to-one correspondence between the Tanner graph and the check matrix. A Tanner graph includes two types of vertices. One type of vertex represents a codeword bit and is called a variable node. The other type of vertex is a check node and represents a check constraint relation. Each check node represents one check constraint relation. Below, an explanation is provided with reference to Figures 1 and 2.

[0057] FIG. 1 is a diagram of a check matrix H of an LDPC code. In FIG. 1, {V i} denotes a set of variable nodes, and {C i} denotes a check node set. In the check matrix H, each row represents one check equation, and each column represents one codeword bit. In FIG. 1, there are eight variable nodes and four check nodes. When a codeword bit is included in the corresponding check equation, the associated bit node and check node are connected by using a connection line to obtain a Tanner graph.

[0058] FIG. 2 is a Tanner graph of a parity check matrix H of an LDPC code. As shown in FIG. 2, the Tanner graph represents the parity check matrix of the LDPC code. For example, for a parity check matrix H having a size of m rows and n columns, the Tanner graph includes two types of nodes: n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the parity check matrix H, respectively, and the m check nodes correspond to the m rows of the parity check matrix H, respectively. A cycle in a Tanner graph consists of connected vertices. A cycle uses one of the vertices as both the start and end point and passes through each node exactly once. The length of a cycle is defined as the number of connecting lines contained in the cycle. The girth of a graph may also be referred to as the size of the graph and is defined as the minimum cycle length in the graph. In FIG. 2, the girth is 6, as shown by the thick connecting lines. Each variable node in the Tanner graph corresponds to one column of the parity check matrix H, i.e., each codeword bit of the LDPC code. Each check node in the Tanner graph corresponds to one row of the check matrix H, i.e., corresponds to the check bits of the LDPC code. The connection between two types of nodes corresponds to the value of an element in the matrix H. If there is a connection between the i-th check node and the j-th variable node, this indicates that the value of the element (i, j) in the matrix H is 1. If there is no connection between the i-th check node and the j-th variable node, the corresponding element is 0.

[0059] Furthermore, in a Tanner graph, a cycle is a closed loop formed by end-to-end connected variable nodes, check nodes, and edges.

[0060] As mentioned above, the LDPC code is a linear block code. In the linear block code, the information sequence to be coded is divided into groups of k bits, and the encoder performs a linear operation on the k information bits to obtain m check bits. Then, the k information bits are combined with the m check bits to obtain a code group with a length of n=k+m. The mapping relationship between the k information bits and the code group with a length of n bits is usually represented by a corresponding check matrix H. A coding sequence can be correspondingly generated based on the check matrix H to complete the coding process. After the coding sequence is transmitted through a channel, the receiving end correspondingly decodes the received signal to determine the original information bits.

[0061] When the code length is long, the check matrix H of the LDPC code is very large. Therefore, the check matrix H is usually divided into blocks, and a complete check matrix H is generated by using a plurality of submatrices of z×z. Specifically, the complete check matrix H is obtained by dividing the base matrix H b may be represented by H b Each element in corresponds to a z×z submatrix, and each submatrix may be represented by the number of cyclic shift bits. Therefore, the storage space required by the complete check matrix H is significantly reduced.

[0062] In this embodiment of the application, the check matrix in the 802.11ac standard is used, and code lengths of 1944, 1296 and 648 are supported. All three code lengths support a code rate of 1 / 2. The base matrix H provided in the 802.11ac standard is b and based on the expansion factor z, the base matrix may be expanded to a complete check matrix for encoding or decoding.

[0063] The LDPC code used in the IEEE 802.11ac and 802.11ax standards is a quasi-cyclic low-density parity-check (QC-LDPC) code. The QC-LDPC code is a type of structured LDPC code. Due to the unique structure of the check matrix of the QC-LDPC code, a simple feedback shift register may be used during encoding to reduce the encoding complexity of the LDPC code.

[0064] The IEEE 802.11ac and 802.11ax standards use a total of 12 check matrixes for LDPC codes and support three code lengths. The three code lengths are 648, 1296, and 1944, respectively. Each code length supports four code rates, namely, 1 / 2, 2 / 3, 3 / 4, and 5 / 6. The check bit portions of the 12 check matrixes all have the same structure.

[0065] For example, the check matrix H of an LDPC code having a code length of 1944 and a code rate of 5 / 6 in the 802.11ac standard is expressed as follows:

number

[0066] The size of the check matrix H is 4 rows and 24 columns, and each element in the check matrix represents a square matrix of order z=N / 24. The element 0 in the matrix represents an all-zero square matrix of size z×z. The element P z i It can be seen that represents a cyclic permutation matrix, and i represents the cyclic shift value. 0≦i≦z-1, where i is an integer. Furthermore, "-" in a matrix represents an all-zero matrix, and "0" represents an identity matrix.

[0067] For example, P z 1 is shown as follows:

number

[0068] When encoding an LDPC code in a WLAN, the transmitting end selects a corresponding parity check matrix from 12 parity check matrices according to a target code length and a target code rate, and the 12 parity check matrices are different from each other.

[0069] To improve the reliability of WLAN transmission, the IR-HARQ mechanism has been introduced into the IEEE 802.11be standard based on the previous 802.11ax standard. To achieve higher throughput with the IR-HARQ mechanism, rate-compatible LDPC codes must be introduced into WLANs to obtain incremental redundancy bits during retransmission. In this way, the receiving end obtains performance gains by combining the initially received bits with the retransmitted incremental redundancy bits.

[0070] The technical solutions of this application are described below with reference to the accompanying drawings.

[0071] The technical solutions of this application may be applied to various wireless communication systems, including, but not limited to, the 5th generation (5G) system or new radio (NR) system, long term evolution (LTE) system, long term evolution-advanced (LTE-A) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, etc. The technical solutions may also be applied to future communication systems, for example, 6th generation mobile communication systems. Furthermore, the technical solutions may also be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine type communication (MTC), internet of things (IoT) communication systems, or other communication systems, etc. Furthermore, the technical solution may be further extended to similar wireless communication systems, such as wireless-fidelity (Wi-Fi) systems or worldwide interoperability for microwave access (WIMAX) systems.Optionally, the wireless communication system may comply with wireless communication standards in the Third Generation Partnership Project (3GPP®), or other wireless communication standards, such as, but not limited to, the 802 series of standards (e.g., 802.11, 802.15, or 802.20) of the Institute of Electrical and Electronics Engineers (IEEE).

[0072] (a) and (b) in Fig. 3 are diagrams of system architecture applicable to the embodiments of this application. The wireless communication system includes at least one network device and one or more terminal devices. The at least one network device communicates with one or more terminal devices by using wireless communication technology. For example, (a) in Fig. 3 shows that the network device communicates with a single terminal device. (b) in Fig. 3 shows that the network device communicates with multiple terminal devices. Optionally, the communication between the network device and the terminal device may further include downlink transmission in which the network device transmits a signal to the terminal device, and uplink transmission in which the terminal device transmits a signal to the network device. This is not limited in this specification. The transmitting end (or encoder) in the following embodiments may be the network device or the terminal device shown in Fig. 3. This is not limited.

[0073] The terminal device in the embodiments of this application may also be referred to as user equipment (UE), access terminal, subscriber unit, subscriber station, mobile station, mobile console, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user equipment. The terminal device in the embodiments of this application may be a device that provides voice and / or data connectivity to a user, and may be configured to connect people, objects, and machines, such as handheld devices or in-vehicle devices with wireless connectivity capabilities. The terminal device in the embodiments of this application may be a mobile phone, a tablet computer (pad), a notebook computer, a palmtop computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc. Optionally, the UE may function as a base station. For example, the terminal may function as a scheduling entity providing sidelink signals between terminals in V2X, D2D, etc.

[0074] In an embodiment of this application, a device configured to realize the functions of a terminal may be a terminal, or may be a device capable of supporting a terminal in realizing the functions, such as a chip system or a chip. The device may be installed in a terminal. In an embodiment of this application, a chip system may include a chip, or may include a chip and other discrete components.

[0075] For example, in an embodiment of this application, the network device may be a device with wireless transceiver functionality. The network device may be a device that provides wireless communication function services and is typically located on the network side, including, but not limited to, a next-generation Node B (gNodeB, gNB) in a fifth-generation (5G) communication system, a base station in a sixth-generation (6G) mobile communication system, a base station in a future mobile communication system, an access node in a wireless fidelity (Wi-Fi) system, an evolved Node B (eNB) in a long-term evolution (LTE) system, a radio network controller (RNC), a Node B (NodeB, NB), a base station controller (BSC), a home base station (e.g., home evolved NodeB or home NodeB, HNB), a baseband unit (BBU), a transmission reception point (TRP), a transmitting point (TP), a base transceiver station (BTS), etc. In the network structure, the network device may include a central unit (CU) node, a distributed unit (DU) node, a RAN device including a CU node and a DU node, or a RAN device including a CU control plane node, a CU user plane node, and a DU node. Alternatively, the network device may be a radio controller in a cloud radio access network (CRAN) scenario, a relay station, an in-vehicle device, a wearable device, etc. Furthermore, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof.Alternatively, the base station may be a communication module, modem, or chip disposed in the above-mentioned device or apparatus. Alternatively, the base station may be a mobile switching center, a device performing base station functions in D2D, V2X, and M2M communications, a network-side device in a 6G network, a device performing base station functions in future communication systems, etc. The base station may support networks of the same access technology or different access technologies, but this is not limited thereto.

[0076] In an embodiment of this application, an apparatus configured to implement the functionality of a network device may be a network device, or may be an apparatus capable of supporting a network device in implementing the functionality, such as a chip system or a chip. The apparatus may be installed in a network device. In an embodiment of this application, a chip system may include a chip, or may include a chip and other discrete components.

[0077] To improve system throughput, this application provides a rate matching method that can be applied to the rate matching process of LDPC codes. Specifically, the rate matching in this application mainly relates to puncturing. When the check matrix of the LDPC code in the 802.11ac standard is reused, a smaller granularity of code rate can be obtained by puncturing check bits in the LDPC codeword. The receiving end may obtain performance gains and improve decoding performance by combining codeword bits of different code rates.

[0078] FIG. 4 is a schematic flow chart of the rate matching method according to this application.

[0079] 410: The transmitting end performs rate matching on the first LDPC codeword having a first code rate according to the priority of the check bits of the mother code to obtain a second LDPC codeword having a second code rate.

[0080] The priority indicates the priority of puncturing check bits of the mother code corresponding to the first LDPC codeword during rate matching. The priority is related to the reliability of the check bits of the mother code, and the reliability of the check bits indicates the degree to which the check bits are affected by noise in the channel transmission process. For example, the reliability of check bits that are susceptible to noise is lower than the reliability of check bits that are not susceptible to noise. In other words, check bits that are more easily affected by noise are more sensitive to noise and have lower reliability. Conversely, check bits that are less easily affected by noise are less sensitive to noise and have higher reliability. Alternatively, the reliability may also be referred to as reliability or the like.

[0081] A higher reliability of the check bits indicates a higher priority for puncturing the check bits during rate matching, or a higher priority for the check bits. Conversely, a lower reliability of the check bits indicates a lower priority for puncturing the check bits during rate matching.

[0082] In one example, the priority of the check bits is in descending order of priority, where check bits with higher confidence are ranked higher in the priority order and check bits with lower confidence are ranked lower in the priority order.

[0083] In another example, the priority of the check bits may alternatively be in ascending order of priority, which is not limited in this specification, where check bits with lower confidence are ranked higher in the priority order and check bits with higher confidence are ranked lower in the priority order.

[0084] In the following embodiment, the explanation is given by using an example in which the priority is in descending order of reliability.

[0085] It should be understood that the mother code in this specification is an LDPC codeword obtained by performing LDPC encoding on system bits based on a check matrix.In other words, the mother code is an LDPC codeword that does not perform rate matching.In this specification, the code length of the mother code is denoted as N, and the code rate of the mother code is denoted as R.

[0086] In one embodiment, the first LDPC code word may be a mother code, in which case the first code rate of the first LDPC code word is the code rate of the mother code, i.e., LDPC encoding is performed on k system bits to obtain the first LDPC code word, and the code rate of the first LDPC code word is the first code rate.

[0087] The transmitting end punctures the check bits of the first LDPC codeword according to the priority of the check bits of the mother code to obtain a second LDPC codeword with a higher code rate.

[0088] In another embodiment, the first LDPC code word may be an LDPC code word obtained through rate matching. For example, the first LDPC code word may be an LDPC code word obtained by puncturing a mother code. In this case, the first code rate of the first LDPC code word is higher than the code rate of the mother code.

[0089] The transmitting end punctures the first LDPC codeword according to the priority of the check bits of the mother code to obtain a second LDPC codeword, the code rate of which is higher than the first code rate.

[0090] Alternatively, the transmitting end gradually fills the puncture positions of the first LDPC codeword based on the priority of the check bits of the mother code to gradually obtain an LDPC codeword with a lower code rate. In this case, rate matching is performed on the first LDPC codeword to obtain a second LDPC codeword with a lower code rate. In other words, the second code rate is lower than the first code rate.

[0091] It can be seen that the priority of check bits of the mother code provided in this application is used for rate matching of LDPC code words. Puncture positions may be added to the puncture pattern of an LDPC code word having a low code rate to obtain a high code rate. Furthermore, the transmitting end may alternatively fill in the puncture positions on the puncture pattern of an LDPC code word having a high code rate to obtain a low code rate. In other words, a high code rate is compatible with a low code rate.

[0092] In the technical solution provided in this application, the priorities of check bits of LDPC codes with different code lengths are different. For example, when the code lengths of the LDPC codes are 1944, 1296, or 648, respectively, the reliability of the check bits of the LDPC codewords may be different. Therefore, the priorities of puncturing check bits of LDPC codewords with different lengths during rate matching are also different, which will be provided separately below.

[0093] 420: The transmitting end transmits the second LDPC codeword.

[0094] The transmitting end performs rate matching on the LDPC codeword based on the priority of puncturing check bits of the mother code of the LDPC code during rate matching, so that the puncturing performance can be improved.

[0095] 5 is a diagram of the rate matching process of the LDPC code according to this application. As shown in FIG. 5, the descending order of priority of check bits of the LDPC code with code length N and code rate R is t1, t2, ..., t k Assume that ,...

[0096] The transmitting end performs LDPC encoding on the information bit sequence (or system bits) to obtain an LDPC codeword, where the LDPC codeword includes k system bits and NO check bits.

[0097] According to the rate matching solution provided in this application, the transmitting end device performs rate matching on the LDPC codeword obtained through encoding based on the priority of the check bits of the mother code of the LDPC code. Specifically, the number of check bits that need to be punctured and are determined by the transmitting end based on the target code rate is N p Assume that the priorities are t1, t2,..., t k Then, the sender selects t1, t2,..., t based on the priority of the check bits. k ,... to the first N p Select N check bits and p Record the bit positions corresponding to the check bits t1,t2,...,t k It should be understood that t1,... are the indices of the check bits. For example, t1 is the index of the check bit with the highest reliability, and the reliability is in descending order from front to back. In the rate matching process, the transmitting end selects N of the LDPC codewords output through encoding. p The transmit end then transmits the punctured LDPC codeword.

[0098] The decoding process at the receiving end will be described below with reference to FIG.

[0099] Figure 6 is a diagram of the decoding process at the receiving end. The receiving end stores information about the priority of check bits of the mother code, and the priority indicates the priority of puncturing the check bits of the mother code during rate matching. The priority is related to the reliability of the check bits of the mother code, and the reliability of the check bits indicates the degree to which the check bits are affected by noise in the channel transmission process. The priority of the check bits of the mother code stored by the receiving end is the same as the priority of the check bits of the mother code stored by the transmitting end, i.e., t1, t2, ..., t k It should be understood that,... The receiving end receives a channel reception sequence, and the channel reception sequence corresponds to a system bit portion and a check bit portion. In the technical solution of this application, the check bit portion is punctured. The receiving end pads the corresponding positions of the channel reception sequence with zeros based on the priority of the check bits of the mother code, and then decodes the LLR sequence corresponding to the zero-padded channel reception sequence. Specifically, the receiving end decodes the LLR sequence based on the priority and the number N of bits to be punctured. p The first N in descending order of priority based on p The receiving end may determine bit positions corresponding to N check bits. p The positions corresponding to the check bits are padded with zeros. Therefore, the positions of the check bits that are punctured by the transmitting end during rate matching are the positions that need to be padded with zeros before the receiving end performs decoding.

[0100] The principle proposed in this application that decoding performance can be improved by puncturing an LDPC code based on the priority of check bits will be described below.

[0101] This application proposes that the locations of check bits that are not sensitive to noise (i.e., check bits that are not easily affected by noise) be determined by collecting statistics on reliability features. IR-HARQ requires that the code rates of LDPC codewords at the receiving end be compatible, i.e., bits transmitted at a higher code rate are included in bits transmitted at a lower code rate. IR-HARQ preferentially punctures (also called punching) these check bits that are not easily affected by noise and have high reliability. This can ensure the recoverability of system variable nodes, especially when the number of punctured bits is large. Furthermore, because bits with higher reliability are more likely to be correctly recovered, check bits with higher reliability are preferentially punctured, so that more useful information can be provided to other system variable nodes in the iterative decoding process, thereby helping to improve puncturing performance.

[0102] Optionally, in one example, the sensitivity of check bits of an LDPC code is first defined based on the following process.

[0103] Initially, the fixed source is an all-zero source. In the absence of noise, a specific number of iterations are performed on an LDPC codeword without rate matching (or an LDPC codeword to be punctured). For example, the number of iterations is compared with a specified threshold n. After the iterative decoding converges, the absolute value |LLR| of the log-likelihood ratio (LLR) of the iterative decoding is used as a reliability feature to determine the reliability order of the check bits or the sensitivity order of the check bits. A smaller value of |LLR| indicates that the bit position corresponding to |LLR| is more sensitive and has lower reliability.

[0104] It should be noted that LDPC code is a linear code, and the sensitivity order of check bits determined by using different sources is similar, so the cycle and degree distribution characteristics of different check bits are the same, and the puncture performance is basically the same.Therefore, in the technical solution of this application, an example is used in which the fixed source is an all-zero source.

[0105] The check bits of the LDPC codeword to be punctured are sorted in descending order of reliability, and the sorting relationship of the check bits is stored in table T. Table T is a check bit sensitivity ordering table, i.e., a check bit priority ordering table in this application. In the ordering table, check bits with higher reliability are placed at the front, and check bits with lower reliability are placed at the back.

[0106] For example, the table T may be expressed by using the following equation (1): T=(t1,t2,...,t K / R-K ) (1)

[0107] T is the reliability order table of the columns included in the check part of the check matrix.The number of columns included in T can be expressed as K / RK, where K represents the number of columns corresponding to the system bits in the check matrix, R represents the code rate, and K / RK represents the number of columns corresponding to the check bits in the check matrix, that is, the number of columns included in the check part.For example, if T is arranged in descending order of reliability, t1 represents the column index of the column with the highest reliability in the check matrix, and t K / R-K is the index of the column in the check matrix that has the lowest reliability.

[0108] The process of establishing the reliability order of the check bits will now be described with reference to FIG.

[0109] 7 is a flowchart for obtaining the reliability order of check bits according to this application. As shown in FIG. 7, in a noise-free environment, an all-zero source is fixed, and LDPC coding with a corresponding code rate and code length is performed, and then modulation is performed, for example, binary phase shift keying (BPSK) modulation is performed. The decoding initial information is set to a fixed value ±x and then sent to an iterative decoder for decoding. After a certain number of iterations (for example, n times), the LLRs of the check bits are output, and the absolute values ​​|LLR| of the LLRs are sorted, for example, in descending order.

[0110] Optionally, the iterative decoder may be specifically a log-SPA iterative decoder. SPA refers to a sum-product algorithm, which is a kind of LDPC decoding algorithm based on iterative decoding, and belongs to soft-decision algorithms. When the log-SPA decoding algorithm is used, the decoding initial information of the additive white Gaussian noise (AWGN) channel is y / σ 2 , y is the channel information, and σ 2 is the noise variance. When the noise variance is 0, the decoding initial information should be ±∞. If this is set directly in the computer program, data overflow will occur. Therefore, when solving the check information, the function shown in equation (2) is used.

number

[0111] The function characteristics of φ(x) are shown in Figure 8. Figure 8 shows an image of the function φ(x) used to determine the reliability order of check bits according to an embodiment of this application. The horizontal axis x indicates the value of the log-likelihood ratio, i.e., the LLR value, transmitted in the LDPC iterative decoding process, and the vertical axis phi(x) indicates the function of x, i.e., φ(x).

[0112] Optionally, as an example, in actual decoding, the decoding initial value x may be set to 3, 4, 5, etc.

[0113] Below, in this application, the priorities of check bits of LDPC code words when the code rate is 1 / 2 and the code lengths are 1944, 1296 and 648 are provided.

[0114] (1) Code rate R = 1 / 2 and code length L = 1944 First, the check matrix of an LDPC code with a code rate of 1 / 2 and a code length of 1944 is given as follows:

number

[0115] As mentioned above, the size of the parity check matrix is ​​12x24, and each element in the parity check matrix represents a square matrix of order z=1944 / 24=81. "-" represents an 81x81 all-zero matrix. Each element i in the parity check matrix represents an 81x81 cyclic permutation matrix, and i represents a cyclic shift value. For example, i=0 represents an identity matrix whose size is 81x81, and i=1 represents a cyclic shift matrix shown in the following formula (3).

number

[0116] It should be understood that the check matrix includes a check portion, and the check portion includes columns used for check bits. Furthermore, it can be seen that the columns related to the order in Table 1 include the 13th to 24th columns of the check matrix. This is because the 13th to 24th columns of the check matrix with a code rate of 1 / 2 and a code length of 1944 correspond to the check portion of the check matrix. The codeword bits corresponding to that portion of the column are all the check bits generated through encoding. According to the method for sorting the reliability of check bits provided in this application, the check portion in the check matrix of an LDPC code with a code rate of 1 / 2 and a code length of 1944 is the 13th to 24th columns of the check matrix. Optionally, the priority of the reliability of the check bits may be the priority of the columns included in the check portion. As an example, the descending order of priority of the 13th to 24th columns included in the check portion may be, for example, the following order 1, namely: 13,14,24,15,23,16,22,17,21,18,20,19 is.

[0117] It can be seen from the above description of the parity check matrix that each column of the mother matrix of the parity check matrix corresponds to z parity check bits of the mother code.It can be seen that each column included in the parity check part of the parity check matrix of the LDPC code with a code rate of 1 / 2 and a code length of 1944 provided above corresponds to z parity check bits of the mother code, and z=1944 / 24=81.Specifically, each column from the 13th column to the 24th column of the parity check matrix of the LDPC code with a code rate of 1 / 2 and a code length of 1944 corresponds to 81 parity check bits.

[0118] In the rate matching process, it is considered that the check bits corresponding to the columns with high priorities are punctured first. Order 1 is used as an example. When the number of check bits that need to be punctured during rate matching is exactly 81, 81 check bits corresponding to the 13th column of the check matrix are punctured. When the number of check bits that need to be punctured is 81×2, 81 check bits corresponding to the 13th column and the 14th column of the check matrix are respectively punctured, and so on. The puncturing of the required number of check bits is completed in descending order of the priorities of the columns shown in Order 1.

[0119] Furthermore, in this application, the priorities of the check bits in any column included in the check part of the check matrix are the same.

[0120] Order 1 is used as an example. The 13th column corresponds to 81 check bits, and the priorities of the 81 check bits are the same. In other examples, the 14th column corresponds to 81 check bits, and the priorities of the 81 check bits corresponding to the 14th column are the same. The same principle applies to other columns in Order 1.

[0121] Without loss of generality, assume that the number of bits to be punctured during rate matching is L. If possible and when L < z, the transmitter selects L out of the z check bits corresponding to the column with the highest priority in the priorities of the check bits for puncturing. The L check bits are any L of the z check bits corresponding to the column with the highest priority among the columns included in the check part (specifically, from the 13th column to the 24th column). In other words, the L check bits may be L randomly selected from the z check bits corresponding to the column with the highest priority. When Order 1 is used as an example, the L check bits are any L of the 81 check bits corresponding to the 13th column within the check part.

[0122] In another possible case, L=mz, and the transmitting end selects check bits corresponding to the first m columns in the check bit priorities sorted in descending order of priority for puncturing. In this case, the number of bits to be punctured is equal to the number of check bits corresponding to the m columns in the check part of the parity check matrix. In this case, the transmitting end punctures the check bits corresponding to the m columns based on the first m columns in descending order of priority.

[0123] In the following, an LDPC code with a code rate of 1 / 2 and a code length of 1944 (i.e., z=81) is used as an example to describe the selection of puncture positions of check bits. When an LDPC code with a code rate of 1 / 2 and a code length of 1296 (i.e., z=54) or an LDPC code with a code rate of 1 / 2 and a code length of 684 (i.e., z=27) is used, the same criteria are used to select puncture positions of check bits.

[0124] Order 1 is used as an example. For example, if the number of bits to be punctured determined based on the target code rate is 81, the 81 check bits corresponding to the 13th column are preferentially punctured. In another example, if the number of bits to be punctured is 81×2, the transmitting end punctures the 81 check bits corresponding to the 13th column and the 81 check bits corresponding to the 14th column.

[0125] Another possible case is L>z. In this case, the transmitting end selects L check bits for puncturing among the tz check bits corresponding to the first t columns sorted in descending order of priority. The L check bits include z(t-1) check bits corresponding to the first t-1 columns of the t columns and p check bits in the t column, where p check bits are any p check bits among the z check bits corresponding to the t column, where both t and p are positive integers and p≦z.

[0126] Order 1 is used as an example. For example, assume that the number of bits to be punctured is 100, where 100 = 81 × 1 + 19. The transmitting end punctures 81 check bits corresponding to the 13th column and 19 check bits among the 81 check bits corresponding to the 14th column. Since the z check bits corresponding to the same column have the same priority, the 19 check bits may be randomly selected from the 81 check bits corresponding to the 14th column.

[0127] In another example, if the number of bits to be punctured is 190, where 190=81×2+28, the transmitting end punctures 81 check bits corresponding to the 13th column and 81 check bits corresponding to the 14th column, and punctures any 28 check bits among the 81 check bits corresponding to the 24th column.

[0128] It should be noted that the column index in order 1 is based on the column index of the parity check matrix, starting from 1. In other words, when the column index of the parity check matrix of a mother code whose code length is 1944 and whose code rate is 1 / 2 is expressed by using 1 to 24, the parity check portion in the parity check matrix is ​​the 13th column to the 24th column of the parity check matrix. Optionally, the index range of the 13th column to the 24th column included in the parity check portion may be expressed as 13 to 24.

[0129] In another possible representation, the column index of the check matrix of the mother code may start from 0, and the column index of the check matrix ranges from 0 to 23. The index of the column corresponding to the check bit and located in the check matrix should range from 12 to 23.

[0130] In the latter expression, during rate matching, the descending order of priority for puncturing columns included in the check portion of the check matrix of an LDPC code having a code rate of 1 / 2 and a code length of 1944 is, for example, the following order 2, that is, 12,13,23,14,22,15,21,16,20,17,19,18 is.

[0131] It should be understood that Order 1 and Order 2 are equivalent, and both represent priorities for puncturing columns corresponding to check bits in a check matrix of an LDPC code having a code rate of 1 / 2 and a code length of 1944 during rate matching. The only difference lies in the different ways of expressing column indices of the check matrix.

[0132] It can be seen that puncturing check bits can further ensure the recoverability of system bits, especially when a large number of bits need to be punctured. Furthermore, check bits with high reliability are preferentially punctured, so that more useful information can be provided to other system variable nodes in the iterative decoding process, thereby improving decoding performance.

[0133] The absolute values ​​of the LLRs of the check bits in the check matrix corresponding to the LDPC code having a code rate of 1 / 2 and a code length of 1944 and the order of reliability of the check bits may be as shown in Table 1. For example, the priority of the check bits may be in descending order of reliability. [Table 1]

[0134] In the "reliability order" in the first row of Table 1, each element a(b) represents the a-th column of the parity check matrix, and the column weight of the a-th column is b. The |LLR| corresponding to the a-th column represents the absolute value of the LLR of the parity check bits of the a-th column, and may reflect the reliability of the parity check bits corresponding to the column. A larger value of |LLR| indicates higher reliability, and conversely, a smaller value of |LLR| indicates lower reliability. For example, 13(3) in Table 1 represents the 13th column of the parity check matrix, and the column weight of the 13th column is 3.

[0135] Furthermore, in the reliability order in Table 1, the indices of the columns included in the check portion of the check matrix range from 1 to 24. Optionally, the columns included in the check portion may alternatively be represented by indices 0 to 23. Alternatively, the information represented in Table 1 may be recorded in other modified formats. All of the above modified formats should be included within the scope of the embodiments of this application.

[0136] Table 2 shows a comparison between the reliability-based puncturing scheme provided in this application, the scheme for puncturing unreliable check bits, and the puncturing scheme in the 802.11ac standard. [Table 2]

[0137] Table 2 shows the column indexes (column indexes start from 1) of the check bits to be preferentially punctured in the check matrix according to the reliability-based puncturing scheme provided in this application when the number of check bits to be punctured is 81×2, 81×4, 81×6, etc. In comparison, the puncturing scheme in the 802.11ac standard has a descending puncturing priority order from column 24 to column 16 of the check matrix. Furthermore, Table 2 also shows an example of puncturing bits in ascending order of reliability according to the reliability-based puncturing scheme provided in this application, for example, the middle row in Table 2 (puncturing unreliable check bits). In the scheme of puncturing unreliable check bits, the transmitting end punctures the check bits in ascending order of reliability. In other words, check bits with low reliability are preferentially punctured.

[0138] Furthermore, it can be further seen from Table 2 that in the technical solution of this application, for a certain code length, the puncture location set of check bits of an LDPC codeword with a high code rate includes the puncture location set of check bits of an LDPC codeword with a low code rate. In other words, the puncture location set of check bits of an LDPC codeword with a low code rate is a proper subset of the puncture location set of check bits of an LDPC codeword with a high code rate.

[0139] For example, when the number of bits to be punctured is 81×2 (i.e., two columns), the puncture position set of the LDPC codeword is represented by using the columns that correspond to the check bits and are in the check matrix, and the set of indices of the punctured columns is {13, 14}.

[0140] When the number of bits to be punctured is 81 × 4 (i.e., 4 columns), the puncture position set of the LDPC codeword is represented by using the columns that correspond to the check bits and are in the check matrix, and the set of indices of the punctured columns is {13, 14, 24, 15}.

[0141] When the number of bits to be punctured is 81 × 6 (i.e., 6 columns), the puncture position set of the LDPC codeword is represented by using the columns that correspond to the check bits and are in the check matrix, and the set of indices of the punctured columns is {13, 14, 24, 15, 23, 16}.

[0142] According to the puncturing principle, it can be seen that a larger number of punctured bits indicates a higher code rate of an LDPC codeword. Therefore, the puncture position set of an LDPC codeword with a low code rate is a proper subset of the puncture position set of an LDPC codeword with a high code rate. In other words, in the puncturing method in this application, a high code rate is compatible with a low code rate. That is, a new puncture position is added to the puncture position set of an LDPC codeword with a low code rate to obtain a puncture position set of an LDPC codeword with a higher code rate.

[0143] (2) Code rate R = 1 / 2 and code length L = 1296 In the following, the check matrix of an LDPC code with a code rate of 1 / 2 and a code length of 1296 is first provided as follows:

number

[0144] As mentioned above, the size of the parity check matrix is ​​12x24, and each element in the parity check matrix represents a square matrix of order z=1296 / 24=54. "-" represents a 54x54 all-zero matrix. Each element i in the parity check matrix represents a 54x54 cyclic permutation matrix, and i represents the cyclic shift value. For example, i=0 represents an identity matrix whose size is 54x54, and i=1 represents a cyclic shift matrix whose cyclic shift matrix is ​​1.

[0145] According to the method for sorting the reliability (or sensitivity to noise) of check bits provided in this application, during rate matching, the descending order of priority for puncturing columns corresponding to check bits in a check matrix of an LDPC code having a code rate of ½ and a code length of 1296 (i.e., columns included in the check part of the check matrix) is, for example, the following order 3, i.e., 13,17,22,18,24,16,23,19,14,21,15,20 is.

[0146] Similarly, order 3 is expressed based on the fact that the column index range of the parity check matrix is ​​1 to 24. When the column index of the parity check matrix starts from 0, the descending order of priority for puncturing columns corresponding to check bits in the parity check matrix of an LDPC codeword having a code rate of 1 / 2 and a code length of 1296 during rate matching is, for example, the following order 4, i.e., 12,16,21,17,23,16,22,18,13,20,14,19 is.

[0147] The absolute values ​​of the LLRs of the check bits and the reliability order of the check bits in the check matrix corresponding to the LDPC codeword with a code rate of 1 / 2 and a code length of 1944 may be as shown in Table 3. [Table 3]

[0148] In the "reliability order" in the first row of Table 3, each element a(b) represents the a-th column of the parity check matrix, and the column weight of the a-th column is b. The |LLR| corresponding to the a-th column represents the |LLR| of the parity check bits in the a-th column.

[0149] Similar to the above LDPC codeword with a code length of 1944, only the reliability of the check bits is sorted in this application, so Table 3 shows the check part of the check matrix of the LDPC codeword with a code rate of 1 / 2 and a code length of 1296. In other words, the reliability order of the check bits in the 13th to 24th columns of the check matrix is ​​the priority order of the check bits in this application.

[0150] In the reliability order of Table 3, the column index of the check matrix may range from 1 to 24, or may be represented by 0 to 23. This is not limited.

[0151] Furthermore, each column of the check matrix of an LDPC codeword with a code rate of 1 / 2 and a code length of 1296 corresponds to 54 check bits of the mother code. The check bits corresponding to any column in the check part of the check matrix have the same priority. For example, the 13th column, which has the highest priority, corresponds to 54 check bits of the mother code, and the 54 check bits have the same priority. If the transmitting end needs to puncture t check bits in the 13th column, and t<54, the t check bits may be randomly selected from the 54 check bits in the 13th column. The same applies to the other columns in Table 3, and the details will not be described again.

[0152] (3) Code rate R = 1 / 2 and code length L = 648 In the following, the check matrix of an LDPC codeword with a code rate of 1 / 2 and a code length of 648 is first provided as follows:

number

[0153] As mentioned above, the size of the parity check matrix is ​​12x24, and each element in the parity check matrix represents a square matrix of order z=648 / 24=27. "-" represents a 27x27 all-zero matrix. Each element i in the parity check matrix represents a 27x27 cyclic permutation matrix, and i represents the cyclic shift value. For example, i=0 represents an identity matrix whose size is 27x27, and i=1 represents a cyclic shift matrix whose cyclic shift matrix is ​​1.

[0154] According to the method for sorting the reliability of check bits provided in this application, during rate matching, the priority of puncturing columns corresponding to check bits in a check matrix of an LDPC codeword with a code rate of 1 / 2 and a code length of 648 is sorted in descending order, for example, into the following order 5, i.e., 13,17,16,20,24,14,19,18,23,22,15,21 is.

[0155] Similarly, the order 5 is expressed based on the fact that the column index range of the check matrix is ​​1 to 24. When the column index of the check matrix starts from 0, the descending order of priority for puncturing columns corresponding to check bits in the check matrix of an LDPC codeword with a code rate of 1 / 2 and a code length of 1296 during rate matching is sorted in descending order, for example, into the following order 6, i.e., 12,16,15,19,23,13,18,17,22,21,14,20 is.

[0156] The absolute values ​​|LLR| of the LLRs of the check bits in the parity check matrix corresponding to the LDPC codeword with a code rate of 1 / 2 and a code length of 648 and the reliability order of the check bits may be as shown in Table 4. [Table 4]

[0157] In the "reliability order" in the first row of Table 4, each element a(b) represents the a-th column of the parity check matrix, and the column weight of the a-th column is b. The |LLR| corresponding to the a-th column represents the |LLR| of the parity check bits in the a-th column.

[0158] Since only the reliability of the check bits is sorted in this application, it can be understood that Table 4 shows the check part of the check matrix of the LDPC codeword whose code rate is 1 / 2 and whose code length is 1296. In other words, the reliability order of the check bits in the 13th to 24th columns of the check matrix is ​​the priority order of the check bits in this application.

[0159] Each column of the check matrix of an LDPC codeword with a code rate of 1 / 2 and a code length of 648 corresponds to 27 check bits of the mother code. Check bits belonging to the same column in the check part of the check matrix have the same priority. For example, the 13th column with the highest priority corresponds to 27 check bits of the mother code, and the 27 check bits have the same priority. If the transmitting end needs to puncture t check bits in the 13th column, and t<27, the t check bits may be randomly selected from the 27 check bits in the 13th column. The same applies to the other columns in Table 4, and the details will not be described again.

[0160] The above describes in detail the rate matching method provided in this application. Below, with reference to Figure 9, the application of the technical solution of this application in an IR-HARQ scenario will be described. In the IR-HARQ scenario, as the number of retransmissions increases, more incremental redundancy bits may be obtained by puncturing more check bits, so that the code rate continuously decreases. This can increase the probability of successful decoding at the receiving end and improve decoding performance.

[0161] FIG. 9 shows an example of application of the rate matching method according to this application.

[0162] Optionally, the operations or processes performed by the receiving end in the flowchart shown in Figure 9 may be performed by a chip, circuit system, etc. disposed in the receiving end device. The circuit system may be, for example, an integrated circuit or a logic circuit. The chip may be a system on a chip (SoC) chip, a baseband modem chip, etc., which is not limited in this specification. In the following, the receiving end device is used as an example for explanation.

[0163] The receiving end may be a terminal device or a network device. It should be understood that the receiving end in the embodiment of this application is also a decoding device. For example, in uplink transmission, the transmitting end is a terminal device, and the receiving end is a network device. In downlink transmission, the transmitting end is a network device, and the receiving end is a terminal device.

[0164] 601: The transmitting end performs LDPC coding on k information bits (also called system bits) according to a required code rate R and code length N to obtain a first LDPC codeword, where the code rate of the first LDPC codeword is R and the code length is N, where k and N are both integers.

[0165] It can be understood that the code rate R of the first LDPC codeword may be used as the basic code rate. For example, R may be 1 / 2. Based on this code rate, a higher code rate, for example, 2 / 3, 3 / 4, or 5 / 6, can be obtained by puncturing the LDPC code.

[0166] LDPC encoding is performed on the information bit sequence based on the above provided check matrices with code rate ½ and code lengths 1944, 1296 and 648 to obtain a first LDPC codeword with code rate ½ and code length N. The value of N may be 1944, 1296 or 648 depending on the check matrix used during encoding.

[0167] For example, if the transmitting end uses a check matrix corresponding to an LDPC code whose code rate is 1 / 2 and whose code length is 1944, the length of the first LDPC codeword obtained through encoding is 1944.

[0168] In another example, if the transmitting end uses a check matrix corresponding to an LDPC code whose code rate is 1 / 2 and whose code length is 1296, the length of the first LDPC codeword obtained through encoding is 1296.

[0169] In another example, if the transmitting end uses a check matrix corresponding to an LDPC code whose code rate is 1 / 2 and whose code length is 648, the length of the first LDPC codeword obtained through encoding is 648.

[0170] In the following, a code length N=1944 is used as an illustrative example.

[0171] 602: The transmitting end performs rate matching on the first LDPC codeword according to the priority of the check bits of the mother code to obtain a second LDPC codeword.

[0172] According to the required code rate (or target code rate) and the priority of the check bits (for example, the reliability order of the check bits in the above embodiment) of the mother code with a code rate of 1 / 2 and a code length N=1944, the transmitting end punctures the check bits of the first LDPC code word to obtain a second LDPC code word with a second code rate.

[0173] In other words, the second LDPC codeword is a codeword obtained by puncturing the first LDPC codeword, and therefore the code rate of the second LDPC codeword (i.e., the second code rate) is greater than the first code rate.

[0174] In this embodiment, an LDPC codeword with a code rate of 1 / 2 is used as a basic codeword, and the basic codeword is punctured to obtain a codeword with a higher code rate (i.e., a second code rate).

[0175] 603: The transmitting end transmits the second LDPC codeword.

[0176] The receiving end receives the first channel receive sequence from the transmitting end.

[0177] 604: The receiving end pads with zeros the corresponding positions of the first LLR sequence corresponding to the first channel received sequence according to the priority of the check bits of the LDPC code having a code rate of 1 / 2 and a code length of N, and then decodes the zero-padded first LLR sequence.

[0178] As described in FIG. 6 above, before performing decoding, the receiving end first pads with zeros the bit positions corresponding to the check bits punctured by the transmitting end, and then performs decoding.

[0179] Since both the receiving end and the transmitting end store information about the priorities of check bits of LDPC codewords with code rates of 1 / 2 and different code lengths, the receiving end may know the positions of the punctured check bits based on the current code rate and the current code length, and therefore, the receiving end pads the positions of these punctured check bits with zeros before performing decoding.

[0180] The receiving end decodes the zero-padded first LLR sequence. If possible, the receiving end successfully decodes all system bits of the second LDPC codeword. In this case, the receiving end performs step 605.

[0181] 605: When the receiving end successfully decodes all the system bits, the receiving end outputs the decoding result.

[0182] After step 605, the next data packet is communicated.

[0183] In another possible case, if the receiving end fails to decode all system bits, the receiving end sends retransmission instruction information to the transmitting end to request the transmitting end to perform retransmission, as described in steps 606 to 608 below.

[0184] 606: The receiving end sends retransmission instruction information to the transmitting end.

[0185] The retransmission instruction information instructs the transmitting end to retransmit the LDPC codeword. Optionally, the retransmission instruction information may further indicate the portion that was not correctly received. For example, the portion that was not correctly received may be a codeword, a media access control protocol data unit (MPDU), etc., depending on the particular configuration.

[0186] The transmitting end receives retransmission instruction information from the receiving end.

[0187] When the receiving end does not correctly decode the system bits of the LDPC codeword, the mechanism that the transmitting end performs retransmission may have several specific implementation methods.In Figure 9, the method that the receiving end sends retransmission instruction information to the transmitting end to request the transmitting end to perform retransmission is used as an example only.This is not limited in this specification.

[0188] 607: The transmitting end transmits a third LDPC codeword having a third code rate, wherein the set of punctured check bits of the third LDPC codeword is a subset of the set of punctured check bits of the second LDPC codeword.

[0189] It can be understood that the second LDPC code having the second code rate cannot be successfully decoded by the receiving end. In the case of retransmission, the code rate is usually reduced to increase the probability of successful decoding by the receiving end. Therefore, in one example, the code rate of the third LDPC code (i.e., the third code rate) is lower than the second code rate.

[0190] Furthermore, in an IR-HARQ scenario, a puncture pattern corresponding to a high code rate is compatible with a puncture pattern corresponding to a low code rate, i.e., a puncture pattern corresponding to a high code rate includes a puncture pattern corresponding to a low code rate, i.e., a puncture position set of a codeword having a low code rate includes a puncture position set of a codeword having a high code rate.

[0191] The transmitting end first transmits a second LDPC codeword having a high code rate. If the receiving end does not correctly decode all system bits of the second LDPC codeword, the transmitting end may retransmit punctured check bits of the second LDPC codeword. The specific number of check bits to be retransmitted may be determined according to transmission requirements, for example, based on a new code rate required for retransmission, a new number of channel resources allocated for retransmission, etc. As an example, assume that the transmitting end retransmits t punctured check bits.

[0192] In an embodiment, during retransmission, the transmitting end may transmit only the punctured check bits, for example, the t check bits may be the first t check bits of all punctured check bits of the first LDPC codeword sorted in descending order of reliability.

[0193] The priority of check bits for a mother code of length N is, in descending order, as follows: {t1,t2,...,t i ,...}, where t i represents the index of the column corresponding to the check bit and in the check matrix of the mother code, and t i is an integer, Assume that it can be shown as follows.

[0194] In this embodiment of the present application, a higher reliability of a check bit indicates a higher priority for puncturing the check bit during rate matching. Thus, the t check bits are arranged in descending order of priority as {t1, t2, ..., t i ,...}.

[0195] In other embodiments, during retransmission, the transmitting end may transmit punctured check bits and part of the system bits, which is not limited in this specification.

[0196] The receiving end receives the second channel receive sequence from the transmitting end.

[0197] 608: The receiving end pads with zeros the corresponding positions of the second LLR sequence corresponding to the second channel received sequence based on the priority of the check bits of the mother code of the LDPC code, and then decodes a combined sequence of the zero-padded second LLR sequence and the zero-padded first LLR sequence.

[0198] The combined sequence is obtained by combining the zero-padded second LLR sequence and the zero-padded first LLR sequence. Specifically, the zero-padded second LLR sequence and the zero-padded first LLR sequence are combined bit by bit. LLR values ​​at the same bit positions in the zero-padded second LLR sequence and the zero-padded first LLR sequence are combined, and LLR values ​​at different bit positions are retained.

[0199] For example, the length of the first zero-padded LLR sequence is 6, and the index positions are 1, 2, 3, 4, and 5, and the LLR values ​​corresponding to the index positions are LLR 11 , LLR 12 , LLR 13 , LLR 14 and LLR 15The length of the second zero-padded LLR sequence is 6, and the index positions are 3, 4, 5, 6, and 7, and the LLR values ​​corresponding to the index positions are LLR 23 , LLR 24 , LLR 25 , LLR 26 and LLR 27 Therefore, the composite sequence is 11 ,LLR 12 ,LLR 13 +LLR 23 ,LLR 14 +LLR 24 ,LLR 15 +LLR 25 ,LLR 26 ,LLR 27}, where the addition of the LLR values ​​is a binary addition.

[0200] In this embodiment of this application, the receiving end performs synthesis based on the LLR sequence is used as an example only. Those skilled in the art may come up with other equivalent modifications or processes. For example, the receiving end can also synthesize soft information obtained through demodulation. This may specifically depend on the decoding mechanism of the receiving end.

[0201] In some cases, when the receiving end successfully acquires all system bits through decoding based on the composite sequence, the receiving end outputs the decoding result, as shown in step 609 .

[0202] Otherwise, the receiving end still fails to obtain the system bits through decoding based on the composite sequence, and the receiving end may request the transmitting end to perform the next retransmission until the receiving end successfully obtains the system bits through decoding or until a specified maximum number of retransmissions is reached, and then the receiving end determines that the decoding has failed, as described in step 610.

[0203] Specifically, if the receiving end fails to recover the system bits during the initial transmission, the transmitting end may retransmit the punctured check bits in descending order of reliability. For example, in the first retransmission, the transmitting end may retransmit the n1 check bits punctured during the initial transmission and having the highest priority in descending order of priority. If the receiving end still fails to perform decoding, the transmitting end retransmits the n2 check bits punctured during the initial transmission and having the second highest priority in descending order of priority. The remaining check bits may be inferred by analogy until all punctured check bits are transmitted. It can be understood that the code rate continuously decreases in this process. If the receiving end still cannot correctly decode the system bits after the transmitting end has retransmitted all punctured check bits, this indicates that the data packet has failed to be transmitted.

[0204] From the above retransmission process, it can be seen that the code rate of the l-th retransmission may satisfy the following relationship:

number

[0205] The above describes in detail the rate matching process and decoding process of the receiving end provided in this application. The following describes the application of the method in IR-HARQ by using an example.

[0206] In one example, the transmitting end and the receiving end store information regarding the priority of check bits of the mother code of the LDPC code.

[0207] The priority of the check bits of the mother code is, in descending order, {t1, t2,..., t i,...}, where t i is an integer. It should be understood that the priority is expressed by using the column index of the check portion of the check matrix of the mother code.

[0208] When an initial IR-HARQ transmission is performed, the transmitting end may determine the number L of check bits that need to be punctured based on the code rate required for the initial IR-HARQ transmission. Based on the number L of check bits that need to be punctured and based on the priorities of the check bits in descending order, the transmitting end selects the first L check bits in the order of priority and records the respective positions of the L check bits. After completing LDPC encoding, the transmitting end performs rate matching. Specifically, the transmitting end punctures the L check bits of the LDPC codeword output after encoding, and then transmits the L check bits.

[0209] During initial transmission, an LDPC codeword with a high code rate is obtained through puncturing, for example, the code rate is 5 / 6.

[0210] For the initial IR-HARQ transmission, the receiving end determines the positions (i.e., indexes) of the first L check bits sorted in descending order of priority according to the priority of the check bits of the mother code based on the current target code length, the current target code rate, and the number L of bits to be punctured, and performs LDPC decoding after padding the positions corresponding to the L check bits with zeros.

[0211] If the initial IR-HARQ transmission fails, i.e., the receiving end fails to decode all system bits, a retransmission in the IR-HARQ mechanism is performed.

[0212] When IR-HARQ retransmission is performed, the transmitting end may determine the number of bits P that need to be punctured for retransmission based on the code rate required for the retransmission or based on the number of channel resources allocated for the retransmission, where P is an integer.

[0213] It can be understood that in order to improve the decoding success rate at the receiving end, the code rate is usually reduced for retransmission. Therefore, the code rate used for retransmission is usually lower than the code rate used for initial transmission. In other words, the number P of bits that need to be punctured in retransmission is less than the number N of bits that need to be punctured in initial transmission.

[0214] For ease of explanation, assume that the code rate used in the first retransmission is R1.

[0215] When performing the first retransmission, the transmitting end may transmit the first n1 check bits among the L check bits punctured during the initial transmission in descending order of priority, where n1 is an integer, i.e., the priorities of the n1 check bits are not lower than the priorities of the check bits other than the n1 check bits among the L check bits.

[0216] The transmitting end transmits n1 check bits.

[0217] The receiving end receives the n1 check bits, combines the sequence corresponding to the n1 check bits and the sequence received during the initial transmission into one sequence, and then decodes the combined sequence.

[0218] If the receiving end successfully decodes all system bits based on the composite sequence, the decoding is successful.

[0219] If the receiving end still fails to recover all system bits based on the composite sequence and the maximum number of retransmissions has not been reached, the next retransmission is performed.

[0220] When performing the second retransmission, the transmitting end may transmit n2 check bits with higher priority than the n1 check bits among the L check bits punctured during the initial transmission, where n2 is an integer.

[0221] Specifically, the transmitting end may select n2 check bits in descending order of priority from the remaining check bits other than n1 check bits among the L check bits punctured during initial transmission.

[0222] The transmitting end transmits n2 check bits.

[0223] The receiving end receives the n2 check bits, combines the sequence corresponding to the n2 check bits, the sequence corresponding to the n1 check bits, and the sequence received during the initial transmission into one sequence, and then decodes the combined sequence.

[0224] The remaining bits may be inferred by analogy until the transmitting end transmits all punctured check bits during the initial transmission. In this case, if the receiving end still cannot accurately restore the system bits, this indicates that the data packet has failed to be transmitted, and the transmission is terminated.

[0225] From the above process, it can be seen that when selecting check bits that need to be punctured during initial transmission, the transmitting end preferentially selects check bits with high priority to perform puncturing, i.e., preferentially punctures check bits with high reliability (or check bits that are not easily affected by noise or are not sensitive to noise). During retransmission, check bits with high priority among the punctured check bits are preferentially retransmitted. The transmitting end follows this principle of puncturing and retransmission, so that the probability of successful decoding by the receiving end can be increased.

[0226] Furthermore, the success rate of decoding by the receiving end is improved, so the number of retransmissions is reduced and the retransmission delay is reduced.

[0227] The transmitting end continuously fills in the punctured check bits, so that the code rate is continuously reduced, for example, gradually reduced from 5 / 6 to 3 / 4, 2 / 3, 1 / 2, etc. This can meet the requirement of increasing redundant bits through retransmission in the IR-HARQ mechanism to reduce the channel coding rate, and can improve the decoding performance.

[0228] The above describes in detail the process of the receiving end performing rate matching on the receiving end and the decoding process of the receiving end with reference to Figures 1 to 9. The following provides a BER performance comparison between the reliability-based puncturing scheme provided in the embodiments of this application and the puncturing scheme in the 802.11ac standard.

[0229] 10-19 show a comparison between the BER performance curves of the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme for different numbers of check bits to be punctured.

[0230] The simulation parameters in Figures 10 to 19 are set as follows: AWGAN channel, BPSK modulation, log-SPA decoding, the maximum number of decoding iterations is 10, a stop-wait retransmission request policy is used, and the maximum number of transmissions to recover data for each frame is 4.

[0231] Furthermore, the performance evaluation parameters considered in Figures 10 to 19 are mainly frame error rate (FER) and throughput. Throughput = (amount of correctly received frames x k) / total number of transmitted bits, where k is the number of information bits in each frame. Furthermore, in the above figures, b / N0 represents the bit error rate, E s / N0 represents the symbol signal-to-noise ratio. The mother code uses a QC-LDPC code with a code length of 1944 or 972 in the 802.11ac standard.

[0232] Specifically, Figure 10 shows the BER performance comparison between the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme (mother code length is 1944) for various numbers of check bits to be punctured.

[0233] FIG. 11 shows the BER performance comparison between the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme (mother code length is 1296) for different numbers of check bits to be punctured.

[0234] FIG. 12 shows the BER performance comparison between the reliability-based puncturing scheme provided in this application and the conventional puncturing scheme (mother code length is 648) for different numbers of check bits to be punctured.

[0235] 10 to 12, "puncturing reliable bits" refers to a puncturing scheme in which reliable (i.e., high reliability) check bits are preferentially punctured based on the reliability provided in this application, "802.11ac puncturing" refers to a puncturing scheme in the 802.11ac standard, also referred to as conventional puncturing in this specification, and "puncturing unreliable bits" refers to a scheme in which unreliable (i.e., low reliability) check bits are preferentially punctured based on their reliability. The numbers in parentheses indicate the number of bits to be punctured, and correspond to the number of bits to be punctured when 2 columns, 4 columns, 6 columns, 8 columns, and 9 columns are punctured, as shown in Table 2.

[0236] Same E sIt can be seen that for / N0, the FER of the reliability-based puncturing scheme provided in this application is lower, which indicates that the reliability-based puncturing scheme provided in this application has better performance than the conventional puncturing scheme.

[0237] FIG. 13 shows an example of application of a puncturing method to an LDPC code with a maximum number of retransmissions of 3 and a mother code length of 1944 in an IR-HARQ mechanism.

[0238] FIG. 14 shows another application example of a puncturing method for an LDPC code in which the maximum number of retransmissions is 3 and the mother code length is 1944 in an IR-HARQ mechanism.

[0239] FIG. 15 shows another application example of a puncturing method for an LDPC code in which the maximum number of retransmissions is 2 and the mother code length is 1944 in an IR-HARQ mechanism.

[0240] FIG. 16 shows another application example of a puncturing method for an LDPC code in which the maximum number of retransmissions is 2 and the mother code length is 1944 in an IR-HARQ mechanism.

[0241] FIG. 17 shows another application example of a puncturing method for an LDPC code in which the maximum number of retransmissions is 1 and the mother code length is 1944 in an IR-HARQ mechanism.

[0242] FIG. 18 shows another application example of a puncturing method for an LDPC code in which the maximum number of retransmissions is 1 and the mother code length is 1944 in an IR-HARQ mechanism.

[0243] FIG. 19 shows an example of application of a puncturing method to an LDPC code in which the maximum number of retransmissions is 1 and the mother code length is 1944 in an IR-HARQ mechanism.

[0244] In the legends of Figures 13 to 19, "proposed scheme" represents the reliability-based puncturing scheme proposed in this application, "standard scheme" represents the standard (i.e., the 802.11ac standard mentioned above) puncturing scheme, and "puncturing unreliable bits" represents the puncturing scheme in which unreliable check bits are punctured, which corresponds to the puncturing schemes in the middle row of Table 2.

[0245] From Figures 13 to 19, the same E s It can be seen that for / N0, the reliability-based puncturing scheme provided in this application has a lower FER and a higher throughput. This indicates that the reliability-based puncturing scheme provided in this application, in which check bits with high reliability are preferentially punctured, has better performance than the conventional puncturing scheme, and also has better performance than the puncturing scheme in which check bits with low reliability are preferentially punctured.

[0246] The communication device in this application will be described below.

[0247] 20 is a block diagram of a communication device 1000 according to an embodiment of the present application. As shown in FIG. 20, the communication device 1000 includes: a processing unit 1100, a receiving unit 1200, and a sending unit 1300.

[0248] Optionally, the communication device 1000 may correspond to a transmitting end in an embodiment of the method.

[0249] In this case, each unit of the communication device 1000 has the following functions.

[0250] The processing unit 1100 is configured to perform rate matching on a first low-density parity-check LDPC codeword having a first code rate based on priorities of check bits of a mother code of the LDPC code to obtain a second LDPC codeword having a second code rate, where the priorities indicate priorities for puncturing the check bits of the mother code during rate matching, and the priorities are related to the reliability of the check bits, which indicates the degree to which the check bits are affected by noise in a channel transmission process.

[0251] The transmitting unit 1300 is configured to transmit a second LDPC codeword.

[0252] Optionally, in an embodiment, the processing unit 1100: The puncturing unit is further configured to select L check bits in the first LDPC codeword for puncturing based on the number L of bits to be punctured and priorities of the check bits of the mother code, where the priorities are in descending order of reliability of the check bits, and the L check bits are the first L check bits in the priorities, where L≧1 and L is an integer.

[0253] Optionally, in an embodiment, the check matrix of the mother code includes a check part, the check part includes columns corresponding to check bits and in the check matrix, and the priority indicates the priority of the columns included in the check part, where each column included in the check part corresponds to z check bits of the mother code, z=N / n, N is the code length of the mother code, and n is the total number of columns included in the check matrix of the mother code.

[0254] Optionally, in an embodiment, the code length of the mother code is 1944, the code rate is ½, the check portion is the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priority of the 13th column to the 24th column is as follows: 13,14,24,15,23,16,22,17,21,18,20,19 is.

[0255] Optionally, in an embodiment, the code length of the mother code is 1296, the code rate is 1 / 2, the check part is from the 13th column to the 24th column in the check matrix of the mother code, and the descending order of the priorities of the 13th column to the 24th column is as follows, that is, 13, 17, 22, 18, 24, 16, 23, 19, 14, 21, 15, 20 is.

[0256] Optionally, in an embodiment, the code length of the mother code is 648, the code rate is 1 / 2, the check part is from the 13th column to the 24th column in the check matrix of the mother code, and the descending order of the priorities of the 13th column to the 24th column is as follows, that is, 13, 17, 16, 20, 24, 14, 19, 18, 23, 22, 15, 21 is.

[0257] Optionally, in an embodiment, the priorities of the z check bits corresponding to any column included in the check part are the same.

[0258] Optionally, in an embodiment, The L check bits in the first LDPC codeword are as follows, that is, When L < z, the L check bits in the first LDPC codeword are L of the z check bits corresponding to the column with the highest priority among the columns included in the check part, where z is a positive integer, or When L > z, the L check bits in the first LDPC codeword are L of the tz check bits corresponding to t columns among the columns included in the check part, where the t columns are the first t columns among the columns included in the check part sorted in descending order of priority, and the L check bits include z(t - 1) check bits corresponding to the first t - 1 columns among the t columns and p check bits in the t-th column, where the p check bits are any p of the z check bits corresponding to the t-th column, and both t and p are positive integers and p ≤ z, or If L=mz, the L check bits in the first LDPC codeword are mz check bits corresponding to m columns in the check portion, where the m columns are the first m columns in the check portion sorted in descending order of priority, where m≧1 and m is an integer. Satisfy one of the following.

[0259] Optionally, in an embodiment, the receiving unit 1200 is further configured to receive retransmission instruction information.

[0260] The processing unit 1100 is further configured to perform rate matching on the codeword to be retransmitted based on the priority of the check bits of the mother code to obtain a third LDPC codeword having a third code rate, where the codeword to be retransmitted is obtained by performing LDPC encoding on the bits to be retransmitted, and a puncture location set of the check bits of the third LDPC codeword is a proper subset of a puncture location set of the check bits of the second LDPC codeword.

[0261] The transmitting unit 1300 is further configured to transmit a third LDPC codeword.

[0262] Optionally, in the above implementation, the receiving unit 1200 and the transmitting unit 1300 may alternatively be integrated into one transceiver unit or one input / output unit, which has both receiving and transmitting functions, which is not limited herein.

[0263] Optionally, the communication device 1000 may be a transmitting end device, or the communication device 1000 may be a component, module, etc., such as an encoder, that is located within the transmitting end device and has the functionality to implement each method embodiment.

[0264] In an implementation, the communication device 1000 is the transmitting end in the above method embodiments, and may have any function of the transmitting end in the method embodiments. In this case, the processing unit 1100 may be a processor. The receiving unit 1200 and the transmitting unit 1300 may be transceivers. The transceiver may specifically include a receiver and a transmitter. The receiver is configured to perform the receiving function, and the transmitter is configured to perform the transmitting function.

[0265] Optionally, in another implementation, the communication device 1000 may be a circuit system in a transmitting end device. In this case, the processing unit 610 may be a chip, a logic circuit, an integrated circuit, a processing circuit, a system on a chip (SoC) chip, etc. The transceiver unit 620 may be a communication interface, which may be an interface circuit, an input / output interface, etc.

[0266] In an embodiment, the communications apparatus 1000 may be an encoder in a transmitting end device.

[0267] In the above embodiments, the functions of the processing unit 1100 may be realized by hardware, or may be realized by hardware executing corresponding software.

[0268] For example, the processing unit 1100 may include one or more processors configured to read and execute computer programs or instructions stored in memory, such that the device in which the communication apparatus 1000 is installed performs the operations and / or processes performed by the transmitting end in the method embodiments of this application, and the memory is located external to the one or more processors.

[0269] Furthermore, the processing unit 1100 may further include one or more memories, and the one or more processors and the one or more memories are connected by using circuits / wires. The one or more processors read computer programs or instructions stored in the one or more memories, so that the device in which the communication apparatus 1000 is installed performs the operations and / or processes performed by the transmitting end in the method embodiments of this application.

[0270] In another example, the processing unit 1100 may be a processor, and the receiving unit 1200 and the transmitting unit 1300 may be interface circuits. The interface circuit is configured to receive computer code or instructions and transmit the computer code or instructions to the processor. The processor executes the computer code or instructions, thereby causing the device in which the communication apparatus 1000 is installed to perform the operations and / or processes performed by the transmitting end in the method embodiments of this application. Optionally, the receiving unit 1200 and the transmitting unit 1300 may be different interface circuits, or alternatively, may be different functions of the same interface circuit. This is not limited thereto.

[0271] Optionally, the communication device 1000 may correspond to a receiving end in an embodiment of the method.

[0272] In this case, the units of the communication device 1000 have the following functions:

[0273] The receiving unit 1200 is configured to receive a first channel receive sequence.

[0274] The processing unit 1100 zero-pads corresponding positions of the first LLR sequence corresponding to the first channel received sequence based on the priority of the check bits of the mother code of the LDPC code, and decodes the zero-padded first LLR sequence. The corresponding positions of the first LLR sequence are positions of check bits to be punctured in a rate matching process of the LDPC codeword corresponding to the first channel received sequence, and the priority of the check bits is related to the reliability of the check bits, which indicates the degree to which the check bits are affected by noise in the channel transmission process.

[0275] The sending unit 1300 is further configured to send a retransmission request to the sending end if the processing unit 1100 fails to decode the LDPC codeword.

[0276] Optionally, in an embodiment, the check bits to be punctured in the rate matching process of the LDPC code word corresponding to the first channel received sequence are the first L check bits in the check bits of the mother code corresponding to the LDPC code word and sorted in descending order of priority, where L is the number of check bits to be punctured, and L is an integer.

[0277] Optionally, in an embodiment, the check matrix of the mother code includes a check part, the check part includes columns that correspond to check bits and are in the check matrix, and the priority indicates the priority of the columns included in the check part, where each column included in the check part corresponds to z codeword bits of the mother code, z=N / n, N represents the code length of the mother code, n represents the total number of columns included in the check matrix of the mother code, and N and n are integers.

[0278] Optionally, in an embodiment, the length of the mother code is 1944, the code rate is ½, the check portion is the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priority of the 13th column to the 24th column is as follows: 13, 14, 24, 15, 23, 16, 22, 17, 21, 18, 20, 19 It is.

[0279] Optionally, in an embodiment, the length of the mother code is 1296, the code rate is 1 / 2, the check part is from the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priorities of the 13th column to the 24th column is as follows, that is, 13, 17, 22, 18, 24, 16, 23, 19, 14, 21, 15, 20 It is.

[0280] Optionally, in an embodiment, the length of the mother code is 648, the code rate is 1 / 2, the check part is from the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priorities of the 13th column to the 24th column is as follows, that is, 13, 17, 16, 20, 24, 14, 19, 18, 23, 22, 15, 21 It is.

[0281] Optionally, in an embodiment, the priorities of the z codeword bits corresponding to any column included in the check part are the same.

[0282] Optionally, in an embodiment, in the rate matching process of the LDPC codeword corresponding to the first channel reception sequence, the L check bits punctured are in the following cases, that is, When L < z, the L punctured check bits are any L of the z check bits corresponding to the column with the highest priority among the columns included in the check part, or if L>z, the L check bits to be punctured are L check bits out of the tz check bits corresponding to t columns in the check part, where the t columns are the first t columns in the check part sorted in descending order of priority, and the L check bits include z(t-1) check bits corresponding to the first t-1 columns out of the t columns and p check bits in the t column, where p check bits are any p check bits out of the z check bits corresponding to the t column, where both t and p are positive integers, and p≦z; or If L=mz, the L punctured check bits are mz check bits corresponding to the m columns in the check part, where the m columns are the first m columns in the check part sorted in descending order of priority. Satisfy one of the following.

[0283] Optionally, in an embodiment, the sending unit 1300 is further configured to send retransmission instruction information to the sending end.

[0284] The receiving unit 1200 is further configured to receive a second channel receive sequence.

[0285] The processing unit 1100 is further configured to pad with zeros corresponding positions in the second LLR sequence corresponding to the second channel received sequence based on the priority of the check bits of the mother code, and decode a combined sequence of the zero-padded second LLR sequence and the zero-padded first LLR sequence, where the set including the positions that need to be padded with zeros in the second LLR sequence is a proper subset of the set including the positions that need to be padded with zeros in the first LLR sequence.

[0286] In the above implementation, the receiving unit 1200 and the transmitting unit 1300 may alternatively be integrated into one transceiver unit or one input / output unit having both receiving and transmitting functions, which is not limited herein.

[0287] Optionally, the communication device 1000 may be a receiving end, or the communication device 1000 may be a component, module, etc., within the receiving end and having the functionality to implement each method embodiment, such as a decryptor (or decoder).

[0288] In an implementation, the communication device 1000 is the receiving end in the above method embodiments, and may have any function of the receiving end device in the method embodiments. In this case, the processing unit 1100 may be a processor, and the receiving unit 1200 and the transmitting unit 1300 may be transceivers. The transceiver may specifically include a receiver and a transmitter. The receiver is configured to perform the receiving function, and the transmitter is configured to perform the transmitting function.

[0289] In another implementation, the communication device 1000 may be a circuit system at the receiving end. In this case, the processing unit 1100 may be a chip, a logic circuit, an integrated circuit, a processing circuit, an SoC chip, etc. The receiving unit 1200 and the transmitting unit 1300 may be a communication interface. The communication interface may be an interface circuit, an input / output interface, etc. Optionally, the receiving unit 1200 and the transmitting unit 1300 may be different interface circuits or different functions of the same interface circuit. This is not limited thereto.

[0290] In an embodiment, the communication apparatus 1000 may be a decryptor in a receiving end device.

[0291] In the above embodiments, the functions of the processing unit 1100 may be realized by hardware, or may be realized by hardware executing corresponding software.

[0292] For example, processing unit 1100 may include one or more processors configured to read and execute computer programs or instructions stored in memory, such that a device in which communication apparatus 1000 is installed performs the operations and / or processes performed by a receiving end in the method embodiments of this application, and the memory is located external to the one or more processors.

[0293] Furthermore, the processing unit 1100 may further include one or more memories, and the one or more processors and the one or more memories are connected by using circuits / wires. The one or more processors read computer programs or instructions stored in the one or more memories, so that the device in which the communication apparatus 1000 is installed performs the operations and / or processes performed by the receiving end in the method embodiments of this application.

[0294] In another example, the processing unit 1100 is a processor, and the receiving unit 1200 and the transmitting unit 1300 are interface circuits configured to receive computer code or instructions and transmit the computer code or instructions to the processor. The processor executes the computer code or instructions, thereby causing the device in which the communication apparatus 1000 is installed to perform the operations and / or processes performed by the receiving end in the method embodiments of this application.

[0295] 21 is a diagram of the structure of a communication device 10 according to the present application. As shown in FIG. 21, the communication device 10 includes one or more processors 11, one or more memories 12, and one or more communication interfaces 13. The processor 11 is configured to control the communication interfaces 13 to transmit and receive signals. The memory 12 is configured to store computer programs. The processor 11 is configured to call the computer programs from the memory 12 and execute the computer programs, thereby causing the communication device 10 to perform the processing performed by the transmitting end or the receiving end in the method embodiments of the present application.

[0296] In FIG. 21, a dashed box behind a component (eg, a processor, memory, or communication interface) indicates that at least one component may be present.

[0297] Optionally, the memory and processor in the above apparatus embodiments may be physically separate units, or the memory and processor may be integrated together.

[0298] Additionally, this application further provides a computer-readable storage medium that stores computer instructions that, when executed on a computer, perform the operations and / or processes performed by a transmitting end in the rate matching method provided in this application.

[0299] This application further provides a computer-readable storage medium that stores computer instructions that, when executed on a computer, enable the computer to perform the operations and / or processes performed by the receiving end in the decoding method provided in this application.

[0300] This application further provides a computer program product, which includes computer code or instructions, which, when executed on a computer, implements the rate matching method in the method embodiment of this application.

[0301] This application further provides a computer program product, which includes computer code or instructions, which, when executed on a computer, realizes the decoding method in the method embodiment of this application.

[0302] The present application further provides a communications device including a processor and an interface circuit, the interface circuit configured to receive computer code or instructions and transmit the computer code or instructions to the processor, the processor configured to execute the computer code or instructions, thereby performing the operations and / or processes performed by the transmitting end in the rate matching method provided in the present application.

[0303] The application further provides a communication device including a processor and an interface circuit, the interface circuit configured to receive computer code or instructions and transmit the computer code or instructions to the processor, the processor configured to execute the computer code or instructions, thereby performing the operations and / or processes performed by the receiving end in the decoding method provided in the application.

[0304] This application further provides a chip, the chip including one or more processors, the one or more processors configured to execute a computer program stored in a memory to perform the operations and / or processes performed by the transmitting end in any of the method embodiments, the memory being located independently of the chip.

[0305] Furthermore, the chip may further include one or more communication interfaces. The one or more communication interfaces may be input / output interfaces, interface circuits, etc. Furthermore, the chip may further include one or more memories.

[0306] This application further provides a chip, the chip including one or more processors, the one or more processors configured to execute a computer program stored in a memory to perform the operations and / or processes performed by the receiving end device in any of the method embodiments, the memory being located independently of the chip.

[0307] Furthermore, the chip may further include one or more communication interfaces. The one or more communication interfaces may be input / output interfaces, interface circuits, etc. Furthermore, the chip may further include one or more memories.

[0308] This application further provides a wireless communication system including a transmitting end and a receiving end in an embodiment of this application.

[0309] Optionally, one of the transmitting end and the receiving end is a network device (eg, a base station), and the other is a terminal device.

[0310] The processor in the embodiments of this application may be an integrated circuit chip and have signal processing capabilities. In the implementation process, the steps in the above method embodiments are realized by using hardware integrated logic circuits in the processor or by using instructions in the form of software. The processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The general-purpose processor may be a microprocessor, or the processor may be any conventional processor, etc. The steps of the method disclosed in the embodiments of this application may be directly presented as being performed and completed by a hardware encoding processor, or may be performed and completed by a combination of hardware modules and software modules in the encoding processor. The software modules may be located in storage media established in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps in the above method in combination with the processor's hardware.

[0311] The memory in the embodiments of this application may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which is used as an external cache. Many types of RAM are available, such as, by way of example and not limitation, static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchlink dynamic random access memory (synchlink DRAM, SLDRAM), and direct Rambus random access memory (direct Rambus RAM, DRRAM). It should be noted that memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0312] As used herein, terms such as "unit" and "system" refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software being executed. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. As illustrated through the use of figures, both computing devices and applications running on computing devices may be components. One or more components may reside within a process and / or thread of execution. Components may be located on one computer and / or distributed between two or more computers. Furthermore, these components may execute from various computer-readable media that store various data structures. Components may communicate using local and / or remote processes based on signals that comprise one or more data packets (e.g., data from two components interacting with other components in a local system, a distributed system, and / or data between networks such as the Internet that interact with other systems using signals).

[0313] Those skilled in the art may recognize that, in combination with the examples described in the embodiments disclosed in this specification, the units and algorithm steps may be realized by electronic hardware, or a combination of computer software and electronic hardware. Whether a function is performed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to realize the described functions for each specific application, but the implementation method should not be considered to go beyond the scope of this application.

[0314] Those skilled in the art can clearly understand that for the purpose of convenient and concise description, the detailed operation processes of the above systems, devices and units may be referred to the corresponding processes in the above method embodiments, and the details will not be described again in this specification.

[0315] In some embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the described device embodiments are merely examples. For example, the division into units is merely a logical division of function, and other divisions may be used in actual implementations. For example, multiple units or components may be combined or integrated into other systems, or some features may be omitted or not implemented. Furthermore, the shown or discussed mutual couplings or direct couplings or communication connections may be realized through some interfaces. Indirect couplings or communication connections between devices or units may be realized in electrical, mechanical, or other forms.

[0316] The units described as separate parts may or may not be physically separate, and the parts shown as units may or may not be physical units, and may be located in one place or distributed across multiple network units. Some or all of the units may be selected based on actual requirements to achieve the objectives of the solutions of the embodiments.

[0317] Furthermore, the functional units in the embodiments of this application may be integrated into one processing unit, each of the units may exist physically alone, or two or more units may be integrated into one unit.

[0318] When a function is realized in the form of a software functional unit and sold or used as an independent product, the function may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application may essentially, or a portion of the technical solution or a portion of the technical solution may be realized in the form of a software product. A computer software product is stored in a storage medium and includes some instructions for instructing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method described in the embodiments of this application. The above storage medium includes any medium capable of storing program code, such as a USB flash drive, a removable hard disk, a read-only memory, a random-access memory, a magnetic disk, or an optical disk.

[0319] The above description is merely a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any variations or replacements that can be easily conceived by those skilled in the art within the technical scope disclosed in this application shall fall within the scope of protection of this application. Therefore, the scope of protection of this application shall be subject to the scope of protection of the claims.

Claims

1. 1. A rate matching method, comprising: a transmitting end performing rate matching on a first LDPC code word having a first code rate based on priorities of check bits of a mother code of a low-density parity-check (LDPC) code to obtain a second LDPC code word having a second code rate, the priorities indicating priorities for puncturing the check bits of the mother code during rate matching, the priorities relating to the reliability of the check bits, and the reliability of the check bits indicating the degree to which the check bits are affected by noise in a channel transmission process; transmitting the second LDPC codeword by the transmitting end; A method comprising:

2. The transmitting end performs rate matching on a first LDPC code word having a first code rate according to the priority of check bits of a mother code; 2. The method of claim 1, comprising: selecting, by the transmitting end, L check bits in the first LDPC codeword for puncturing based on a number L of bits to be punctured and the priorities of the check bits of the mother code, wherein the priorities are in descending order of the reliability of the check bits, and the L check bits are first L check bits in the priorities, where L≧1 and L is an integer.

3. 3. The method according to claim 1, wherein the check matrix of the mother code includes a check portion, the check portion including columns corresponding to check bits and present in the check matrix, the priority indicating a priority of the columns included in the check portion, each of the columns included in the check portion corresponding to z check bits of the mother code, z=N / n, N is a code length of the mother code, and n represents a total number of columns included in the check matrix of the mother code.

4. The code length of the mother code is 1944, the code rate is 1 / 2, the check portion is the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priority of the 13th column to the 24th column is as follows: 13,14,24,15,23,16,22,17,21,18,20,19 The method of claim 3, wherein

5. The code length of the mother code is 1296, the code rate is 1 / 2, the check part is from the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priorities of the 13th column to the 24th column is as follows, that is, 13,17,22,18,24,16,23,19,14,21,15,20 The method according to claim 3, which is as described above.

6. The code length of the mother code is 648, the code rate is 1 / 2, the check part is from the 13th column to the 24th column in the check matrix of the mother code, and the descending order of priorities of the 13th column to the 24th column is as follows, that is, 13,17,16,20,24,14,19,18,23,22,15,21 The method according to claim 3, which is as described above.

7. The method according to any one of claims 4 to 6, wherein the priorities of the z check bits corresponding to any column included in the check part are the same.

8. The L check bits in the first LDPC codeword are as follows, that is, When L < z, the L check bits in the first LDPC codeword are L of the z check bits corresponding to the column with the highest priority among the columns included in the check part, where z is a positive integer, or When L > z, the L check bits in the first LDPC codeword are L of the tz check bits corresponding to t columns among the columns included in the check part, the t columns are the first t columns among the columns included in the check part sorted in descending order of priority, the L check bits include z(t - 1) check bits corresponding to the first t - 1 columns among the t columns and p check bits in the tth column, the p check bits are any p of the z check bits corresponding to the tth column, and both t and p are positive integers and p ≤ z, or When L = mz, the L check bits in the first LDPC codeword are mz check bits corresponding to m columns among the columns included in the check part, the m columns are the first m columns among the columns included in the check part sorted in descending order of priority, m ≥ 1, and m is an integer The method according to claim 7, which satisfies one of the above.

9. After the second LDPC codeword is transmitted by the transmitting end, the method includes The step of receiving retransmission instruction information by the transmitting end, performing rate matching on the codeword to be retransmitted based on the priority of the check bits of the mother code, by the transmitting end, to obtain a third LDPC codeword having a third code rate, the codeword to be retransmitted being obtained by performing LDPC encoding on the bits to be retransmitted, and a puncture position set of the check bits of the third LDPC codeword being a proper subset of a puncture position set of the check bits of the second LDPC codeword; transmitting the third LDPC codeword by the transmitting end; The method of claim 8 further comprising:

10. A communication device, a processing unit configured to perform rate matching on a first LDPC code word having a first code rate to obtain a second LDPC code word having a second code rate based on priorities of check bits of a mother code of a low-density parity-check (LDPC) code, the priorities indicating priorities for puncturing the check bits of the mother code during rate matching, the priorities being related to reliability of the check bits, and the reliability of the check bits indicating a degree to which the check bits are affected by noise in a channel transmission process; a transceiver unit configured to transmit the second LDPC codeword; A communication device comprising:

11. The processing unit 11. The communication device of claim 10, wherein the communication device is specifically configured to select L check bits in the first LDPC codeword for puncturing based on a number L of bits to be punctured and the priorities of the check bits of the mother code, the priorities being in descending order of the reliability of the check bits, and the L check bits are first L check bits in the priorities, where L≧1 and L is an integer.

12. The check matrix of the mother code includes a check part, the check part includes columns corresponding to check bits and existing in the check matrix, the priority indicates the priority of the columns included in the check part, each of the columns included in the check part corresponds to z check bits of the mother code, z = N / n, N is the code length of the mother code, and n represents the total number of columns included in the check matrix of the mother code. The communication device according to claim 10 or 11.

13. The code length of the mother code is 1944, the code rate is 1 / 2, the check part is the 13th column to the 24th column in the check matrix of the mother code, and the descending order of the priorities of the 13th column to the 24th column is as follows, that is, 13,14,24,15,23,16,22,17,21,18,20,19 The communication device according to claim 12.

14. The code length of the mother code is 1296, the code rate is 1 / 2, the check part is the 13th column to the 24th column in the check matrix of the mother code, and the descending order of the priorities of the 13th column to the 24th column is as follows, that is, 13,17,22,18,24,16,23,19,14,21,15,20 The communication device according to claim 12.

15. The code length of the mother code is 648, the code rate is 1 / 2, the check part is the 13th column to the 24th column in the check matrix of the mother code, and the descending order of the priorities of the 13th column to the 24th column is as follows, that is, 13,17,16,20,24,14,19,18,23,22,15,21 The communication device according to claim 12.

16. The priorities of the z check bits corresponding to any column included in the check part are the same. The communication device according to any one of claims 13 to 15.

17. The L check bits in the first LDPC codeword are as follows, that is, When L < z, the L check bits in the first LDPC codeword are L of the z check bits corresponding to the column with the highest priority among the columns included in the check part, z is a positive integer, or if L>z, the L check bits in the first LDPC codeword are L check bits among tz check bits corresponding to t columns of the columns included in the check portion, the t columns being the first t columns of the columns included in the check portion sorted in descending order of priority, the L check bits include z(t-1) check bits corresponding to the first t-1 columns of the t columns and p check bits in the t-th column, the p check bits being any p check bits among z check bits corresponding to the t-th column, where both t and p are positive integers, and p≦z; or If L=mz, the L check bits in the first LDPC codeword are mz check bits corresponding to m columns included in the check portion, the m columns being the first m columns of the columns included in the check portion sorted in descending order of priority, m≧1, and m is an integer. The communication device according to claim 16, wherein one of the following is satisfied:

18. the transceiver unit is further configured to receive retransmission instruction information; the processing unit is further configured to perform rate matching on the codeword to be retransmitted based on the priority of the check bits of the mother code to obtain a third LDPC codeword having a third code rate, the codeword to be retransmitted being obtained by performing LDPC encoding on the bits to be retransmitted, and a puncture position set of check bits of the third LDPC codeword is a proper subset of a puncture position set of check bits of the second LDPC codeword; 20. The communications device of claim 17, wherein the transceiver unit is further configured to transmit the third LDPC codeword.

19. A communication device including a processor and an interface circuit, 10. A communication device, wherein the interface circuit is configured to receive computer code or instructions and transmit the computer code or instructions to the processor, such that when the processor executes the computer code or instructions, the method of any one of claims 1 to 9 is implemented.

20. 1. A communications device including at least one processor, 10. A communication device, wherein the at least one processor is coupled to at least one memory, the at least one processor being configured to execute computer programs or instructions stored in the at least one memory to enable the communication device to perform the method of any one of claims 1 to 9.

21. 1. A computer-readable storage medium, comprising: A computer-readable storage medium storing computer instructions that, when executed on a computer, implement the method of any one of claims 1 to 9.

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