Semiconductor chip package and manufacturing method thereof

Abstract

The present invention relates to a semiconductor chip package and a manufacturing method thereof, the semiconductor chip package including a lead frame having a first side and a second side opposite to each other, the lead frame having a first groove recessed from the first side, an adhesive filled in the first groove, and a semiconductor chip mounted on the first side of the lead frame and the adhesive, wherein the width of the first groove is not greater than the width of the semiconductor chip.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor chip package and a method for manufacturing the same, and more particularly to a semiconductor chip package having a lead frame. [Background technology]

[0002] A semiconductor chip can be attached to the chip pad of a lead frame with adhesive and electrically connected to the lead contact of the lead frame with conductive wires. A mold compound is then formed to encapsulate the power chip and lead frame. As packaging structures become smaller, the chip pad area shrinks and the edge distance from the power chip to the chip pad also shortens, which can lead to adhesive overflow. Furthermore, lead frames are typically thin and have precise patterns, which can lead to damage or deformation due to mechanical or thermal stress during the manufacturing process. One of the goals of the present invention is to prevent adhesive overflow and improve the stability of the lead frame, thereby increasing the manufacturing yield. Summary of the Invention

[0003] An embodiment of the present disclosure relates to a semiconductor chip package, including a lead frame having a first side and a second side opposite each other, the lead frame having a first groove recessed from the first side, an adhesive filled in the first groove, and a semiconductor chip mounted on the first side of the lead frame and the adhesive, wherein the width of the first groove is not greater than the width of the semiconductor chip.

[0004] An embodiment of the present disclosure relates to a semiconductor chip package, including a lead frame having a first side and a second side opposite each other, the lead frame having a first groove recessed from the first side, an adhesive filled in the first groove, a semiconductor chip mounted on the first side of the lead frame and the adhesive, and a carrier mounted on the second side of the lead frame.

[0005] An embodiment of the present disclosure relates to a method for manufacturing a semiconductor chip package, the method including: obtaining a lead frame having a first side and a second side opposite each other, the lead frame having a first groove recessed in the first side of the lead frame; filling the first groove with adhesive; and placing a semiconductor chip on the first side of the lead frame and the adhesive, wherein the width of the first groove is no greater than the width of the semiconductor chip.

[0006] Some exemplary embodiments of the present disclosure can be best understood by reading the following detailed description in conjunction with the drawings, in which: It should be noted that the various features may not be drawn to scale, and in fact the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 1A shows a perspective view of a portion of a semiconductor chip package according to some embodiments of the present subject matter. [Figure 1B] FIG. 1B illustrates a perspective view of a portion of a semiconductor chip package according to some embodiments of the present subject matter. [Figure 1C] FIG. 1C illustrates a cross-sectional view of a semiconductor chip package according to some embodiments of the present subject matter. [Figure 2A] FIG. 2A illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 2B] FIG. 2B illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 3A-1] FIG. 3A-1 illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 3A-2] 3A-2 illustrate one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 3B] FIG. 3B illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 3C] FIG. 3C illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 3D-1] FIG. 3D-1 illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 3D-2] FIG. 3D-2 illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 3E-1] FIG. 3E-1 illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 3E-2] FIG. 3E-2 illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 3F] FIG. 3F illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 3G] FIG. 3G illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 3H] FIG. 3H illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. [Figure 4A]FIG. 4A shows a perspective view of a portion of a semiconductor chip package according to some embodiments of the present subject matter. [Figure 4B] FIG. 4B illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present subject matter. DETAILED DESCRIPTION OF THE INVENTION

[0008]

[0013] The same or similar parts are designated with like reference numerals in the drawings and detailed description.

[0014] Certain embodiments of the present disclosure can be more readily understood from the following detailed description and drawings.

[0009] The following disclosure provides many different embodiments or examples for implementing various features of the provided targets. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, a reference to forming a first feature above or on a second feature can include embodiments in which the first and second features form direct contact, and can also include embodiments in which a separate feature is formed between the first and second features, where the first and second features do not necessarily form direct contact. Also, in this disclosure, drawing numbers and / or letters may be duplicated within each example. This duplication is done for simplicity and clarity and does not, in itself, indicate a relationship between each of the embodiments and / or arrangements discussed.

[0010] Although the following detailed discussion of exemplary embodiments of the present disclosure provides numerous application concepts that can be embodied in a variety of specific environments, it should be understood that the specific embodiments discussed are illustrative and are not intended to limit the scope of the present disclosure.

[0011] The present disclosure provides a semiconductor chip package and a method for manufacturing the same.

[0012] In the semiconductor chip package disclosed herein, a semiconductor chip is attached to a chip pad of a lead frame with an adhesive and electrically connected to the lead contact of the lead frame via a conductive member (such as a conductor wire or copper strip). The adhesive is filled into the grooves of the chip pad, preventing overflow of the adhesive and improving the stability of the lead frame, thereby increasing the yield of the manufacturing process. Furthermore, the semiconductor chip package disclosed herein uses a jig to fix the lead frame on the carrier during the manufacturing process, thereby preventing warping of the lead frame. The portion of the carrier that supports the chip pad is made of a material with a relatively high thermal conductivity to enhance the thermal conductivity of the semiconductor chip package.

[0013] FIG. 1A shows a perspective view of a portion of a semiconductor chip package 1a according to some embodiments of the present invention.

[0014] The semiconductor chip package 1a may include a carrier 20, a lead frame 10, and a semiconductor chip 11. The carrier 20, the lead frame 10, and the semiconductor chip 11 may be stacked one-sidedly. The semiconductor chip 11 and the carrier 20 may be mounted on opposite sides of the lead frame 10.

[0015] The carrier 20 may include a portion 11ac (also referred to as a first portion) having a relatively high thermal conductivity and portions 11gm, 11sm, and 11dm (also referred to as first portions) having a relatively low thermal conductivity. The portions 11ac, 11gm, 11sm, and 11dm may be substantially separated. The portions 11ac, 11gm, 11sm, and 11dm may not be in direct contact with each other. The portions 11ac, 11gm, 11sm, and 11dm may be separated from each other by an insulating layer (e.g., insulating layer 30 in FIG. 1C).

[0016] The portion 11ac can overlap the semiconductor chip 11. For example, the portion 11ac, a part of the lead frame 10 (e.g., the chip pad 11a), and the semiconductor chip 11 can be stacked in one direction. The portions 11gm, 11sm, and 11dm do not need to overlap the semiconductor chip 11.

[0017] The sizes (e.g., width, thickness, area, etc.) of portions 11ac, 11gm, 11sm, and 11dm may be the same as or different from one another. The width of portion 11ac may be larger than that of portion 11gm, portion 11sm, or portion 11dm. Furthermore, the thicknesses of portions 11ac, 11gm, portion 11sm, and portion 11dm may be the same as one another.

[0018] Portion 11ac may include a ceramic material, such as an oxide (such as beryllium oxide (BeO) or alumina (Al2O3)), a nitride (such as aluminum nitride (AlN) or silicon nitride (Si3N4)), a boride (such as boron nitride (BN)), a carbide (such as silicon carbide (SiC)), another ceramic material (such as diamond (C)), or a combination of two or more thereof. Portion 11ac has a thermal conductivity of 100 Wm -1 K -1 Higher or 150Wm -1 K -1 Higher or 200Wm -1 K -1 For example, portion 11ac may include aluminum nitride (AlN), which has a thermal conductivity of 170 Wm -1 K -1 ~230Wm -1 K -1 It may be between.

[0019] The portion 11ac can be configured to conduct heat from the semiconductor chip 11 to the outside through a portion (e.g., chip pad 11a) of the lead frame 10. Using the portion 11ac with relatively high thermal conductivity can increase thermal conductivity by at least 10% compared to an exemplary embodiment that does not use a material with relatively high thermal conductivity, thereby achieving the effect of reducing the resistance value of the device.

[0020] Portion 11gm, portion 11sm, and portion 11dm can include a metallic material, including a conductive material such as a metal, a metal alloy, or a metal silicide. Illustrative conductive materials can include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), or other metals or alloys, or a combination of two or more thereof.

[0021] Portions 11gm, 11sm, and 11dm can be configured as external terminals to provide electrical connection between semiconductor chip package 1a and an external device (e.g., a printed circuit board (PCB), other packages, or other electronic components).

[0022] In some embodiments, portion 11ac can include a metallic material such as those listed for portions 11gm, 11sm, and 11dm.

[0023] The lead frame 10 may include chip pads 11a, gate lead contacts 11g, source lead contacts 11s, and drain lead contacts 11d. The chip pads 11a, gate lead contacts 11g, source lead contacts 11s, and drain lead contacts 11d may be substantially separable. The chip pads 11a, gate lead contacts 11g, source lead contacts 11s, and drain lead contacts 11d may not be in direct contact with each other. The chip pads 11a, gate lead contacts 11g, source lead contacts 11s, and drain lead contacts 11d may be separated from each other by an encapsulant (e.g., encapsulant 14 in FIG. 1C).

[0024] The chip pad 11a, gate lead contact 11g, source lead contact 11s, and drain lead contact 11d may have the same or different sizes (e.g., width, thickness, area, etc.). The width of the chip pad 11a may be larger than the width of the gate lead contact 11g, source lead contact 11s, or drain lead contact 11d. Furthermore, the thicknesses of the chip pad 11a, gate lead contact 11g, source lead contact 11s, and drain lead contact 11d may be the same.

[0025] The lead frame 10 may include a metallic material, including a conductive material such as a metal or metal alloy, such as gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metals or alloys, or a combination of two or more thereof.

[0026] The chip pads 11a can be configured to support the semiconductor chip 11. For example, the semiconductor chip 11 can be placed on the chip pads 11a. The gate lead contacts 11g, the source lead contacts 11s, and the drain lead contacts 11d can be configured to couple (or electrically connect) with electrical terminals of the semiconductor chip 11. The gate lead contacts 11g, the source lead contacts 11s, and the drain lead contacts 11d can be configured to couple (or electrically connect) the electrical terminals of the semiconductor chip 11 to external terminals (e.g., portions 11gm, 11sm, and 11dm of the carrier 20).

[0027] Referring to FIG. 1B, FIG. 1B illustrates the lead frame 10 of the semiconductor chip package 1a of FIG. 1A.

[0028] The lead frame 10 may have a surface (or first surface, first side) 101 and a surface (or second surface, second side) 102 facing each other. The chip pad 11a of the lead frame 10 may have a groove (or first groove) 11ar recessed from the surface 101. The gate lead contact 11g and the source lead contact 11s of the lead frame 10 may have grooves (or second grooves) 11gr and 11sr recessed from the surface 102. Although the groove 11ar in FIG. 1B is square or rectangular, the present disclosure is not limited thereto. In some embodiments, the top view of the groove 11ar may be rectangular, circular, hexagonal, or any other shape. In some embodiments, the groove 11ar can be adapted to various packages by adjusting the position, shape, occupied area ratio, quantity, etc. of the groove 11ar.

[0029] The adhesive 13 may be filled into the recessed grooves 11ar of the chip pads 11a of the lead frame 10. The adhesive 13 may have a surface 131 that is substantially coplanar with the surface 101 of the lead frame 10. The adhesive 13 may include a conductive adhesive, a conductive epoxy resin, and / or a solder.

[0030] Referring back to FIG. 1A, when the semiconductor chip 11 is supported on the chip pad 11a, the adhesive 13 in FIG. 1B is completely covered by the semiconductor chip 11, which prevents the adhesive 13 from spilling out and improves the stability of the lead frame 10, thereby improving the yield of the manufacturing process.

[0031] The semiconductor chip 11 may include circuit components such as transistors, resistors, capacitors, and interconnect structures to form an integrated circuit (IC). In some embodiments, the semiconductor chip 11 may include a metal-oxide-semiconductor field-effect transistor (MOSFET), such as an NMOS, PMOS, or CMOS, a voltage feedback device, and / or a switch. In some embodiments, the semiconductor chip 11 may include a double-diffused MOSFET (DMOSFET), an insulated-gate bipolar transistor (IGBT), a junction gate field-effect transistor (JFET), a power bipolar transistor, or a power diode (e.g., a power Schottky diode).

[0032] The semiconductor chip 11 may have a surface 111 and a surface 112 opposite to the surface 111. The surface 112 may be in contact (e.g., direct contact) with an adhesive (e.g., adhesive 13 in FIG. 1B ). The surface 112 may be in contact (e.g., direct contact) with a surface of the lead frame 10 (e.g., surface 101 in FIG. 1B ) and may conduct heat to the portion 11ac of the carrier 20.

[0033] One or more electrical terminals may be exposed from surface 111 and / or surface 112 of semiconductor chip 11. For example, the gate G and source S of semiconductor chip 11 may be located on the same side of semiconductor chip 11, and the drain D may be located on the opposite side. The gate G and source S of semiconductor chip 11 may be located on surface 111, and the drain D may be located on surface 112.

[0034] The gate G of the semiconductor chip 11 can be coupled (or electrically connected) to a gate lead contact 11g of the lead frame 10 by a conductive wire 11gw. The gate lead contact 11g can be configured to couple (or electrically connect) the gate G of the semiconductor chip 11 to an external terminal (e.g., portion 11gm of the carrier 20).

[0035] The source S of the semiconductor chip 11 may be coupled (or electrically connected) to a source lead contact 11s of the lead frame 10 by a conductive wire 11sw. The source lead contact 11s may be configured to couple (or electrically connect) the source S of the semiconductor chip 11 to an external terminal (e.g., a portion 11sm of the carrier 20).

[0036] The drain D of the semiconductor chip 11 can be bonded (or electrically connected) to the adhesive 13. The drain D of the semiconductor chip 11 can be bonded (or electrically connected) to a drain lead contact 11d of the lead frame 10 via the adhesive 13, the chip pad 11a, and the conductive wire 11dw. The drain lead contact 11d can be configured to bond (or electrically connect) the drain D of the semiconductor chip 11 to an external terminal (e.g., the portion 11dm of the carrier 20).

[0037] In some embodiments, the conductors 11gw, 11sw and 11dw may be replaced by copper strips or pieces, and the electrical terminals of the semiconductor chip 11 may be connected to the lead frame 10 by a copper clip bonding method.

[0038] In some embodiments, a non-conductive ceramic material can be used for portion 11ac to improve thermal conductivity. Because chip pad 11a is carried on portion 11ac and portion 11ac does not need to conduct electricity, the drain D of semiconductor chip 11 must be coupled (or electrically connected) to an external terminal (e.g., portion 11dm of carrier 20) by conductive wire 11dw and drain lead contact 11d. In some embodiments, a conductive metallic material can be used for portion 11ac to provide an optimal conductive path to drain D.

[0039] 1C shows a cross-sectional view of a semiconductor chip package 1a according to some embodiments of the present disclosure. In some embodiments, the cross-sectional view of FIG. 1C is taken along section line AA' of the semiconductor chip package 1a in FIG. 1A. Identical or similar elements are designated by the same reference numerals, and detailed descriptions of identical or similar elements will not be repeated.

[0040] In addition to the carrier 20, the lead frame 10, and the semiconductor chip 11, the semiconductor chip package 1a may further include an encapsulant 14 and an insulating layer 30. To clearly show the relationship between the components, the encapsulant 14 and the insulating layer 30 are omitted from the perspective view of FIG. 1A. In the cross-sectional view of FIG. 1C, portions 11gm and 11sm of the carrier 20 and the gate lead contact 11g and source lead contact 11s of the lead frame 10 are omitted.

[0041] The insulating layer 30 can be filled in the carrier 20. For example, the insulating layer 30 can be filled between any two of the portions 11ac, 11gm, 11sm, and 11dm of the carrier 20. The insulating layer 30 can be in contact with a portion of the encapsulant 14.

[0042] The encapsulant 14 may contact, cover, or coat the semiconductor chip 11. Referring to FIG. 1B , the encapsulant 14 may contact, cover, or coat the chip pads 11a, gate lead contacts 11g, source lead contacts 11s, and drain lead contacts 11d of the lead frame 10. The encapsulant 14 may contact, cover, or coat the surface 101 of the lead frame 10. The encapsulant 14 does not need to contact the adhesive 13. By filling the grooves 11gr and 11sr with the encapsulant 14, the structural stability of the lead frame 10 can be improved.

[0043] The insulating layer 30 and the encapsulant 14 may each comprise an insulating or dielectric material. Examples of insulating materials include filled epoxy resins, molding compounds, polyimides, phenolic compounds, silicon-containing materials, or combinations thereof. Examples of dielectric materials include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiNO), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), undoped silicon glass (USG), fluorosilicate glass (FSG), spin-on glass (SOG), any combination of two or more thereof, and the like. The insulating layer 30 and the encapsulant 14 may comprise the same material. Alternatively, the insulating layer 30 and the encapsulant 14 may comprise different materials.

[0044] In some embodiments, the insulating layer 30 may use a ceramic material to reduce the coefficient of thermal expansion (CTE) and improve thermal conductivity between the carrier 20 (which may include a metallic material) and the encapsulant 14 (which may include an insulating material).

[0045] As described above, the adhesive 13 can be filled into the grooves 11ar of the chip pads 11a of the lead frame 10 to completely cover the semiconductor chip 11. The width w1 of the adhesive 13 or the grooves 11ar does not need to be greater than the width w2 of the semiconductor chip 11. The width w1 of the adhesive 13 or the grooves 11ar may be approximately equal to the width w2 of the semiconductor chip 11. The width w1 of the adhesive 13 or the grooves 11ar may be less than the width w2 of the semiconductor chip 11.

[0046] 2A and 2B illustrate one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present disclosure. In some embodiments, the cross-sectional view of FIG. 2B is a cross-sectional view of the structure of FIG. 2A taken along section line BB'. At least some of these drawings have been simplified to better understand aspects of the present disclosure.

[0047] 2A, the manufacturing method includes obtaining a lead frame 10 and fixing the lead frame 10 on a carrier 20 using a jig 21. The lead frame 10 is sandwiched between the jig 21 and the carrier 20. The jig 21 and the carrier 20 are installed on opposite sides of the lead frame 10. The jig 21 and the lead frame 10 may collectively define a plurality of through holes 21h. Fixing pins 21p may pass through the through holes 21h to fix the jig 21 and the lead frame 10 on the carrier 20.

[0048] The jig 21 may have two openings for exposing the device area of ​​the lead frame 10. By adjusting the position, shape, occupied area ratio, number, etc. of the openings, it can be applied to various packages, and is not limited to the form shown in FIG.

[0049] The lead frame 10 may have a device area exposed from the jig 21 and an edge area where the through-holes 21h are provided. The edge area surrounds the periphery of the device area. The device area includes multiple units, one of which can be separated from the other units by a single cut. The semiconductor chip package 1a in FIGS. 1A, 1B, and 1C may include one unit. The lead frame area 3a in FIG. 3A-1 may include two units.

[0050] 2B , carrier 20 can include a portion (also referred to as a first portion) 20c having a relatively high thermal conductivity and a portion (also referred to as a second portion) 20m having a relatively low thermal conductivity. Portion 20c can include a ceramic material, such as those listed above for portion 11ac. Portion 20m can include a metallic material, such as those listed above for portions 11gm, 11sm, and 11dm. Portions 20c can be spaced apart within portion 20m. In some embodiments, the locations of portions 20c can correspond to chip pads used to support semiconductor chips within leadframe 10.

[0051] 3A-1, 3A-2, 3B, 3C, 3D-1, 3D-2, 3E-1, 3E-2, 3F, 3G, and 3H illustrate one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present disclosure. At least some of these figures have been simplified to better understand aspects of the present disclosure. For simplicity, the following figures illustrate the manufacturing process on leadframe area 3a of leadframe 10, which may include two units. The manufacturing process for other areas of leadframe 10 is similar.

[0052] 3A-1 and 3A-2, in some embodiments, the cross-sectional view of FIG. 3A-2 is a cross-sectional view of the lead frame area 3a of the lead frame 10 of FIG. 3A-1 along the cutting line CC'. The manufacturing method includes obtaining a lead frame 10. The lead frame 10 before single cutting may include interconnected chip pads 11a and 12a, gate lead contacts 11g and 12g, source lead contacts 11s and 12s, and drain lead contacts 11d and 12d. The chip pad 12a may be configured to carry another semiconductor chip (e.g., the semiconductor chip 12 of FIG. 3D-1). The gate lead contact 12g, the source lead contact 12s, and the drain lead contact 12d may be configured to couple (or electrically connect) with electrical terminals of the other semiconductor chip. The gate lead contact 12g, the source lead contact 12s, and the drain lead contact 12d can be configured to couple (or electrically connect) the electrical terminal of the aforementioned separate semiconductor chip to an external terminal (e.g., portion 12gm and portion 12sm of carrier 20 in FIG. 3G), respectively. As shown in FIG. 3A-2, the chip pad 11a of the lead frame 10 can have a recessed groove 11ar recessed from the surface 101. The gate lead contact 12g and the source lead contact 12s of the lead frame 10 can have recessed grooves 12gr and 12sr recessed from the surface 102.

[0053] 3B , the manufacturing method includes placing a carrier 20 on a surface 102 of a lead frame 10. A position of a portion 20c of the carrier 20 may correspond to a chip pad 11a of the lead frame 10. In some embodiments, the manufacturing method may include inserting a fixing pin (e.g., fixing pin 21p in FIG. 2A ) into a through-hole (e.g., through-hole 21h in FIG. 2A ) of the lead frame 10. In some embodiments, the manufacturing method may include fixing the lead frame 10 on the carrier 20 using a jig (e.g., jig 21 in FIG. 2A ).

[0054] 3C, the manufacturing method includes filling the groove 11ar with adhesive 13. In some embodiments, the adhesive 13 can be formed by screen printing or spot bonding. The adhesive 13 can have a surface 131 that is approximately coplanar with the surface 101 of the lead frame 10.

[0055] 3D-1 and 3D-2, in some embodiments, the cross-sectional view of FIG. 3D-2 is a cross-sectional view of the leadframe area 3a of the leadframe 10 of FIG. 3D-1 along the cutting line DD'. The manufacturing method includes placing a semiconductor chip 11 on the surface 101 of the leadframe 10 and the adhesive 13. In some embodiments, the manufacturing method may further include placing a semiconductor chip 12. The gate G and source S of the semiconductor chip 12 may be located on the same side of the semiconductor chip 12, and the drain D may be located on the opposite side. A detailed description of the semiconductor chip 12 can be found by referring to the semiconductor chip 11, and will not be repeated here. As shown in FIG. 3D-2, the adhesive 13 is completely covered by the semiconductor chip 11. The width w1 of the adhesive 13 or the groove 11ar may not exceed the width w2 of the semiconductor chip 11. The width w1 of the adhesive 13 or the groove 11ar may be approximately equal to the width w2 of the semiconductor chip 11. The width w1 of the adhesive 13 or the groove 11ar may be smaller than the width w2 of the semiconductor chip 11.

[0056] 3E-1 and 3E-2, in some embodiments, the cross-sectional view of FIG. 3E-2 is a cross-sectional view of the lead frame area 3a of the lead frame 10 of FIG. 3E-1 along the section line EE'. The manufacturing method includes forming conductive wires to bond (or electrically connect) electrical terminals of the semiconductor chip 11. For example, the gate G of the semiconductor chip 11 is bonded (or electrically connected) to the gate lead contact 11g of the lead frame 10 via a conductive wire 11gw. The source S of the semiconductor chip 11 is bonded (or electrically connected) to the source lead contact 11s of the lead frame 10 via a conductive wire 11sw. The drain D of the semiconductor chip 11 is bonded (or electrically connected) to the drain lead contact 11d of the lead frame 10 via the adhesive 13, the chip pad 11a, and the conductive wire 11dw.

[0057] In some embodiments, the manufacturing method may further include forming conductive wires to bond (or electrically connect) electrical terminals of the semiconductor chip 12. For example, the gate G of the semiconductor chip 12 is bonded (or electrically connected) to the gate lead contact 12g of the lead frame 10 via a conductive wire 12gw. The source S of the semiconductor chip 12 is bonded (or electrically connected) to the source lead contact 12s of the lead frame 10 via a conductive wire 12sw. The drain D of the semiconductor chip 12 is bonded (or electrically connected) to the drain lead contact 12d of the lead frame 10 via an adhesive, a chip pad 12a, and a conductive wire 12dw.

[0058] 3F, the manufacturing process includes covering the lead frame 10, the semiconductor chip 11, and other semiconductor chips (e.g., the semiconductor chip 12 in FIG. 3E-1) with an encapsulant 14. The encapsulant 14 can be filled into grooves recessed from the surface 102, such as the grooves 12gr and 12sr in FIG. 3A-2 and the grooves 11gr and 11sr in FIG. 1A. In some embodiments, the encapsulant 14 can be formed by, for example, printing, compression molding, transfer molding, liquid encapsulation, vacuum lamination, spin coating, or other suitable process.

[0059] Referring to FIG. 3G, the manufacturing method includes removing a portion of carrier 20 to form groove 20r. In some embodiments, the manufacturing method includes removing a portion of carrier 20 with a relatively low thermal conductivity (or a metal portion, e.g., portion 20m in FIG. 3B ) to prevent a portion of carrier 20 with a relatively high thermal conductivity (or a ceramic portion, e.g., portion 20c in FIG. 3B ) from contacting the portion with a relatively low thermal conductivity. As shown in FIG. 3G, the portion with a relatively high thermal conductivity (or a ceramic portion, e.g., portion 20c in FIG. 3B ) is separated from the rest of carrier 20 to form portion 11ac. In some embodiments, portion 11ac may have a width approximately equal to the width of chip pad 11a.

[0060] The portions with relatively low thermal conductivity (or metal portions, for example, portion 20m in FIG. 3B) are separated from one another to form portions 11dm, 12gm, and 12sm. Portions 11dm and 11ac are part of semiconductor chip package 1a in FIG. 1A. Portions 12gm and 12sm are part of the package of another semiconductor chip (such as semiconductor chip 12 in FIG. 3E-1).

[0061] In some embodiments, the groove 20r can be formed by a laser drilling process. In some embodiments, the groove 20r can expose a portion of the encapsulant 14. In some embodiments, the groove 20r can have a substantially constant width. In some embodiments, the groove 20r can have a different slope, gradually widening toward the encapsulant 14 or gradually narrowing toward the encapsulant 14.

[0062] 3H, the method includes filling the trenches 20r with an insulating layer 30. The insulating layer 30 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or other deposition processes. In some embodiments, a polishing process, such as a chemical mechanical polishing (CMP) process, can be performed to polish and remove the insulating layer 30 outside the trenches 20r.

[0063] In some embodiments, the manufacturing method includes performing a single cut to separate the individual structures. The single cut can be performed, for example, using a dicing saw, a laser, or other suitable cutting technique. The semiconductor structure formed through these steps can be the same as the semiconductor chip package 1a shown in FIG. 1A.

[0064] 4A shows a perspective view of a portion of a semiconductor chip package 4a according to some embodiments of the present disclosure. The semiconductor chip package 4a is similar to the semiconductor chip package 1a shown in FIG. 1A, except that the gate G, source S, and drain D of the semiconductor chip 11 of the semiconductor chip package 4a are located on the same side, such as the surface 111. The drain D can be coupled (or electrically connected) to a drain lead contact 11d of the lead frame 10 via a conductive wire 11dw.

[0065] 4B illustrates one or more stages in a method for manufacturing a semiconductor chip package according to some embodiments of the present disclosure. FIG. 4B is similar to FIG. 3E-1, except that the gate G, source S, and drain D of the semiconductor chip 12 in FIG. 4B are located on the same side. The drain D can be coupled (or electrically connected) to a drain lead contact 11d of the lead frame 10 via a copper strip 12dp. The source S can be coupled (or electrically connected) to a source lead contact 12s of the lead frame 10 via a copper strip 12sp.

[0066] For ease of description, spatial terms such as "below," "lower," "bottom," "above," "top," "left side," and "right side" are used throughout the text to describe the relationship of one component or feature shown in the drawings to one or more other components or features. In addition to the orientation depicted in the drawings, spatial terms may also cover different orientations of the device during use or operation. Other methods of orientation (such as rotated 90 degrees or other orientations) of the device may be used, and spatial terms used throughout the text may be interpreted accordingly. When a component is described as being "connected" or "coupled" to another component, it should be understood that the component may be directly connected or coupled to the other component, or that intermediate components may be present.

[0067] As used herein, the terms "generally," "nearly," "essentially," and "about" are used to describe and interpret small variations. When used in connection with an event or circumstance, the term can refer to instances in which the event or circumstance definitely occurred and instances in which the event or circumstance is imminent. When used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein include the endpoints unless expressly stated otherwise. The term "substantially coplanar" can refer to two surfaces positioned along the same plane being within a few micrometers (μm) of each other, e.g., within 10 μm, 5 μm, 1 μm, or 0.5 μm of each other. When numerical values ​​or characteristics are referred to as being "approximately" the same, the term can refer to values ​​within ±10%, ±5%, ±1% or ±0.5% of the mean value of the value.

[0068] The foregoing has outlined certain exemplary features and detailed aspects of the present disclosure. The exemplary embodiments described in this disclosure may readily be used as a basis for designing or modifying other processes and structures to carry out the same or similar purposes and / or achieve the same or similar advantages of the exemplary embodiments described herein. Various alterations, substitutions, and modifications may be made to such equivalent structures without departing from the spirit and scope of the present disclosure.

Claims

1. In semiconductor chip packages, a lead frame having a first side and a second side facing each other, the lead frame having a first groove recessed from the first side of the lead frame; an adhesive filled in the first groove; a semiconductor chip disposed on the first side of the lead frame and on the adhesive; Including, The width of the first groove is not greater than the width of the semiconductor chip. A semiconductor chip package comprising:

2. 2. The semiconductor chip package of claim 1, wherein the adhesive has a surface that is substantially coplanar with a surface of the first side of the lead frame.

3. 2. The semiconductor chip package of claim 1, wherein the adhesive is completely covered by the semiconductor chip.

4. 2. The semiconductor chip package of claim 1, wherein the lead frame has a second groove recessed from the second side of the lead frame, and the semiconductor chip package further comprises an encapsulant filled in the second groove.

5. 2. The semiconductor chip package of claim 1, wherein the lead frame has chip pads for carrying the semiconductor chip and drain lead contacts substantially separated from the chip pads.

6. 6. The semiconductor chip package of claim 5, wherein the semiconductor chip has a gate, a source, and a drain, the drain being located on one side of the semiconductor chip, the gate and the source being located on another opposing side of the semiconductor chip, and the drain being coupled to the drain lead contact via the adhesive, the chip pad, and a conductive wire.

7. a carrier disposed on the second side of the lead frame; 10. The semiconductor chip package of claim 1 further comprising:

8. 8. The semiconductor chip package of claim 7, wherein the carrier has a first portion and a second portion, the first portion having a greater thermal conductivity coefficient than the second portion.

9. 9. The semiconductor chip package of claim 8, wherein the first portion comprises a ceramic portion and the second portion comprises a metal portion.

10. 9. The semiconductor chip package of claim 8, wherein the first portion of the carrier overlaps the semiconductor chip, and the second portion of the carrier does not overlap the semiconductor chip.

11. 9. The semiconductor chip package of claim 8, wherein the second portion of the carrier includes a first external terminal, a second external terminal, and a third external terminal of the semiconductor chip package.

12. In semiconductor chip packages, a lead frame having a first side and a second side facing each other, the lead frame having a first groove recessed from the first side of the lead frame; an adhesive filled in the first groove; a semiconductor chip disposed on the first side of the lead frame and on the adhesive; a carrier disposed on the second side of the lead frame; 1. A semiconductor chip package comprising:

13. 13. The semiconductor chip package of claim 12, wherein the carrier has a first portion and a second portion, the first portion having a greater thermal conductivity coefficient than the second portion.

14. 14. The semiconductor chip package of claim 13, wherein the first portion comprises a ceramic portion and the second portion comprises a metal portion.

15. 14. The semiconductor chip package of claim 13, wherein the first portion of the carrier overlaps the semiconductor chip and the second portion of the carrier does not overlap the semiconductor chip.

16. 14. The semiconductor chip package of claim 13, wherein the second portion of the carrier includes a first external terminal, a second external terminal, and a third external terminal of the semiconductor chip package.

17. 1. A method for manufacturing a semiconductor chip package, comprising: obtaining a lead frame having a first side and a second side opposite each other, the lead frame having a first groove recessed from the first side of the lead frame; Filling the first groove with adhesive; a semiconductor chip is placed on the first side of the lead frame and on the adhesive, and a width of the first groove is not greater than a width of the semiconductor chip; 2. A method for manufacturing a semiconductor chip package, comprising:

18. placing a carrier on the second side of the lead frame; The method of claim 17 further comprising:

19. placing the carrier on the second side of the lead frame; Fixing the lead frame on the carrier using a jig The method of claim 18, comprising:

20. The method of claim 18 , wherein the carrier has a first portion and a second portion, the first portion having a greater coefficient of thermal conductivity than the second portion.

21. removing a portion of the second portion of the carrier after placing the carrier on the second side of the lead frame to prevent the second portion from contacting the first portion; The method of claim 20 further comprising:

22. removing a portion of the second portion of the carrier; forming a first external terminal, a second external terminal and a third external terminal that are separated from each other on the second portion; The method of claim 21 , comprising:

23. filling an insulating layer between the first external terminal, the second external terminal, and the third external terminal; The method of claim 22 further comprising:

24. The drain of the semiconductor chip is coupled to a drain lead contact of a lead frame via a conductive wire. The method of claim 17 further comprising:

25. The lead frame and the semiconductor chip are covered with a sealant, and the sealant is filled into a second groove recessed from the second side of the lead frame. The method of claim 17 further comprising:

Images