Circuit board and semiconductor package including same

Abstract

The circuit board according to the embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer, and a circuit pattern layer disposed between the first insulating layer and the second insulating layer, wherein the second insulating layer has a cavity penetrating the upper and lower surfaces of the second insulating layer, and the circuit pattern layer includes an electrode pad disposed on the bottom surface of the cavity, and a dummy electrode disposed on the bottom surface of the cavity at a distance from the electrode pad and surrounding the outside of the electrode pad.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] As the performance of electrical / electronic products continues to improve, technologies for mounting more packages on a circuit board with limited size are being proposed and researched.

[0003] A typical semiconductor package has a structure in which multiple chips are arranged. Recently, the size of semiconductor packages has increased due to the high specifications of products to which semiconductor packages are applied and the adoption of multiple chips such as HBM (High Bandwidth Memory). As a result, semiconductor packages now include interposers to connect multiple chips.

[0004] In addition, semiconductor packages used in products that provide the Internet of Things (IOT), autonomous vehicles, and high-performance servers are required to have high performance and reliability in line with the trend toward higher integration.

[0005] Furthermore, the semiconductor package has a vertical connection structure between multiple substrates, interposers, and semiconductor devices, so that the semiconductor package may have a large vertical thickness depending on the thickness and number of the circuit boards, interposers, and semiconductor devices.

[0006] Therefore, semiconductor packages use circuit boards with cavities to reduce their vertical thickness.

[0007] In this case, a desmear process must be performed in the process of manufacturing a circuit board including a cavity, because if the desmear process is not performed, the adhesion between the molding member disposed in the cavity and the circuit board will be reduced, which may result in the molding member being separated from the circuit board.

[0008] Furthermore, when the desmear process is performed, the bottom surface of the cavity may be etched along with the sidewall of the cavity, which may cause damage to the bottom surface of the cavity and result in problems with the physical reliability of the circuit board.

[0009] Furthermore, the bottom surface of the cavity may be the top surface of the thermosetting resin containing glass fibers. When the desmear process is performed, the thermosetting resin is etched, which may result in the glass fibers in the thermosetting resin being exposed through the cavity. Furthermore, the exposed glass fibers may act as a factor causing defects such as copper migration.

[0010] (Patent Document 1) KR10-2012-0045639A Summary of the Invention [Problem to be solved by the invention]

[0011] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0012] Also, embodiments provide a circuit board including the cavity and a semiconductor package including the same.

[0013] Furthermore, the embodiments provide a circuit board capable of improving circuit integration and a semiconductor package including the same.

[0014] Furthermore, the embodiments provide a circuit board and a semiconductor package including the same that can solve the reliability problem caused by the glass fiber provided in the insulating layer being exposed through the cavity.

[0015] Furthermore, the embodiments provide a circuit board capable of improving adhesion between a plurality of insulating layers including different insulating materials, and a semiconductor package including the same.

[0016] Furthermore, the embodiments provide a circuit board with improved warpage characteristics and a semiconductor package including the same.

[0017] Furthermore, the embodiments provide a circuit board capable of preventing the generation of foreign matter on the side surface and a semiconductor package including the same.

[0018] Furthermore, the embodiments provide a circuit board capable of improving heat dissipation characteristics and a semiconductor package including the same.

[0019] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0020] The circuit board according to the embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer, and a circuit pattern layer disposed between the first insulating layer and the second insulating layer, wherein the second insulating layer has a cavity penetrating the upper and lower surfaces of the second insulating layer, and the circuit pattern layer includes an electrode pad disposed on the bottom surface of the cavity, and a dummy electrode disposed on the bottom surface of the cavity at a distance from the electrode pad and surrounding the outside of the electrode pad.

[0021] The outer surface of the first insulating layer has a step with the outer surface of the second insulating layer.

[0022] The first insulating layer and the second insulating layer contain different insulating materials.

[0023] The second insulating layer includes a photocurable resin.

[0024] The outer surface of the second insulating layer is located further inward than the outer surface of the first insulating layer.

[0025] The circuit board further includes a protective layer disposed on the second insulating layer, and an outer surface of the protective layer has a step with an outer surface of the second insulating layer.

[0026] The protective layer is provided to cover the outer surface of the second insulating layer.

[0027] The outer surface of the second insulating layer has a slope such that the outer width of the second insulating layer decreases or increases from the upper surface of the second insulating layer toward the lower surface of the second insulating layer.

[0028] The protective layer also has an opening that overlaps the cavity in the vertical direction, and the inclination of the inner wall of the opening is different from the inclination of the inner wall of the cavity.

[0029] Furthermore, the direction in which the inner wall of the opening is inclined is different from the direction in which the inner wall of the cavity is inclined.

[0030] In addition, the slope of the inner wall of the cavity of the second insulating layer includes a first portion connected to the bottom surface of the second insulating layer and having a linear slope such that the width of the cavity narrows toward the top surface of the second insulating layer, and a second portion provided between the top surface of the second insulating layer and the first portion and having a curved slope such that the width of the cavity increases toward the bottom surface of the second insulating layer.

[0031] The circuit board further includes a first through electrode that penetrates the first insulating layer and a second through electrode that horizontally overlaps the cavity and penetrates the second insulating layer, and the vertical thickness of the second through electrode is smaller than the vertical thickness of the electrode pad and the thickness of the first through electrode.

[0032] The second insulating layer may be formed of a plurality of layers, and the cavity may penetrate at least one of the plurality of layers of the second insulating layer.

[0033] Further, the second insulating layer includes a first layer disposed on the first insulating layer and a second layer disposed on the first layer, and the second through electrode includes one through part that penetrates the first layer and a second through part that penetrates the second layer, and the first through part and the second through part are in direct contact with each other.

[0034] Furthermore, the first penetrating part has a slope in which its width decreases from the top surface to the bottom surface of the first penetrating part, the second penetrating part has a slope in which its width decreases from the top surface to the bottom surface of the second penetrating part, and the horizontal center of the first penetrating part is offset from the horizontal center of the second penetrating part.

[0035] The circuit pattern layer further includes a pad portion that does not overlap the cavity in a vertical direction, and a connection pattern that connects the pad portion to the electrode pad, and the dummy electrode is provided to surround the outside of the electrode pad at a position spaced apart from the electrode pad and the connection pattern.

[0036] The semiconductor device further includes a connecting member disposed within the cavity and on the electrode pad.

[0037] The first through electrodes are provided in plurality, and at least one of the plurality of first through electrodes overlaps the dummy electrode in the vertical direction.

[0038] Meanwhile, a semiconductor package according to an embodiment includes any one of the above-described circuit boards and a semiconductor device disposed on the circuit board.

[0039] The semiconductor elements may be arranged in a plurality on the circuit board along at least one of a vertical direction and a horizontal direction. [Effects of the Invention]

[0040] The circuit board of the embodiment may include a first insulating layer and a second insulating layer disposed on the first insulating layer. The first insulating layer may include a first insulating material, and the second insulating layer may include a second insulating material different from the first insulating material. The outer surface of the first insulating layer may have a step with respect to the outer surface of the second insulating layer. This improves adhesion between the first insulating layer and the second insulating layer while preventing the circuit board from warping in a specific direction.

[0041] For example, the first insulating layer may contain a thermosetting resin, and the second insulating layer may contain a photocurable resin. This may reduce the adhesion between the first insulating layer and the second insulating layer. Furthermore, the first insulating layer and the second insulating layer may have different thermal expansion coefficients. Therefore, the difference in thermal expansion coefficients between the first insulating layer and the second insulating layer may cause the circuit board to warp significantly in a specific direction. In this case, the warpage of the circuit board may be caused by the second insulating layer containing the photocurable resin.

[0042] Therefore, in the embodiment, the outer width of the second insulating layer may be smaller than the outer width of the first insulating layer. Therefore, in the embodiment, the second insulating layer may prevent the circuit board from warping in a specific direction. Through this, the embodiment may improve the physical reliability and electrical reliability of the circuit board.

[0043] Furthermore, in the embodiment, a first protective layer may be disposed on the second insulating layer while enclosing the upper and outer surfaces of the second insulating layer. The first protective layer may protect the circuit pattern layer disposed on the second insulating layer and improve adhesion between the first insulating layer and the second insulating layer. This improves adhesion between the first insulating layer and the second insulating layer. This solves the physical reliability problem of the second insulating layer peeling from the first insulating layer or the circuit pattern layer disposed on the second insulating layer peeling from the second insulating layer.

[0044] In addition, the circuit board of the embodiment may include a third insulating layer disposed below the first insulating layer. The third insulating layer may be disposed below the first insulating layer while having an insulating material and a structure corresponding to the second insulating layer. For example, the structure of the third insulating layer may be symmetrical to the structure of the second insulating layer with respect to the first insulating layer. This may solve the problem of warpage of the circuit board caused by an asymmetric structure, thereby improving the electrical and / or physical reliability of the circuit board and a semiconductor package including the same.

[0045] Meanwhile, the outer surface of the circuit board in the embodiment does not include a portion corresponding to the second insulating layer and / or the third insulating layer. For example, the outer surface of the second insulating layer and / or the third insulating layer may be covered with the first protective layer and the second protective layer. As a result, the outer surface of the second insulating layer and / or the third insulating layer does not need to be exposed to the outside of the circuit board. As a result, the embodiment can solve the problem of damage caused by the outer surface of the second insulating layer and / or the third insulating layer, which has relatively weak rigidity, being exposed to the outside of the circuit board. Furthermore, the embodiment can solve the problem of foreign matter being generated by the second insulating layer and / or the third insulating layer during a sawing process in a process of manufacturing circuit boards in strip units. Therefore, the embodiment can improve the overall product reliability of the circuit board and the semiconductor package.

[0046] The circuit board of the embodiment may include a first circuit pattern layer disposed on the first insulating layer. The second insulating layer may include a cavity. The first circuit pattern layer may include a first circuit pattern portion disposed on a first region of the first insulating layer that vertically overlaps the cavity. In this case, the planar area occupied by the first circuit pattern portion in the first region may be in the range of 50% to 90% of the entire planar area of ​​the first region. That is, the planar area of ​​the portion of the first region of the first insulating layer where the first circuit pattern portion is not disposed may be in the range of 10% to 50% of the entire planar area of ​​the first region. This prevents damage to the top surface of the first region of the first insulating layer during a desmear process after the cavity is formed. This prevents reliability issues, such as copper migration, that occur due to etching of the first region of the first insulating layer during the desmear process. Therefore, the embodiment may improve the electrical reliability of the circuit board and a semiconductor package including the circuit board.

[0047] In addition, in the embodiment, the thickness of the through electrode that overlaps the cavity in the horizontal direction can be made smaller than the thickness of the electrode pad of the first circuit pattern layer. Furthermore, the thickness of the through electrode that overlaps the cavity in the horizontal direction and penetrates the second insulating layer can be reduced to 1 / 1.5, even 1 / 2, even 1 / 3, or even 1 / 3.5 of the thickness of the through electrode that penetrates the first insulating layer. As a result, the embodiment can reduce the signal transmission distance and minimize the resulting signal transmission loss.

[0048] In addition, the embodiment may provide a through electrode in which the second insulating layer is provided in multiple layers and each of the multiple layers of the second insulating layer is provided with a through part. In this case, pads such as lands may not be provided between the through parts that overlap each other in the vertical direction. Therefore, the embodiment may simplify the process for forming the through electrode and improve product yield. Furthermore, the embodiment may also be configured such that the horizontal centers of the multiple through parts that should overlap each other in the vertical direction are offset from each other, thereby improving design freedom.

[0049] Furthermore, the embodiment may be advantageous in selecting conditions for the desmear process because it is not necessary to consider damage to the first insulating layer during the desmear process. This may improve the adhesion between the second insulating layer and the second circuit pattern layer disposed on the second insulating layer. Specifically, the cavity may be formed together with the through hole in the process of forming the through hole corresponding to the second through electrode in the second insulating layer. This may allow the second circuit pattern layer to be disposed on the second insulating layer after the desmear process. Therefore, the embodiment is advantageous in selecting conditions for the desmear process, and the desmear process may be performed under conditions that improve the adhesion between the second insulating layer and the second circuit pattern layer. This may improve the adhesion between the second insulating layer and the second circuit pattern layer.

[0050] The first circuit pattern portion may include first electrode pads on which connection members are disposed and dummy electrodes other than the first electrode pads. The dummy electrodes may protect the upper surface of the first region of the first insulating layer while improving the rigidity and heat dissipation characteristics of the circuit board. As a result, the embodiment may improve the product reliability of the circuit board and a semiconductor package including the same. The embodiment may also include a through-hole that penetrates the first insulating layer and is connected to the dummy electrode. The embodiment may allow heat transferred from the dummy electrode to be dissipated to the outside via the through-hole. As a result, the embodiment may further improve the heat dissipation characteristics of the circuit board. As a result, the embodiment may improve the operational reliability of the circuit board and a semiconductor package including the circuit board.

[0051] The first circuit pattern unit also includes a connection pattern electrically connected to the first electrode pad. The connection pattern can directly connect the plurality of electrode pads disposed in the first region and the second region of the first insulating layer. That is, in the embodiment, a connection pattern that directly connects the first electrode pad and the second electrode pad is disposed on the first insulating layer. As a result, the embodiment can reduce the signal transmission distance between the first electrode pad and the second electrode pad. Furthermore, the embodiment can minimize signal transmission loss due to the reduction in the signal transmission distance. As a result, the embodiment can improve the electrical characteristics of the circuit board and a semiconductor package including the same. Furthermore, the embodiment can improve the circuit integration density of the circuit board. [Brief explanation of the drawings]

[0052] [Figure 1a] 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 1b] FIG. 10 is a cross-sectional view showing a semiconductor package according to a second embodiment. [Figure 1c] FIG. 10 is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 1d] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. [Figure 1e]FIG. 10 is a cross-sectional view showing a semiconductor package according to a fifth embodiment. [Figure 1f] FIG. 10 is a cross-sectional view showing a semiconductor package according to a sixth embodiment. [Figure 1g] FIG. 13 is a cross-sectional view showing a semiconductor package according to a seventh embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing the circuit board of the first embodiment. [Figure 3] 3 is a plan view of the circuit board of FIG. 2 with some components removed. [Figure 4] 3 is a cross-sectional view taken along the AA' direction in FIG. 2 according to an embodiment. [Figure 5] 3 is a cross-sectional view taken along the AA' direction of FIG. 2 in another embodiment. [Figure 6] FIG. 3 is a cross-sectional view showing a first modified example of the circuit board of FIG. [Figure 7] 7 is a plan view of the circuit board of FIG. 6 with some components removed. [Figure 8] 3 is a cross-sectional view showing a second modified example of the circuit board of FIG. 2. FIG. [Figure 9] FIG. 10 is a cross-sectional view showing a circuit board according to a second embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a circuit board according to a third embodiment. [Figure 11] 11 is a plan view of the circuit board of FIG. 10 with some components removed. [Figure 12] FIG. 10 is a cross-sectional view showing a circuit board according to a fourth embodiment. [Figure 13] 13 is a plan view of the circuit board of FIG. 12 with some components removed. [Figure 14] 3 is a diagram showing a semiconductor package including the circuit board of FIG. 2. [Figure 15-20] 3A to 3C are diagrams showing a method for manufacturing the circuit board of FIG. 2 according to an embodiment in the order of steps. [Figure 21] FIG. 10 is a cross-sectional view showing a circuit board according to a fifth embodiment. [Figure 22] 22 is a plan view of the circuit board of FIG. 21 with some components removed. [Figure 23]FIG. 22 is a cross-sectional view taken along the AA' direction in FIG. 21 according to one embodiment. [Figure 24] 22 is a diagram showing a planar shape of the second through electrode of FIG. 21. FIG. [Figure 25] FIG. 22 is a diagram showing the planar shape of the cavity in FIG. 21. [Figure 26] FIG. 10 is a cross-sectional view showing a circuit board according to a sixth embodiment. [Figure 27] FIG. 22 is a cross-sectional view taken along the AA' direction in FIG. 21 according to the seventh embodiment. [Figure 28] FIG. 22 is a cross-sectional view taken along the AA' direction in FIG. 21 according to the eighth embodiment. [Figure 29] FIG. 13 is a cross-sectional view showing a circuit board according to a ninth embodiment. [Figure 30] FIG. 23 is a cross-sectional view showing a circuit board according to a tenth embodiment. [Figure 31] FIG. 23 is a cross-sectional view showing a circuit board according to an eleventh embodiment. [Figure 32] FIG. 23 is a cross-sectional view showing a circuit board according to a twelfth embodiment. [Figure 33] FIG. 33 is a plan view in which one configuration of the circuit board in FIG. 32 is omitted. [Figure 34] FIG. 23 is a cross-sectional view showing a circuit board according to a thirteenth embodiment. [Figure 35] FIG. 35 is a plan view in which one configuration of the circuit board in FIG. 34 is omitted. [Figure 36-41] 22A to 22D are diagrams showing a method for manufacturing the circuit board of FIG. 21 in the order of steps. DETAILED DESCRIPTION OF THE INVENTION

[0053] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0054] However, the technical concept of the present invention is not limited to the described embodiments, but may be realized in various different forms, and one or more of the components of the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0055] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as meanings commonly understood by those of ordinary skill in the art to which the present invention belongs, and commonly used terms such as predefined terms may be interpreted in light of the contextual meaning of the relevant art. Furthermore, the terms used in the embodiments of the present invention are intended to describe the embodiments and do not limit the present invention.

[0056] In this specification, unless otherwise specified in the phrase, the singular can also include the plural, and when referring to "A and (and) at least one (or more) of B and C," it can include one or more of all combinations that can be combined with A, B, and C. Furthermore, terms such as first, second, A, B, (a), and (b) can be used to describe components of the present invention.

[0057] Such terms are used merely to distinguish a component from other components, and are not limited by the nature, order, or sequence of the components. When a component is described as being "coupled," "coupled," or "connected" to another component, it includes not only the case where the component is directly coupled, coupled, or connected to the other component, but also the case where the component is "coupled," "coupled," or "connected" by another component between the component and the other component.

[0058] Furthermore, when it is stated that something is formed or placed "above or below" a component, "above" or "below" not only refers to the case where two components are in direct contact with each other, but also includes the case where one or more other components are formed or placed between the two components. Furthermore, when it is expressed as "above" or "below," it can mean not only the upward direction based on one component, but also the downward direction.

[0059] -Electronic Devices-

[0060] Prior to describing the embodiments, an electronic device to which the semiconductor package of the embodiments is applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various semiconductor elements may be mounted in the semiconductor package.

[0061] The semiconductor device may include active and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0062] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

[0063] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0064] Furthermore, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0065] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package according to the embodiment may have various package structures including the circuit board described below.

[0066] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, and Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0067] Referring to FIG. 1 a, the semiconductor package of the first embodiment may include a first circuit board 10 , a second circuit board 20 , and a semiconductor device 30 .

[0068] The first circuit board 10 may refer to a semiconductor package circuit board.

[0069] For example, the first circuit board 10 may provide a space to which at least one external circuit board is coupled. The external circuit board may refer to the second circuit board 20 coupled on the first circuit board 10. The external circuit board may also refer to a main board included in an electronic device coupled below the first circuit board 10.

[0070] Although not shown in the drawings, the first circuit board 10 may provide a space in which at least one semiconductor element is mounted.

[0071] The first circuit board 10 may include at least one insulating layer, a circuit pattern layer disposed on the at least one insulating layer, and a through electrode that penetrates the at least one insulating layer.

[0072] A second circuit board 20 may be disposed on the first circuit board 10 .

[0073] The second circuit board 20 may be an interposer. For example, the second circuit board 20 may provide a space in which at least one semiconductor device is mounted. The second circuit board 20 may be connected to at least one semiconductor device 30. For example, the second circuit board 20 may provide a space in which a first semiconductor device 31 and a second semiconductor device 32 are mounted. The second circuit board 20 may electrically connect the first semiconductor device 31 and the second semiconductor device 32, and may also electrically connect the first and second semiconductor devices 31 and 32 to the first circuit board 10. That is, the second circuit board 20 may function as a horizontal connection between multiple semiconductor devices and a vertical connection between the semiconductor device and a package circuit board.

[0074] 1a shows two semiconductor elements 31 and 32 disposed on the second circuit board 20, but is not limited to this. For example, one semiconductor element may be disposed on the second circuit board 20, or alternatively, three or more semiconductor elements may be disposed on the second circuit board 20.

[0075] The second circuit board 20 may be disposed between at least one semiconductor device 30 and the first circuit board 10 .

[0076] In one embodiment, the second circuit board 20 may be an active interposer that functions as a semiconductor device. When the second circuit board 20 functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first circuit board 10 and function as multiple logic chips. Having the function of a logic chip may mean having the functions of both active and passive devices. Unlike passive devices, active devices do not need to have linear current-voltage characteristics. An active interposer may have the function of an active device. Furthermore, the active interposer may perform the function of a logic chip while also transmitting signals between the first circuit board 10 and a second logic chip disposed thereon.

[0077] According to another embodiment, the second circuit board 20 may be a passive interposer. For example, the second circuit board 20 may function as a signal relay between the semiconductor device 30 and the first circuit board 10 and may have passive element functions such as a resistor, capacitor, or inductor. For example, the number of terminals on the semiconductor device 30 is gradually increasing due to factors such as 5G, the Internet of Things (IOT), improved image quality, and increased communication speed. That is, the number of terminals provided on the semiconductor device 30 is increasing, and as a result, the width of the terminals and the spacing between the terminals are decreasing. In this case, the first circuit board 10 is connected to the main board of the electronic device. Therefore, in order to ensure that the electrodes provided on the first circuit board 10 have the width and spacing required to be connected to the semiconductor device 30 and the main board, respectively, the thickness of the first circuit board 10 would increase or the layer structure of the first circuit board 10 would become complex. Therefore, in the first embodiment, the second circuit board 20 is disposed between the first circuit board 10 and the semiconductor device 30. The second circuit board 20 may include electrodes having fine widths and intervals corresponding to the terminals of the semiconductor element 30 .

[0078] The semiconductor package includes a first connection member 41 disposed between the first circuit board 10 and the second circuit board 20. The first connection member 41 couples the second circuit board 20 to the first circuit board 10 and electrically connects them.

[0079] The semiconductor package may include a second connection member 42 disposed between the second circuit board 20 and the semiconductor element 30. The second connection member 42 may electrically connect the semiconductor element 30 to the second circuit board 20 while coupling the semiconductor element 30 to the second circuit board 20.

[0080] The semiconductor package includes a third connection member 43 disposed on the lower surface of the first circuit board 10. The third connection member 43 can electrically connect the first circuit board 10 to the main board while coupling them to each other.

[0081] In this case, the first connection member 41, the second connection member 42, and the third connection member 43 can electrically connect the multiple components using at least one bonding method of wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection member 41, the second connection member 42, and the third connection member 43 have the function of electrically connecting the multiple components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as the electrically connected part, not the solder or wire.

[0082] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material containing at least one of Sn, Ag, and Cu. The direct inter-metal bonding method may refer to directly bonding multiple components through recrystallization by applying heat and pressure between the multiple components without using materials such as solder, wire, or conductive adhesive. The direct inter-metal bonding method may refer to a bonding method using a second connecting member 42. In this case, the second connecting member 42 may refer to a metal layer formed between the multiple components through recrystallization.

[0083] Specifically, the first connecting member 41, the second connecting member 42, and the third connecting member 43 can bond multiple components to each other using a TC (Terminal Compression) bonding method. The TC bonding method can refer to a method of bonding multiple components by applying heat and pressure to the first connecting member 41, the second connecting member 42, and the third connecting member 43.

[0084] In this case, a protrusion may be arranged on the electrodes on which the first connecting member 41, the second connecting member 42, and the third connecting member 43 are arranged in at least one of the first circuit board 10 and the second circuit board 20. The protrusion may protrude outward from the first circuit board 10 or the second circuit board 20.

[0085] The protrusion may be referred to as a bump, a post, or a pillar. Preferably, the protrusion may refer to an electrode of the second circuit board 20 on which a second connection member 42 for coupling with the semiconductor device 30 is disposed. That is, as the pitch of the terminals of the semiconductor device 30 becomes finer, short circuits may occur between the second connection members 42, which connect conductive adhesives such as solder to the terminals of the semiconductor device 30. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection member 42. In addition, the electrode of the second circuit board 20 on which the second connection member 42 is disposed may include a protrusion to ensure consistency, diffusion strength, and diffusion prevention strength to prevent intermetallic compounds (IMCs) formed between the conductive adhesives such as solder and the protrusions from diffusing into the interposer and / or the circuit board.

[0086] Referring to FIG. 1b, the semiconductor package of the second embodiment may differ from the semiconductor package of the first embodiment in that a connecting member 21 is disposed on a second circuit board 20. Recently, as the number of signals that semiconductor devices must process increases, the size of semiconductor devices tends to increase. However, this increase in the area of ​​semiconductor devices poses a problem of reduced yield. Therefore, there is a trend to divide the size of the pattern or functional portion of a semiconductor device, arrange chiplets on a circuit board, and embed a connecting member 21, which functions to electrically connect the chiplets, within the circuit board. However, the connecting member 21 is not limited to this and may also connect a semiconductor device to a semiconductor device having another function, such as a memory. For example, the connecting member 21 may include a redistribution layer. The connecting member 21 may function to electrically connect multiple semiconductor devices horizontally. For example, the connecting member 21 may include a redistribution layer because a semiconductor device generally requires a large area. Because there is a large difference between the width of the circuit pattern of a semiconductor package and that of a semiconductor device, a buffer for the circuit pattern is required for electrical connection. The buffering role may mean having an intermediate size between the size of the circuit pattern of the semiconductor package, such as the width of the circuit pattern of the semiconductor device, such as the width of the circuit pattern, and the redistribution layer may include a function of performing a buffering role.

[0087] In one embodiment, the connecting member 21 may include a silicon material, and the connecting member 21 may include a silicon circuit substrate and a redistribution layer disposed on the silicon circuit substrate.

[0088] In other embodiments, the connecting member 21 may include an organic material, for example, an organic circuit board that includes an organic material instead of a silicon circuit board.

[0089] The connecting member 21 may be embedded in the second circuit board 20, but is not limited to this. For example, the connecting member 21 may be arranged to have a protruding structure on the second circuit board 20. Alternatively, the second circuit board 20 may include a cavity, and the connecting member 21 may be arranged in the cavity of the second circuit board 20. The connecting member 21 may horizontally connect multiple semiconductor elements arranged on the second circuit board 20.

[0090] 1c, the semiconductor package of the third embodiment may include a second circuit board 20 and a semiconductor device 30. In this regard, the semiconductor package of the third embodiment has a structure in which the first circuit board 10 is removed compared to the semiconductor package of the second embodiment.

[0091] That is, the second circuit board 20 of the third embodiment can function as both an interposer and a package circuit board.

[0092] The first connecting member 41 disposed on the lower surface of the second circuit board 20 can couple the second circuit board 20 to the main board of the electronic device.

[0093] Referring to FIG. 1 d, the semiconductor package of the fourth embodiment may include a first circuit board 10 and a semiconductor device 30 .

[0094] In this case, the semiconductor package of the fourth embodiment has a structure in which the second circuit board 20 is removed, as compared with the semiconductor package of the second embodiment.

[0095] That is, the first circuit board 10 of the fourth embodiment can function as a package circuit board and also as a connection between the semiconductor devices 30 and the main board. To this end, the first circuit board 10 can include a connection member 11 for connecting between the plurality of semiconductor devices. The connection member 11 can be a silicon bridge or an organic bridge for connecting between the plurality of semiconductor devices.

[0096] Referring to FIG. 1e, the semiconductor package of the fifth embodiment further includes a third semiconductor element 33 compared to the semiconductor package of the fourth embodiment.

[0097] For this reason, a fourth connecting member 44 may be disposed on the lower surface of the first circuit board 10. A third semiconductor element 33 may be disposed on the fourth connecting member 44. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor elements are mounted on both the upper and lower sides.

[0098] In this case, the third semiconductor element 33 may have a structure in which it is disposed on the lower surface of the second circuit board 20 in the semiconductor package of FIG. 1c.

[0099] Referring to FIG. 1f, the semiconductor package of the sixth embodiment includes a first circuit board 10.

[0100] A first semiconductor element 31 may be disposed on the first circuit board 10. To this end, a first connecting member 41 may be disposed between the first circuit board 10 and the first semiconductor element 31.

[0101] The first circuit board 10 may also include a conductive coupling portion 45. The conductive coupling portion 45 may further protrude from the first circuit board 10 toward the second semiconductor element 32. The conductive coupling portion 45 may be referred to as a bump, or alternatively as a post. The conductive coupling portion 45 may be disposed in a protruding structure on an electrode disposed on the top side of the first circuit board 10.

[0102] The second semiconductor element 32 may be disposed on the conductive coupling part 45. In this case, the second semiconductor element 32 may be connected to the first circuit board 10 via the conductive coupling part 45. In addition, a second connection member 42 may be disposed on the first semiconductor element 31 and the second semiconductor element 32.

[0103] As a result, the second semiconductor element 32 can be electrically connected to the first semiconductor element 31 via the second connection member 42 .

[0104] That is, the second semiconductor element 32 may be connected to the first circuit board 10 through the conductive coupling portion 45 and also to the first semiconductor element 31 through the second connecting member 42 .

[0105] At this time, the second semiconductor element 32 can be supplied with a power signal and / or power via the conductive coupling portion 45. In addition, the second semiconductor element 32 can transmit and receive communication signals to and from the first semiconductor element 31 via the second connecting member 42.

[0106] The semiconductor package of the sixth embodiment provides a power supply signal and / or power to the second semiconductor element 32 via the conductive coupling portion 45, thereby enabling the provision of sufficient power for driving the second semiconductor element 32 and smooth control of power supply operation.

[0107] As a result, the embodiment can improve the driving characteristics of the second semiconductor device 32. That is, the embodiment can solve the problem of insufficient power supplied to the second semiconductor device 32. Furthermore, the embodiment allows at least one of the power signal and the communication signal of the second semiconductor device 32 to be provided via different paths via the conductive coupling part 45 and the second connection member 42. As a result, the embodiment can solve the problem of loss of the communication signal due to the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0108] Meanwhile, in the sixth embodiment, the second semiconductor device 32 may be arranged on the first circuit board 10 in a package-on-package (POP) structure in which a plurality of package circuit boards are stacked. For example, the second semiconductor device 32 may be a memory package including a memory chip. The memory package may be coupled to the conductive coupling part 45. In this case, the memory package may not be connected to the first semiconductor device 31.

[0109] Meanwhile, the semiconductor package in the sixth embodiment may include a molding member 46. The molding member 46 may be disposed between the first circuit board 10 and the second semiconductor element 32. For example, the molding member 46 may mold the first connecting member 41, the second connecting member 42, the first semiconductor element 31, and the conductive coupling portion 45.

[0110] 1g, the semiconductor package of the seventh embodiment may include a first circuit board 10, a first connecting member 41, a semiconductor device 30, and a third connecting member 43. The semiconductor package of the seventh embodiment differs from the semiconductor package of the fourth embodiment in that the connecting member 11 is removed and the first circuit board 10 includes multiple circuit board layers.

[0111] The first circuit board 10 may include multiple substrate layers, such as a first circuit board layer 10A corresponding to a package circuit board and a second circuit board layer 10B corresponding to a connecting member.

[0112] In other words, the semiconductor package of the seventh embodiment may include a first circuit board layer 10A and a second circuit board layer 10B in which the first circuit board 10 (package circuit board) and the second circuit board 20 (interposer) shown in FIG. 1A are integrally formed. The material of the insulating layer of the second circuit board layer 10B may be different from the material of the insulating layer of the first circuit board layer 10A. For example, the material of the insulating layer of the second circuit board layer 10B may include a photo-curable material. For example, the second circuit board layer 10B may be a photo-imageable dielectric (PID). Furthermore, the second circuit board layer 10B may include a photo-curable material, thereby enabling miniaturization of electrodes. Therefore, in the seventh embodiment, the second circuit board layer 10B may be formed by sequentially stacking insulating layers of a photo-curable material on the first circuit board layer 10A and then forming miniaturized electrodes on the insulating layers of the photo-curable material. Thus, the second circuit board layer 10B may have a function of a rewiring layer including miniaturized electrodes, and may have a function of connecting a plurality of semiconductor elements 31 and 32 horizontally.

[0113] The circuit board of the embodiment will be described below.

[0114] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals, the same or corresponding components are denoted by the same reference numerals, and redundant description thereof will be omitted.

[0115] FIG. 2 is a cross-sectional view showing the circuit board of the first embodiment, FIG. 3 is a plan view of the circuit board of FIG. 2 with some components removed, FIG. 4 is a cross-sectional view of one embodiment taken along the A-A' direction of FIG. 2, and FIG. 5 is a cross-sectional view of one embodiment taken along the A-A' direction of FIG. 2.

[0116] Prior to describing the circuit board of the embodiment, the circuit board described below may refer to the circuit board included in the semiconductor package of any one of the embodiments of Figures 1a to 1g. Preferably, the circuit board of the embodiment described below may be the first circuit board 10 and / or the second circuit board 20 of Figures 1a to 1g. The first circuit board 10 and / or the second circuit board 20 may include a cavity.

[0117] In this case, a connecting member may be disposed in the cavity. If the circuit board is a first circuit board 10, the connecting member may be one of a second circuit board and a semiconductor element. If the circuit board is a second circuit board 20, the connecting member may be one of a semiconductor element and a connecting board.

[0118] Referring to FIG. 2, the circuit board of the embodiment includes multiple insulating layers. Each of the multiple insulating layers may have a single-layer structure, or may instead be composed of multiple layers. Specifically, the circuit board may include a first insulating layer 111 and a second insulating layer 112. In this case, the first insulating layer 111 may be formed as a single layer as shown in FIG. 2, or may be formed as multiple layers. The second insulating layer 112 may include a cavity 150. If the second insulating layer 112 is formed as multiple layers, the cavity 150 may penetrate the multiple layers of the second insulating layer 112. However, for convenience of explanation, the following description will be given assuming that the first insulating layer 111 and the second insulating layer 112 each include a single layer.

[0119] The first insulating layer 111 and the second insulating layer 112 may contain different insulating materials. For example, the first insulating layer 111 may contain a thermosetting resin. The second insulating layer 112 may contain a photocurable resin.

[0120] The first insulating layer 111 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the first insulating layer 111 may include reinforced or ductile plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the first insulating layer 111 may include sapphire. For example, the first insulating layer 111 may include an optically isotropic film. For example, the first insulating layer 111 may include cyclic olefin copolymer (COC), cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the first insulating layer 111 may be formed of a material including an inorganic filler and an insulating resin. For example, the first insulating layer 111 may have a structure in which inorganic filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0121] The second insulating layer 112 may include an insulating material different from that of the first insulating layer 111. Preferably, the second insulating layer 112 may include a photocurable resin. The photocurable resin allows for cavity formation through an exposure and development process, thereby removing the stopper required for the cavity formation process. The content of ceramic particles, such as SiO2, contained in the second insulating layer 112 containing the photocurable resin may be higher than the content of ceramic particles contained in the first insulating layer 111 containing the thermosetting resin. Based on this, it may be possible to distinguish the interface between the photocurable resin and the thermosetting resin. For example, when performing XPS (X-ray Photoelectron Spectroscopy) analysis of the photocurable resin, relatively high power peak values ​​may be detected for both acrylic and epoxy. Furthermore, when performing XPS analysis of the thermosetting resin, a peak value may be detected only for the epoxy.

[0122] The first insulating layer 111 and the second insulating layer 112 may each have a thickness in the range of 10 μm to 60 μm. If the thickness of the first insulating layer 111 and the second insulating layer 112 is less than 10 μm, the circuit pattern layer included in the circuit board may not be stably protected. If the thickness of each of the first insulating layer 111 and the second insulating layer 112 exceeds 60 μm, the overall thickness of the circuit board may increase. Furthermore, if the thickness of each of the first insulating layer 111 and the second insulating layer 112 exceeds 60 μm, the thickness of the circuit pattern layer and the through electrodes may also increase accordingly, which may increase the loss of signals transmitted through the circuit patterns. In this case, the thickness of the first insulating layer 111 and the second insulating layer 112 may correspond to the distance in the thickness direction between the circuit pattern layers arranged on different layers. For example, the thickness of the first insulating layer 111 may refer to the vertical distance between the bottom surface of the first circuit pattern layer 121 and the top surface of the third circuit pattern layer 123. For example, the thickness of the second insulating layer 112 may refer to the vertical linear distance in the thickness direction between the upper surface of the first circuit pattern layer 121 and the lower surface of the second circuit pattern layer 122 .

[0123] The second insulating layer 112 may include a cavity 150. The cavity 150 may penetrate the top and bottom surfaces of the second insulating layer 112. The cavity 150 may include a bottom surface and sidewalls. The bottom surface of the cavity 150 may refer to the top surface of the first insulating layer 111 that vertically overlaps the cavity 150. And the sidewall of the cavity 150 may refer to the sidewall of the second insulating layer 112 that includes the cavity 150.

[0124] The sidewalls of the cavity 150 may have a slope. For example, the sidewalls of the cavity 150 may have a slope such that the width of the cavity 150 decreases from the upper surface of the second insulating layer 112 to the lower surface thereof. However, the embodiment is not limited thereto. For example, the sidewalls may have a slope such that the width of the cavity 150 decreases from the lower surface of the second insulating layer 112 to the upper surface thereof. Furthermore, although the sidewalls are shown in the drawings as having a single slope, the embodiment is not limited thereto. For example, the sidewalls may be provided so as to have a plurality of different slopes.

[0125] The top surface of the first insulating layer 111 may be divided into a plurality of regions. For example, the first insulating layer 111 may include a first region R1 that vertically overlaps the cavity 150. In this case, if the cavities 150 have different widths in the thickness direction of the second insulating layer 112, the first region R1 may refer to a region that vertically overlaps a lower region of the cavity 150 that corresponds to the lower end of the sidewall. For example, the first region R1 may refer to a region of the top surface of the first insulating layer 111 that does not contact the second insulating layer 112.

[0126] The first insulating layer 111 may also include a second region R2 that does not vertically overlap the cavity 150. The second region R2 may refer to a region of the top surface of the first insulating layer 111 that is covered with the second insulating layer 112.

[0127] On the surfaces of the first insulating layer 111 and the second insulating layer 112, a circuit pattern layer is disposed.

[0128] For example, a first circuit pattern layer 121 may be disposed between the upper surface of the first insulating layer 111 and the lower surface of the second insulating layer 112. For example, a second circuit pattern layer 122 may be disposed on the upper surface of the second insulating layer 112. For example, a third circuit pattern layer 123 may be disposed on the lower surface of the first insulating layer 111. The first circuit pattern layer 121 may be disposed on the first insulating layer 111. For example, the first circuit pattern layer 121 may protrude above the upper surface of the first insulating layer 111. The second circuit pattern layer 122 may protrude above the upper surface of the second insulating layer 112. The second circuit pattern layer 122 may refer to the uppermost circuit pattern layer disposed on the uppermost side of the circuit board. The third circuit pattern layer 123 may protrude below the lower surface of the first insulating layer 111. The third circuit pattern layer 123 may refer to the lowermost circuit pattern layer disposed on the lowermost side of the circuit board.

[0129] The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each include electrode pads and traces (or electrode patterns) according to their functions. The electrode pads may be mounting electrode pads on which elements or chips are mounted, or terminal electrode pads connected to an external circuit board. The traces may be long signal wiring lines connecting multiple electrode pads. The traces are fine patterns having a width smaller than that of the electrode pads. For example, in an embodiment, the spacing between multiple traces may be in the range of 2 μm to 15 μm, and the line width of each trace may be in the range of 2 μm to 15 μm.

[0130] The circuit pattern layers may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The circuit pattern layers may also be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0131] The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 25 μm. If the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 is less than 10 μm, the resistance of the circuit pattern increases, which can reduce signal transmission efficiency. For example, if the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 is less than 10 μm, signal transmission loss can increase. For example, if the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 is more than 25 μm, the line width of the circuit pattern increases, which can increase the overall volume of the circuit board.

[0132] The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 can be formed using conventional printed circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed description thereof will be omitted here.

[0133] 3, the first circuit pattern layer 121 may include a first electrode pad 121-1 disposed on the first region R1 of the first insulating layer 111. The first electrode pad 121-1 may vertically overlap the cavity 150. Therefore, the first electrode pad 121-1 may not be in contact with the second insulating layer 112.

[0134] The first circuit pattern layer 121 may include a second electrode pad 121-2 disposed on the second region R2 of the first insulating layer 111. The second electrode pad 121-2 may not vertically overlap the cavity 150. Therefore, the second electrode pad 121-2 may be covered by the second insulating layer 112.

[0135] The first circuit pattern layer 121 may further include a dummy electrode 121-2 arranged in the first region R1 of the first insulating layer 111. The dummy electrode 121-2 may be arranged in an area of ​​the first region R1 of the first insulating layer 111 where the first electrode pad 121-1 is not arranged.

[0136] For example, in the circuit board of the first embodiment, a dummy electrode 121-2 spaced apart from the first electrode pad 121-1 may be disposed on the first region R1 of the first insulating layer 111. The dummy electrode 121-2 may protect a portion of the first region R1 of the first insulating layer 111 where the first electrode pad 121-1 is not disposed. For example, the dummy electrode 121-2 may also be referred to as a protective electrode or barrier electrode that protects the first region R1 of the first insulating layer 111.

[0137] That is, only the first electrode pad 121-1 is disposed in the first region R1 of the first insulating layer 111 of a general circuit board. In this case, if a desmear process is performed after the formation of the cavity 150 without disposing the dummy electrode 121-2, the region of the first region R1 of the first insulating layer 111 where the first electrode pad 121-1 is not disposed may also be etched. When the first region R1 of the first insulating layer 111 is etched in the desmear process, a problem may occur in that glass fibers contained in the first insulating layer 111 are exposed through the cavity 150. The exposed glass fibers may cause reliability problems such as copper migration.

[0138] Therefore, in the circuit board of the embodiment, the dummy electrode 121-2 is disposed in a portion of the first region R1 of the first insulating layer 111 where the first electrode pad 121-1 is not disposed. The dummy electrode 121-2 can prevent etching of the first region R1 of the first insulating layer 111 during the desmear process. As a result, the embodiment can prevent reliability problems such as copper migration that occur due to etching of the first region R1 of the first insulating layer 111. Therefore, the embodiment can improve the electrical reliability of the circuit board.

[0139] As a result, the embodiment may be advantageous in selecting desmear process conditions because it is not necessary to consider damage to the first insulating layer 111 during the desmear process. As a result, the embodiment may improve the adhesion between the second insulating layer 112 and the second circuit pattern layer 122 disposed on the second insulating layer 112. Specifically, the cavity 150 may be formed together with the through hole in the process of forming the through hole corresponding to the second through electrode 132 in the second insulating layer 112. As a result, in the embodiment, the second circuit pattern layer 122 may be disposed on the second insulating layer 112 after the desmear process. Therefore, the embodiment is advantageous in selecting desmear process conditions, and the desmear process may be performed under conditions that can improve the adhesion between the second insulating layer 112 and the second circuit pattern layer 122. As a result, the embodiment may improve the adhesion between the second insulating layer 112 and the second circuit pattern layer 122.

[0140] The dummy electrode 121-2 may be spaced apart from the first electrode pad 121-1 on the first region R1. For example, the dummy electrode 121-2 may be disposed so as to surround the first electrode pad 121-1 without contacting the first electrode pad 121-1. For example, the dummy electrode 121-2 may be spaced apart from the first electrode pad 121-1 by a first width W1. The first width W1 may be in the range of 10 μm to 30 μm. For example, the first width W1 may be in the range of 12 μm to 28 μm. For example, the first width W1 may be in the range of 15 μm to 25 μm.

[0141] If the first width W1 is less than 10 μm, a problem may occur in that the connecting member is connected to the dummy electrode 121-2 when the connecting member is disposed on the first electrode pad 121-1. In this case, the dummy electrode 121-2 is not electrically connected to other patterns on the first circuit pattern layer 121, so a problem such as a short circuit does not occur even if the connecting member is connected to the dummy electrode 121-2. However, if the connecting member is connected to the dummy electrode 121-2, the signal transmission characteristics between the connecting member and the first circuit pattern layer 121 may be degraded. For example, if the first width W1 is less than 10 μm, the electrical characteristics of the circuit board may be degraded.

[0142] If the first width W1 exceeds 30 μm, an etchant used in a desmear process may penetrate into the space between the first electrode pad 121-1 and the dummy electrode 121-2. If the etchant penetrates, a problem may occur in that the top surface of the space in the first insulating layer 111 may also be etched.

[0143] The first circuit pattern layer 121 is disposed to occupy at least a certain area of ​​the entire area of ​​the first region R1 of the first insulating layer 111. Specifically, the first circuit pattern layer 121 may include a first circuit pattern portion disposed in the first region R1 of the first insulating layer 111 and a second circuit pattern portion disposed in the second region R2. In this case, the first circuit pattern portion may refer to the first electrode pads 121-1 and the dummy electrodes 121-2. Furthermore, the second circuit pattern portion may refer to the second electrode pads.

[0144] The planar area of ​​the first circuit pattern portion can be in the range of 50% to 90% of the planar area of ​​the first region R1 of the first insulating layer 111. The planar area of ​​the first circuit pattern portion can be in the range of 50% to 90% of the planar area of ​​the first region R1 of the first insulating layer 111. For example, the planar area of ​​the first circuit pattern portion can be in the range of 55% to 85% of the planar area of ​​the first region R1 of the first insulating layer 111. For example, the planar area of ​​the first circuit pattern portion can be in the range of 60% to 85% of the planar area of ​​the first region R1 of the first insulating layer 111. In other words, the planar area of ​​the portion of the first region R1 of the first insulating layer 111 that contacts the first circuit pattern layer 121 can be in the range of 50% to 90%, 55% to 85%, or 60% to 85% of the entire planar area of ​​the first region R1. That is, the planar area of ​​the portion of the first region R1 of the first insulating layer 111 that does not contact the first circuit pattern layer 121 can be in the range of 10% to 50%, 15% to 45%, or 15% to 40% of the total planar area of ​​the first region R1.

[0145] If the planar area of ​​the first circuit pattern portion is less than 50% of the planar area of ​​the first region R1 of the first insulating layer 111, a problem may occur in that the upper surface of the first region R1 of the first insulating layer 111 where the first circuit pattern portion is not arranged is etched in the desmearing process after the formation of the cavity 150. Furthermore, if the planar area of ​​the first circuit pattern portion exceeds 90% of the planar area of ​​the first region R1 of the first insulating layer 111, a problem may occur in that part of the connecting member comes into contact with the dummy electrode 121-2 in the process of arranging the connecting member.

[0146] The dummy electrode 121-2 does not contact the second insulating layer 112. The dummy electrode 121-2 may be disposed only on the first region R1 of the first insulating layer 111. Furthermore, the dummy electrode 121-2 may not contact the sidewall of the second insulating layer 112 that comprises the cavity 150.

[0147] Referring again to Figure 2, the circuit board of the embodiment includes a through electrode. The through electrode can function to electrically connect circuit pattern layers arranged on different layers. The through electrode can also be called a "via."

[0148] The through electrodes penetrate the first insulating layer 111 and the second insulating layer 112 included in the circuit board, thereby electrically connecting circuit patterns arranged on different layers. In this case, the through electrodes may be formed by penetrating only one insulating layer, or alternatively, may be formed by penetrating at least two or more insulating layers in common.

[0149] For example, the circuit board includes a first through electrode 131. The first through electrode 131 may be formed to penetrate the first insulating layer 111. The first through electrode 131 may electrically connect the first circuit pattern layer 121 and the third circuit pattern layer 123. For example, the upper surface of the first through electrode 131 may be directly connected to the lower surface of the first circuit pattern layer 121. For example, the lower surface of the first through electrode 131 may be directly connected to the third circuit pattern layer 123.

[0150] As a result, the first circuit pattern layer 121 and the third circuit pattern layer 123 are electrically connected to each other through the first through electrodes 131, and can transmit signals.

[0151] In this case, the first through-electrode 131 may include a first through portion connected to the first electrode pad 121-1 and a second through portion connected to the second electrode pad 121-2. In the first embodiment, the dummy electrode 121-2 is disposed in the first region R1, so that the first electrode pad 121-1 and the second electrode pad 121-2 cannot be directly connected to each other on the first insulating layer 111. Therefore, the first electrode pad 121-1 and the second electrode pad 121-2 in the first embodiment may be electrically connected to each other via the first through portion and the second through portion of the first through-electrode 131.

[0152] The circuit board also includes a second through electrode 132. The second through electrode 132 may be formed to penetrate the second insulating layer 112. The second through electrode 132 may electrically connect the first circuit pattern layer 121 and the second circuit pattern layer 122. For example, a lower surface of the second through electrode 132 may be directly connected to the first circuit pattern layer 121. For example, an upper surface of the second through electrode 132 may be directly connected to the second circuit pattern layer 122. As a result, the first circuit pattern layer 121 and the second circuit pattern layer 122 may be directly electrically connected to each other via the second through electrode 132, thereby transmitting signals.

[0153] The first through electrode 131 and the second through electrode 132 can be formed by forming through holes that penetrate the first insulating layer 111 and the second insulating layer 112, and filling the insides of the formed through holes with a conductive material.

[0154] The through holes may be formed by any one of mechanical, laser, and chemical processing methods. When the through holes are formed by mechanical processing, methods such as milling, drilling, and routing may be used. When the through holes are formed by laser processing, methods such as UV or CO2 laser may be used. When the through holes are formed by chemical processing, chemicals including aminosilanes, ketones, etc. may be used, and at least one of the insulating layers may be opened through this.

[0155] Once the through holes are formed, the insides of the through holes can be filled with a conductive material to form the first through electrode 131 and the second through electrode 132. The metal material forming the first through electrode 131 and the second through electrode 132 can be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the conductive material can be filled by any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet printing, and dispensing.

[0156] The circuit board may include a first protective layer 141 and a second protective layer 142. The first protective layer 141 and the second protective layer 142 may be disposed on the outermost portions of the circuit board. For example, the first protective layer 141 may be disposed on the first outermost or bottom side of the circuit board. For example, the first protective layer 141 may be disposed on the lower surface of the first insulating layer 111. For example, the second protective layer 142 may be disposed on the second outermost or top side of the circuit board. For example, the second protective layer 142 may be disposed on the upper surface of the second insulating layer 112. The first protective layer 141 may include at least one opening (not shown). For example, the first protective layer 141 may include an opening that vertically overlaps at least one of the third circuit pattern layers 123. For example, the first protective layer 141 may include an opening that vertically overlaps a terminal electrode pad (not shown) of the third circuit pattern layer 123, on which a conductive coupling portion for connection to an external circuit board is disposed. The second protective layer 142 may include at least one opening (not shown). For example, the second protective layer 142 may include an opening that vertically overlaps at least one of the second circuit pattern layers 122. For example, the second protective layer 142 may include an opening that vertically overlaps a terminal electrode pad (not shown) of the second circuit pattern layer 122, on which a conductive coupling portion for connecting to a memory circuit board or an interposer circuit board is disposed. The second protective layer 142 may also include a through-hole (not shown) that vertically overlaps the cavity 121 of the second insulating layer 112. The first protective layer 141 and the second protective layer 142 may include an insulating material. The first protective layer 141 and the second protective layer 142 may include various materials that can be applied and then cured by heating to protect the surfaces of the insulating layer and the circuit pattern layer. The first protective layer 141 and the second protective layer 142 may be resist layers. For example, the first protective layer 141 and the second protective layer 142 may be solder resist layers containing an organic polymer material. As an example, the first protective layer 141 and the second protective layer 142 may contain an epoxy acrylate resin. In particular, the first protective layer 141 and the second protective layer 142 may contain a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc.However, the embodiment is not limited thereto, and it goes without saying that the first protective layer 141 and the second protective layer 142 may be any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0157] A surface treatment layer (not shown) may be disposed within the openings of the first protective layer 141 and the second protective layer 142 that vertically overlap the second circuit pattern layer 122 and the third circuit pattern layer 123. The surface treatment layer may be formed to improve soldering properties while preventing corrosion and oxidation of the surfaces of the third circuit pattern layer 123, which vertically overlaps the openings of the first protective layer 141, and the second circuit pattern layer 122, which vertically overlaps the openings of the second protective layer 142. The surface treatment layer may be an organic solderability preservative (OSP) layer. For example, the surface treatment layer may be an organic layer formed of an organic substance such as benzimidazole. However, examples are not limited thereto. For example, the surface treatment layer may be a plating layer. For example, the surface treatment layer may include at least one of a nickel (Ni) plating layer, a palladium (Pd) plating layer, and a gold (Au) plating layer.

[0158] The first electrode pads 121-1, the second electrode pads 121-2, and the dummy electrodes 121-2 of the first circuit pattern layer 121 may have the same layer structure.

[0159] According to the embodiment of FIG. 4, the first circuit pattern layer 121 includes a plurality of metal layers. The first circuit pattern layer 121 includes a first metal layer 121a disposed on the first insulating layer 111. The first metal layer 121a may be a seed layer for electrolytic plating of the second metal layer 121b of the first circuit pattern layer 121. For example, the first metal layer 121a may be a chemical copper plating layer. For example, the first metal layer 121a may be a copper foil layer (Cu foil). In one embodiment, the first metal layer 121a may include only one of a chemical copper plating layer and a copper foil layer. In another embodiment, the first metal layer 121a may include both a chemical copper plating layer and a copper foil layer. The thickness of the first metal layer 121a may be in the range of 1.0 μm to 4.0 μm. Preferably, the thickness of the first metal layer 121a may be in the range of 1.2 μm to 3.5 μm. More preferably, the thickness of the first metal layer 121a is in the range of 1.5 μm to 3.0 μm. If the thickness of the first metal layer 121a is less than 1.0 μm, the first metal layer 121a may not function as a seed layer. If the thickness of the first metal layer 121a is less than 1.0 μm, it may be difficult to form the first metal layer 121a with a uniform thickness on the upper surface of the first insulating layer 111. If the thickness of the first metal layer 121a is greater than 4.0 μm, the time required to etch the first metal layer 121a may increase. If the thickness of the first metal layer 121a is greater than 4.0 μm, deformation of the second metal layer 121b may occur during etching of the first metal layer 121a. Deformation of the second metal layer 121b may mean that the side portions of the first metal layer 121a are also etched, increasing the difference between the width of the upper surface and the width of the lower surface of the second metal layer 121b.

[0160] The second metal layer 121b is disposed on the first metal layer 121a. The second metal layer 121b may be an electroplated layer formed by electroplating using the first metal layer 121a as a seed layer. The thickness of the second metal layer 121b may correspond to the total thickness of the first circuit pattern layer 121 minus the thickness of the first metal layer 121a. The total thickness of the first circuit pattern layer 121 has already been described above, so a detailed description thereof will be omitted. Meanwhile, the first electrode pad 121-1, the second electrode pad 121-2, and the dummy electrode 121-2 of the first circuit pattern layer 121 each include a first metal layer 121a and a second metal layer 121b. In this case, the first electrode pad 121-1, the second electrode pad 121-2, and the dummy electrode 121-2 refer to a circuit pattern including the same first metal layer 121a and second metal layer 121b, which may be divided according to their placement positions and functions.

[0161] According to the embodiment of FIG. 5, the dummy electrode 121-2 may have a thickness different from the thickness of at least one of the first electrode pad 121-1 and the second electrode pad 121-2. For example, the dummy electrode 121-2 may have a layer structure different from that of at least one of the first electrode pad 121-1 and the second electrode pad 121-2. For example, each of the first electrode pad 121-1 and the second electrode pad 121-2 may include a first metal layer 121a and a second metal layer 121b. In contrast, the dummy electrode 121-2 may include only the first metal layer 121a. This means that, in the process of forming the first circuit pattern layer 121, the second metal layer 121b may not be formed in the portion corresponding to the dummy electrode 121-2. Therefore, the dummy electrode 121-2 may include only the first metal layer 121a, unlike the first electrode pad 121-1 and the second electrode pad 121-2. Through this, the embodiment may reduce the process time for manufacturing the first circuit pattern layer 121. Furthermore, the embodiment may reduce the cost or materials required for manufacturing the circuit board.

[0162] 6 is a cross-sectional view showing a first modified example of the circuit board of FIG. 2, FIG. 7 is a plan view of the circuit board of FIG. 6 with some components removed, and FIG. 8 is a cross-sectional view showing a second modified example of the circuit board of FIG. 2.

[0163] Referring to FIGS. 6 and 7, the circuit board of the first modified example may differ from the circuit board of the first embodiment in the arrangement positions of the dummy electrodes.

[0164] Specifically, the circuit board of the first modified example may include a dummy electrode 121-2A disposed on the first insulating layer 111. The dummy electrode 121-2A may include a portion in contact with the second insulating layer 112.

[0165] For example, at least a portion of the portion of the dummy electrode 121-2A that is disposed in the frame region of the bottom surface of the cavity 150 may be in contact with the second insulating layer 112. For example, the dummy electrode 121-2A may include a portion that extends from the portion disposed in the first region R1 to be disposed in the second region R2. Therefore, at least a portion of the upper surface of the dummy electrode 121-2A may be covered by the second insulating layer 112. Specifically, the dummy electrode 121-2A may include a first portion 121-2A1 that is disposed in the first region R1 and has an upper surface exposed through the cavity 150. The dummy electrode 121-2A may also include a second portion 121-2A2 that is disposed in the second region R2 and has an upper surface covered by the second insulating layer 112. The first portion 121-2A1 and the second portion 121-2A2 of the dummy electrode 121-2A may be connected to each other.

[0166] As a result, in the embodiment, at least a portion of the dummy electrode 121-2A can be covered by the second insulating layer 112. As a result, there may be no separation region between the dummy electrode 121-2A and the sidewall of the cavity 150. Therefore, in the embodiment, it is possible to prevent the etching solution used in the desmear process from penetrating into the separation region between the sidewall of the cavity 150 and the dummy electrode 121-2A.

[0167] 8, the circuit board of the second modified example may differ from the circuit board of the first embodiment in the arrangement position of the dummy electrode. Specifically, the circuit board of the second modified example may include a dummy electrode 121-2B arranged on the first insulating layer 111. The dummy electrode 121-2B may include a portion in contact with the second insulating layer 112. For example, at least a portion of the portion of the dummy electrode 121-2B arranged in the frame region of the bottom surface of the cavity 150 may contact the second insulating layer 112. For example, the dummy electrode 121-2B may be arranged only in the first region R1. In this case, the frame of the dummy electrode 121-2B may correspond to the sidewall of the cavity 150. For example, the side of the frame of the dummy electrode 121-2B may be covered by the second insulating layer 112 that includes the cavity 150.

[0168] That is, in the first modified example, at least a portion of the dummy electrode 121-2A is arranged in the second region R2, thereby providing a structure in which a portion of the upper surface of the dummy electrode 121-2A is covered with the second insulating layer 112. In the second modified example, the dummy electrode 121-2B is arranged only in the first region R1, thereby providing a structure in which only a portion of the side surface of the dummy electrode 121-2B is covered with the second insulating layer 112.

[0169] FIG. 9 is a cross-sectional view showing a circuit board according to the second embodiment.

[0170] Referring to FIG. 9, the circuit board of the second embodiment may have a different structure of the first through electrodes 131 compared to the circuit board of the first embodiment.

[0171] The first through electrode 131 of the circuit board of the first embodiment is connected to the first electrode pad 121-1 and the second electrode pad 121-2, and may not be connected to the dummy electrode 121-2. The circuit board of the second embodiment may include multiple through holes depending on their positions.

[0172] For example, the first through-electrode 131 may include a first through-portion 131-1 that vertically overlaps the first region R1. The first through-portion 131-1 may vertically overlap the first electrode pad 121-1. For example, the first through-portion 131-1 may be a signal through-electrode connected to the first electrode pad 121-1.

[0173] The first through-hole electrode 131 may also include a second through-hole portion 131-2 that vertically overlaps the first region R1 and is horizontally spaced apart from the first through-hole portion 131-1. The second through-hole portion 131-2 may vertically overlap the dummy electrode 121-2. For example, the second through-hole portion 131-2 may be a dummy through-hole electrode connected to the dummy electrode 121-2. In this case, a plurality of second through-hole portions 131-2 may be provided. For example, the second through-hole portion 131-2 may include a plurality of through-hole portions that are horizontally spaced apart and commonly connected to one dummy electrode 121-2.

[0174] In this case, the dummy electrodes 121-2 and the second through portions 131-2 may function to improve the heat dissipation characteristics of the circuit board. For example, the dummy electrodes 121-2 and the second through portions 131-2 may transfer heat generated from the connecting member disposed in the cavity 150 to the outside of the circuit board. As a result, the embodiment may improve the heat dissipation characteristics of the circuit board and a semiconductor package including the same. Therefore, the embodiment may improve the product reliability of the circuit board and a semiconductor package including the same.

[0175] The first through-electrode 131 may also include a third through-hole 131-3 that vertically overlaps the second region R2. The third through-hole 131-3 may vertically overlap the second electrode pad 121-2. The third through-hole 131-3 may be electrically connected to the second electrode pad 121-2.

[0176] FIG. 10 is a cross-sectional view showing a circuit board according to the third embodiment, and FIG. 11 is a plan view of the circuit board of FIG. 10 with some components removed.

[0177] 10 and 11, the circuit board of the third embodiment may have a different structure of the first circuit pattern layer 121 compared to the circuit board of the first embodiment.

[0178] The circuit board of the third embodiment may include a first insulating layer 211, a second insulating layer 212, a first circuit pattern layer 221, a second circuit pattern layer 222, a third circuit pattern layer 223, a first through electrode 231, a second through electrode 232, a first protective layer 241, and a second protective layer 242.

[0179] The first insulating layer 211, the second insulating layer 212, the second circuit pattern layer 222, the third circuit pattern layer 223, the first through electrode 231, the second through electrode 232, the first protective layer 241, and the second protective layer 242 have the same structure as the corresponding configurations of the circuit board of the first embodiment, and detailed description thereof will be omitted.

[0180] The first circuit pattern layer 221 may include a first electrode pad 221-1 arranged in a first region R1, and may also include a second electrode pad 221-3 arranged in a second region R2.

[0181] The first circuit pattern layer 221 may also include a dummy electrode 221-2 disposed in the first region R1 and electrically and physically separated from the first electrode pad 221-1.

[0182] On the other hand, in the first embodiment, the first electrode pad and the second electrode pad are not directly connected to each other by the first circuit pattern layer.

[0183] Alternatively, the first electrode pad 221-1 and the second electrode pad 221-3 of the first circuit pattern layer 221 of the third embodiment may be directly connected to each other by the first circuit pattern layer 221.

[0184] Specifically, the first electrode pad 221-1 and the second electrode pad 221-3 can transmit and receive electrical signals to and from each other on the first insulating layer 111 without being connected to the first through-electrode 231.

[0185] For this purpose, the first circuit pattern layer 221 may include a connecting pattern 221-4.

[0186] The connecting pattern 221-4 may be disposed on the first region R1 and the second region R2 of the first insulating layer 211. In this case, the first circuit pattern layer 221 may include a plurality of connecting patterns, and the connecting pattern 221-4 described below may refer to a connecting pattern that connects the first electrode pad 221-1 and the second electrode pad 221-3 among the plurality of connecting patterns.

[0187] The connecting pattern 221-4 may directly connect the first electrode pad 221-1 arranged in the first region R1 to the second electrode pad 221-3 arranged in the second region R2. This reduces the signal transmission distance between the first electrode pad 221-1 and the second electrode pad 221-3. Therefore, the embodiment may minimize signal transmission loss and further improve the electrical characteristics of the circuit board and a semiconductor package including the same.

[0188] The connecting pattern 221-4 may be disposed in the first region R1 and may include a first portion 221-41 connected to the first electrode pad 221-1. The connecting pattern 221-4 may also be disposed in the second region R2 and may include a second portion 221-42 connected to the second electrode pad 221-3. The first portion 221-41 and the second portion 221-42 of the connecting pattern 221-4 may be directly connected to each other. Therefore, the first electrode pad 221-1 and the second electrode pad 221-3 may directly transmit and receive electrical signals to and from each other using the connecting pattern 221-4 without using the first through electrode 231. Therefore, in the embodiment, the circuit integration density of the circuit board may be improved by disposing the connecting pattern 221-4 in the first region R1 of the first insulating layer 211.

[0189] The connecting pattern 221-4 may be in contact with the first electrode pad 221-1 in the first region R1 but may be physically separated from the dummy electrode 221-2. Furthermore, in the first embodiment, the first circuit pattern portion occupying 50% to 90%, 55% to 85%, or 60% to 85% of the total area of ​​the first region R1 includes the first electrode pad 121-1 and the dummy electrode 121-2. In the third embodiment, the first circuit pattern portion occupying 50% to 90%, 55% to 85%, or 60% to 85% of the total area of ​​the first region R1 may include the first electrode pad 221-1, the dummy electrode 221-2, and the connecting pattern 221-4.

[0190] FIG. 12 is a cross-sectional view showing a circuit board according to the fourth embodiment, and FIG. 13 is a plan view of the circuit board of FIG. 12 with some components removed.

[0191] Referring to FIGS. 12 and 13, the circuit board of the fourth embodiment may have a different structure of the first circuit pattern layer compared to the circuit board of the third embodiment.

[0192] The circuit board of the fourth embodiment may include a first insulating layer 311, a second insulating layer 312, a first circuit pattern layer 321, a second circuit pattern layer 322, a third circuit pattern layer 323, a first through electrode 331, a second through electrode 332, a first protective layer 341, and a second protective layer 342.

[0193] The first insulating layer 311, the second insulating layer 312, the second circuit pattern layer 322, the third circuit pattern layer 323, the first through electrode 331, the second through electrode 332, the first protective layer 341, and the second protective layer 342 have the same structure as the corresponding configurations of the circuit board of the third embodiment, and detailed description thereof will be omitted.

[0194] The first circuit pattern layer 321 may include a first electrode pad 321-1 arranged in the first region R1. The second circuit pattern layer 321 may include a second electrode pad 321-3 arranged in the second region R2. The first circuit pattern layer 321 may include a connecting pattern 321-4 arranged in the first region R1. Unlike the third embodiment, the first circuit pattern layer 321 of the circuit board of the fourth embodiment does not need to include a dummy electrode. That is, in the circuit boards of the first and second embodiments, the first circuit pattern portion includes a first electrode pad and a dummy electrode, and the arrangement of the dummy electrode can protect the upper surface of the first insulating layer during the desmear process.

[0195] In the circuit board of the third embodiment, the first circuit pattern portion includes a first electrode pad, a dummy electrode, and a connecting pattern, and the arrangement of the connecting pattern and the dummy electrode can directly connect the first electrode pad and the second electrode pad while protecting the upper surface of the first insulating layer.

[0196] In addition, in the circuit board of the fourth embodiment, the first circuit pattern portion may include a first electrode pad 321-1 and a connecting pattern 321-4. In the fourth embodiment, the first electrode pad 321-1 and the second electrode pad 321-3 may be directly connected to each other while protecting the top surface of the first region R1 of the first insulating layer 311 using the connecting pattern 321-4 without disposing a dummy electrode.

[0197] Therefore, in the fourth embodiment, the first circuit pattern portion occupying 50% to 90%, 55% to 85%, or 60% to 85% of the total area of ​​the first region R1 can include the first electrode pad 321-1 and the connecting pattern 321-4. In this case, if only the connecting pattern directly connecting the first electrode pad 321-1 and the second electrode pad 321-3 is arranged, the first circuit pattern portion does not need to occupy 50% or more of the total area of ​​the first region R1. As a result, connecting patterns other than the connecting pattern connecting the first electrode pad 321-1 and the second electrode pad 321-3 can also be arranged in the first region R1.

[0198] 13, the connecting pattern 321-4 may include a first connecting pattern 321-41 disposed in the first region R1 and the second region R2 and connecting the first electrode pad 321-1 to the second electrode pad 321-3. The connecting pattern 321-4 may also include a second connecting pattern 321-42 disposed in the first region R1 and the second region R2 and connecting the second electrode pads. That is, the second connecting pattern 321-42 connects the second electrode pads disposed in the second region R2. Conventionally, the connecting pattern connecting the second electrode pads has not been disposed in the first region R1, which perpendicularly overlaps the cavity. This is because the second insulating layer having the cavity contains a thermosetting material, not a photo-curable material such as PID, which eliminates the need to form a fine pattern within the cavity. Therefore, even if the glass fibers of the first insulating layer are partially exposed during the desmear process, reliability is not significantly affected.

[0199] Alternatively, the embodiment may include second connection patterns 321-42 that connect the second electrode pads together. The second connection patterns 321-42 may electrically connect the second electrode pads together through the first region R1. This allows the embodiment to further improve the circuit integration of the circuit board and the semiconductor package.

[0200] FIG. 14 is a diagram showing a semiconductor package including the circuit board of FIG.

[0201] 14, the package circuit board may include a connection member 410 disposed on a first electrode pad 121-1 and a connecting member 420 disposed on the connection member 410. The connecting member may be any one of the second circuit board, the semiconductor device, and the connecting member described with reference to FIGS. 1a to 1g.

[0202] A molding member 430 may be disposed in the cavity 150. The molding member 430 may be disposed in the cavity 150 by molding the connecting member 420. The molding member 430 may also mold the dummy electrode 121-2. In this case, the molding member 430 is connected to the dummy electrode 121-2, thereby dissipating heat transferred via the dummy electrode 121-2 to the outside. The molding member 430 may have a low dielectric constant to enhance heat dissipation characteristics. For example, the dielectric constant Dk of the molding member 430 may be 0.2 to 10. For example, the dielectric constant Dk of the molding member 430 may be 0.5 to 8. For example, the dielectric constant Dk of the molding member 430 may be 0.8 to 5. Thus, in this embodiment, the molding member 430 has a low dielectric constant, thereby enhancing the heat dissipation characteristics of the connecting member.

[0203] 15 to 20 are diagrams showing the manufacturing method of the circuit board of FIG. 2 according to the embodiment in the order of steps.

[0204] 15 , an embodiment provides an insulating member based on the manufacture of a circuit board. For example, the embodiment provides an insulating member including a first insulating layer 111 and a metal layer on the first insulating layer 111. The metal layer may include a metal layer 121a disposed on the first insulating layer 111 and a metal layer 123a disposed below the first insulating layer 111. The metal layer 121a may be used as a seed layer for forming a first circuit pattern layer 121 by electroplating. The metal layer 123a may be used as a seed layer for forming a third circuit pattern layer 123 by electroplating.

[0205] 16 , in an embodiment, electrolytic plating is performed using metal layers 121a and 123a as seed layers to form first through electrodes 131 that penetrate the second metal layer of the first circuit pattern layer 121, the second metal layer of the third circuit pattern layer 123, and the first insulating layer 111. In this case, in one embodiment, the formed first circuit pattern layer 121 may include first electrode pads, second electrode pads, and dummy electrodes. In another embodiment, the first circuit pattern layer 121 may include first electrode pads, second electrode pads, dummy electrodes, and a connecting pattern. In still another embodiment, the first circuit pattern layer 121 may include first electrode pads, second electrode pads, and a connecting pattern.

[0206] 17, in this embodiment, a second insulating layer 112 may be disposed on a first insulating layer 111. At this time, a first metal layer 122a of the second circuit pattern layer 122, which is a seed layer of the second circuit pattern layer 122, may be disposed on the upper surface of the second insulating layer 112.

[0207] 18 , in an embodiment, a second metal layer 122b of the second circuit pattern layer 122 may be formed by performing electrolytic plating using the first metal layer 122a of the second circuit pattern layer 122 as a seed layer. At this time, a second through electrode 132 penetrating the second insulating layer 112 may be formed together with the second metal layer 122b. At this time, in the drawing, the process of forming the second through electrode 132 and the process of forming the cavity 150 are shown as separate processes. However, the embodiment is not limited thereto. For example, the cavity 150 may be formed together with the through hole in the process of forming the through hole for the second through electrode 132.

[0208] Next, referring to FIG. 19, a process of exposing and developing the first region R1 of the first insulating layer 112 to form the cavity 150 can be performed.

[0209] Next, referring to FIG. 20, in an embodiment, a process of forming a first protective layer 141 under the first insulating layer 111 and forming a second protective layer 142 on the second insulating layer 112 may be performed.

[0210] Fig. 21 is a cross-sectional view showing a circuit board of a fifth embodiment, Fig. 22 is a plan view of the circuit board of Fig. 21 with some components removed, Fig. 23 is a cross-sectional view of one embodiment taken along the A-A' direction of Fig. 21, Fig. 24 is a diagram showing the planar shape of the second through electrode of Fig. 21, and Fig. 25 is a diagram showing the planar shape of the cavity of Fig. 21. The circuit board of the fifth embodiment will be described below with reference to Figs. 21 to 25, but detailed descriptions of components that are the same as or correspond to those of the circuit boards shown in Figs. 2 to 13 will be omitted.

[0211] The circuit board includes an insulating layer 1110, which may include a first insulating layer 1111, a second insulating layer 1112, and a third insulating layer 1113. Exemplarily, the circuit board may further include a third insulating layer 1113 in addition to the insulating layers of the circuit boards shown in FIGS.

[0212] The first insulating layer 1111 may include a first layer 1111-1, a second layer 1111-2, a third layer 1111-3, and a fourth layer 1111-4, but this embodiment is not limited thereto, and the number of layers of the first insulating layer 1111 may vary depending on the embodiment. The second insulating layer 1112 may be disposed on the first insulating layer 1111. The second insulating layer 1112 may include a cavity 1150. If the second insulating layer 1112 is formed of multiple layers, the cavity 1150 may penetrate the multiple layers of the second insulating layer. The third insulating layer 1113 may be disposed below the first insulating layer 1111. Each of the second insulating layer 1112 and the third insulating layer 1113 may be formed of multiple layers, but for convenience of explanation, they will be described below as being formed of a single layer. In this case, if the first insulating layer 1111 has a multi-layer structure, the upper surface of the first insulating layer 1111 described below may refer to the upper surface of the uppermost layer of the first insulating layer 1111, and the lower surface of the first insulating layer 1111 may refer to the lower surface of the lowermost layer of the first insulating layer 1111. The first insulating layer 1111, the second insulating layer 1112, and the third insulating layer 1113 may contain different insulating materials. For example, the first insulating layer 1111 may contain a thermosetting resin. The second insulating layer 1112 and the third insulating layer 1113 may contain a photocurable resin.

[0213] 22 and 23, the second insulating layer 1112 may include a cavity 1150. The cavity 1150 may penetrate the upper and lower surfaces of the second insulating layer 1112. The cavity 1150 may include a bottom surface 1111US1 and a sidewall 1112IS. The cavity 1150 has been described with reference to FIGS. 2 to 13, so a detailed description thereof will be omitted.

[0214] The cavity 1150 may be formed by exposing and developing the second insulating layer 1112 containing a photocurable resin. Therefore, the planar shape of the cavity 1150 may have various shapes. For example, referring to (a) of FIG. 25, the planar shape of the cavity 1150 may be a square. For example, referring to (b) of FIG. 25, the planar shape of the cavity 1150 may be a plus (+) shape. For example, referring to (c) of FIG. 25, the planar shape of the cavity 1150 may be a square with an open central region. For example, referring to (d) of FIG. 25, the planar shape of the cavity 1150 may be an "L" shape.

[0215] The top surface of the first insulating layer 1111 may be divided into a plurality of regions. For example, the first insulating layer 1111 may include a first region that vertically overlaps the cavity 1150. In this case, if the width of the cavity 1150 varies in the thickness direction of the second insulating layer 1112, the first region may refer to a region that vertically overlaps a lower region of the cavity 1150 corresponding to the lower end of the sidewall 1112IS. The first insulating layer 1111 may also include a second region that does not vertically overlap the cavity 1150. The second region may refer to a region of the top surface of the first insulating layer 1111 that is covered by the second insulating layer 1112. The first insulating layer 1111 may also include a third region that does not vertically overlap the cavity 1150 and is not in contact with the second insulating layer 1112. The third region may correspond to a periphery region of the first insulating layer 1111. For example, the third region may correspond to an outer region of the top surface of the first insulating layer 1111 adjacent to the side surface of the first insulating layer 1111. The second insulating layer 1112 may not be disposed in the third region of the first insulating layer 1111. The outer width OW1 of the first insulating layer 1111 may be different from the outer width OW2 of the second insulating layer 1112. Preferably, the outer width OW1 of the first insulating layer 1111 may be larger than the outer width OW2 of the second insulating layer 1112. Here, the outer width may refer to the horizontal width and / or distance between two opposing outer surfaces of each insulating layer.

[0216] The outer surface 111OS of the insulating layer 1111 may be located outer than the outer surface 112OS of the second insulating layer 1112. The outer surface 112OS of the second insulating layer 1112 may be located inner than the outer surface 111OS of the first insulating layer 1111. The second insulating layer 1112 may include an open region vertically overlapping the third region of the first insulating layer 1111. Thus, the open region of the second insulating layer 1112 may be connected to the outer surface 112OS of the second insulating layer 1112. Therefore, the outer width OW2 of the second insulating layer 1112 may be smaller than the outer width OW1 of the first insulating layer 1111 by the width of the open region. For example, the outer width OW1 of the first insulating layer 1111 may be larger than the outer width OW2 of the second insulating layer 1112 by the width of the open region. The open region may refer to the second through hole VH2 shown in FIG. 34. The open region of the second insulating layer 1112 may be formed with through holes and cavities 1150 corresponding to the second through electrodes 1132. For example, the open region of the second insulating layer 1112 may be formed with the through holes and cavities 1150 through an exposure and development process. Therefore, the outer surface 112OS of the second insulating layer 1112 may have a slope. For example, the outer surface 112OS of the second insulating layer 1112 may be inclined at a constant slope from the upper surface of the second insulating layer 1112 toward the lower surface of the second insulating layer 1112. For example, the horizontal distance between the outer surface 112OS of the second insulating layer 1112 and the outer surface 111OS of the first insulating layer 1111 may be different from each other in the vertical direction.

[0217] The outer surface 112OS of the second insulating layer 1112 may have a slope such that the horizontal distance decreases as it approaches the outer surface 111OS of the first insulating layer 1111. However, embodiments are not limited thereto. For example, the outer surface 112OS of the second insulating layer 1112 may have a slope such that the horizontal distance increases as it approaches the outer surface 111OS of the first insulating layer 1111. The outer surface 112OS of the second insulating layer 1112 may have a slope such that the outer width OW2 of the second insulating layer 1112 changes from the upper surface of the second insulating layer 1111 toward the lower surface of the second insulating layer 1112. For example, the outer surface 112OS of the second insulating layer 1112 may have a slope such that the outer width OW2 of the second insulating layer 1112 increases from the upper surface of the second insulating layer 1111 toward the lower surface of the second insulating layer 1112. However, embodiments are not limited thereto. For example, the outer surface 112OS of the second insulating layer 1112 may have a slope such that the outer width OW2 of the second insulating layer 1112 decreases from the upper surface of the second insulating layer 1111 toward the lower surface of the second insulating layer 1112.

[0218] As a result, the outer surface 111OS of the first insulating layer 1111 and the outer surface 112OS of the second insulating layer 1112 may have a horizontal step. For example, the step may refer to the horizontal distance W1 between the outer surface 111OS of the first insulating layer 1111 and the outer surface 112OS of the second insulating layer 1112. The horizontal distance W1 may be in the range of 2 μm to 30 μm. For example, the horizontal distance W1 may be in the range of 3 μm to 28 μm. For example, the horizontal distance W1 may be in the range of 5 μm to 25 μm. If the horizontal distance W1 is less than 2 μm, the effect of improving the adhesion between the first insulating layer 1111 and the second insulating layer 1112 according to the embodiment may be insufficient. As a result, if the first insulating layer 1111 moves away from the second insulating layer 1112 and rises onto the first electrode pad portion during the mounting process of the semiconductor device, poor contact may occur during mounting of the semiconductor device. Furthermore, if the horizontal distance W1 exceeds 30 μm, the circuit integration density may be reduced. For example, if the horizontal distance W1 exceeds 30 μm, it may mean that the second circuit pattern layer 1122 cannot be disposed in the region of the second insulating layer 1112 corresponding to the horizontal distance W1 across the entire area of ​​the substrate. This may result in a decrease in circuit integration due to an increase in the area where the second circuit pattern layer 1122 cannot be disposed. As a result, the embodiment may improve the adhesion of the insulating layer 1110 of the circuit board.

[0219] For example, the first insulating layer 1111 and the second insulating layer 1112 may contain different insulating materials. Furthermore, the second insulating layer 1112 may contain a photocurable resin, unlike the first insulating layer 1111. This may reduce the adhesion between the first insulating layer 1111 and the second insulating layer 1112. Furthermore, the first insulating layer 1111 and the second insulating layer 1112 may have different thermal expansion coefficients. Therefore, the difference in thermal expansion coefficients between the first insulating layer 1111 and the second insulating layer 1112 may cause the board to warp significantly in a specific direction. In this case, the embodiment makes the outer width OW2 of the second insulating layer 1112 smaller than the outer width OW1 of the first insulating layer 1111. Therefore, the embodiment can prevent the circuit board from warping in a specific direction by the second insulating layer 1112. As a result, the embodiment can improve the physical and electrical reliability of the circuit board. Furthermore, in the embodiment, a first protective layer 1141 may be disposed on the second insulating layer 1112, enveloping the upper surface and outer surface 112OS of the second insulating layer 1112. The first protective layer 1141 may protect the circuit pattern layer disposed on the second insulating layer 1112 while improving adhesion between the first insulating layer 1111 and the second insulating layer 1112. This may improve adhesion between the first insulating layer 1111 and the second insulating layer 1112. This may solve the physical reliability problem of the second insulating layer 1112 peeling off from the first insulating layer 1111 or the circuit pattern layer disposed on the second insulating layer 1112 peeling off from the second insulating layer 1112. The structure of the first protective layer 1141 will be described in more detail below.

[0220] The third insulating layer 1113 may be disposed below the first insulating layer 1111. The layer structure of the third insulating layer 1113 may be symmetrical to the layer structure of the second insulating layer 1112 with respect to the first insulating layer 1111. This allows the embodiment to solve the problem of warpage of the circuit board caused by an asymmetric structure, thereby improving the electrical reliability and / or physical reliability of the circuit board and a semiconductor package including the same.

[0221] For example, the outer width of the third insulating layer 1113 may be smaller than the outer width OW1 of the first insulating layer 1111. This allows an outer surface 113OS of the third insulating layer 1113 and an outer surface 111OS of the first insulating layer 1111 to have a step.

[0222] 21, the outer surface 113OS of the third insulating layer 1113 and the outer surface 112OS of the second insulating layer 1112 are positioned on the same vertical line, but this is not limiting. For example, the outer surface 113OS of the third insulating layer 1113 and the outer surface 112OS of the second insulating layer 1112 may have a step based on the warping direction of the circuit board.

[0223] For example, if the circuit board warps significantly in a first vertical direction, the outer surface 112OS of the second insulating layer 1112 may be located further inward than the outer surface 113OS of the third insulating layer 1113. Conversely, if the circuit board warps significantly in a second vertical direction opposite the first vertical direction, the outer surface 112OS of the second insulating layer 1112 may be located further outward than the outer surface 113OS of the third insulating layer 1113.

[0224] A circuit pattern layer 1120 may be disposed on the first insulating layer 1111, the second insulating layer 1112, and the third insulating layer 1113.

[0225] For example, a first circuit pattern layer 1121 may be disposed on the first insulating layer 1111. For example, a first circuit pattern layer may be disposed on the lower surface of the first layer 1111-1 of the first insulating layer 1111, between the upper surface of the first layer 1111-1 and the lower surface of the second layer 1111-2, between the upper surface of the second layer 1111-2 and the lower surface of the third layer 1111-3, between the upper surface of the third layer 1111-3 and the lower surface of the fourth layer 1111-4, and on the upper surface of the fourth layer 1111-4.

[0226] A second circuit pattern layer 1122 may be disposed on the second insulating layer 1112. A third circuit pattern layer 1123 may be disposed under the third insulating layer 1113.

[0227] The first circuit pattern layer 1121 may include a plurality of circuit patterns disposed on the upper surface of the first insulating layer 1111. For example, the first circuit pattern layer 1121 may include a plurality of circuit patterns disposed on the fourth layer 1111-4 of the first insulating layer 1111.

[0228] The first circuit pattern layer 1121 may include a first electrode pad 1121-1 disposed on a first region of the first insulating layer 1111. The first electrode pad 1121-1 may vertically overlap the cavity 1150. Therefore, the first electrode pad 1121-1 may not be in contact with the second insulating layer 1112. The first circuit pattern layer 1121 may include a second electrode pad 1121-2 disposed on a second region of the first insulating layer 1111. The second electrode pad 1121-2 may not vertically overlap the cavity 1150. Therefore, the second electrode pad 1121-2 may be covered by the second insulating layer 1112.

[0229] 21 again, the circuit board of the embodiment may include a through electrode 1130. The through electrode 1130 may function to electrically connect circuit pattern layers arranged on different layers to each other. The through electrode may also be referred to as a "via."

[0230] The through electrode may penetrate at least one of the first insulating layer 1111, the second insulating layer 1112, and the third insulating layer 1113 included in the circuit board, thereby electrically connecting circuit patterns arranged on different layers. In this case, the through electrode 1130 may be formed by penetrating only one insulating layer, or alternatively, may be formed by penetrating at least two or more insulating layers in common.

[0231] The first through electrode 1131 may be formed to penetrate the first insulating layer 1111. For example, the first through electrode 1131 may penetrate at least one of the first layer 1111-1, the second layer 1111-2, the third layer 1111-3, and the fourth layer 1111-4 of the first insulating layer 1111. The first through electrode 1131 may electrically connect the first circuit pattern layers 1121 arranged on different layers of the first insulating layer 1111 to each other. The second through electrode 1132 may penetrate the second insulating layer 1112. The second through electrode 1132 may electrically connect the first circuit pattern layer 1121 and the second circuit pattern layer 1122. The third through electrode 1133 may penetrate the third insulating layer 1113. The third through electrode 1133 may electrically connect the first circuit pattern layer 1121 and the third circuit pattern layer 1123 .

[0232] The through-holes penetrating the first insulating layer 1111 and the through-holes penetrating the second insulating layer 1112 and the third insulating layer 1113 may be formed in different ways. For example, the first insulating layer 1111 may contain a thermosetting resin. Therefore, the through-holes may be formed in the first insulating layer 1111 through a laser process. For example, the second insulating layer 1112 and the third insulating layer 1113 may contain a photo-curable resin. The through-holes may be formed in the second insulating layer 1112 and the third insulating layer 1113 through an exposure and development process. Therefore, in one embodiment, the through-holes penetrating the first insulating layer 1111 and the through-holes penetrating the second insulating layer 1112 and the third insulating layer 1113 may have different planar shapes. Furthermore, in another embodiment, the through-holes penetrating the first insulating layer 1111 and the through-holes penetrating the second insulating layer 1112 and the third insulating layer 1113 may have the same planar shape. Therefore, according to the embodiment, the first through-hole electrode 1131 may have the same planar shape as the second through-hole electrode 1132 and the third through-hole electrode 1133, or may have different planar shapes. For example, the planar shape of the first through-hole electrode 1131 may be circular or elliptical. The second through-hole electrode 1132 and the third through-hole electrode 1133 may have various planar shapes.

[0233] For example, referring to (a) of FIG. 24, the planar shapes of the second through-hole electrode 1132 and the third through-hole electrode 1133 may be circular or elliptical, similar to the first through-hole electrode 1131. For example, referring to (b) of FIG. 24, the planar shapes of the second through-hole electrode 1132 and the third through-hole electrode 1133 may be rectangular, different from the first through-hole electrode 1131. For example, referring to (c) of FIG. 24, the planar shapes of the second through-hole electrode 1132 and the third through-hole electrode 1133 may be triangular, different from the first through-hole electrode 1131. That is, the second through-hole electrode 1132 and the third through-hole electrode 1133 may be filled in through-holes formed by exposure and development processes. Through-holes of various planar shapes can be formed through the exposure and development processes. Therefore, the second through-hole electrode 1132 and the third through-hole electrode 1133 may have the same planar shape as the first through-hole 1131, or may have different planar shapes.

[0234] The first protective layer 1141 and the second protective layer 1142 may be disposed on the outermost layer of the circuit board. For example, the first protective layer 1141 may be disposed on the uppermost side of the circuit board. For example, the first protective layer 1141 may be disposed on the second insulating layer 1112. For example, the second protective layer 1142 may be disposed on the lowermost side of the circuit board. The surfaces of the first protective layer 1141 and the second protective layer 1142 may have a step. For example, the lower surface of the first protective layer 1141 may have a step. For example, the upper surface of the second protective layer 1142 may have a step. Specifically, the first protective layer 1141 may be disposed on the second insulating layer 1112. The lower surface of the first protective layer 1141 may include a portion that is lower than the upper surface of the second insulating layer 1112. The lower surface of the first protective layer 1141 may include a portion located lower than the upper and lower surfaces of the second circuit pattern layer 1122. For example, the first protective layer 1141 may include a portion disposed in an open region of the second insulating layer 1112. The first protective layer 1141 may be provided to fill the open region of the second insulating layer 1112. Therefore, at least a portion of the first protective layer 1141 may be in contact with the first insulating layer 1111. For example, the first protective layer 1141 may be disposed on the first insulating layer 1111 to cover the second insulating layer 1112. Specifically, the first protective layer 1141 may include an opening that vertically overlaps with the cavity 1150. The first protective layer 1141 may also include a portion in contact with the upper surface 1112US of the second insulating layer 1112. Furthermore, the first protective layer 1141 may include a portion in contact with the outer surface 112OS of the second insulating layer 1112. The first protective layer 1141 may also include a portion in contact with the upper surface 111US2 of the third region of the first insulating layer 1111. The outer surface 112OS of the second insulating layer 1112 does not have to be exposed to the outside. That is, the outer surface 112OS of the second insulating layer 1112 does not have to be exposed to the outside because it is covered with the first protective layer 1141. Therefore, the outer surface of the circuit board of the embodiment may include a portion formed by the first insulating layer 1111 and a portion formed by the first protective layer 1141. In other words, the outer surface of the circuit board of the embodiment may not include a portion formed by the second insulating layer 1112.As a result, in an embodiment, the first protective layer 1141 may be disposed on the first insulating layer 1111 to surround the second insulating layer 1112. Therefore, in an embodiment, the physical reliability problem and / or electrical reliability problem of the second insulating layer 1112 and / or the second circuit pattern layer 1122 being separated from the first insulating layer 1111 may be solved. Correspondingly, the second protective layer 1142 may be disposed below the third insulating layer 1113. The upper surface of the second protective layer 1142 may include a portion positioned higher than the lower surface of the third insulating layer 1113. The upper surface of the second protective layer 1142 may also include portions positioned higher than the upper and lower surfaces of the third circuit pattern layer 1123. For example, the second protective layer 1142 may include a portion disposed in an open region of the third insulating layer 1113. The second protective layer 1142 may be provided to fill the open region of the third insulating layer 1113. Therefore, at least a portion of the second protective layer 1142 can be in contact with the first insulating layer 1111. For example, the second protective layer 1142 can be disposed below the first insulating layer 1111, covering the third insulating layer 1113. The second protective layer 1142 can include a portion in contact with the lower surface of the third insulating layer 1113, a portion in contact with the outer surface 113OS of the third insulating layer 1113, and a portion in contact with the lower surface of the first insulating layer 1111. As a result, the outer surface 113OS of the third insulating layer 1113 does not need to be exposed to the outside because it is covered by the second protective layer 1142. Therefore, the outer surface of the circuit board of the embodiment can include only a portion formed by the first insulating layer 1111, a portion formed by the first protective layer 1141, and a portion formed by the second protective layer 1142. In other words, the outer surface of the circuit board of the embodiment does not need to include a portion formed by the second insulating layer 1112 and a portion formed by the third insulating layer 1113. As a result, in an embodiment, the first protective layer 1141 and the second protective layer 1142 can be disposed above and / or below the first insulating layer 1111 to surround the second insulating layer 1112 and the third insulating layer 1113. Therefore, in an embodiment, it is possible to solve the physical reliability problem and / or the electrical reliability problem of the second insulating layer 1112, the second circuit pattern layer 1122, the third insulating layer 1113, and the third circuit pattern layer 1123 being separated from the first insulating layer 1111.

[0235] FIG. 26 is a cross-sectional view showing a circuit board according to a sixth embodiment.

[0236] Referring to Figure 26, the circuit board of the sixth embodiment is similar in structure to the circuit board of the first embodiment of Figure 21, but may differ from the structure of the circuit board of the first embodiment in that a cavity 1160 is provided in the third insulating layer 1113.

[0237] For example, a first cavity 1150 may be provided in the second insulating layer 1112. Also, a second cavity 1160 may be provided in the third insulating layer 1113. Therefore, the first circuit pattern layer 1121 may be disposed on the first insulating layer 1111 and may include a first electrode pad portion 1121-1a exposed through the first cavity 1150.

[0238] In addition, the first circuit pattern layer 1121 may include a second electrode pad portion 1121-1b disposed under the first insulating layer 1111 and exposed through the second cavity 1160.

[0239] FIG. 27 is a cross-sectional view showing a circuit board according to a seventh embodiment.

[0240] Referring to FIG. 27, the circuit board according to the seventh embodiment may have a different structure compared to the circuit board according to the fifth embodiment in terms of the thickness of the second insulating layer and the thickness of the through electrode penetrating the second insulating layer.

[0241] The second insulating layer 1112 is disposed on the first insulating layer 1111 and may contain a different insulating material from the first insulating layer 1111. In this case, the outer surface of the second insulating layer 1112 may have a step with respect to the outer surface of the first insulating layer 1111. Furthermore, the circuit board may have a symmetrical structure in which the second insulating layer 1112, which is an upper buildup layer, and the third insulating layer 1113, which is a lower buildup layer, are arranged symmetrically with respect to the first insulating layer 1111. This prevents the circuit board from warping significantly in a specific direction, and also ensures adhesion between the second insulating layer 1112 and the first insulating layer 1111.

[0242] Therefore, the embodiment can significantly reduce the thickness of the second insulating layer 1112 compared to the prior art. For example, in the prior art, the second insulating layer 1112 has a thickness above a certain level to prevent warping of the circuit board and ensure adhesion between layers of the circuit board. Therefore, in the prior art, the second through electrode 1132 penetrating the second insulating layer 1112 has a thickness above a certain level. Specifically, the thickness of the second through electrode 1132 in the prior art is greater than the thickness of the first circuit pattern layer 1121 and / or the thickness of the second circuit pattern layer 1122.

[0243] In contrast, in the embodiment, the thickness of the second insulating layer 1112 may be reduced, thereby reducing the thickness of the second through electrode 1132 penetrating the second insulating layer 1112. Exemplarily, the thickness T3 of the second through electrode 1132 in the embodiment may be smaller than the thickness T1 of the first circuit pattern layer 1121 and / or the thickness T2 of the second circuit pattern layer 1122. Through this, the embodiment may reduce the thickness of the second through electrode 1132, thereby reducing the signal transmission distance through the second through electrode 1132. Therefore, the embodiment may minimize signal transmission loss, thereby improving product reliability. Furthermore, the embodiment may enable thinner circuit boards and semiconductor packages.

[0244] Furthermore, the thickness T3 of the second through electrode 1132 may be smaller than the thickness of the first through electrode 1131 penetrating the first insulating layer 1111. Exemplarily, the first insulating layer 1111 may be a thermosetting resin containing glass fiber, or may be a thermosetting resin such as ABF that does not contain glass fiber. Furthermore, in the embodiment, the thickness T3 of the second through electrode 1132 can be reduced by the above-described structural features, and further, the ratio of the thickness T3 of the second through electrode 1132 to the thickness of the first through electrode 1131 can be reduced to a range of more than 1:1.5 and less than 1:3.5. As a result, the embodiment may reduce the signal transmission distance, minimize signal transmission loss, and enable thinner circuit boards and semiconductor packages.

[0245] FIG. 28 is a cross-sectional view showing a circuit board according to an eighth embodiment.

[0246] Referring to FIG. 28, the circuit board according to the eighth embodiment may differ from the circuit board according to the seventh embodiment in that the slope of the inner wall of the opening of the first protective layer 1141 and the slope of the inner wall of the cavity 1150 may be different.

[0247] Referring briefly to the fifth to seventh embodiments, the first protective layer 1141 has an opening that vertically overlaps with the cavity 1150. In this case, the slope of the inner wall of the opening of the first protective layer 1141 may be different from the slope of the inner wall of the cavity 1150. For example, the slope of the inner wall of the opening of the first protective layer 1141 may be closer to 90 degrees than the slope of the inner wall of the cavity 1150.

[0248] In contrast, the inner wall 1142IS forming the opening 1142T of the first protective layer 1141 of the eighth embodiment may have a slope such that the width of the opening 1142T changes from the upper surface to the lower surface of the first protective layer 1141. In this case, the inner wall 1142IS of the opening 1142T of the first protective layer 1141 may have a slope such that the width of the opening 1142T increases from the upper surface to the lower surface of the first protective layer 1141. That is, the slope of the inner wall 1142IS of the opening 1142T of the first protective layer 1141 may be different from the slope of the inner wall 1121IS of the cavity 1150 of the second insulating layer 1112. The direction of the slope of the inner wall 1142IS of the opening 1142T of the first protective layer 1141 may be different from the direction of the slope of the inner wall 1121IS of the cavity 1150 of the second insulating layer 1112. The slope of the inner wall 1142IS of the opening 1142T of the first protective layer 1141 may be opposite to the slope of the inner wall 1121IS of the cavity 1150 of the second insulating layer 1112. This increases the contact area between the cavity 1150 and the molding member (not shown) filling the opening 1142T, thereby resolving the mechanical reliability issue of the molding member peeling off from the circuit board. For example, the slope of the inner wall 1142IS of the opening 1142T may be opposite to the slope of the inner wall 1112IS of the cavity 1150, thereby serving as an anchor for more firmly bonding the molding member. Therefore, this embodiment allows the connecting member to be stably positioned within the cavity 1150, thereby enabling the connecting member to operate stably.

[0249] The slope of the inner wall 1112IS of the cavity 1150 of the second insulating layer 1112 may include a first portion 1112ISa connected to the lower surface of the second insulating layer 1112 and / or the bottom surface of the cavity 1150 and having a linear slope such that the width of the cavity 1150 gradually increases toward the upper surface of the second insulating layer 1112. The slope of the inner wall 1112IS of the cavity 1150 of the second insulating layer 1112 may include a second portion 1112ISb connected to the upper surface of the second insulating layer 1112 and / or the inner wall 1142IS of the opening 1142T of the first protective layer 1141 and having a curved slope such that the width of the cavity 1150 decreases toward the lower surface of the second insulating layer 1112. In this case, the second portion 1112ISb of the inner wall 1112IS of the cavity 1150 of the second insulating layer 1112 may improve the processability of the process of filling the molding material. Exemplarily, the second portion 1112ISb of the inner wall 1112IS of the cavity 1150 of the second insulating layer 1112 may improve the flowability of the molding liquid, allowing the molding liquid to flow more easily inside the cavity 1150, thereby preventing voids in the cavity 1150 that are not filled with the molding liquid.

[0250] FIG. 29 is a cross-sectional view showing a circuit board according to a ninth embodiment.

[0251] Referring to FIG. 29, the circuit board of the ninth embodiment may differ from the circuit board of the fifth embodiment in the number of second insulating layers and the resulting cavity structure.

[0252] For example, the second insulating layer 1112 may be formed of multiple layers. For example, the second insulating layer 1112 may include a first layer 1112-1 disposed on the first insulating layer 1111 and a second layer 1112-2 disposed on the first layer 1112-1. The second insulating layer 1112 may include a cavity 1150. The cavity 1150 may penetrate the second insulating layer 1112. For example, the cavity 1150 may include a first part 1151 that penetrates the first layer 1112-1 of the second insulating layer 1112 and a second part 1152 that penetrates the second layer 1112-2 of the second insulating layer 1112. For example, if the second insulating layer 1112 includes multiple layers, the cavity 1150 may penetrate the multiple layers of the second insulating layer 1112. In this case, the first part 1151 and the second part 1152 of the cavity 1150 may be formed in separate processes. For example, the first part 1151 of the cavity 1150 may be formed together with the first through hole in the process of forming the first through hole in the first layer 1112-1 of the second insulating layer 1112. Also, the second part 1152 of the cavity 1150 may be formed together with the second through hole in the process of forming the second through hole in the second layer 1112-2 of the second insulating layer 1112. As a result, the first part 1151 and the second part 1152 of the cavity 1150 may have different widths. For example, the cavity 1150 may include a plurality of side walls. For example, the cavity 1150 may include a first side wall 112-1IS corresponding to the first part 1151. Also, the cavity 1150 may include a second side wall 112-2IS corresponding to the second part 1152. The first side wall 1112IS and the second side wall 112-2IS may have a step. For example, the width of the first component 1151 and the width of the second component 1152 may be different from each other.

[0253] As a result, the sidewall of the cavity 1150 of the embodiment may have a stepped shape, thereby increasing the contact area with the molding member filling the cavity 1150. Therefore, the embodiment may improve the adhesion between the molding member and the circuit board, thereby resolving the physical reliability issue of the molding member being separated from the circuit board.

[0254] The outer surfaces of the first layer 1112-1 and the second layer 1112-2 of the second insulating layer 1112 may also have a step. This may increase the contact area between the first protective layer 1141 and the first and second layers 1112-1 and 1112-2 of the second insulating layer 1112. This may solve the problem of physical reliability, where the second insulating layer 1112 is separated from the first insulating layer 1111. In this case, the structure of the third insulating layer 1113 may correspond to the structure of the second insulating layer 1112 described with reference to FIG. 27.

[0255] FIG. 30 is a cross-sectional view showing a circuit board according to a tenth embodiment.

[0256] Referring to FIG. 30, the circuit board of the tenth embodiment may differ from the circuit board of the ninth embodiment in the structure of the cavity.

[0257] The second insulating layer 1112 may be formed of multiple layers. For example, the second insulating layer 1112 may include a first layer 1112-1 disposed on the first insulating layer 1111 and a second layer 1112-2 disposed on the first layer 1112-1. The cavity 1150 may be selectively formed in the second layer 1112-2 of the second insulating layer 1112. For example, the cavity 1150 may penetrate the second layer 1112-2 of the second insulating layer 1112. That is, the cavity 1150 formed in the circuit board of the tenth embodiment may penetrate some of the layers of the second insulating layer 1112. Therefore, the insulating layer forming the bottom surface of the cavity 1150 may be a layer of the second insulating layer 1112 that does not contain glass fibers. Therefore, in this embodiment, even if a desmear process is performed after the cavity 1150 is formed, exposure of glass fibers can be prevented.

[0258] FIG. 31 is a cross-sectional view showing a circuit board according to an eleventh embodiment.

[0259] Referring to FIG. 31, the circuit board of the eleventh embodiment may differ from the circuit board of the ninth embodiment in the structure of the second through electrodes.

[0260] The second insulating layer 1112 may include a first layer 1112-1 and a second layer 1112-1. A first through part 1132-1 of the second through electrode may be disposed in the first layer 1112-1 of the second insulating layer 1112. A second through part 1132-2 of the second through electrode may be disposed in the second layer 1112-2 of the second insulating layer 1112.

[0261] In this case, the first through part 1132-1 and the second through part 1132-2 of the second through electrode may be formed by exposing and developing the first layer 1112-1 and the second layer 1112-2 of the second insulating layer 1112, respectively, and filling the interior of the through hole with a conductive material. In this case, the upper surface of the first through part 1132-1 may be in direct contact with the lower surface of the second through part 1132-2. Exemplarily, a pad corresponding to the land of the through electrode may not be provided between the first through part 1132-1 and the second through part 1132-2. Exemplarily, when the through hole is formed by a laser process, a pad corresponding to the land that serves as a stopper in the laser process should be provided between the first through part 1132-1 and the second through part 1132-2. In contrast, in this embodiment, the through hole may be formed using an exposure and development process instead of a laser process, thereby omitting the pad corresponding to the land. Therefore, the embodiment can simplify the manufacturing process by omitting the pad that the second through electrode should have between the first through part 1132-1 and the second through part 1132-2, thereby improving product yield.

[0262] That is, the first through part 1132-1 has an upper surface, a lower surface, and a side surface 1132-1S. The side surface 1132-1S of the first through part 1132-1 described above may have a slope that gradually decreases in width toward the upper and lower surfaces of the first through part 1132-1. The side surface 1132-1S of the first through part 1132-1 may connect the upper and lower surfaces of the first through part 1132-1. The second through part 1132-2 has an upper surface, a lower surface, and a side surface 1132-2S. The side surface 1132-2S of the second through part 1132-2 described above may have a slope that gradually decreases in width toward the upper and lower surfaces of the second through part 1132-2. The side surface 1132-2S of the second through part 1132-2 may connect the upper and lower surfaces of the second through part 1132-2.

[0263] In this case, the side surface 1132-1S of the first through-hole 1132-1 and the side surface 1132-2S of the second through-hole 1132-2 may have a step in the vertical direction. Exemplarily, the horizontal center of the first through-hole 1132-1 may be offset from the horizontal center of the second through-hole 1132-2. Therefore, in an embodiment, the centers of the first through-hole 1132-1 and the second through-hole 1132-2 may be offset from each other, thereby eliminating the need for a pad that would be provided between them. Therefore, in an embodiment, even if the positions of the first through-hole 1132-1 and the second through-hole 1132-2 do not precisely match, the mechanical reliability and / or electrical reliability of the circuit board may not be affected. This may improve the mechanical reliability and / or electrical reliability of the circuit board while increasing the design freedom of the first through-hole 1132-1 and the second through-hole 1132-2.

[0264] FIG. 32 is a cross-sectional view showing a circuit board according to a twelfth embodiment, and FIG. 33 is a plan view of the circuit board of FIG. 32 with one configuration omitted.

[0265] Referring to Figures 32 and 33, the circuit board of the eighth embodiment may differ from the circuit board of the fifth embodiment in the structure of the first circuit pattern layer 1121 exposed through the cavity 1150 of the second insulating layer 1112 and the structure of the first through electrode 1131.

[0266] The first circuit pattern layer 1121 may include a first electrode pad 1121-1 disposed on the first insulating layer 1111 and vertically overlapping the cavity 1150. The first circuit pattern layer 1121 may also include a second electrode pad 1121-2 disposed on the first insulating layer 1111 and not vertically overlapping the cavity 1150. The first circuit pattern layer 1121 may further include a dummy electrode 1121-3 disposed on the first insulating layer 1111 and at least a portion of which vertically overlaps the cavity 1150. The dummy electrode 1121-3 may be disposed in a region of the first insulating layer 1111 vertically overlapping the cavity 1150 where the first electrode pad 1121-1 is not disposed. For example, the circuit board may further include a dummy electrode 1121-3 spaced apart from the first electrode pad 1121-1 on the first region of the first insulating layer 1111. The dummy electrode 1121-3 may function to protect a portion of the top surface 1111US1 of the first region of the first insulating layer 1111 where the first electrode pad 1121-1 is not disposed. For example, the dummy electrode 1121-3 may also be referred to as a protective pattern or barrier pattern that protects the top surface 1111US1 of the first region of the first insulating layer 1111. Therefore, the dummy electrode 1121-3 may prevent etching of the top surface 1111US1 of the first region of the first insulating layer 1111 during the desmear process. As a result, the embodiment may prevent reliability issues, such as copper migration, that may occur due to etching of the top surface 1111US1 of the first region of the first insulating layer 1111. Therefore, the embodiment may improve the electrical reliability of the circuit board.

[0267] The dummy electrode 1121-3 may be spaced apart from the first electrode pad 1121-1 on the upper surface 1111US1 of the first region. The dummy electrode 1121-3 may be spaced apart from the first electrode pad 1121-1 by a first width W2. The first width W2 may be in the range of 10 μm to 30 μm. This has been described with reference to FIGS. 2 to 13, so a detailed description thereof will be omitted.

[0268] A first through-electrode 1131 may be disposed in the first insulating layer 1111. At this time, the first through-electrode 1131 may include a plurality of through-holes. For example, the first through-electrode 1131 may include a first through-hole 1131-1 that vertically overlaps the first electrode pad 1121-1. The first through-hole 1131-1 may be a signal through-electrode electrically connected to the first electrode pad 1121-1.

[0269] The first through-hole electrode 1131 may also include a second through-hole portion 1131-2 that vertically overlaps the first region and is horizontally spaced apart from the first through-hole portion 1131-1. The second through-hole portion 1131-2 may vertically overlap the dummy electrode 1121-3. For example, the second through-hole portion 1131-2 may be a dummy through-hole electrode connected to the dummy electrode 1121-3. In this case, a plurality of second through-hole portions 1131-2 may be provided. For example, the second through-hole portion 1131-2 may include a plurality of through-hole portions that are horizontally spaced apart and commonly connected to one dummy electrode 1121-3.

[0270] In this case, the dummy electrodes 1121-3 and the second through-holes 1131-2 may function to improve the heat dissipation characteristics of the circuit board. For example, the dummy electrodes 1121-3 and the second through-holes 1131-2 may transfer heat generated from the connection member disposed in the cavity 1150 to the outside of the circuit board. As a result, the embodiment may improve the heat dissipation characteristics of the circuit board and a semiconductor package including the same. Therefore, the embodiment may improve the product reliability of the circuit board and a semiconductor package including the same.

[0271] FIG. 34 is a cross-sectional view showing a circuit board according to a thirteenth embodiment, and FIG. 35 is a plan view of the circuit board of FIG. 34 with one configuration omitted.

[0272] 34 and 35, the first circuit pattern layer 1121 of the circuit board of the thirteenth embodiment may include a first electrode pad 1121-1 arranged in a first region. The first circuit pattern layer 1121 may also include a second electrode pad 1121-2 arranged in a second region. The first circuit pattern layer 1121 may also include a dummy electrode 1121-3 arranged in the first region and electrically and physically separated from the first electrode pad 1121-1. The first electrode pad 1121-1 and the second electrode pad 1121-2 can directly transmit and receive electrical signals to and from each other on the first insulating layer 1111 without connection via the first through-electrode 1131. To this end, the first circuit pattern layer 1121 may include a connecting pattern 1121-4. The connecting pattern 1121-4 may be arranged on the first and second regions of the first insulating layer 1111. In this case, the first circuit pattern layer 1121 may include a plurality of connection patterns, and a connection pattern 1121-4 described below may refer to a connection pattern that connects the first electrode pad 1121-1 and the second electrode pad 1121-2 among the plurality of connection patterns. The connection pattern 1121-4 may directly connect the first electrode pad 1121-1 arranged in the first region to the second electrode pad 1121-2 arranged in the second region. This reduces the signal transmission distance between the first electrode pad 1121-1 and the second electrode pad 1121-2. Therefore, the embodiment may minimize signal transmission loss and further improve the electrical characteristics of the circuit board and a semiconductor package including the same. The connection pattern 1121-4 may include a first portion arranged in the first region and connected to the first electrode pad 1121-1. The connection pattern 1121-4 may also include a second portion arranged in the second region and connected to the second electrode pad 1121-2. The first and second portions of the connecting pattern 1121-4 may be directly connected to each other, so that the first electrode pad 1121-1 and the second electrode pad 1121-2 can directly transmit and receive electrical signals to and from each other using the connecting pattern 1121-4 without using the first through electrode 1131.Thus, in the embodiment, the connection pattern 1121-4 is disposed in the first region of the first insulating layer 1111, thereby improving the circuit integration density of the circuit board.

[0273] The connecting pattern 1121-4 may be in contact with the first electrode pad 1121-1 in the first region but may be physically separated from the dummy electrode 1121-3. Furthermore, the first circuit pattern portion occupying 50% to 90%, 55% to 85%, or 60% to 85% of the total area of ​​the upper surface 1111US1 of the first region may include the first electrode pad 1121-1 and the dummy electrode 1121-3. The first circuit pattern portion occupying 50% to 90%, 55% to 85%, or 60% to 85% of the total area of ​​the first region may include the first electrode pad 1121-1, the dummy electrode 1121-3, and the connecting pattern 1121-4.

[0274] 36 to 41 are diagrams showing the manufacturing method of the circuit board of FIG. 21 in the order of steps.

[0275] 36, an embodiment may perform a process for manufacturing an inner layer of a circuit board, where the inner layer of the circuit board may include a first insulating layer 1111, a first through electrode 1131, and a first circuit pattern layer 1121.

[0276] 37, in an embodiment, a second insulating layer 1112 may be disposed on a first insulating layer 1111. In addition, in an embodiment, a third insulating layer 1113 may be disposed below the first insulating layer 1111. In this case, the second insulating layer 1112 and the third insulating layer 1113 may include an insulating material different from that of the first insulating layer 1111. For example, the second insulating layer 1112 and the third insulating layer 1113 may include a photocurable resin.

[0277] Next, referring to FIG. 38 , an embodiment may perform a process of exposing and developing the second insulating layer 1112 and the third insulating layer 1113, respectively. For example, an embodiment may perform a process of exposing and developing the second insulating layer 1112 to form a first through hole VH1, a second through hole VH2, and a cavity 1150. The first through hole VH1 in the second insulating layer 1112 may be provided corresponding to a region where the second through electrode 1132 is disposed. The second through hole VH2 in the second insulating layer 1112 may penetrate a frame region of the second insulating layer 1112. This may expose the top surface of the frame region of the first insulating layer 1111 through the second through hole VH2 in the second insulating layer 1112. Correspondingly, the third insulating layer 1113 may also have a first through hole VH1 and a second through hole VH2.

[0278] Next, referring to FIG. 39, in an embodiment, a process of forming a second circuit pattern layer 1122, a second through electrode 1132, a third circuit pattern layer 1123, and a third through electrode 1133 may be performed.

[0279] 40, in an embodiment, a process of forming a first resist layer 1141R on the second insulating layer 1112 may be performed. The first resist layer 1141R may be provided by filling the second through-hole VH2 and the cavity 1150 of the second insulating layer 1112. In addition, in an embodiment, a process of forming a second resist layer 1142R under the third insulating layer 1113 may be performed. The second resist layer 1142R may be provided by filling the second through-hole VH2 of the third insulating layer 1113.

[0280] 41, in an embodiment, a process may be performed in which an opening that vertically overlaps the cavity 1150 and an opening that vertically overlaps the second circuit pattern layer 1122 are formed in the first resist layer 1141R to form the first protective layer 1141. In addition, in an embodiment, a process may be performed in which an opening that vertically overlaps the third circuit pattern layer 1123 is formed in the second resist layer 1142R to form the second protective layer 1142.

[0281] Meanwhile, when a circuit board having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it functions as a signal transmission device, it can solve noise problems. As a result, the circuit board having the above-described inventive features can maintain stable functionality of IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0282] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0283] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0284] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. a first insulating layer; a second insulating layer disposed on the first insulating layer; a circuit pattern layer disposed between the first insulating layer and the second insulating layer; the second insulating layer includes a cavity penetrating an upper surface and a lower surface of the second insulating layer; The circuit pattern layer is an electrode pad disposed on the bottom surface of the cavity; a dummy electrode disposed on the bottom surface of the cavity and spaced apart from the electrode pad and surrounding the electrode pad.

2. The circuit board according to claim 1 , wherein an outer surface of the first insulating layer has a step with an outer surface of the second insulating layer.

3. The circuit board according to claim 2 , wherein the first insulating layer and the second insulating layer include different insulating materials.

4. The circuit board according to claim 3 , wherein the second insulating layer includes a photocurable resin.

5. The circuit board according to claim 4 , wherein the outer surface of the second insulating layer is located further inward than the outer surface of the first insulating layer.

6. further comprising a protective layer disposed on the second insulating layer; The circuit board according to claim 2 , wherein an outer surface of the protective layer has a step with an outer surface of the second insulating layer.

7. The circuit board according to claim 6 , wherein the protective layer is provided to cover an outer surface of the second insulating layer.

8. The circuit board according to claim 2 , wherein the outer surface of the second insulating layer has a slope such that the outer width of the second insulating layer decreases or increases from the upper surface of the second insulating layer toward the lower surface of the second insulating layer.

9. the protective layer has an opening that vertically overlaps the cavity; The circuit board of claim 6 , wherein the slope of the inner wall of the opening is different from the slope of the inner wall of the cavity.

10. The circuit board according to claim 9 , wherein the direction of the inclination of the inner wall of the opening is different from the direction of the inclination of the inner wall of the cavity.

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