Semiconductor package and semiconductor package manufacturing method

Abstract

The technical idea of ​​the present invention provides a semiconductor package manufacturing method including the steps of: arranging a plurality of dies on a carrier while spacing them horizontally apart; a first sawing step of sawing the carrier to separate it into sub-panels on which the plurality of dies are arranged; a step of testing the dies; and a second sawing step of sawing between each die on the sub-panel to separate it into individual semiconductor packages, wherein the carrier includes a plurality of first regions in which the dies are arranged and a second region in which the dies are not arranged, and a first horizontal distance from a side of the carrier to the first regions is shorter than a second horizontal distance from the first regions to the first regions.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package and a method for manufacturing the semiconductor package, and more particularly to a method for manufacturing a wafer level package. [Background technology]

[0002] As the total cost of semiconductors continues to rise, there is a growing need to reduce costs in the packaging process, as the cost reduction in the front-end process has reached its limit.In addition, the increasing performance of various mobile devices is increasing the number of input / output (I / O) terminals required for semiconductors.

[0003] In this context, wafer level packaging (WLP) technology is gaining attention. This technology performs the semiconductor packaging process at the wafer level and separates the wafer-level semiconductor packages into individual units. Fan-out wafer level packaging (FONLP) and fan-out panel level packaging (FOPLP) are technologies that mount chips directly on wafers instead of PCBs. FONLP and FOPLP reduce the manufacturing cost of semiconductor packages by not using PCBs, and also enable miniaturization of semiconductor packages, improved heat dissipation, reduced power consumption, and improved frequency bands.

[0004] In FOWLP or FOPLP, individual dies are reassembled in wafer form on a carrier, molded, and then packaged through a fan-out type redistribution layer (RDL) process and bumping process. Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE INVENTION A technical object of the present invention is to provide a semiconductor package and a method for manufacturing the semiconductor package that have improved structural stability.

[0006] Another technical object of the present invention is to provide a semiconductor package and a method for manufacturing the semiconductor package with improved warpage control capability. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems, the technical idea of ​​the present invention provides a semiconductor package manufacturing method including the steps of arranging a plurality of dies on a carrier while spacing them apart horizontally; a first sawing step of sawing the carrier to separate it into sub-panels on which the plurality of dies are arranged; a step of testing the dies; and a second sawing step of sawing the sub-panels between the dies to separate them into individual semiconductor packages, wherein the carrier includes a plurality of first regions in which the dies are arranged and a second region in which the dies are not arranged, and a first horizontal distance from a side of the carrier to the first regions is shorter than a second horizontal distance from the first regions to the first regions.

[0008] The first sawing step may be performed by sawing along a first scribe lane disposed in the second region.

[0009] A first horizontal distance from the edge of the carrier to the first region may be smaller than a third horizontal distance from the first region to an edge of the sub-panel that is relatively closer to the first scribe lane.

[0010] The sub-panel may have the first region surrounded by the second region in plan view.

[0011] The carrier may be separated into a plurality of sub-panels, and at least two of the plurality of sub-panels may have different horizontal areas.

[0012] In order to solve the above-mentioned problems, another technical idea of ​​the present invention provides a semiconductor package including a carrier, an adhesive layer arranged on the carrier, and a plurality of dies arranged on the adhesive layer and adhered by the adhesive layer, wherein the carrier includes a plurality of first regions in which the dies are arranged and a second region in which the dies are not arranged, and the horizontal distance from an edge of the carrier to the first regions is smaller than the horizontal distance from the first regions to the first regions.

[0013] The technical idea of ​​the present invention to solve the above-mentioned problems provides a semiconductor package manufacturing method, comprising: a step of arranging a plurality of dies and a dummy die spaced apart on a carrier; a first sawing step of sawing the carrier to separate it into sub-panels on which the plurality of dies and the dummy die are arranged; a step of testing the dies; and a second sawing step of sawing between the dies of the sub-panel to separate it into individual semiconductor packages, wherein the carrier includes a plurality of first regions in which the dies are arranged and a second region in which no die is arranged, and the dummy die is arranged adjacent to a side of the first region.

[0014] The horizontal area of ​​the dummy die may be different from the horizontal area of ​​the die.

[0015] From a plan view, inside the sub-panel, the dummy die may surround the die and be arranged along at least one side of the sub-panel.

[0016] The dummy die may be arranged along an edge of the carrier.

[0017] From a plan view, the dummy dies may be arranged in one or more rows or columns inside the sub-panel.

[0018] Another technical idea of ​​the present invention to solve the above-mentioned problems can provide a semiconductor package including a carrier, an adhesive layer arranged on the carrier, and a plurality of dies and dummy dies arranged on the adhesive layer and adhered by the adhesive layer, wherein the carrier includes a plurality of first regions in which the dies and dummy dies are arranged and a second region in which no dies are arranged, and the dummy dies are arranged adjacent to at least one side of the first region.

[0019] From a plan view, inside the sub-panel, the second region surrounds the first region, and the dummy die may be arranged along the edge of the carrier.

[0020] From a planar perspective, the dummy die may be arranged inside the first region along at least two or more sides of the first region. [Effects of the Invention]

[0021] The semiconductor package and the method for manufacturing the semiconductor package according to the present invention can secure the area of ​​the second region surrounding the first region where the die is arranged, thereby improving the structural stability of the semiconductor package.

[0022] Furthermore, the semiconductor package and the method for manufacturing the semiconductor package according to the present invention can improve the warpage control capability of the semiconductor package by disposing a dummy die adjacent to the side of the first region where the die is disposed.

[0023] Furthermore, in the semiconductor package and the method for manufacturing the semiconductor package according to the present invention, the dummy die surrounds the semiconductor die, thereby improving the structural stability of the semiconductor package. [Brief explanation of the drawings]

[0024] [Figure 1a] 1 is a layout diagram of a semiconductor package according to an embodiment of the present invention. [Figure 1b]1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 1c] 10 is a layout diagram showing a state in which the semiconductor package has been separated into sub-panels by a first sawing. FIG. [Figure 2] 1 is a layout diagram of a semiconductor package according to an embodiment of the present invention; [Figure 3] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 4a] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 4b] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 4c] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 4d] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 4e] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5a] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5b] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5c] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5d] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6] 1 is a layout diagram of a semiconductor package according to an embodiment of the present invention; [Figure 7a] 1 is a layout diagram of a semiconductor package according to an embodiment of the present invention; [Figure 7b] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 7c] 10 is a layout diagram showing a state in which the semiconductor package has been separated into sub-panels by a first sawing. FIG. [Figure 8]1 is a layout diagram of a semiconductor package according to an embodiment of the present invention; [Figure 9] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 10a] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 10b] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 10c] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 10d] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 10e] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11a] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11b] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11c] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11d] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 12] 1 is a layout diagram of a semiconductor package according to an embodiment of the present invention; [Figure 13] 1 is a layout diagram of a semiconductor package according to an embodiment of the present invention; [Figure 14] 1 is a layout diagram of a semiconductor package according to an embodiment of the present invention; [Figure 15] 1 is a layout diagram of a semiconductor package according to an embodiment of the present invention; [Figure 16] 1A to 1C are cross-sectional views illustrating a process of a semiconductor package manufacturing method according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a process of a semiconductor package manufacturing method according to an embodiment of the present invention. [Figure 18]1A to 1C are cross-sectional views illustrating a process of a semiconductor package manufacturing method according to an embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a process of a semiconductor package manufacturing method according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0025] A semiconductor package manufacturing method according to the present invention includes the steps of: arranging a plurality of dies on a carrier while spaced apart horizontally; a first sawing step of sawing the carrier to separate it into sub-panels on which the plurality of dies are arranged; a step of testing the dies; and a second sawing step of sawing the sub-panels between the dies to separate them into individual semiconductor packages, wherein the carrier includes a plurality of first regions in which the dies are arranged and a second region in which the dies are not arranged, and a first horizontal distance from a side of the carrier to the first regions is smaller than a second horizontal distance from the first regions to the first regions.

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein. In order to clearly explain the present invention, parts that are not relevant to the description are omitted in the drawings, and the same reference numerals are used throughout the specification to refer to the same or similar components.

[0027] As used herein, terms such as "comprise" or "have" are intended to describe the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0028] In this specification, spatially relative terms such as "front," "rear," "upper," or "lower" may be used to describe the relationship between components shown in the drawings. These are relative terms defined based on what is shown in the drawings, and the positional relationship may be reversed depending on the orientation.

[0029] Unless there are special circumstances, a component being "in front of," "behind," "above," or "below" another component does not only mean that it is disposed "in front of," "behind," "above," or "below" the other component in direct contact with it, but also includes the case where the other component is disposed between them. Furthermore, unless there are special circumstances, a component being "connected" to another component does not only mean that they are directly connected to each other, but also includes the case where they are indirectly connected to each other.

[0030] The semiconductor package manufacturing method according to the embodiment of the present invention can be applied to wafer level packages. The semiconductor package manufacturing method according to the embodiment of the present invention makes it possible to manufacture a semiconductor package without using a PCB substrate. The embodiment of the present invention can be applied to fan-out panel level packages (FOPLPs).

[0031] 1a is a layout diagram of a semiconductor package according to an embodiment of the present invention, and FIG. 1b is a cross-sectional view of the semiconductor package according to an embodiment of the present invention, specifically a cross-sectional view taken along line BB' in FIG. 1a. FIG. 1c is a layout diagram showing a state in which the semiconductor package has been separated into sub-panels by a first sawing. For convenience of explanation, FIG. 1b exemplarily shows a case in which two dies are arranged in each first region R1.

[0032] 1a to 1c, a semiconductor package 1 may include a carrier 100, an adhesive layer 110 disposed on the carrier 100, and a plurality of dies 10 disposed on the adhesive layer 110. The semiconductor package 1 may also include a plurality of sub-panels SP.

[0033] 1a exemplarily shows four sub-panels SP arranged on one carrier 100, the number of sub-panels SP arranged on one carrier 100 may be varied in various ways. In some embodiments, one semiconductor package 1 may include three or fewer or five or more sub-panels SP.

[0034] The dies 10 may be arranged in a plurality of rows and columns on the carrier 100. The dies 10 may include connection portions 11 for input / output connection with the outside. For example, the connection portions 11 may be pads. The connection portions 11 may also be electrically connected to posts 20 (fillers). The posts 20 may include, for example, copper. The dies 10 may be mounted on the surface of the carrier 100 using a PnP (Pick and Place) method.

[0035] The carrier 100 may be formed in the form of a panel. The carrier 100 may be exemplarily referred to as a main panel. For example, the carrier 100 preferably has physical properties that can withstand pressure during molding. For example, the carrier 100 may be a glass panel, i.e., a glass substrate with a rectangular frame. For example, the carrier may be a 600 mm x 600 mm glass substrate. In this way, when a panel is used as the carrier 100, more dies 10 may be packaged in one carrier 100.

[0036] For example, the carrier 100 may be made of Alloy 42. Alloy 42 is a thermal expansion alloy and may be a special performance alloy (SPA) having a low and limited coefficient of thermal expansion within a certain temperature range.

[0037] From a planar perspective, the carrier 100 may include a first region R1 in which the die 10 is disposed and a second region R2 in which the die 10 is not disposed. The first region R1 may include an active region, and the second region R2 may include a handling region and a sawing region.

[0038] The active area may refer to the area where the die 10 and / or dummy die 12 are mounted. The handling area may refer to the non-active area and may be referred to as the marking area. The sawing area may be referred to as the cutting area and / or the separation area.

[0039] The carrier 100, i.e., the main panel, can be sawed and separated into a plurality of sub-panels SP. The sub-panels SP then include active areas and handling areas, and the dies 10 in the active areas can then be separated to form unit semiconductor packages (2 in FIG. 4e).

[0040] From a planar perspective, a first scribe lane SL1 may be arranged inside the second region R2. The carrier 100 may be cut along the first scribe lane SL1 to separate the semiconductor package 1 into a plurality of sub-panels SP. From a planar perspective, a second scribe lane (not shown) may be arranged inside the first region R1. The sub-panel SP may be separated into individual semiconductor packages (2 in FIG. 3e) along the second scribe lane (not shown).

[0041] The adhesive layer 110 may be formed by applying an adhesive to the carrier 100. The adhesive layer 110 can attach the die 10 and the carrier 100 to each other. As another example, the adhesive layer 110 may be formed by tape lamination. As another example, the adhesive layer 110 may be attached to the carrier 100 by heating.

[0042] The first horizontal distance L1 from the side of the carrier 100 to the first region R1 may be smaller than the second horizontal distance L2 between the multiple first regions R1. If the first horizontal distance L1 from the side of the carrier 100 to the first region R1 is smaller than the second horizontal distance L2 between the multiple first regions R1, the second region R2 will sufficiently surround the first region R1 after sawing the carrier 100, making it easy to handle the sub-panel SP. For example, the second horizontal distance L2 may be greater than twice the first horizontal distance L1.

[0043] Furthermore, the first horizontal distance L1 from the side of the carrier 100 to the first region R1 may be smaller than the third horizontal distance L3 from the first region R1 to the side of the sub-panel SP that is relatively close to the first scribe lane SL1.

[0044] The first to third horizontal distances L1, L2, and L3 may refer to distances extending parallel to a first horizontal direction, a second horizontal direction (X direction, Y direction), and / or a diagonal direction.

[0045] FIG. 2 is a layout diagram of a semiconductor package according to an embodiment of the present invention.

[0046] Referring to Fig. 2, the semiconductor package 1a of this embodiment may include a plurality of sub-panels SP having different horizontal areas. While Figs. 1a to 1c show that the horizontal areas of the sub-panels SP are the same, Fig. 2 shows that the horizontal areas of the sub-panels SP may be different. That is, the horizontal areas of at least two of the plurality of sub-panels SP may be different.

[0047] The horizontal area of ​​the sub-panel SP may vary depending on the horizontal area (size) of the die 10 and / or the horizontal area (size) of the dummy die 12, the pattern of the redistribution layer (40 in FIG. 4a) and / or the mask.

[0048] FIG. 3 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention, specifically showing a molding layer disposed on the semiconductor package of FIGS. 1a to 1c.

[0049] 3, a molding layer 30 (Front-Mold) that encases the side and top surfaces of the die 10 may be disposed on the adhesive layer 110. That is, the molding layer 30 may encase the connection portions 11 of the die 10. The molding layer 30 may include, for example, an epoxy resin.

[0050] 4a to 4e are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. Specifically, in the method of manufacturing a semiconductor package illustrated in Fig. 4a to 4e, a first sawing is performed with the die 10 and the carrier 100 attached to each other.

[0051] 3 and 4a, the upper surface of the molding layer 30 of the semiconductor package of Fig. 3 may be grinded. Here, the lower surface of the molding layer 30 may refer to the surface that is in direct contact with the adhesive layer 110, and the upper surface of the molding layer 30 may refer to the surface opposite the lower surface of the molding layer 30.

[0052] The upper surface of the molding layer 30 may be ground, so that the upper surface of the die 10 and the upper surface of the molding layer 30 are positioned at substantially the same vertical level. Here, the lower surface of the die 10 may refer to the surface closest to the adhesive layer 110, and the upper surface of the die 10 may refer to the surface opposite the lower surface of the die 10. In the process of grinding the upper surface of the molding layer 30, some of the posts 20 may also be ground. Therefore, the posts 20 of the die 10 may be exposed to the outside.

[0053] 4a and 4b, a redistribution process may be performed on the front surface of the die 10 where the posts 20 are exposed. That is, a redistribution layer (RDL) 40 may be formed on the top surface of the die 10. The redistribution layer 40 may include an insulating layer 42, redistribution lines 44, and conductive vias 46. The insulating layer 42 may be formed of an insulating material, for example, a photo-imageable dielectric (PID) resin, and may further include an inorganic filler. The insulating layer 42 may have a multi-layer structure according to the multi-layer structure of the redistribution lines 44. The redistribution lines 44 may be formed in multiple layers and connected to each other by the conductive vias 46.

[0054] The conductive vias 46 may be configured to transmit electrical signals and / or heat inside the semiconductor package 1. The conductive vias 46 may be made of a metal or an alloy thereof, such as, but not limited to, molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc. The conductive vias 46 may be formed by exposing and developing a photosensitive insulating material.

[0055] 1a, 1c, 4b, and 4c, the semiconductor package 1 can be separated into a plurality of sub-panels SP through a first sawing. In this embodiment, the first sawing is performed while the carrier 100 is attached. The first sawing can be performed along a first scribe lane SL1, which can be located in a second region R2 of the carrier 100 from a planar perspective.

[0056] Referring to FIGS. 4c and 4d, after the die 10 of the sub-panel SP is tested through the conductivity of the rewiring layer 40, the carrier 100 and adhesive layer 110 can be separated from the die 10 (Carrier De-bond).

[0057] 1a, 1c, 4d, and 4e, the sub-panel SP may be second sawed into individual semiconductor packages 2. From a planar perspective, the second sawing may be performed along a second scribe lane (not shown) within the first region R1. The second scribe lane (not shown) may extend along a line between the plurality of dies 10.

[0058] 5a to 5d are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. Specifically, in the method of manufacturing a semiconductor package illustrated in Fig. 5a to 5d, a first sawing is performed after the carrier 100 and the adhesive layer 110 are separated from the die 10.

[0059] 4 and 5a, the carrier 100 and adhesive layer 110 of the semiconductor package 1 of FIG. 4 can be removed (Carrier De-bond). Furthermore, a lamination layer 200 can be disposed on the bottom surface of the semiconductor package 1 from which the carrier 100 has been removed. For example, the lamination layer 200 can be disposed through the attachment of a BSP lamination film. In the process of removing the carrier 100 from the semiconductor package 1, the bottom surface of the die 10 can be exposed, but the top surface of the die 10 may not be exposed because it is molded by the molding layer 30.

[0060] 5a and 5b, the upper surface of the molding layer 30 may be ground so that the upper surface of the die 10 and the upper surface of the molding layer 30 are at substantially the same vertical level.

[0061] 5b and 5c, a redistribution process may be performed on the front surface of the die 10 where the posts 20 are exposed. That is, a redistribution layer 40 may be formed on the top surface of the die 10. Although only one redistribution layer 40 is shown on the molding layer 30 in FIG. 5c, two or more redistribution layers 40 may be formed as needed.

[0062] 1a, 1c, 5c, and 5d, the semiconductor package may be separated into sub-panels SP through a first sawing. In this embodiment, the carrier 100 is first sawed while it is separated from the die 10. That is, this embodiment shows that the lamination layer 200 is first sawed while it is attached to the die 10. The first sawing may be performed along a first scribe lane SL1, which may be located in a second region R2 of the carrier 100 from a planar perspective.

[0063] 1a, 1c, 4e, and 5d, after testing the dies 10 of the sub-panel SP, the sub-panel SP may be second sawed into individual semiconductor packages 5. From a planar perspective, the second sawing may be performed along a second scribe lane (not shown) within the first region R1. The second scribe lane (not shown) may be disposed along and between the multiple dies 10 within the first region R1.

[0064] FIG. 6 is a layout diagram of a semiconductor package according to an embodiment of the present invention.

[0065] 6, semiconductor package 1b may include a carrier 100, and a plurality of dies 10 and a dummy die 12 on the carrier 100. Since the carrier 100 and the plurality of dies 10 in FIG. 6 are substantially the same as the carrier 100 and the plurality of dies 10 in the semiconductor package 1 in FIGS. 1a to 1c, only the dummy die 12 will be described here.

[0066] The dummy die 12 may be disposed in the second region R2 of the carrier 100. When the dummy die 12 is disposed in the second region R2, the rigidity of the carrier 100 can be increased, and warpage of the carrier 100 can be easily controlled. According to one embodiment of the present invention, from a planar perspective, the dummy die 12 may be disposed in the handling region and / or the sawing region of the second region R2. The dummy die 12 may be removed after the first sawing and / or the second sawing. For example, the dummy die 12 may be disposed on the first scrape lane SL1 region (i.e., disposed in the sawing region) and / or the dummy die 12 may be disposed in the handling region.

[0067] For example, dummy die 12 may refer to a die that has no electrical function. Dummy die 12 may be formed of a homogenous material without any circuitry, metal lines, and / or sublayers therein. Dummy die 12 may not include test terminals and may include dummy wafer, silicon (Si), glass, and / or quartz.

[0068] The dummy die 12 may be placed on the carrier 100 in the same step as the die 10 and / or the die 10 may be placed on the carrier 100 first, followed by the dummy die 12.

[0069] According to one embodiment of the present invention, the horizontal area of ​​the dummy die 12 may be the same as the horizontal area of ​​the die 10. According to another embodiment of the present invention, the horizontal area of ​​the dummy die 12 may be different from the horizontal area of ​​the die 10. For example, the horizontal area of ​​the dummy die 12 may be larger than the horizontal area of ​​the die 10. Furthermore, the shape of the top surface of the dummy die 12 may be the same as and / or different from the shape of the top surface of the die 10.

[0070] 7a is a layout diagram of a semiconductor package according to an embodiment of the present invention, and FIG. 7b is a cross-sectional view of the semiconductor package according to an embodiment of the present invention, specifically a cross-sectional view taken along line BB' in FIG. 7a. FIG. 7c is a layout diagram showing a state in which the semiconductor package has been separated into sub-panels by first sawing. For convenience of explanation, FIG. 7b exemplarily shows a case in which two dies and two dummy dies are arranged in each first region R1. The following description will be made with reference to FIGS. 1 to 6, and the above content will be briefly described or omitted.

[0071] 7a to 7c, the semiconductor package 2 may include a carrier 100, an adhesive layer 110 disposed on the carrier 100, and a plurality of dies 10 and dummy dies 12 disposed on the adhesive layer 110. Further, the carrier 100 may include a plurality of sub-panels SP. From a planar perspective, the carrier 100 may be divided into a first region R1 where the dies 10 and dummy dies 12 are disposed and a second region R2 where the dies 10 and dummy dies 12 are not disposed.

[0072] The dies 10 and / or dummy dies 12 may be arranged in a plurality of rows and columns on the carrier 100. The dies 10 may include connection portions 11 for input / output connection with the outside. For example, the connection portions 11 may be pads. The connection portions 11 may also be electrically connected to posts 20 (fillers). The posts 20 may include, for example, copper. The dies 10 may be mounted on the surface of the carrier 100 using a PnP (Pick and Place) method. The dummy dies 12 may not include, for example, the connection portions 11 and / or the posts 20.

[0073] The die 10 and the dummy die 12 may be arranged in a first region R1 of the carrier 100. The dummy die 12 may be arranged adjacent to a side of the first region R1. When the dummy die 12 is arranged adjacent to a side of the first region R1, the dummy die 12 may be arranged adjacent to a side of the sub-panel SP. This increases the rigidity of the sub-panel SP, making it easier to control warpage of the sub-panel SP. According to one embodiment of the present invention, the dummy die 12 may be arranged along the side of the carrier 100 from a planar perspective. The dummy die 12 may be arranged in the first region R1, and the dummy die 12 may remain on the carrier 100 after the first sawing. The dummy die 12 may be removed after the second sawing.

[0074] FIG. 8 is a layout diagram of a semiconductor package according to an embodiment of the present invention.

[0075] Referring to Fig. 8, the semiconductor package 2a of this embodiment may include a plurality of sub-panels SP having different horizontal areas. While Fig. 7a illustrates that the horizontal areas of the sub-panels SP are the same, Fig. 8 illustrates that the horizontal areas of the sub-panels SP may be different from each other. That is, the horizontal areas of at least two of the plurality of sub-panels SP may be different from each other.

[0076] The horizontal area of ​​the sub-panel SP may vary depending on the horizontal area (size) of the die 10 and / or the horizontal area (size) of the dummy die 12, the pattern of the redistribution layer 40, and / or the mask.

[0077] Even if the horizontal areas of the respective sub-panels SP are different, the die 10 and the dummy die 12 can be arranged in the first region R1 of the carrier 100. The dummy die 12 can be arranged adjacent to the side of the carrier 100 within the first region R1. When the dummy die 12 is arranged adjacent to the side of the carrier 100, the rigidity of the sub-panel SP can be increased, and warpage of the sub-panel SP can be easily controlled.

[0078] FIG. 9 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention, specifically showing a molding layer disposed on the semiconductor package of FIGS. 7a to 7c.

[0079] 10a to 10e are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. Specifically, in the method of manufacturing a semiconductor package shown in Fig. 10a to 10e, a first sawing is performed in a state where the die 10 and the carrier 100 are attached to each other.

[0080] Compared with the method for manufacturing the semiconductor package 5 of FIGS. 3 to 4e, the method for manufacturing the semiconductor package 5 of FIGS. 9 to 10e may further include a dummy die 12. In addition, the molding layer 30 may wrap the side surfaces of the die 10, the side surfaces of the dummy die 12, the top surface of the die 10, and the top surface of the dummy die 12 on the adhesive layer 110. Posts 20 may be formed on the die 10, but posts 20 may not be formed on the dummy die 12. That is, the top surface of the dummy die 12 may be in direct contact with the molding layer 30. Except for the above features, the method for manufacturing the semiconductor package 5 of FIGS. 9 to 10e may be substantially the same as the method for manufacturing the semiconductor package 5 of FIGS. 3 to 4e.

[0081] 11a to 11d are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. Specifically, in the method of manufacturing a semiconductor package illustrated in Fig. 11a to 11d, a first sawing step is performed after the die 10 and the carrier 100 are separated.

[0082] Compared with the method for manufacturing the semiconductor package 5 of FIGS. 5a to 5d, the method for manufacturing the semiconductor package 5 of FIGS. 11a to 11d may further include a dummy die 12. In addition, the molding layer 30 may wrap the side surfaces of the die 10, the side surfaces of the dummy die 12, the top surface of the die 10, and the top surface of the dummy die 12 on the adhesive layer 110. Posts 20 may be formed on the die 10, but posts 20 may not be formed on the dummy die 12. That is, the top surface of the dummy die 12 may be in direct contact with the molding layer 30. Except for the above features, the method for manufacturing the semiconductor package 5 of FIGS. 11a to 11d may be substantially the same as the method for manufacturing the semiconductor package 5 of FIGS. 5a to 5d.

[0083] FIG. 12 is a layout diagram of a semiconductor package according to an embodiment of the present invention.

[0084] 12, semiconductor package 2b includes a carrier 100, and a plurality of dies 10 and a dummy die 12a disposed on the carrier 100. Since the carrier 100 and the plurality of dies 10 in FIG. 12 are substantially the same as the carrier 100 and the plurality of dies 10 in the semiconductor package 2 in FIGS. 7a to 7c, only the dummy die 12a will be described here.

[0085] The horizontal area of ​​the dummy die 12a may be different from the horizontal area of ​​the die 10. For example, the horizontal area of ​​the dummy die 12a may be larger than the horizontal area of ​​the die 10. Furthermore, the shape of the top surface of the dummy die 12a may be the same as and / or different from the shape of the top surface of the die 10.

[0086] Furthermore, the dummy die 12a may be arranged adjacent to only some of the sides of the first region R1. While FIG. 12 exemplarily illustrates the dummy die 12a being arranged adjacent to two opposing sides of the first region R1, the dummy die 12a may be arranged adjacent to one or more sides of the first region R1. That is, the dummy die 12a may be arranged along at least one side of the first region R1. Furthermore, the dummy die 12a may be arranged adjacent to only some of the sides of the sub-panel SP. That is, the dummy die 12a may be arranged along at least one side of the sub-panel SP.

[0087] FIG. 13 is a layout diagram of a semiconductor package according to an embodiment of the present invention.

[0088] 13, a semiconductor package 2c may include a carrier 100 and a plurality of dies 10 and a dummy die 12 disposed on the carrier 100. The carrier 100, the plurality of dies 10, and the dummy die 12 in FIG. 13 may be substantially the same as the carrier 100, the plurality of dies 10, and the dummy die 12 in the semiconductor package 2 in FIGS. 7a to 7c.

[0089] A first horizontal distance L1 from an edge of the carrier 100 to the first region R1 may be smaller than a second horizontal distance L2 between the plurality of first regions R1. When the first horizontal distance L1 from an edge of the carrier 100 to the first region R1 is smaller than the second horizontal distance L2 between the plurality of first regions R1, after sawing the carrier 100, the second region R2 sufficiently surrounds the first region R1, making it easy to handle the sub-panel SP.

[0090] The first and second horizontal distances L1 and L2 may refer to distances extending parallel to a first horizontal direction, a second horizontal direction (X direction, Y direction), and / or a diagonal direction.

[0091] FIG. 14 is a layout diagram of a semiconductor package according to an embodiment of the present invention.

[0092] 14, the semiconductor package 2d may have dummy dies 12 arranged in two rows and two columns within the first region R1. This is merely an example, and the number of rows and columns in which the dummy dies 12 are arranged is not limited thereto. For example, the dummy dies 12 may be arranged in three or more rows and / or columns within the region R1.

[0093] FIG. 15 is a layout diagram of a semiconductor package according to an embodiment of the present invention.

[0094] 15, from a plan view, the dummy die 12 of the semiconductor package 2e may surround the die 10. The dummy die 12 may be disposed on the first region R1, and the dummy die 12 may also be disposed on the carrier 100 after the first sawing. The dummy die 12 may be removed after the second sawing.

[0095] 16 is a cross-sectional view showing a process of a semiconductor package manufacturing method according to an embodiment of the present invention. FIG. 17 is a cross-sectional view showing a cross section of a semiconductor package immediately before a detachment process of a carrier 100 and an adhesive layer 110 is performed in the process of a semiconductor package manufacturing method according to an embodiment of the present invention. More specifically, each step of a semiconductor package manufacturing method according to an embodiment of the present invention will be described in detail.

[0096] 16 and 17, posts 20 can be formed on the top surface of the die 10. The posts 20 in this embodiment are formed on the die 10 and can be copper stud bumps.

[0097] Subsequently, a step of forming an adhesive layer 110 on the carrier 100 is performed. Next, a step of placing the die 10 with the posts 20 formed thereon is performed on the adhesive layer 110. The die 10 is mounted on the carrier 100.

[0098] Next, a step of molding the semiconductor package (Front-Mold) is performed. In this step, the die 10 arranged on the top of the carrier 100 is molded by the molding layer 30. That is, the die 10 and posts 20 arranged on the adhesive layer 110 are molded by the molding layer 30. At this time, the molding layer 30 may include an epoxy resin.

[0099] Next, a step (Co-grind) is performed in which the top side of the semiconductor package is ground to expose the posts 20 on the die 10. Through this step, the top surfaces of the posts 20 are exposed, and the posts 20 can be electrically connected to the redistribution lines 44 and conductive vias 46 through the exposed top surfaces.

[0100] Next, a step of forming redistribution lines 44, conductive vias 46, and an insulating layer 50 on the upper surface of the semiconductor package is performed. In this step, the redistribution lines 44 and the conductive vias 46 may be formed on the insulating layer 50. The insulating layer 50 may be made of a resin coated film (RCF). In addition, an under bump metallurgy (UBM) layer 70 may be formed on top of the redistribution lines 44 and the conductive vias 46. The UBM layer 70 may be electrically connected to the redistribution lines 44 and the conductive vias 46. The UBM layer 70 may be formed on a passivation layer 60 formed on the insulating layer 50. Through this step, the redistribution lines 44, the conductive vias 46, and the UBM layer 70 on the passivation layer 60 are formed (RCF-UBM).

[0101] Thereafter, a step of disposing an electrical connection member 80 on the UBM layer 70 is performed. The electrical connection member 80 may be in the shape of a ball (ball mount).

[0102] Finally, a detachment step is performed to remove the carrier 100 and the adhesive layer 110 from the bottom surface of the semiconductor package. The carrier 100 and the adhesive layer 110 can be removed by applying heat.

[0103] Meanwhile, in this embodiment, the second sawing process for separating the semiconductor package into individual die units can be performed before or after removing the carrier 100 and adhesive layer 110 .

[0104] 18 is a cross-sectional view showing a process of a semiconductor package manufacturing method according to an embodiment of the present invention. 19 is a cross-sectional view showing a cross section of a semiconductor package immediately before a back-grinding process is performed in the process of a semiconductor package manufacturing method according to an embodiment of the present invention. More specifically, each process of a semiconductor package manufacturing method according to an embodiment of the present invention will be described in detail below.

[0105] 18 and 19, posts 20 can be formed on the top surface of the die 10. The posts 20 in this embodiment are formed on the die 10 and can be copper stud bumps.

[0106] Subsequently, a step of forming an adhesive layer 110 on the carrier 100 is performed. Next, a step of placing the die 10 with the posts 20 formed thereon is performed on the adhesive layer 110. The die 10 is mounted on the carrier 100.

[0107] Next, a step of molding the semiconductor package (Front-Mold) is performed. In this step, the die 10 arranged on the top of the carrier 100 is molded by the molding layer 30. That is, the die 10 and posts 20 arranged on the adhesive layer 110 are molded by the molding layer 30. At this time, the molding layer 30 may include an epoxy resin.

[0108] Next, a step of removing the carrier 100 (Carrier De-bond) is performed. By removing the carrier 100 in this step, the underside of the semiconductor package is exposed. This also exposes the underside of the die 10. However, the top and side surfaces of the die 10 on which the posts 20 are formed are not exposed because they are molded by the molding layer 30.

[0109] Next, a step of forming a laminate layer 200 on the lower surface of the semiconductor package from which the carrier 100 has been removed is performed. For example, the lamination layer 200 can be formed by attaching a BSP lamination film.

[0110] Next, a step (Co-grind) is performed in which the top side of the semiconductor package is grinded to expose the posts 20 on the die 10. Through this step, the top surfaces of the posts 20 are exposed, and the posts 20 can be electrically connected to the redistribution lines 44 and conductive vias 46 through the exposed top surfaces.

[0111] Next, a step of forming redistribution lines 44, conductive vias 46, and an insulating layer 50 on the upper surface of the semiconductor package is performed. In this step, the redistribution lines 44 and the conductive vias 46 may be formed on the insulating layer 50. The insulating layer 50 may be made of a resin coated film (RCF). In addition, a passivation layer 60 and an under bump metallurgy (UBM) layer 70 may be formed on top of the redistribution lines 44 and the conductive vias 46. The UBM layer 70 may be electrically connected to the redistribution lines 44 and the conductive vias 46. The UBM layer 70 may be formed on the passivation layer 60 formed on the insulating layer 50. Through this step, the redistribution lines 44, the conductive vias 46 disposed on the insulating layer 50, and the UBM layer 70 disposed on the passivation layer 60 are formed (RCF-UBM).

[0112] Thereafter, a step of disposing an electrical connection member 80 on the UBM layer 70 is performed. The electrical connection member 80 may be in the shape of a ball (ball mount).

[0113] Finally, a step is performed to remove the laminate layer 200 from the bottom surface of the semiconductor package. The laminate layer 200 can be removed by grinding the bottom surface of the semiconductor package (Back-grind).

[0114] Meanwhile, in this embodiment, the second sawing process for separating the semiconductor package into individual dies can be performed before or after removing the laminate layer 200 .

Claims

1. disposing a plurality of dies on a carrier in horizontally spaced-apart relation; a first sawing step of sawing the carrier to separate it into sub-panels on which the plurality of dies are arranged; testing the die; a second sawing step of sawing between the dies of the sub-panel to separate them into individual semiconductor packages; the carrier includes a plurality of first regions in which the dies are arranged and a second region in which the dies are not arranged; 10. The method for manufacturing a semiconductor package, wherein a first horizontal distance from a side of the carrier to the first region is smaller than a second horizontal distance from the first region to the first region.

2. 2. The method of claim 1, wherein the first sawing step is performed by sawing along a first scribe lane disposed in the second region.

3. A first horizontal distance from the edge of the carrier to the first region is:

3. The method of claim 2, wherein the horizontal distance is smaller than a third horizontal distance from the first region to a side of the sub-panel that is relatively close to the first scribe lane.

4. The sub-panel comprises: From a planar point of view, 2. The method of claim 1, wherein the first region is surrounded by a second region.

5. the carrier is separated into a plurality of the sub-panels; 2. The semiconductor package according to claim 1, wherein at least two of the plurality of sub-panels have different horizontal areas.

6. Career and an adhesive layer disposed on the carrier; a plurality of dies disposed on the adhesive layer and adhered by the adhesive layer; the carrier includes a plurality of first regions in which the dies are arranged and a second region in which the dies are not arranged; A semiconductor package, wherein a horizontal distance from the side of the carrier to the first region is smaller than a horizontal distance from the first region to the first region.

7. The semiconductor package according to claim 6 , wherein a first scribe lane along which the carrier is sawed is disposed in the second region.

8. From a planar point of view, 7. The semiconductor package of claim 6, wherein the first region is surrounded by the second region.

9. disposing a plurality of dies and a dummy die spaced apart from one another on a carrier; a first sawing step of sawing the carrier to separate it into sub-panels on which the plurality of dies and a dummy die are arranged; testing the die; a second sawing step of sawing between the dies of the sub-panel to separate them into individual semiconductor packages; the carrier includes a plurality of first regions in which the dies are arranged and a second region in which the dies are not arranged; The method for manufacturing a semiconductor package, wherein the dummy die is disposed adjacent to a side of the first region.

10. 10. The method of claim 9, wherein the horizontal area of ​​the dummy die is different from the horizontal area of ​​the die.

11. From a planar point of view, Within the sub-panel: The dummy die is Surrounding the die, The method for manufacturing a semiconductor package according to claim 9, wherein the insulating film is disposed along at least one side of the sub-panel.

12. 10. The method of claim 9, wherein the dummy die is arranged along a side of the carrier.

13. From a planar point of view, 10. The semiconductor package of claim 9, wherein the dummy dies are arranged in one or more rows or columns within the sub-panel.

14. Career and an adhesive layer disposed on the carrier; a plurality of dies and a dummy die disposed on the adhesive layer and adhered by the adhesive layer; the carrier includes a plurality of first regions in which the die and dummy die are arranged and a second region in which the die is not arranged; The semiconductor package, wherein the dummy die is disposed adjacent to at least one side of the first region.

15. From a planar point of view, Inside the subpanel, the second region surrounds the first region; The semiconductor package according to claim 14 , wherein the dummy die is disposed along a side of the carrier.

16. From a planar point of view, The dummy die is Within the first region, The semiconductor package according to claim 14 , wherein the first region is disposed along at least two sides thereof.

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