In-package patch antenna

Abstract

In some examples, a semiconductor package (300) includes a semiconductor substrate (1039) including a device side having circuitry formed therein. The package also includes a conductive layer (1000) disposed over the semiconductor substrate, a patch antenna (112) coupled to the conductive layer and to the device side of the semiconductor substrate, and a molding compound (304) covering the patch antenna. The molding compound has a dielectric constant in the range of 3.4 to 3.5 and a loss tangent in the range of 0.0025 to 0.013.

Description

[Technical Field]

[0001] Devices that engage in wireless communications may include one or more antennas. Such antennas may be incorporated into wireless devices in a variety of configurations. In some configurations, the antenna may be included on a semiconductor die along with circuitry configured to operate the antenna for wireless communications. Such antennas are sometimes referred to as "on-chip antennas" because they are on the semiconductor die or are co-located in the same semiconductor package as the semiconductor die. Summary of the Invention

[0002] In some examples, a semiconductor package includes a semiconductor substrate, the semiconductor substrate including a device side having circuitry formed therein. The package also includes a conductive layer disposed over the semiconductor substrate, a patch antenna coupled to the conductive layer and to the device side of the semiconductor substrate, and a molding compound covering the patch antenna. The molding compound has a dielectric constant in the range of 3.4 to 3.5 and a loss tangent in the range of 0.0025 to 0.013.

[0003] In some examples, a method for manufacturing a semiconductor package includes bonding a first conductive layer to a semiconductor substrate; bonding a second conductive layer to the first conductive layer using a via, the via extending through an insulating layer between the first and second conductive layers, the second conductive layer being farther from the semiconductor substrate than the first conductive layer; forming a cavity in a surface of the second conductive layer facing away from the semiconductor substrate, the cavity having a metal floor and a plurality of metal walls, the floor and the plurality of walls being coupled to a ground connection of the semiconductor substrate through the via; disposing a patch antenna in the cavity; and covering the patch antenna with a molding compound. [Brief explanation of the drawings]

[0004] [Figure 1A]1 is a perspective view of a patch antenna semiconductor die configured to efficiently radiate wireless signals, in accordance with various examples.

[0005] [Figure 1B] 1 is a top view of a patch antenna semiconductor die configured to efficiently radiate wireless signals, in accordance with various examples.

[0006] [Figure 1C] 1 is a side view of a patch antenna semiconductor die configured to efficiently radiate wireless signals, in accordance with various examples.

[0007] [Figure 2A] 1 is a perspective view of a patch antenna configured to efficiently radiate wireless signals, in accordance with various examples.

[0008] [Figure 2B] 1 is a top view of a patch antenna configured to efficiently radiate wireless signals, in accordance with various examples.

[0009] [Figure 3A] 1 is a perspective view of a patch antenna semiconductor package configured to efficiently radiate wireless signals, in accordance with various examples.

[0010] [Figure 3B] 1 is a top view of a patch antenna semiconductor package configured to efficiently radiate wireless signals, in accordance with various examples.

[0011] [Figure 3C] 1 is a side view of a patch antenna semiconductor package configured to efficiently radiate wireless signals, in accordance with various examples.

[0012] [Figure 4] 10 is a graph illustrating radiation efficiency as a function of thickness of various molding compounds in a patch antenna semiconductor package, according to various examples.

[0013] [Figure 5A] 1 is a perspective view of a patch antenna semiconductor package and a radiation gain pattern that efficiently radiates a wireless signal, in accordance with various examples.

[0014] [Figure 5B] 1 is a perspective view of a patch antenna semiconductor package and a radiation gain pattern that efficiently radiates a wireless signal, in accordance with various examples.

[0015] [Figure 5C] 1 is a perspective view of a patch antenna semiconductor package and a radiation gain pattern that efficiently radiates a wireless signal, in accordance with various examples.

[0016] [Figure 6] 1 is a 3D polar plot of the gain of a wireless signal efficiently radiated by a patch antenna semiconductor package, in accordance with various examples.

[0017] [Figure 7] 1 is a graph illustrating gain and return loss as a function of frequency of a signal radiated by a patch antenna package, in accordance with various examples.

[0018] [Figure 8] 10 is a graph illustrating radiation efficiency as a function of signal frequency for various ranges of dielectric constants of patch antenna semiconductor package molding compounds, in accordance with various examples.

[0019] [Figure 9] 10 is a graph illustrating radiation efficiency as a function of signal frequency for various ranges of loss tangents of patch antenna semiconductor package molding compounds, in accordance with various examples.

[0020] [Figure 10] 1 is a cross-sectional side view of a patch antenna semiconductor die configured to efficiently radiate wireless signals, in accordance with various examples.

[0021] [Figure 11] 1 is a flowchart of a method for manufacturing a patch antenna semiconductor package, in accordance with various examples.

[0022] [Figure 12A] 1 is a process flow of a method for manufacturing a patch antenna semiconductor package, according to various examples. [Figure 12B] 1 is a process flow of a method for manufacturing a patch antenna semiconductor package, according to various examples. [Figure 12C] 1 is a process flow of a method for manufacturing a patch antenna semiconductor package, according to various examples. [Figure 12D] 1 is a process flow of a method for manufacturing a patch antenna semiconductor package, according to various examples. [Figure 12E] 1 is a process flow of a method for manufacturing a patch antenna semiconductor package, according to various examples. [Figure 12F] 1 is a process flow of a method for manufacturing a patch antenna semiconductor package, according to various examples. [Figure 12G] 1 is a process flow of a method for manufacturing a patch antenna semiconductor package, according to various examples. [Figure 12H] 1 is a process flow of a method for manufacturing a patch antenna semiconductor package, according to various examples. [Figure 12I] 1 is a process flow of a method for manufacturing a patch antenna semiconductor package, according to various examples. [Figure 12J] 1 is a process flow of a method for manufacturing a patch antenna semiconductor package, according to various examples. DETAILED DESCRIPTION OF THE INVENTION

[0023] On-chip antennas suffer from several drawbacks that reduce their radiation efficiency during operation. These drawbacks are particularly problematic in the millimeter-wave range, e.g., the 30 GHz to 300 GHz range. For example, in some semiconductor package configurations, on-chip patch antennas (i.e., antennas comprising a planar sheet of metal coupled to or positioned in close proximity to a ground plane) are positioned at an undesirable distance from the ground plane. Therefore, this configuration of two metal plates (antenna and ground plane) separated by a dielectric exhibits capacitive behavior, tending to store energy rather than radiate it. This reduces operational efficiency. Additionally, molding compounds used to cover semiconductor package components containing patch antennas have inherent properties that impart significant dielectric loss to radiated energy. Furthermore, structures adjacent to the patch antenna and the semiconductor package containing the antenna can reflect or absorb radiated energy, thereby reducing radiation efficiency. When wireless signals are radiated with low directionality (i.e., the radiated energy is not focused in a specific direction), the signal is more likely to encounter these nearby structures, which can reduce the total amount of energy that can reach the intended wireless communication destination.

[0024] This disclosure describes various examples of patch antenna semiconductor packages that alleviate the above-mentioned problems. In particular, the example packages include a semiconductor die having a ground structure that extends through the die from the device (i.e., circuit element) side of the silicon near the bottom of the die to a patch antenna near the top of the die. The ground structure may include, for example, four walls, each of which includes a series of metal layers and vias connected in a chain configuration, extending vertically through the die by connecting to the silicon at one end (e.g., at a ground node of the silicon) and extending at the other end to a cavity that houses the patch antenna. Also, in some examples, the cavity at the top of the package may contain the patch antenna and may have a floor and walls covered by or composed of metal that is connected to the chain of metal layers and vias described above. During operation, the ground structure directs radiated energy vertically and outward away from the die, preventing energy from radiating horizontally. In this way, the ground structure promotes radiation of energy in desired directions instead of dissipating the energy horizontally (sideways) or in other undesired directions. Although the ground structure is described as having four walls, the ground structure may have a different number of walls (e.g., three or five walls).

[0025] Additionally, in some examples, the semiconductor packages described herein include a molding compound that covers package components, such as the semiconductor die and patch antenna. The molding compound has certain properties important for improving radiation efficiency and directivity. For optimal performance, experimental simulation data indicates that it is important for the molding compound of the semiconductor package to have a dielectric constant between 2.36 and 3.4 and a loss tangent between 0.013 and 0.0025. The molding compound may have other characteristics that also improve radiation efficiency, such as a thickness (between the patch antenna and the top of the molding compound) of approximately one-quarter of the wavelength of the radiated signal. (A molding compound thickness of one-quarter of the signal wavelength is used because, in wave theory, this thickness contributes to constructive interference and therefore radiation efficiency, e.g., because, as a wave incident from the antenna traverses the one-quarter wavelength molding compound thickness, it is reflected from the medium interface back toward the antenna, thus traversing another one-quarter wavelength distance and combining with the wave incident from the antenna.) These and other features are described with reference to the drawings.

[0026] FIG. 1A is a perspective view of a patch antenna semiconductor die 100 configured to efficiently radiate wireless signals, according to various examples. Die 100 may be included as part of a semiconductor package, as described below. Die 100 includes a portion 102 and a portion 104. In some examples, portion 104 is part of portion 102 but is shown as a separate component for ease of understanding. Portion 102 may include various components, such as a silicon substrate including the device side on which circuit elements are formed. Portion 102 may also include a back end of line (BEOL), including metal layers, insulating materials separating the metal layers from one another, and vias connecting the metal layers. Some of the metal layers may form a network to facilitate communication between various circuit elements on the device side of the silicon. These features are described below. Portion 104 may include the final or top metal layer of the BEOL. Thus, the BEOL extends across both portions 102 and 104. Some of the metal layers may form a network to facilitate communication between various circuit elements on the device side of the silicon and bond pads 306 on portion 104 .

[0027] Portion 104 includes a cavity 106. Cavity 106 has a floor 108 and a number of walls 110. As discussed, cavity 106 and floor 108 may overlie or be constructed from a metal layer of portion 104. The cavity houses a patch antenna 112 (e.g., a 45 nm complementary metal oxide semiconductor (CMOS) process). Cavity 106 may have any suitable size and shape to house patch antenna 112. Patch antenna 112 includes a radiating portion 114 and a feed line 116 coupled to radiating portion 114. Radiating portion 114 may be of any suitable shape and size to radiate energy (signal) outward and away from portion 104. The feed line 116 extends horizontally from the radiating portion 114 as shown, and at a point distal to the radiating portion 114, the feed line 116 couples vertically downward to the back-end of the optical fiber in the portion 102. The feed line 116 provides a signal between the back-end of the optical fiber in the portion 102 and the radiating portion 114.

[0028] The floor 108 and / or walls 110 of the cavity 106 include metal that is coupled to a ground node in the die 100. In some examples, the floor 108 and / or walls 110 are separate from the portion 104, which may itself be the top-most metal layer, but are coupled to or in contact with the portion 104. In other examples, the floor 108 and / or walls 110 are part of the portion 104 (e.g., the top-most metal layer). In some examples, the back-end of the circuit (BEOL) of the portions 102 and 104 (described in more detail below) connects to a ground node on the silicon in the portion 102 through a series of connections in the back-end of the circuit (BEOL) of the portion 102, which extends from the silicon to the portion 104, the floor 108, and the walls 110. This forms one wall of the aforementioned ground structure. Additional similar walls may also be formed in the die 100, and these walls may be coupled to each other, just as the walls of a rectangular prism may be coupled to each other. The ground structure prevents or blocks energy from radiating horizontally. Figure 1B is a top view of a die 100, and Figure 1C is a side view of a die 100, according to various examples.

[0029] 2A and 2B provide more detailed views of the patch antenna 112 of FIGS. 1A-1C. Specifically, FIG. 2A is a perspective view of the patch antenna 112 configured to efficiently radiate wireless signals, according to various examples. FIG. 2B is a top view of the patch antenna 112 configured to efficiently radiate wireless signals, according to various examples. The cavity 106 has specific dimensions to promote radiation efficiency, and these dimensions are expressed relative to the patch antenna 112. The distance 118 between any point on the wall 110 and the nearest point on the patch antenna 112 should be in the range of 20 microns to 30 microns; a distance 118 smaller than this range is disadvantageous because it increases coupling between the patch and the ground wall, and a distance larger than this range is disadvantageous because it increases surface wave modes. The length of the patch antenna 112 is approximately half the wavelength of the signal transmitted from or received by the patch antenna 112, and the width of the patch antenna 112 is adjusted to generate a wide bandwidth, as desired. The patch antenna 112 receives communications from circuit elements within the die 100 via the feed line 116 and radiates energy in response; similarly, the patch antenna 112 receives communications wirelessly and provides corresponding signals to the feed line 116 to the circuit elements. In some examples, the feed line 116 is a microstrip. In some examples, the feed line 116 is a 50 ohm microstrip having a width of approximately 17 microns. In some examples, the patch antenna 112 is configured to operate in the millimeter-wave range (e.g., 30 GHz to 300 GHz). The circuit elements in communication with the patch antenna 112 may be located on the silicon, in the BEOL of the die 100, on the floor 108, or any combination thereof.

[0030] FIG. 3A is a perspective view of a patch antenna semiconductor package 300 configured to efficiently radiate wireless signals, according to various examples. In some examples, the package 300 includes a substrate 302 on which a semiconductor die 100 is disposed. For example, the die 100 may be disposed on the substrate 302 by a die attach film. A molding compound 304 may be applied to cover the die 100 and the substrate 302. Circuit elements within the die 100 (e.g., circuit elements formed on silicon) may communicate with electronics outside the package 300 by wire bonds 310 that couple bond pads 306 to conductive terminals 308. The conductive terminals 308 are exposed outside the molding compound 304, thereby allowing the conductive terminals 308 to be bonded (e.g., soldered) to metal contacts on a printed circuit board or other device. FIG. 3B is a top view of the structure of FIG. 3A, and FIG. 3C is a side view of the structure of FIG. 3A.

[0031] The molding compound 304 has specific properties that improve radiation efficiency. The thickness of the molding compound 304, measured from the top surface of the patch antenna 112 to the top surface of the molding compound 304, is approximately one-quarter of the wavelength of the signal that the patch antenna 112 is configured to radiate. Experimental data indicates that a molding compound 304 having this thickness (i.e., one-quarter of the wavelength of the signal that the patch antenna 112 is configured to radiate) provides a 20% improvement in radiation efficiency compared to a molding compound without this specific thickness. Therefore, the thickness of this molding compound is important to achieve the approximately 20% improvement in radiation efficiency, and molding compounds thinner or thicker than this thickness result in inferior radiation efficiency. In addition to the thickness of the molding compound 304, the composition of the molding compound 304 also affects radiation efficiency. Table 1 provides experimental data showing the critical material properties of the molding compound 304 for achieving superior radiation efficiency, particularly with respect to the dielectric constant and loss tangent of the molding compound 304. Materials 1 through 5 listed in Table 1 are epoxy-based molding compounds containing silica filler particles. Table 1. Experimental data showing the key material properties of molding compound 304 for achieving superior radiation efficiency. JPEG2025529437000002.jpg46138

[0032] Figure 4 shows the performance of Materials 1 through 5 in Table 1. Specifically, Figure 4 illustrates the radiation efficiency as a function of molding compound 304 thickness at a frequency of 300 GHz. The thickness of molding compound 304 is defined as the distance from the top surface of patch antenna 112 to the top surface of molding compound 304. 300 GHz is the frequency at which patch antenna 112 radiates energy. The behavior shown in Figure 4 applies not only to 300 GHz but also to a range of frequencies in the mm-wave band. In graph 400 of Figure 4, curve 402 shows the performance of Material 1, curve 404 shows the performance of Material 2, curve 406 shows the performance of Material 3, curve 408 shows the performance of Material 4, and curve 410 shows the performance of Material 5. The smaller the loss tangent of a given material, the higher the radiation efficiency of that material. This is true for electromagnetic waves propagating through any dielectric medium. However, the radiation efficiency of materials with different dielectric constants is not as easily predictable. As described below, experiments have shown that the specific process (e.g., a radio frequency (RF) CMOS process) used to form the back-end-of-line (BEOL) metal layers of a semiconductor die in a given package, the properties of the intermetal dielectric materials used in the BEOL metal layers, and the manner in which these materials interact with the dielectric constant of molding compound 304 contribute to the radiation efficiency of molding compound 304. The thickness of molding compound 304 is shown on the x-axis of graph 400, while the y-axis represents radiation efficiency. Curve 402 shows that Material 1 performs particularly poorly relative to Materials 2-5 in the molding compound thickness range of 0.0 mm to 0.18 mm, and performs relatively well in the molding compound thickness ranges of 0.2 mm to 0.3 mm and 0.5 mm to 0.6 mm. Curve 404 shows that Material 2 consistently outperforms Materials 1 and 3-5, or at least that none of Materials 1 and 3-5 outperforms Material 2. Therefore, Material 2 is a good candidate for improving radiation efficiency. Curve 406 shows that one or more of materials 1, 2, 4, and 5 generally outperform material 3 across most molding compound thickness ranges, and therefore material 3 is not a good candidate for inclusion in molding compound 304.Curve 408 shows that Material 4 outperforms the other materials in most of the mold compound thickness ranges of 1.2 mm to 1.8 mm and 0.4 mm to 0.46 mm, but Material 4 does not outperform Material 2 at any thickness. Finally, curve 410 shows that Material 5 is generally one of the worst performers of Materials 1 to 5. Comparing the relative performance of Materials 1 to 5, Material 2 clearly outperforms the remaining materials, and Material 1 also outperforms Materials 3 to 5 and is comparable to Material 2 in the mold compound thickness ranges of 0.2 mm to 0.3 mm and 0.5 mm to 0.6 mm.

[0033] 4, when Material 2 is used, the thickness of molding compound 304 may be 0.13 mm to 0.25 mm or 0.4 mm to 0.53 mm for optimal performance. Based on the results shown in FIG. 4, when Material 3 is used, the thickness of molding compound 304 may be 0 mm to 0.16 mm, or 0.16 mm to 0.3 mm, or 0.425 mm to 0.56 mm for optimal performance.

[0034] FIG. 5A is a perspective view of a semiconductor package 300 and the radiation gain pattern of an efficiently radiated wireless signal, according to various examples. In particular, FIG. 5A shows the radiation gain (radiation) pattern in the φ=0° plane 500 and the φ=90° plane 502. As shown, the radiation pattern is directional, meaning that the radiation pattern extends primarily from the patch antenna 112 in a direction perpendicular to the patch antenna 112. The radiation pattern assumes a molding compound 304 of Material 3 (Table 1), a thickness of 140 microns, and an operating frequency of 300 GHz (although similar radiation patterns may result from other operating frequencies in the millimeter-wave range). FIGS. 5B and 5C provide alternative side views of the radiation pattern shown in FIG. 5A, according to various examples.

[0035] FIG. 6 provides another illustration of the gain (radiation) pattern provided by semiconductor package 300. The illustration in FIG. 6 is a 3D polar plot of gain at 300 GHz, but similar radiation patterns may result from other operating frequencies in the millimeter-wave frequency range. FIG. 6 assumes molding compound 304 of Material 3 (Table 1) and a thickness of 140 microns. As shown in FIG. 6, the peak gain is approximately 4.363 dB. Importantly, the peak gain level is perpendicular to patch antenna 112 (FIG. 5A), e.g., along a vertical axis extending perpendicularly from patch antenna 112 as indicated by reference numeral 602, and the minimum gain level is perpendicular to such vertical axis as indicated by reference numeral 604.

[0036] 7 is a graph 700 illustrating gain and return loss (in dB) as a function of frequency (in GHz) of a signal radiated by patch antenna semiconductor package 300, according to various examples. Graph 700 includes curve 702 (return loss with molding compound 304 present in semiconductor package 300), curve 704 (return loss without molding compound 304 present in semiconductor package 300), curve 706 (peak gain without molding compound 304 present in semiconductor package 300), and curve 708 (peak gain with molding compound 304 present in semiconductor package 300). As curves 702 and 704 show, the presence of molding compound 304 within package 300 results in wider impedance bandwidth performance over a sweep of operating frequencies from 270 GHz to 330 GHz. As curves 706 and 708 show, over a sweep of operating frequencies from 270 GHz to 330 GHz, the presence of molding compound 304 in package 300 consistently produces superior gain compared to the absence of molding compound 304 in package 300.

[0037] FIG. 8 is a graph 800 illustrating radiation efficiency as a function of signal frequency for a range of molding compound dielectric constant values, according to various examples. Graph 800 includes curves 802, 804, 806, 808, 810, 812, 814, 816, and 818 for dielectric constant values ​​of 1, 1.5, 2, 2.5, 3, 3.5, 3.55, 4, and 5, respectively. The molding compound loss tangent is held constant at 0.013 to facilitate an even comparison of the range of dielectric constant values. As shown, for the frequency sweep range of 270 GHz to 330 GHz, curve 814 (dielectric constant 3.55) has the highest area under the curve (AUC) and therefore the best overall performance among the various molding compound dielectric constants.

[0038] FIG. 9 is a graph 900 illustrating radiation efficiency as a function of signal frequency for a range of molding compound loss tangent values, according to various examples. Graph 900 includes curves 902, 904, 906, 908, 910, 912, and 914 for loss tangent values ​​of 0.0095, 0.008, 0.0065, 0.005, 0.0035, 0.002, and 0.0005, respectively. The molding compound's dielectric constant is held constant at 3.55 to facilitate an even comparison of loss tangent values ​​across this range. As shown, for a frequency sweep range of 270 GHz to 330 GHz, the curve representing the lowest loss tangent (in this case, curve 914, corresponding to a loss tangent of 0.0005) produces the highest radiation efficiency. These experimental data are useful for determining the molding compound's dielectric constant and loss tangent value combination with the highest radiation efficiency, as shown in Table 1.

[0039] FIG. 10 is a cross-sectional side view of a patch antenna semiconductor die 100 configured to efficiently radiate wireless signals, according to various examples. Die 100 includes a silicon substrate 1039 (also referred to herein as silicon 1039, although other types of semiconductors may be used in place of silicon) having a device side containing circuit elements and a non-device side opposite the device side. The device side faces upward toward the remaining structure of die 100. Die 100 includes multiple metal layers 1000-1008. Die 100 also includes portion 104, which is the top-most metal layer. Metal layer 1000 is coupled to silicon 1039 through via 1009 (e.g., to a ground node on the device side of silicon 1039). Metal layers 1001-1008 are coupled to metal layers 1000-1007 by vias 1010-1017, respectively. A via 1018 couples metal layer 1008 to portion 104 (e.g., a top-most metal layer of the back-end) and / or floor 108 and / or wall 110. Metal layers 1000-1008, vias 1009-1018, portion 102, and floor 108 and wall 110 of cavity 106 form a ground wall, as described above. Die 100 also includes metal layers 1019-1027 and vias 1028-1037. Metal layers 1020-1027 are coupled to metal layers 1019-1026 by vias 1029-1036, respectively. In some examples, via 1037 couples metal layer 1027 to portion 104 (e.g., a top-most metal layer of the back-end) and / or floor 108 and / or wall 110. The diagram of FIG. 10 therefore shows two ground walls. Die 100 includes two additional ground walls that are not visible in the plan view of FIG. 10 . Together, these four ground walls form the ground structure described herein. The spaces between the ground walls are vertically aligned with patch antenna 112. Therefore, during operation, energy radiated by patch antenna 112 propagates vertically, and the ground structure comprised of the aforementioned ground walls prevents or at least mitigates horizontal / lateral radiation. This provides directionality to the energy radiation, causing more energy to radiate vertically, specifically upward from die 100, thereby increasing radiation efficiency. Alternative configurations are contemplated and within the scope of this disclosure.An insulating material 1038 (eg, polyimide) covers the various metal layers and vias within die 100 as shown.

[0040] 10, the metal layers in portion 102 are shown as having a combined thickness that is greater than the thickness of silicon 1039. However, in some instances, the thickness of silicon 1039 may substantially exceed the combined thickness of the metal layers in portion 102.

[0041] FIG. 11 is a flowchart of a method 1100 for fabricating a patch antenna semiconductor package, such as package 300, according to various examples. FIGS. 12A-12J are process flows for methods for fabricating a patch antenna semiconductor package, such as package 300, according to various examples. Accordingly, FIGS. 11 and 12A-12J are now described simultaneously. Method 1100 begins with bonding a first conductive layer to a silicon substrate (1102). FIG. 12A shows silicon 1039 and vias 1028 and 1009 formed on the device side of silicon 1039. Vias 1028 and 1009, as well as the remaining vias and conductive / metal layers described herein, can be formed by any suitable technique, such as plating techniques using appropriate seed layers and / or other materials. FIG. 12B shows application of insulating material 1038 to silicon 1039 and vias 1028 and 1009. FIG. 12C shows the formation of conductive layers 1019 and 1000 which are coupled to vias 1028 and 1009, respectively.

[0042] The method 1100 includes coupling a second conductive layer to the first conductive layer using a first via, the first via extending through an insulating layer between the first conductive layer and the second conductive layer, the second conductive layer being further from the silicon than the first conductive layer (1104). Figure 12D shows the formation of vias 1029 and 1010 on the conductive layers 1019 and 1000, respectively. Figure 12E shows the application of insulating material 1038 to the vias 1029 and 1010 and the conductive layers 1019 and 1000. Figure 12F shows the formation of conductive layers 1020 and 1001 coupled to the vias 1029 and 1010, respectively.

[0043] Method 1100 also includes coupling the third conductive layer to the second conductive layer by a second via extending through the insulating material (1106). Method 1100 further includes forming a cavity in a surface of the third conductive layer facing away from the silicon, the cavity having a floor and multiple walls (1108). Method 1100 includes forming a metal layer in the cavity, the metal layer being included in at least one of the floor and walls of the cavity (e.g., the floor and at least one wall are composed of the metal layer), the metal layer being coupled to a ground connection of the silicon through the first and second conductive layers and the first and second vias (1110). Figure 12G shows the formation of vias 1030 and 1011 along with the application of additional insulating material 1038. Figure 12H shows the formation of third conductive layer 104 and cavity 106 in the top surface of third conductive layer 104. In some examples, a cavity is formed in the third conductive layer 104 via appropriate photolithography and plating techniques. In some examples, a metal layer is formed on the floor 108 and one or more walls 110 of the cavity 106, with the metal layer on the floor 108 contacting the vias 1011 and 1030. In some examples, the floor 108 and walls 110 are part of the third conductive layer 104, and the vias 1030, 1011 are coupled to the third conductive layer 104, the floor 108, and / or the walls 110.

[0044] Method 1100 includes disposing 1112 a patch antenna within the cavity. FIG. 12I shows patch antenna 112 disposed within cavity 106. In some examples, patch antenna 112 is part of a metal layer (not explicitly shown) within portion 102. In addition to coupling to circuit elements on silicon 1039, feed line 116 may also be coupled to circuit elements formed in the metal layer of portion 102, circuit elements formed on floor 108, or a combination thereof. Method 1100 includes bonding the semiconductor die to a substrate (e.g., a printed circuit board), wire-bonding bond pads on the die to conductive terminals, and covering 1114 the patch antenna, as well as various conductive and insulating layers, the cavity, the conductive terminals, and the substrate, with a molding compound. FIG. 12J shows an example package 300 including substrate 302 and molding compound 304 that covers various components of package 300. Although package 300 of FIG. 12J has a different number of conductive layers and vias than die 100 in FIG. 10, any suitable number of conductive layers and / or vias may be useful.

[0045] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform a certain action, (A) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B through an intervening component C, where intervening component C does not change the functional relationship between device A and device B, allowing device B to be controlled by device A through a control signal generated by device A.

[0046] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the configuration and / or layout of hardware components, through the device's interconnections, or through a combination thereof.

[0047] Circuit elements or devices described herein as including particular components may instead be combined with those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be combined with at least some of the passive elements and / or sources during or after manufacture, e.g., by an end user and / or third party, to form the described structure.

[0048] Use of the term "ground" and variations thereof in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this description. As used herein, unless otherwise specified, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of that parameter. Modifications may be made to the described examples, and other embodiments are possible, within the scope of the claims of the present invention.

Claims

1. A semiconductor package comprising: a semiconductor substrate including a device side having circuit elements formed therein; a conductive layer disposed above the semiconductor substrate; a patch antenna coupled to the conductive layer and to the device side of the semiconductor substrate; a molding compound covering the patch antenna, the molding compound having a dielectric constant in the range of 3.4 to 3.5 and a loss tangent in the range of 0.0025 to 0.013; 1. A semiconductor package comprising:

2. 10. The semiconductor package of claim 1, wherein the molding compound has a dielectric constant of about 3.4 and a loss tangent of about 0.0025.

3. 3. The semiconductor package of claim 2, wherein the molding compound has a vertical thickness in the range of 0.13 mm to 0.25 mm.

4. 3. The semiconductor package of claim 2, wherein the molding compound has a vertical thickness in the range of 0.4 mm to 0.53 mm.

5. 10. The semiconductor package of claim 1, wherein the molding compound has a dielectric constant of about 3.5 and a loss tangent of about 0.

013.

6. 6. The semiconductor package of claim 5, wherein the molding compound has a vertical thickness in the range of 0 mm to 0.16 mm.

7. 6. The semiconductor package of claim 5, wherein the molding compound has a vertical thickness in the range of 0.16 mm to 0.3 mm.

8. 6. The semiconductor package of claim 5, wherein the molding compound has a vertical thickness in the range of 0.425 mm to 0.56 mm.

9. 10. The semiconductor package of claim 1, wherein the molding compound has a vertical thickness of one-quarter of a wavelength of a signal that the patch antenna is configured to radiate.

10. A semiconductor package comprising: a semiconductor substrate including a device side having circuit elements formed therein; a plurality of conductive layers disposed above the semiconductor substrate, each of the plurality of conductive layers being coupled to another one of the plurality of conductive layers by a different via, the plurality of conductive layers including a top conductive layer disposed farthest from the semiconductor substrate; a ground member in the cavity of the top conductive layer, the ground member being coupled to a ground connection in the circuit element through the via; a patch antenna within the cavity; a molding compound covering the patch antenna; Including, the molding compound has a dielectric constant in the range of 3.4 to 3.5, and the thickness from the patch antenna to the top surface of the molding compound is about one-quarter of the wavelength of a radio signal to be radiated by the patch antenna; Semiconductor package.

11. 11. The semiconductor package of claim 10, wherein the ground member is included in the floor of the cavity.

12. 11. The semiconductor package of claim 10, wherein the ground member covers a plurality of walls of the cavity.

13. 11. The semiconductor package of claim 10, wherein the molding compound has a dielectric constant of about 3.

4.

14. 11. The semiconductor package of claim 10, wherein the molding compound has a loss tangent of about 0.0025.

15. A semiconductor package comprising: a semiconductor substrate including a device side having circuit elements formed therein; a plurality of conductive layers disposed above the semiconductor substrate, each of the plurality of conductive layers being coupled to another one of the plurality of conductive layers by a different via, the plurality of conductive layers including a top conductive layer disposed farthest from the semiconductor substrate; a ground member in the cavity of the top conductive layer, the ground member being coupled to a ground connection in the circuit element through the via, the ground member being contained in a floor portion of the cavity and a wall portion of the cavity; a patch antenna within the cavity; a molding compound covering the patch antenna, the molding compound having a dielectric constant in the range of 3.4 to 3.5 and a loss tangent in the range of 0.0025 to 0.013; 1. A semiconductor package comprising:

16. 16. The semiconductor package of claim 15, wherein the ground member covers all walls of the cavity.

17. 17. The semiconductor package of claim 16, wherein the distance between the edge of the patch antenna and the nearest wall of the cavity is between 20 and 30 microns.

18. 16. The semiconductor package of claim 15, wherein the molding compound has a dielectric constant of about 3.4 and a loss tangent of about 0.0025.

19. 20. The semiconductor package of claim 18, wherein the molding compound has a vertical thickness in the range of 0.13 mm to 0.25 mm.

20. 20. The semiconductor package of claim 18, wherein the molding compound has a dielectric constant of about 3.5 and a loss tangent of about 0.

013.

21. 1. A method for manufacturing a semiconductor package, comprising: coupling the first conductive layer to a semiconductor substrate; coupling a second conductive layer to the first conductive layer using a via, the via extending through an insulating layer between the first conductive layer and the second conductive layer, the second conductive layer being further from the semiconductor substrate than the first conductive layer; forming a cavity in a surface of the second conductive layer facing away from the semiconductor substrate, the cavity having a metal floor and a plurality of metal walls, the floor and the plurality of walls being coupled to a ground connection of the semiconductor substrate through the via; disposing a patch antenna within the cavity; covering the patch antenna with a molding compound; A method comprising:

22. The method of claim 21, wherein the molding compound has a dielectric constant in the range of 3.4 to 3.

5.

23. 22. The method of claim 21, wherein the molding compound has a loss tangent of about 0.0025.

24. 22. The method of claim 21, wherein the molding compound has a loss tangent of about 0.013.

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