Highly Connected Parametric Gates

Abstract

One or more systems, devices, and / or methods of manufacture and / or use provided herein relate to quantum computing processes for achieving greater connectivity of qubits to more-than-nearest neighbors and / or to multiple nearest neighbors. The system may include a tunable first coupler coupled to a first qubit, a tunable second coupler coupled to a second qubit, and a junction coupling the first and second couplers, both of which are parametrically excitable. The first and second couplers may comprise superconducting quantum interference devices or Josephson junctions. The junction may include a central hub or node separately coupled to the first and second couplers. The first and second couplers may be configured to capacitively or inductively couple the first and second qubits to one another to perform a controlled-Z (CZ) gate or an iSWAP gate.

Description

[Technical Field]

[0001] The present disclosure relates to the implementation of quantum circuits in quantum devices, and more particularly to the implementation of parametric gates that utilize qubits that have high interconnectivity with each other. [Background technology]

[0002] In quantum computing systems, it can be difficult to couple qubits over long distances without affecting the quality of qubit measurements and / or the state of one or more of the coupled or adjacent qubits in a system with multiple qubits. These challenges can increase as quantum computing devices scale in size and quantity of qubits. Summary of the Invention

[0003] The following presents a summary to provide a basic understanding of one or more embodiments described herein. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, systems, computer-implemented methods, apparatuses, and / or computer program products can provide processes for coupling qubits and activating one or more bonds coupling the qubits to one another.

[0004] Generally, an electronic device may be provided that can use all-to-all connections between multiple qubits and enable the operation of parametric gates.

[0005] According to an embodiment, an electronic device may include a tunable first coupler coupled to a first quantum bit, a tunable second coupler coupled to a second quantum bit, and a junction coupling the first coupler and the second coupler, wherein the first coupler and the second coupler are parametrically excitable.

[0006] Advantages of the electronic devices shown above may be larger quantum volumes and improved quantum algorithm implementation and / or performance, which may result from fewer gates, fewer swaps, and / or fewer errors (or fewer error introductions).

[0007] According to another embodiment, a method of performing a quantum gate operation may include applying, by a system operatively coupled to a processor, a first bias and a first parametric excitation to a first coupler coupled to a first qubit; applying, by the system, a second bias and a second parametric excitation to a second coupler coupled to a second qubit and to the first coupler; and performing, by the system, a parametric gate operation utilizing the first qubit and the second qubit.

[0008] Advantages of the methods presented above may be larger quantum volumes and improved quantum algorithm implementations and / or demonstrations, which may result from fewer gates, fewer swaps, and / or fewer errors (or fewer error introductions).

[0009] According to yet another embodiment, an electronic device can include a plurality of tunable couplers having a superconducting quantum interference device, each tunable coupler separately coupled to a respective quantum bit, and a junction coupling the plurality of tunable couplers by an all-to-all coupling, wherein the plurality of tunable couplers are not otherwise coupled to one another except by the junctions, and wherein the first coupler and the second coupler are parametrically excitable.

[0010] Advantages of the electronic devices shown above may be larger quantum volumes and improved quantum algorithm implementation and / or performance, which may result from fewer gates, fewer swaps, and / or fewer errors (or fewer error introductions).

[0011] Yet another advantage of one or more embodiments described herein may be that multiple electronic devices and / or systems may be used in combination with one another to reduce thermal population of loading.

[0012] Yet another advantage of one or more embodiments described herein may be to utilize the same electronic device and / or system, such as one having four or more qubits, to perform multiple highly connected operations, such as at least partially simultaneously with one another. Indeed, such an electronic device may utilize a single junction separately coupled to each of the four qubits.

[0013] One or more of the innovations, frameworks, systems, devices, and / or methods described herein may additionally and / or alternatively be described as follows.

[0014] The electronic device can include a tunable first coupler coupled to a first quantum bit, a tunable second coupler coupled to a second quantum bit, and a junction coupling the first coupler and the second coupler, wherein the first coupler and the second coupler are parametrically excitable.

[0015] According to the electronic device, the first coupler and the second coupler may comprise a superconducting quantum interference device or a Josephson junction.

[0016] According to the electronic device of any preceding paragraph of this section, the junction can have a central hub or node separately coupled to the first coupler and the second coupler.

[0017] According to the electronic device of any preceding paragraph of this section, the junction can have a central hub, and optionally the central hub can include a loop of series coupled inductors.

[0018] The electronic device of any preceding paragraph of this section may further comprise a third coupler coupled to a third qubit, wherein the junction may couple the first coupler, the second coupler, and the third coupler, and optionally the third coupler may be parametrically excitable, and optionally the junction may be separately coupled to the first coupler, the second coupler, and the third coupler.

[0019] According to the electronic device of any preceding paragraph of this section, the junction may provide a unique coupling between the first qubit and the second qubit.

[0020] According to the electronic device of any preceding paragraph of this section, the first coupler and the second coupler may be configured to capacitively or inductively couple the first qubit and the second qubit to one another, and may optionally be configured to perform a controlled-Z (CZ) gate utilizing the first qubit and the second qubit.

[0021] According to the electronic device of any preceding paragraph of this section, the first coupler and the second coupler may be configured to capacitively or inductively couple the first qubit and the second qubit to one another, and may optionally be configured to perform an iSWAP gate utilizing the first qubit and the second qubit.

[0022] A method of performing a quantum gate operation may include applying, by a system operably coupled to a processor, a first bias and a first parametric excitation to a first coupler coupled to a first quantum bit; applying, by the system, a second bias and a second parametric excitation to a second coupler coupled to a second quantum bit and to the first coupler; and performing, by the system, a parametric gate operation utilizing the first quantum bit and the second quantum bit.

[0023] The method may further comprise applying, by the system, the first parametric excitation and the second parametric excitation at respective frequencies that are a difference between the respective frequencies of the first qubit and the second qubit.

[0024] The method of any preceding paragraph of this section may further comprise applying, by the system, the first parametric excitation and the second parametric excitation when the first qubit is in a respective excited state and the second qubit is in a respective excited state.

[0025] The method of any preceding paragraph of this section may further comprise applying, by a system, the first parametric excitation and the second parametric excitation at respective frequencies that are the difference between the respective frequencies of the first qubit and the second qubit, plus or minus anharmonicity of the first and second qubits.

[0026] The method of any preceding paragraph of this section may further comprise applying, by the system, the first parametric excitation and the second parametric excitation when one of the first qubit or the second qubit is in a respective excited state and the other of the first qubit or the second qubit is in a respective ground state.

[0027] The method of any preceding paragraph of this section may further include inductively coupling, by the system, the first coupler and the second coupler through a pair of radio frequency superconducting quantum interference devices in the first coupler and the second coupler.

[0028] The method of any preceding paragraph of this section may further comprise capacitively coupling, by the system, the first coupler and the second coupler by a single coupling node.

[0029] The method of any preceding paragraph of this section may further comprise applying, by the system, a third bias and a third parametric excitation to a third coupler coupled to a third qubit; optionally applying, by the system, a fourth bias and a fourth parametric excitation to a fourth coupler coupled to a fourth qubit; and optionally, performing, by the system, a second parametric gate operation utilizing the third qubit and the fourth qubit in parallel with the parametric gate operation, wherein the first coupler, the second coupler, the third coupler, and the fourth coupler are optionally coupled to each other by a single junction.

[0030] The electronic device can include a superconducting quantum interference device, a plurality of tunable couplers separately coupled to respective quantum bits, and a junction coupling the plurality of tunable couplers by all-to-all coupling, wherein the first coupler and the second coupler are parametrically excitable.

[0031] According to the electronic device, the junction may have a central hub, and optionally, the central hub may include a loop of series coupled inductors, and optionally, the number of series coupled inductors may be equal to the number of adjustable couplers of the plurality of adjustable couplers.

[0032] According to the electronic device of any preceding paragraph of this section, the plurality of tunable couplers may be configured to capacitively or inductively couple the respective pairs of qubits to one another, and may optionally be configured to implement a controlled-Z (CZ) gate or an iSWAP gate utilizing the respective pairs of qubits.

[0033] According to the electronic device of any preceding paragraph of this section, the plurality of tunable couplers and the junction may be jointly configured to perform a first parametric gate operation using a pair of tunable couplers from the plurality of tunable couplers, and optionally, in parallel with the first parametric gate operation, perform a second parametric gate operation using a different pair of tunable couplers from the plurality of tunable couplers. [Brief explanation of the drawings]

[0034] [Figure 1] 1 shows a schematic diagram of a quantum system according to one or more embodiments described herein.

[0035] [Figure 2] 2 shows a schematic diagram of an embodiment of an electronic device that can be utilized in the quantum system of FIG. 1 according to one or more embodiments described herein.

[0036] [Figure 3] 3 shows a pair of plots illustrating simulations of different quantum gate implementations utilizing the electronic device of FIG. 2 in accordance with one or more embodiments described herein.

[0037] [Figure 4] 10 shows a block diagram of another electronic device embodiment that can be utilized in the quantum system of FIG. 1 according to one or more embodiments described herein.

[0038] [Figure 5] 5 shows three plots illustrating a simulation of a quantum iSWAP gate performance utilizing qubits 1 and 2 of the electronic device of FIG. 4 in accordance with one or more embodiments described herein.

[0039] [Figure 6] 5 shows three plots illustrating a simulation of a quantum iSWAP gate performance utilizing qubits 2 and 3 of the electronic device of FIG. 4 in accordance with one or more embodiments described herein.

[0040] [Figure 7] 5 shows three plots illustrating a simulation of a quantum iSWAP gate performance utilizing qubits 1 and 3 of the electronic device of FIG. 4 in accordance with one or more embodiments described herein.

[0041] [Figure 8] 10 shows a block diagram of yet another embodiment of an electronic device that can be utilized in the quantum system of FIG. 1 according to one or more embodiments described herein.

[0042] [Figure 9] 10 shows a block diagram of yet another embodiment of an electronic device that can be utilized in the quantum system of FIG. 1 according to one or more embodiments described herein.

[0043] [Figure 10] 10 shows a block diagram of another electronic device embodiment that can be utilized in the quantum system of FIG. 1 according to one or more embodiments described herein.

[0044] [Figure 11] 1 illustrates a process flow for a method of manufacturing an electronic device according to one or more embodiments described herein.

[0045] [Figure 12] 1 illustrates a process flow for a method of using an electronic device according to one or more embodiments described herein.

[0046] [Figure 13] 1 illustrates a block diagram of an exemplary non-limiting operating environment in which one or more embodiments described herein may be provided.

[0047] [Figure 14] 1 illustrates a block diagram of an exemplary, non-limiting cloud computing environment in accordance with one or more embodiments described herein.

[0048] [Figure 15] 1 illustrates an exemplary, non-limiting block diagram of abstraction model layers according to one or more embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0049] The following detailed description is merely exemplary and is not intended to limit the embodiments and / or the application or uses of the embodiments. Furthermore, no binding obligation is intended by any express or implied information presented in the foregoing Summary section or the Detailed Description section. One or more embodiments will now be described with reference to the drawings, in which like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It will be apparent, however, that in various instances, one or more embodiments may be practiced without these specific details.

[0050] As used herein, a quantum circuit may include a set of operations, such as gates, that are performed on a set of real-world, physical qubits to obtain one or more qubit measurements. A quantum processor may include one or more real-world, physical qubits. Generally, in a quantum device, a pair of superconducting Josephson junction qubits (e.g., transmon qubits) may be capacitively coupled to a length of coplanar waveguide.

[0051] The implementation of quantum gates in quantum devices can be complicated by coupling constraints on qubits relative to one another. Failure to comply with these constraints can affect the quality of qubit measurements and / or the state of one or more of the couplings or adjacent qubits due to the nature (e.g., hardware) used for coupling. Even when these constraints are complied with, additional gate operations can occur due to the coupling constraints that must be complied with.

[0052] These limitations may limit the modularity, placement, and / or distance between qubits and / or qubit chips containing them, respectively. This limited placement itself may limit the types of operations (e.g., quantum gates) that can be performed. Furthermore, the hardware used to couple qubits generally may, in one or more cases, introduce some error, such as some degree of decoherence and / or some degree of quantum noise, affecting the availability and / or coherence of the qubits. Quantum noise may refer to noise attributable to the discrete and / or probabilistic nature of quantum interactions. For example, in conventional superconducting processors of quantum devices, qubit connectivity is traditionally limited to nearest-neighbor qubits. Operations that utilize quantum information transfer beyond nearest neighbors result in the use of additional swap operations. These additional operations may introduce error and / or increase circuit depth. Circuit depth refers to the length (e.g., amount of gates) of the quantum circuit being implemented. A longer quantum circuit may consume a longer coherence time of one or more qubits, thereby reducing the availability of coherence for the longer quantum circuit and / or other quantum operations being performed.

[0053] Therefore, it may be desirable to reduce the limitations on qubit connectivity. Quantum volume may benefit from having higher connectivity, such as connectivity to more than just nearest neighbors and / or connectivity to multiple nearest neighbors. Quantum volume may refer to the number of gates that can be performed in a quantum operation, given qubit coherence and / or system noise. Alternatively and / or additionally, quantum volume may refer to the number of quantum circuits, such as repeated executions of a quantum circuit, that can be performed, given qubit coherence and / or system noise.

[0054] One or more embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout.

[0055] As used herein, the terms "entity," "requesting entity," and "user entity" may refer to a machine, device, component, hardware, software, smart device, and / or human being.

[0056] As used herein, "combiner," "combiner element," and "combining element" may be interchangeable.

[0057] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that, in various instances, one or more embodiments may be practiced without these specific details.

[0058] Additionally, the embodiments illustrated in one or more figures described herein are merely exemplary, and thus the architecture of the embodiments is not limited to the systems, devices, and / or components illustrated therein, or to any particular order, connection, and / or coupling of the systems, devices, and / or components illustrated therein. For example, in one or more embodiments, a non-limiting system described herein, such as non-limiting system 100 of FIG. 1, may further comprise, be associated with, and / or be coupled to, one or more computers and / or computing-based elements described herein with reference to an operating environment, such as operating environment 1300 shown in FIG. 13. In one or more described embodiments, the computers and / or computing-based elements can be used in connection with implementing one or more of the systems, devices, components, and / or computer-implemented operations illustrated and / or described in connection with FIG. 1 and / or other figures described herein.

[0059] Turning first generally to Figure 1, one or more embodiments described herein may include one or more electronic devices, systems, and / or apparatuses capable of providing a process for performing one or more quantum operations, such as executing one or more quantum gates. Figure 1 illustrates a block diagram of an exemplary, non-limiting system 100 capable of providing such a probing process according to one or more embodiments described herein. While reference is made herein to one or more processes, simplifications, and / or uses of non-limiting system 100, the descriptions provided herein, both above and below, may also relate to one or more other, non-limiting systems described herein, such as the devices / systems of Figures 2, 4, and / or 8-10, which are described in more detail below.

[0060] The following / above description refers to the operation of one quantum program from one quantum job request. This operation may include one or more readouts from the cryogenic environment electronics within the cryogenic chamber 116 by room temperature control / readout electronics 112 outside the cryogenic chamber 116. That is, one or more of the processes described herein may additionally and / or alternatively be scalable, such as including the execution of one or more quantum programs and / or quantum job requests in parallel with one another. Scalability of efficient readout may be enabled by utilizing multiple semiconductor devices 111.

[0061] In one or more embodiments, non-limiting system 100 can be a hybrid system, and thus can include both one or more classical systems, such as a quantum program-implemented system, and one or more quantum systems, such as quantum system 101. In one or more other embodiments, quantum system 101 can function separately from, but in combination with, a classical system.

[0062] In such instances, one or more communications between one or more components of non-limiting system 100 and the classical system may be facilitated by wired and / or wireless means, including, but not limited to, utilizing a cellular network, a wide area network (WAN) (e.g., the Internet), and / or a local area network (LAN). Suitable wired or wireless technologies for facilitating communications include, but are not limited to, Wireless Fidelity (Wi-Fi), Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX), Enhanced General Packet Radio Service (Enhanced GPRS), 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE), 3rd Generation Partnership Project 2 (3GPP2) Ultra Mobile Broadband (UMB), This may include High Speed ​​Packet Access (HSPA), Zigbee and other 802.XX wireless technologies or legacy telecommunications technologies or combinations thereof, BLUETOOTH®, Session Initiation Protocol (SIP), ZIGBEE®, RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 over Low Power Wireless Area Network), Z-Wave, Advanced and Adaptive Network Technology (ANT), Ultra-Wideband (UWB) standard protocols, other proprietary or combinations thereof, non-proprietary communication protocols or combinations thereof.

[0063] In one or more other embodiments, a classical system may provide quantum job requests 104, qubit mappings, quantum circuits to be executed, and / or the like. Such a classical system may analyze one or more quantum measurement readouts 120. Additionally, such a classical system may manage a queue of quantum circuits to be operated on one or more qubits of the quantum logic circuit of each quantum system 101.

[0064] For example, in one or more embodiments, a non-limiting system described herein, such as non-limiting system 100 shown in Figure 1, and / or the system may further comprise, be associated with, and / or be coupled to one or more computers and / or computing-based elements described herein with reference to an operating environment, such as operating environment 1300 shown in Figure 13. In one or more described embodiments, the computers and / or computing-based elements may be used in connection with implementing one or more of the systems, devices, components, and / or computer-implemented operations shown and / or described in connection with Figure 1 and / or other figures described herein.

[0065] A quantum system 101 (e.g., a quantum computer system, a superconducting quantum computer system, and / or the like) may utilize quantum algorithms and / or quantum circuits, including computing components and / or devices, for performing quantum operations and / or functions on input data to generate results that can be output to an entity. Quantum circuits may include quantum bits (qubits), e.g., multi-bit qubits, physical circuit-level components, higher-level components, and / or functions. Quantum circuits may include physical pulses that may be configured (e.g., arranged and / or designed) to perform desired quantum functions and / or computations on data (e.g., input data and / or intermediate data derived from the input data) to generate one or more quantum results as output. Quantum results, e.g., quantum measurements 120, may be responsive to a quantum job request 104 and associated input data and may be based, at least in part, on the input data, the quantum functions, and / or the quantum computations.

[0066] In one or more embodiments, quantum system 101 may include one or more quantum components, such as quantum manipulation component 103, quantum processor 106, quantum readout / control electronics 112, waveform generator 110, and / or quantum logic circuit 108 including one or more qubits (e.g., qubits 107A, 107B, and / or 107C), also referred to herein as qubit devices 107A, 107B, and 107C.

[0067] Quantum processor 106 may be any suitable processor. Quantum processor 106 may generate one or more instructions to control one or more processes in quantum logic circuit 108 and / or waveform generator 110.

[0068] Quantum operations component 103 may obtain (e.g., download, receive, retrieve, and / or the like) quantum job requests 104 requesting the execution of one or more quantum programs. Quantum operations component 103 may determine one or more quantum logic circuits, e.g., quantum logic circuit 108, for executing the quantum programs. Request 104 may be provided in any suitable format, e.g., text format, binary format, and / or another suitable format. In one or more embodiments, request 104 may be received by a component other than a component of quantum system 101, e.g., by a component of a classical system coupled to and / or in communication with quantum system 101.

[0069] Waveform generator 110 can perform one or more waveform operations to operate and / or affect one or more quantum circuits on one or more qubits 107A, 107B, and / or 107C. For example, waveform generator 110 can operate one or more qubit effectors, such as qubit oscillators, harmonic oscillators, pulse generators, and / or the like, to cause one or more pulses to simulate and / or manipulate the states of one or more qubits 107A, 107B, and / or 107C included in quantum system 101.

[0070] The waveform generator 110 can include one or more semiconductor devices 111 having respective closely inter-integrated resonant tunneling diodes (RTDs) and field effect transistors (FETs). This inter-integration can provide flow between the RTDs and FETs along their respective substrates or base surfaces (e.g., where the substrate would be removed if the substrate were removed).

[0071] Using semiconductor devices 111, such as semiconductor chips, the waveform generator 110 can generate qubit-controlled pulses using low power, such as less than 1 milliwatt per qubit (mW / qubit). In terms of quantity, the power utilized by such semiconductor devices can be more easily cooled (e.g., dissipated) by cooling systems such as those inside respective cryogenic chambers.

[0072] Waveform generator 110 may, for example, be combined with quantum processor 106 to perform quantum logic circuit operations on one or more qubits of the circuit (e.g., qubits 107A, 107B, and / or 107C). ​​In response, quantum operations component 103 may output the results of one or more quantum jobs, such as one or more quantum measurements 120 in response to quantum job request 104.

[0073] The quantum logic circuit 108, and some or all of the waveform generator 110 and / or quantum processor 106, may be housed in a cryogenic environment generated by a cryogenic chamber 116, such as a dilution refrigerator. Thus, the semiconductor device 111 may be utilized in a cryogenic environment. Indeed, signals may be generated by the waveform generator 110 to affect one or more qubits 107A-C. If the qubits 107A, 107B, and 107C are superconducting qubits, cryogenic temperatures, such as about 4 Kelvin (K) or less, may be utilized to facilitate functions of these physical qubits. Accordingly, the elements of the waveform generator 110, including the semiconductor device 111, would also be constructed to operate at such cryogenic temperatures.

[0074] 2-12, various embodiments of devices / systems are described herein that may be utilized, where applicable, as at least a portion of quantum processor 106 or quantum logic circuit 108. For example, each of Figures 2 and 4-10 illustrates, at least generally or in block diagram form, an electronic device that may be utilized as at least a portion of quantum processor 106 or quantum logic circuit 108 shown in Figure 1. However, the description of the aspects of Figures 2-12 may be valid in their own right apart from any suggested direct or other relationship to the aspect of Figure 1.

[0075] 2 shows a schematic diagram of a device 200 having a first qubit Q1 (202), a second qubit Q2 (204), and multiple couplers CP1 (206) and CP2 (208). The first and second qubits 202 / 204 are coupled to each other by multiple couplers 206 / 208, also referred to herein as coupling elements or coupler elements. The multiple couplers 206 / 208 are coupled to each other by junctions J (210). In the illustrated embodiment, junctions 210 comprise capacitors. In addition, capacitors are coupled between the first qubit 202 and the first coupler 206, and between the second qubit 204 and the second coupler 208.

[0076] Each of couplers 206 and 208 may be tunable, for example, a tunable superconducting quantum interference device (SQUID) or a direct current (DC) SQUID. Each may comprise a Josephson junction (JJ) 212. Each SQUID 206, 208 may be biased by a biasing element 214. As used herein, a "tunable" coupler may refer to any coupler whose frequency can be changed due to current flowing in a nearby biasing element.

[0077] In general, couplers 206 and 208 may be thought of as access devices that can be biased and excited to enable active coupling of the qubits to which the couplers are physically connected. That is, the coupler associated with each qubit (e.g., coupler 206 associated with qubit 202 and coupler 208 associated with qubit 204) may be activated by applying a bias, with an excitation of the superimposed difference frequency of each qubit being applied to the coupler between selected qubits. Alternatively, the excitation may be a difference frequency with additional positive / negative anharmonicity. As used herein, the difference frequency may be the absolute difference between the resonant frequencies of the qubits at rest (state 0).

[0078] The excitation can be sinusoidal / parametric, square, baseband, and / or other. The use of sinusoidal pulses can have advantages if the applied frequency can allow for differentiation between pairs of couplers, as will be explained further below. Activating each of the two respective couplers can allow for operation only between the qubits connected by the couplers, e.g., if excitation can be transferred between the qubits.

[0079] For example, an entanglement swapping gate, in which a qubit acquires a phase of I when the qubit states are swapped (iSWAP gate), can be implemented with qubits 202 and 204, with one of the qubits starting in an excited state, by applying a bias to each of couplers 206 and 208, and then operating an excitation, such as a parametric excitation, at the difference frequency. A simulation of this operation is shown in Figure 3, where plot 300 is for device 200 with qubit Q1 (202) at 5 gigahertz (GHz), qubit Q2 (204) at 5.4 GHz, a difference frequency of 0.4 GHz, coupler CP1 (206) operating at 15.22 GHz (zero flux bias), and coupler CP2 (208) operating at 15.22 GHz (zero flux bias).

[0080] Note that each of the two couplers operates at the same frequency. Also note that the Josephson junctions 212 of couplers 206 and 208 can be larger than those of conventionally utilized SQUID junctions.

[0081] Specifically, looking at plot 300, as shown, the excitation frequency is approximately 395 megahertz (MHz). Plot 300 shows the results of a simulation where qubit Q1 starts in an excited state and qubit Q2 starts in the |10> state. A flux bias and a sinusoidal excitation frequency of ∼395 MHz, the difference frequency of both qubits, are simultaneously applied to couplers attached to Q1 and Q2. A chevron pattern is observed where oscillations are observed between the |10> and |01> states as a function of flux pulse length and frequency.

[0082] The scale of plot 300 shows the overlap of the quantum state <\psi| of the two qubits with the state |01> of the two qubits over time (the order of the qubits in the tensor product is Q1 first and Q2 second). That is, <\psi| varies with time. The overlap is |<\psi|01>| 2 is given by

[0083] Moving away from plot 300 and instead looking at plot 350 in another example, a two-qubit gate, a controlled-Z (CZ gate), can be implemented using qubits 202 and 204, with both qubits starting in excited states, by applying a bias to each of couplers 206 and 208, and then operating an excitation, such as a parametric excitation, at a difference frequency, where the difference frequency applied to each is modified by anharmonicity. As used herein, anharmonicity is a property of the qubits and couplers. When a CZ gate is applied and both qubits 202 and 204 are in excited states, a parametric excitation of a different frequency, + / - the anharmonicity of qubits 202 and 204, is applied to couplers 206 and 208, thereby activating couplers 206 and 208 for CZ gate implementation. The anharmonicity of couplers 206 and 208 is not considered in this activation.

[0084] A simulation of this operation is shown in Figure 3, where plot 350 is for device 200 with a qubit Q1 / Q2 anharmonic of -0.6648 GHz applied to each of the two couplers 206 and 208, with the same values ​​as above. As shown in plot 350, the excitation frequency is approximately 738 MHz. Plot 350 shows similar results to those of plot 300, with both qubits Q1 and Q2 starting from excited states. Oscillations are observed between the |11> and |20> states.

[0085] The scale of plot 350 shows the overlap of the quantum state <\psi| of the two qubits with respect to time and the state |20> of the two qubits (the order of the qubits in the tensor product is Q1 first and Q2 second). That is, <\psi| varies with time. The overlap is |<\psi|20>| 2 is given by

[0086] For the simulations that resulted in the graph of FIG. 3, a Hamiltonian simulation was used in which the qubits and couplers were treated as Duffing oscillators using Equation 1.

[0087] Formula 1:

number

[0088] Equation 2 represents the coupling of qubits to couplers and the coupling between couplers.

[0089] Formula 2:

number

[0090] Equation 3 represents the direct coupling terms of only the nearest neighbor circuit elements.

[0091] Formula 3:

number

[0092] 4, another electronic device 400 is shown in accordance with embodiments described herein. Electronic device 400 is similar to electronic device 200, but utilizes three qubits Q1, Q2, and Q3 along with a node-type junction 402 and three separate couplers. Capacitors are utilized between each qubit-coupler pair and between each coupler and node junction 402. With electronic device 400, each qubit Q1, Q2, and Q3 is individually and separately coupled to junction 402 by a respective separate coupler. In other words, junction 402 provides the only coupling between the qubits, where the qubits are not otherwise coupled to each other except by junction 402. That is, every coupler is coupled to every other coupler by junction 402.

[0093] 5-7, plots of a simulation of an iSWAP gate implementation utilizing electronic device 400 of FIG. 4 are shown, in accordance with one or more embodiments described herein. In each of FIGS. 5-7, Q1 has a resonant frequency of 5 GHz, Q2 has a resonant frequency of 5.3 GHz, and Q3 has a resonant frequency of 5.7 GHz. Qubits Q1, Q2, and Q3 are capacitively coupled to one another by node 402.

[0094] The bias information at the top of Figures 5-7 is a DC offset (e.g., 214) applied to the combiner while the parametric excitation is applied (e.g., a square pulse interleaved with a sinusoidal pulse generally referenced as 214). Notably, the bias 214 is non-zero.

[0095] Turning first to FIG. 5, a set of three graphs is shown illustrating a simulation of an iSWAP gate implementation utilizing qubits Q1 and Q2 of electronic device 400 of FIG. 4. A set of three plots, 500, 550, and 580, show the excitation frequency and pulse duration of each qubit separately. The right side of each plot 500, 550, and 580 shows the population in each qubit as a function of parametric excitation frequency and pulse duration. In FIG. 5, the population is transferred between Q1 and Q2, which corresponds to the difference frequency of both qubits.

[0096] Turning now to Figure 6, a set of three graphs is shown illustrating a simulation of an iSWAP gate implementation utilizing qubits Q2 and Q3 of electronic device 400 of Figure 4. A set of three plots, 600, 650, and 680, show the excitation frequency and pulse duration of each qubit separately. The right side of each plot 600, 650, and 680 shows the population in each qubit as a function of parametric excitation frequency and pulse duration. In Figure 6, the population is transferred between Q2 and Q3, which corresponds to the difference frequency of both qubits.

[0097] Turning now to Figure 7, a set of three graphs is shown illustrating a simulation of an iSWAP gate implementation utilizing qubits Q1 and Q3 of electronic device 400 of Figure 4. A set of three plots, 700, 750, and 780, show the excitation frequency and pulse duration of each qubit separately. The right side of each plot, 700, 750, and 780, shows the population in each qubit as a function of parametric excitation frequency and pulse duration. In Figure 7, the population is transferred between Q1 and Q3, which corresponds to the difference frequency of both qubits.

[0098] With respect to Figures 5-7, it is noted that inductive coupling of qubits, rather than the simulated capacitive coupling, will show the same results as shown because the qubits function with the same underlying Hamiltonian (the underlying physical description). Although the implementation in terms of circuits will be different, the physics will likely be the same, and so Figures 5-7 also represent simulations of inductive coupling.

[0099] 8, another electronic device 800 is shown in accordance with one or more embodiments described herein. Electronic device 800 is similar to electronic device 400, but includes four qubits instead of the three qubits of electronic device 400. Q1 has a resonant frequency of 5 GHz, Q2 has a resonant frequency of 5.3 GHz, Q3 has a resonant frequency of 5.7 GHz, and Q4 has a resonant frequency of 5.8 GHz. All four qubits are individually coupled to respective couplers (not shown) and are ultimately coupled only to each other by junctions 802. That is, every coupler is coupled to every other coupler by junctions 802.

[0100] By using parametric excitation applied at a difference frequency between selected pairs of qubits, parallel, highly connected operations can be utilized simultaneously using device 800. For example, a parametric gate can be operated using two of the qubits, and a second parametric gate can be operated using the other two of the qubits. With parametric / sinusoidal pulses, the applied frequency can allow for differentiation between pairs of qubits, allowing operations to be performed in parallel.

[0101] Turning now to Figures 9 and 10, inductive coupling of qubits is illustrated, as compared to the capacitive coupling in Figures 2-4. Inductive coupling is similar to capacitive coupling and also utilizes junction coupling, with couplers individually coupled to each qubit. Note that in Figures 9 and 10, the inductive coupling can be galvanic or non-galvanic.

[0102] 9, another electronic device 900 is shown in accordance with one or more embodiments described herein. Device 900 includes a first qubit 902, a tunable first coupler 906, a second qubit 904, and a tunable second coupler 908. A junction 910 may be included in electronic device 900 by a portion of each of couplers 906 and 908. In other words, a biasing element 912 between couplers 906 and 908 may be considered a junction 910. Each coupler 906, 908 may include a radio frequency (RF) SQUID, such as one having a resonant frequency of 14 GHz to 15 GHz.

[0103] An iSWAP gate can be implemented using qubits 902 and 904, with one of the qubits starting in an excited state, by applying a bias to each of couplers 906 and 908, and then operating an excitation, such as a parametric excitation, at the difference frequency.

[0104] In another example, a CZ gate can be implemented using qubits 902 and 904, with both qubits starting in excited states, by applying a bias to each of couplers 906 and 908, and then manipulating an excitation, such as a parametric excitation, at the difference frequency to + / - the anharmonicity of the qubits.

[0105] 10, another electronic device 1000 is shown in accordance with one or more embodiments described herein. Electronic device 1000 comprises a plurality of qubits, including qubits 1002 and 1004, and a plurality of couplers, including couplers 1006 and 1008. Each qubit is individually inductively coupled to a separate respective coupler. Each coupler is inductively coupled to every other coupler by junction 1010. Junction 1010 comprises a loop including a plurality of series-connected inductors 1012, one inductor 1012 per coupler. That is, there are individual inductor 1012 / coupler pairs.

[0106] An iSWAP gate can be implemented using pairs of qubits, such as qubits 1002 and 1004, where one of the qubits starts in an excited state, by applying a bias to each of couplers 1006 and 1008, and then operating an excitation, such as a parametric excitation, at the difference frequency.

[0107] The inductors 1012 can be differentiated by selecting the qubits that are desired to be coupled together to perform the overall operation. In one or more embodiments, the loop junction 1010 may not be fully activated. Rather, only two qubits at a time are activated in each portion of the loop junction 1010. The differentiation is done by selecting the qubits, applying separate qubit biases to those qubits, and applying a signal with the appropriate frequency difference between the two qubits.

[0108] In another example, a CZ gate can be implemented using multiple qubit pairs, such as qubits 1002 and 1004, where both qubits start in excited states, by applying a bias to each of couplers 1006 and 1008, and then manipulating an excitation, such as a parametric excitation, at the difference frequency to + / - the anharmonicity of the qubits.

[0109] 2 , in one or more embodiments, entity 280 may perform one or more operations to manufacture an electronic device and / or system according to one or more embodiments described herein. For example, entity 280, such as a manufacturing system, may include a controller and / or processor 282. Processor 282 may issue one or more instructions to cause the manufacturing of the electronic device and / or system. For example, entity 280 may further include one or more nodes 284, such as manufacturing devices, that may be controlled by controller 282 to manufacture the electronic device and / or system. In one example, node 284 may be controlled to couple coupler elements to qubit chips, and / or the like.

[0110] In one or more embodiments, entity 280 and / or another manufacturing entity may perform one or more operations (e.g., manufacturing operations) corresponding to one or more electronic devices and / or systems described herein.

[0111] 11 illustrates a flow diagram of an exemplary, non-limiting method 1100 that can provide a process for at least partially constructing an electronic device, such as the non-limiting devices of FIGS. 1, 2, 4, and / or 8-10, in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements and / or processes used in each embodiment are omitted for the sake of brevity.

[0112] At 1102, non-limiting method 1100 can include coupling together a first qubit and a tunable first coupler (eg, by entity 280).

[0113] At 1104, non-limiting method 1100 can include coupling (eg, by entity 280) the second qubit and the tunable second coupler to one another.

[0114] At 1106, non-limiting method 1100 can include coupling (eg, by entity 280) the first coupler and the second coupler to one another by a junction.

[0115] At 1108, non-limiting method 1100 may include utilizing a central hub or node (e.g., by entity 280) for the junction that is separately coupled to the first coupler and the second coupler.

[0116] At 1110, non-limiting method 1100 can include utilizing a loop of series coupled inductors for the junction (eg, by entity 280).

[0117] At 1112, non-limiting method 1100 can include providing a unique coupling between the first qubit and the second qubit via a junction (e.g., junctions 210, 402, 802, 912, and / or 1010).

[0118] At 1114, non-limiting method 1100 may include capacitively coupling (eg, by entity 280) the first qubit and the second qubit with a first coupler and a second coupler.

[0119] At 1116, non-limiting method 1100 may include inductively coupling (eg, by entity 280) the first qubit and the second qubit with the first coupler and the second coupler.

[0120] At 1118, non-limiting method 1100 can include coupling the third quantum bit and the tunable third coupler to one another (e.g., by entity 280) and coupling the tunable third coupler to the junction (e.g., by entity 280).

[0121] At 1120, non-limiting method 1100 may further include coupling a pulse generating component to the electronic device (eg, by entity 280) that generates pulses that affect one or more qubits.

[0122] 12 illustrates a flow diagram of an exemplary, non-limiting method 1200 that can provide, at least in part, a process for using an electronic device, such as the non-limiting devices of FIGS. 1, 2, 4, and / or 8-10, in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements and / or processes used in each embodiment are omitted for the sake of brevity.

[0123] At 1202, non-limiting method 1200 can include applying, by a system operably coupled to a processor (e.g., by quantum manipulation component 103), a first bias and a first parametric excitation to a first coupler coupled to a first quantum bit.

[0124] At 1204, non-limiting method 1200 can include applying, by the system (e.g., by quantum manipulation component 103), a second bias and a second parametric excitation to a second coupler coupled to the second quantum bit and to the first coupler.

[0125] At 1206, non-limiting method 1200 can include performing, by the system (eg, by quantum operation component 103), a parametric gate operation utilizing the first qubit and the second qubit.

[0126] At 1208, non-limiting method 1200 can include applying, by the system (e.g., by quantum manipulation component 103), a first parametric excitation and a second parametric excitation at respective frequencies that are a difference between the respective frequencies of the first quantum bit and the second quantum bit.

[0127] At 1210, non-limiting method 1200 can include applying, by the system (e.g., by quantum manipulation component 103), a first parametric excitation and a second parametric excitation when the first qubit is in a respective excited state and the second qubit is in a respective excited state.

[0128] At 1212, non-limiting method 1200 can include applying, by the system (e.g., by quantum manipulation component 103), a first parametric excitation and a second parametric excitation at respective frequencies that are the difference between the respective frequencies of the first qubit and the second qubit, plus or minus anharmonicity of the first and second qubits.

[0129] At 1214, non-limiting method 1200 can include applying, by the system (e.g., by quantum manipulation component 103), a first parametric excitation and a second parametric excitation when one of the first qubit or the second qubit is in a respective excited state and the other of the first qubit or the second qubit is in a respective ground state.

[0130] At 1216, the non-limiting method 1200 can include inductively coupling the first coupler and the second coupler by the system (e.g., by the quantum manipulation component 103) using a pair of radio frequency superconducting quantum interference devices in the first coupler and the second coupler.

[0131] At 1218, the non-limiting method 1200 can include capacitively coupling, by the system (eg, by quantum manipulation component 103), the first coupler and the second coupler by a single coupling node.

[0132] At 1220, non-limiting method 1200 can include applying, by the system (e.g., by quantum operation component 103), a third bias and a third parametric excitation to a third coupler coupled to the third qubit; applying, by the system (e.g., by quantum operation component 103), a fourth bias and a fourth parametric excitation to a fourth coupler coupled to the fourth qubit; and performing, by the system (e.g., by quantum operation component 103), a second parametric gate operation utilizing the third qubit and the fourth qubit in parallel with the parametric gate operation, wherein the first coupler, the second coupler, the third coupler, and the fourth coupler are coupled to each other by a single junction.

[0133] For simplicity of explanation, the computer-implemented and non-computer-implemented methods provided herein are depicted and / or described as a series of actions. It should be understood that the subject innovation is not limited by the depicted acts and / or the order of acts. For example, acts may occur in one or more orders, and / or simultaneously, and with other acts not shown and described herein. Furthermore, not all depicted acts may be utilized to implement computer-implemented and non-computer-implemented methods in accordance with the described subject matter. In addition, computer-implemented and non-computer-implemented methods may alternatively be represented as a series of interrelated states via state diagrams or events. Additionally, the computer-implemented methods described below and throughout this specification may be stored on an article of manufacture for transferring and transporting the computer-implemented methods to a computer. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0134] Systems, devices, or combinations thereof are described (or further described, or combinations thereof) herein with respect to interactions between one or more components. Such systems and / or components may include these components or subcomponents designated therein, one or more of the designated components and / or subcomponents, and / or additional components. Subcomponents may be implemented as components communicatively coupled to other components rather than being included in a parent component. One or more components, subcomponents, or combinations thereof may be combined into a single component that provides aggregate functionality. Components may interact with one or more other components not specifically described herein for brevity, but known to those skilled in the art.

[0135] In summary, one or more systems, devices, and / or methods of manufacture and / or use provided herein relate to quantum computing processes for achieving higher connectivity of qubits to more than nearest neighbors and / or to multiple nearest neighbors. The system may include a tunable first coupler coupled to a first qubit, a tunable second coupler coupled to a second qubit, and a parametrically excitable junction coupling the first and second couplers. Each of the first and second couplers may comprise a superconducting quantum interference device or a Josephson junction. The junction may include a central hub or node separately coupled to each of the first and second couplers. The first and second couplers may be configured to capacitively or inductively couple the first and second qubits to one another to perform a controlled-Z (CZ) gate or an iSWAP gate.

[0136] An advantage of one or more of the electronic devices, systems, and / or methods set forth above may be a larger quantum volume and improved implementation and / or demonstration of quantum algorithms, which may result from fewer gates, fewer swaps, and / or fewer errors (or reduced error introduction).

[0137] Yet another advantage of one or more embodiments described herein may be that multiple electronic devices and / or systems may be used in combination with one another to reduce thermal population of loading.

[0138] Yet another advantage of one or more embodiments described herein may be to utilize the same electronic device and / or system, such as one having four or more qubits, to perform multiple highly connected operations, such as at least partially simultaneously with one another. Indeed, such an electronic device may utilize a single junction separately coupled to each of the four qubits.

[0139] In view of one or more embodiments described herein, a practical application of the systems, computer-implemented methods, and / or computer program products described herein can be greater quantum volume throughput of quantum systems utilizing the electronic devices described herein. Such is a useful and practical application of computers to provide for the operation of extended (e.g., improved and / or optimized) quantum circuits, such as those in which the electronic devices are configured with quantum logic circuits having multiple qubits, such as about 27 qubits, or 1000 qubits, or more. Generally, such computerized tools can constitute concrete and tangible technological improvements in the field of quantum computing.

[0140] Furthermore, one or more embodiments described herein can be utilized in real-world systems based on the disclosed teachings. For example, one or more embodiments described herein can function within a quantum system that can receive a pulse as an input to affect one or more qubits in one or more of the electronic devices and / or systems described herein.

[0141] Additionally, the electronic devices and / or methods described herein can be implemented in one or more domains, such as the quantum domain, to enable scaled quantum program execution. Indeed, the use of electronic devices described herein may be scalable, such that elements of embodiments described herein may be used in large numbers in the same overall quantum logic circuit or quantum processor of a quantum system. Coupling / quantum operations of one or more qubits, e.g., parametric operations, can be performed simultaneously with one another using the same electronic devices described herein.

[0142] One or more systems and / or electronic devices have been described (and / or will be further described) herein with respect to interactions between one or more components. Such systems and / or components may include these components or subcomponents designated therein, one or more of the designated components and / or subcomponents, and / or additional components. Subcomponents may be implemented as components communicatively coupled to other components rather than being included in a parent component. One or more components, subcomponents, or combinations thereof may be combined into a single component that provides aggregate functionality. Components may interact with one or more other components not specifically described herein for brevity but known to those skilled in the art.

[0143] One or more embodiments described herein are, in one or more embodiments, inherently and / or inseparably linked to computer technology and cannot be implemented outside of a computing environment. The systems, computer-implemented methods, and / or computer program products described herein are highly useful in the fields of quantum computing and superconducting quantum systems and cannot sensibly and equally feasibly be implemented outside of a computing environment.

[0144] One or more embodiments described herein may utilize hardware and / or software to solve problems that are highly technical, non-abstract, and cannot be performed as a set of mental actions by a human. For example, a human, or even thousands of humans, cannot efficiently, accurately, and / or effectively combine qubits and / or perform quantum gates in the manner of one or more embodiments described herein. Furthermore, a human mind, or a person with pen and paper, cannot perform one or more of these processes in the same way as one or more embodiments described herein.

[0145] In one or more embodiments, one or more of the processes described herein may be executed by one or more specialized computers (e.g., specialized processing units, specialized classical computers, specialized quantum computers, specialized hybrid classical / quantum systems, another type of specialized computer, or a combination thereof) to perform defined tasks for one or more of the techniques described above. One or more embodiments described herein, components thereof, or combinations thereof may be utilized to solve new problems that arise through the use of advances in the technologies mentioned above, quantum computing systems, cloud computing systems, computer architectures, or another technology, or a combination thereof.

[0146] One or more embodiments described herein may be fully operational (e.g., fully powered on, fully running, and / or another function) to perform one or more other functions, while also performing one or more of the one or more operations described herein.

[0147] 13-15, detailed descriptions are provided to provide additional context for one or more embodiments described herein in FIGS. 1-12.

[0148] Figure 13 and the following discussion are intended to provide a brief, general description of a suitable operating environment 1300 in which one or more embodiments described herein in Figures 1-12 may be implemented. For example, one or more components and / or other aspects of the embodiments described herein may be implemented in, accessible through, or otherwise associated with operating environment 1300. Additionally, while one or more embodiments are described above in the general context of computer-executable instructions that may be executed on one or more computers, those skilled in the art will recognize that one or more embodiments may also be implemented as or in combination with other program modules, as a combination of hardware and software, or a combination thereof.

[0149] Generally, program modules include routines, programs, components, data structures, or the like, or combinations thereof, that perform particular tasks, implement particular abstract data types, or combinations thereof. Additionally, the methods described above can be practiced with other computer system configurations, including single-processor or multi-processor computer systems, minicomputers, mainframe computers, Internet of Things (IoT) devices, distributed computing systems, and personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, and / or the like, each of which can be operatively coupled to one or more associated devices.

[0150] Computing devices typically include a variety of media, which may include computer-readable storage media, machine-readable storage media, communication media, or a combination thereof. The two terms are used interchangeably herein as follows: A computer-readable storage medium or machine-readable storage medium may be any available storage medium that can be accessed by a computer, and includes both volatile and nonvolatile media, removable and non-removable media. By way of example, and not limitation, a computer-readable storage medium, machine-readable storage medium, or a combination thereof may be implemented in connection with any method or technology for storage of information, such as computer-readable, machine-readable, or a combination thereof, instructions, program modules, structured data, unstructured data, or a combination thereof.

[0151] A computer-readable storage medium may include, but is not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), Blu-ray disc (BD) and / or other optical disc storage, magnetic cassettes, magnetic tape, magnetic disc storage and / or other magnetic storage devices, solid-state drives or other solid-state storage devices, and / or other tangible and / or non-transitory media that may be used to store specified information. In this regard, the terms "tangible" or "non-transitory" herein as applied to storage, memory, and / or computer-readable medium are understood as modifiers to exclude merely transmitting transitory signals per se, and do not waive any right to all standard storage, memory, and / or computer-readable media that are not merely transmitting transitory signals per se.

[0152] The computer-readable storage medium may be accessed by one or more local or remote computing devices, for example, via access requests, queries, other data retrieval protocols, or combinations thereof, for various operations on the information stored by the medium.

[0153] Communication media typically embodies computer-readable instructions, data structures, program modules, or other structured or unstructured data in a modulated data signal, such as a carrier wave or other transport mechanism, and includes any information delivery or transport medium. The term "modulated data signal" or signal refers to a signal that has one or more of its characteristics set and / or changed in such a manner as to encode information in the signal or signals. By way of example, and not limitation, communication media may include wired media, such as a wired network, a direct-wired connection, wireless media (such as acoustic, RF, infrared, other wireless media, or combinations thereof), or combinations thereof.

[0154] 13, an exemplary operating environment 1300 for implementing one or more embodiments of the aspects described herein can include a computer 1302 including a processing unit 1306, a system memory 1304, and / or a system bus 1308. One or more aspects of the processing unit 1306 can be applied to the processors associated with the devices of FIGS. 1, 2, 4, and / or 8-10.

[0155] Memory 1304 may store one or more computer- and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processing unit 1306 (e.g., a classical processor, a quantum processor, and the like, or a combination thereof), can provide for the performance of operations defined by the executable components and / or instructions. For example, memory 1304 can store computer- and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processing unit 1306, can provide for the performance of one or more functions described herein with respect to the devices of Figures 1, 2, 4, and / or 8-10, as described herein with or without reference to one or more figures of one or more embodiments.

[0156] The memory 1304 may include volatile memory (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), and / or the like), and / or non-volatile memory (e.g., read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and / or the like), which may utilize one or more memory architectures.

[0157] Processing unit 1306 may include one or more types of processors and / or electronic circuits (e.g., classical processors, quantum processors, and / or the like) that may implement one or more computer- and / or machine-readable, writable, and / or executable components and / or instructions, which may be stored in memory 1304. For example, processing unit 1306 may perform one or more operations that may be specified by computer-readable, machine-readable, or any combination thereof, writable, executable, or any combination thereof, components, instructions, or any combination thereof, including, but not limited to, logic, control, input / output (I / O), arithmetic, the like, or any combination thereof. In one or more embodiments, processing unit 1306 may be any one or more commercially available processors. In one or more embodiments, processing unit 1306 may include one or more central processing units, multi-core processors, microprocessors, dual microprocessors, microcontrollers, systems-on-chips (SOCs), array processors, vector processors, quantum processors, another type of processor, or a combination thereof. An example of a processing unit 1306 may be utilized to implement one or more embodiments described herein.

[0158] The system bus 1308 may couple system components, including but not limited to the system memory 1304, to the processing unit 1306. The system bus 1308 may include one or more types of bus structures that may further interconnect a memory bus, a peripheral bus, a local bus, or combinations thereof (with or without a memory controller) using one or more of a variety of commercially available bus architectures. The system memory 1304 may include a ROM 1310, a RAM 1312, or a combination thereof. The basic input / output system (BIOS) may be stored in non-volatile memory such as a ROM, an erasable programmable read-only memory (EPROM), an EEPROM, or a combination thereof. The BIOS contains the basic routines that help transfer information between elements within the computer 1302, such as during start-up. The RAM 1312 may include a high-speed RAM, such as static RAM for caching data.

[0159] The computer 1302 may include an internal hard disk drive (HDD) 1314 (e.g., EIDE, SATA), one or more external storage devices 1316 (e.g., a magnetic floppy disk drive (FDD), memory stick, or flash drive reader, memory card reader, the like, or a combination thereof), a drive 1320 (e.g., a solid-state drive or optical disk drive, etc.) that can read from or write to a disk 1322, such as a CD-ROM disk, DVD, BD, the like, or a combination thereof. Additionally and / or alternatively, if a solid-state drive is involved, the disk 1322 may not be included unless separate. While the internal HDD 1314 is shown as located within the computer 1302, the internal HDD 1314 may also be configured for external use in a suitable chassis (not shown). Additionally, although not shown in the operating environment 1300, a solid-state drive (SSD) may be used in addition to or in place of the HDD 1314. HDD 1314, external storage device 1316, and drive 1320 may be connected to system bus 1308 by HDD interface 1324, external storage interface 1326, and drive interface 1328, respectively. HDD interface 1324 for external drive implementations may include Universal Serial Bus (USB) and / or Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technologies. Other external drive connection technologies are within the contemplation of the embodiments described herein.

[0160] The drives and their associated computer-readable storage media provide non-volatile storage of data, data structures, computer-executable instructions, etc. For computer 1302, the drives and storage media correspond to the storage of any data in a suitable digital format. Although the above description of computer-readable storage media refers to each type of storage device, other types of computer-readable storage media, now existing or developed in the future, may be used in the exemplary operating environment, and / or any such storage media may include computer-executable instructions for performing the methods described herein.

[0161] A number of program modules may be stored in the drives and RAM 1312, including an operating system 1330, one or more applications 1332, other program modules 1334, program data 1336, or a combination thereof. All or portions of the operating system, applications, modules, data, or a combination thereof may also be cached in RAM 1312. The systems, methods, or combinations thereof described herein may be implemented using one or more commercially available operating systems, combinations of operating systems, or combinations thereof.

[0162] Computer 1302 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary may emulate a hardware environment for operating system 1330, and the emulated hardware may optionally differ from the hardware shown in FIG. 13. In a related embodiment, operating system 1330 may include one virtual machine (VM) of multiple VMs hosted on computer 1302. Additionally, operating system 1330 may provide a runtime environment, such as the JAVA runtime environment or the .NET framework, for application 1332. A runtime environment is a consistent execution environment that may allow application 1332 to run on any operating system that includes the runtime environment. Similarly, operating system 1330 may support containers, and application 1332 may be in the form of a container. A container is a lightweight, standalone, executable package of software that includes, for example, code, runtime, system tools, system libraries, configuration for an application, or a combination thereof.

[0163] Additionally, computer 1302 may be enabled with a security module, such as a Trusted Processing Module (TPM). For example, a TPM allows a boot component to hash the next boot component in time and wait for the resulting match against a secure value before loading the next boot component. This process may occur at any layer of computer 1302's code execution stack, for example, applied at the application execution level, the operating system (OS) kernel level, or a combination thereof, thereby enabling security at any level of code execution.

[0164] An entity may enter, send, or perform commands, information, or a combination thereof into computer 1302 through one or more wired / wireless input devices, such as a keyboard 1338, a touchscreen 1340, a pointing device such as a mouse 1342, or a combination thereof. Other input devices (not shown) may include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control, other remote control, or a combination thereof, a joystick, a virtual reality controller, a virtual reality headset, or a combination thereof, a gamepad, a stylus pen, an image input device such as a camera, a gesture sensor input device, a visual motion sensor input device, an emotion or facial expression detection device, a biometric input device such as a fingerprint scanner, an iris scanner, or a combination thereof, the like, or a combination thereof. These and other input devices may be connected to the processing unit 1306 through an input device interface 1344, which may be coupled to the system bus 1308, but may also be connected to other interfaces, such as a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR interface, a BLUETOOTH interface, and the like, or combinations thereof.

[0165] Alternatively, additionally, or in combination, a monitor 1346 or other type of display device may be connected to the system bus 1308 via an interface, such as a video adapter 1348. In addition to the monitor 1346, computers typically include other peripheral output devices (not shown), such as speakers, printers, and the like, or a combination thereof.

[0166] Computer 1302 may operate in a networked environment using logical connections via wired and / or wireless communications to one or more remote computers, such as remote computer 1350. Remote computer 1350 may be a workstation, server computer, router, personal computer, portable computer, microprocessor-based entertainment equipment, peer device, other common network node, or combination thereof, and typically includes many or all of the elements described with respect to computer 1302, although for purposes of simplicity, only memory / storage device 1352 is shown. Additionally and / or alternatively, computer 1302 may be communicatively coupled (e.g., communicatively, electrically, operatively, optically, and / or similarly) to one or more external systems, sources, and / or devices (e.g., classical and / or quantum computing devices, communications devices, and / or similar devices) via data cables (e.g., High-Definition Multimedia Interface (HDMI), Recommended Standard (RS) 232, Ethernet cables, and / or the like).

[0167] In one or more embodiments, the network may include one or more wired networks, wireless networks, or combinations thereof, including, but not limited to, a cellular network, a wide area network (WAN) (e.g., the Internet), or a local area network (LAN). For example, one or more embodiments described herein may be configured to communicate with, but not be limited to, wireless networks such as Wireless Fidelity (Wi-Fi), Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX), Enhanced General Packet Radio Service (Enhanced GPRS), 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE), 3rd Generation Partnership Project 2 (3GPP2) Ultra Mobile Broadband (UMB), High Speed ​​Packet Access (HSPA), ZigBee, and others. It may communicate with one or more external systems, sources, and / or devices, such as computing devices (and vice versa), using virtually any specified wired or wireless technology, including bee and other 802.XX wireless technologies and / or legacy telecommunications technologies, BLUETOOTH®, Session Initiation Protocol (SIP), ZIGBEE®, RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 over Low Power Wireless Area Network), Z-Wave, ANT, Ultra-Wideband (UWB) standard protocols, and / or other proprietary and / or non-proprietary communication protocols.In a related example, one or more embodiments described herein may include hardware (e.g., a central processing unit (CPU), a transceiver, a decoder, quantum hardware, a quantum processor, and / or the like), software (e.g., a set of threads, a set of processes, running software, a quantum pulse schedule, a quantum circuit, a quantum gate, and / or the like), and / or a combination of hardware and / or software that supports communication of information between one or more embodiments described herein and external systems, sources, and / or devices (e.g., computing devices, communication devices, and / or the like).

[0168] The logical connections depicted include wired / wireless connectivity to a local area network (LAN) 1354 and / or larger networks, such as a wide area network (WAN) 1356. LAN and WAN networking environments may be commonplace in offices and companies and may facilitate enterprise-wide computer networks, such as intranets, all of which may be connected to a general communications network, e.g., the Internet.

[0169] When used in a LAN networking environment, the computer 1302 may be connected to the local network 1354 through a wired and / or wireless communication network interface or adapter 1358. The adapter 1358 may facilitate wired, wireless, or a combination thereof communication to the LAN 1354. The LAN 1354 may also include a wireless access point (AP) disposed thereon for communicating with the adapter 1358 in a wireless mode.

[0170] When used in a WAN networking environment, the computer 1302 may include a modem 1360 and may be connected by means such as the Internet to a communications server on the WAN 1356, or by other means for establishing communications over the WAN 1356, or a combination thereof. The modem 1360, which may be internal, external, or a combination thereof, and wired, wireless, or a combination thereof, may be connected to the system bus 1308 via the input device interface 1344. In a networked environment, program modules depicted relative to the computer 1302, or portions thereof, may be stored in the remote memory storage device 1352. The network connections shown are merely exemplary, and one or more other means of establishing a communications link between computers may be used.

[0171] When used in either a LAN or WAN networking environment, computer 1302 may access a cloud storage system or other network-based storage system in addition to, instead of, or in combination with external storage device 1316 described above, such as, but not limited to, a networked virtual machine that provides one or more aspects of information storage, processing, or a combination thereof. Generally, a connection between computer 1302 and a cloud storage system may be established over LAN 1354 or WAN 1356, for example, by adapter 1358 or modem 1360, respectively. Upon connecting computer 1302 to an associated cloud storage system, external storage interface 1326 may manage the storage provided by the cloud storage system like other types of external storage, such as with the aid of adapter 1358, modem 1360, or a combination thereof. For example, external storage interface 1326 may be configured to provide access to cloud storage sources as if the sources were physically connected to computer 1302.

[0172] The computer 1302 may be operable to communicate with any wireless device, entity, or combination thereof operably arranged in wireless communication, such as a printer, scanner, desktop, portable computer, or combination thereof, portable data assistant, communications satellite, telephone, any equipment or location associated with a radio-detectable tag (e.g., a kiosk, newsstand, store shelf, the like, or combination thereof), or combination thereof. This may include Wireless Fidelity (Wi-Fi) and BLUETOOTH® wireless technologies. As such, communication may be in a predefined structure similar to a traditional network, or may simply be ad-hoc communication between at least two devices.

[0173] The example embodiments described herein may be utilized in conjunction with distributed computing environments (e.g., cloud computing environments) where certain tasks are performed by remote processing devices that are linked through a communications network, such as those described below with respect to Figure 15. In a distributed computing environment, program modules may be located in both local and remote memory storage devices or a combination thereof.

[0174] For example, one or more embodiments described herein, and / or one or more components thereof, may utilize one or more computing resources of a cloud computing environment 1450 described below with reference to diagram 1400 of FIG. 14 and / or one or more functional abstraction layers (e.g., quantum software and / or the like) described below with reference to FIG. 15 to perform one or more operations according to one or more embodiments described herein. For example, one or more of the cloud computing environment 1450, the functional abstraction layers 1560, 1570, 1580, 1590, or combinations thereof, may include one or more classical computing devices (e.g., classical computers, classical processors, virtual machines, servers, the like, or combinations thereof), quantum hardware, quantum software (e.g., quantum computing devices, quantum computers, quantum processors, quantum circuit simulation software, superconducting circuits, the like, or combinations thereof), or combinations thereof, that may be utilized by one or more embodiments described herein, components thereof, or combinations thereof, to perform one or more operations according to one or more embodiments described herein. For example, one or more embodiments, components thereof, or combinations thereof described herein may utilize one or more such classical computing resources, quantum computing resources, or combinations thereof to perform one or more classical mathematical functions, quantum mathematical functions, or combinations thereof, calculations, equations, or combinations thereof, computing, processing scripts, or combinations thereof, algorithms, models (e.g., artificial intelligence (AI) models, machine learning (ML) models, similar models, or combinations thereof), other operations according to one or more embodiments described herein, or combinations thereof.

[0175] Although one or more embodiments described herein include detailed descriptions of cloud computing, it should be understood that implementation of the teachings referred to herein is not limited to cloud computing environments. Rather, one or more embodiments described herein can be implemented in conjunction with any other type of computing environment now known or developed in the future.

[0176] Cloud computing is a service delivery model that enables convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and / or services) that can be rapidly provisioned and released with minimal management effort or interaction with the service provider. The cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0177] The characteristics are as follows:

[0178] On-Demand Self-Service: Cloud consumers can unilaterally provision computing capacity, such as server time and network storage, automatically as needed, without requiring human interaction with the service provider.

[0179] Wide network access: Capabilities are available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., cell phones, laptops, and PDAs).

[0180] Resource Pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with various physical and virtual resources dynamically allocated and reallocated according to demand. Although consumers generally have no control or knowledge of the exact location of the resources provided, there is an implication of location independence in that they may be able to specify location at a higher level of abstraction (e.g., country, state, or data center, or a combination thereof).

[0181] Rapid Elasticity: Capacity can be rapidly and elastically provisioned, in one or more cases automatically, for rapid scale out and rapidly released for rapid scale in. To the consumer, the capacity available for provisioning can appear unlimited and can be purchased in any amount at any time.

[0182] Measured Services: Cloud systems automatically control and optimize resource usage by leveraging measurement capabilities at one or more levels of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, or active user accounts, or a combination thereof). Resource usage can be monitored, controlled, reported, or a combination thereof, providing transparency to both providers and consumers of utilized services.

[0183] The service model is as follows:

[0184] Software as a Service (SaaS): The consumer is offered the ability to use a provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through a thin-client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or individual application capabilities or any combination thereof, with the possible exception of limited user-specific application configuration settings.

[0185] Platform as a Service (PaaS): The ability offered to consumers is to deploy applications they create or acquire, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, or a combination thereof, but does have control over the deployed applications and, in some cases, application hosting environment configuration.

[0186] Infrastructure as a Service (IaaS): The ability offered to consumers is to provision processing, storage, network, and other basic computing resources, or a combination thereof, onto which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but does have control over the operating system, storage, deployed applications, and possibly limited control over selected networking components (e.g., host firewalls), or a combination thereof.

[0187] The deployment model is as follows:

[0188] Private Cloud: Cloud infrastructure is operated exclusively for an organization. It can be managed by the organization or a third party and can exist on-premise or off-premise.

[0189] Community Cloud: Cloud infrastructure is shared by multiple organizations to support a specific community with shared interests (e.g., roles, security requirements, policies, compliance considerations, or a combination thereof). It may be managed by the organizations or a third party and may exist on-premises or off-premises.

[0190] Public Cloud: Cloud infrastructure is made available to the general public or large industry organizations and is owned by organizations that sell cloud services.

[0191] Hybrid Cloud: A combination of two or more clouds (private, community, or public) that remain distinct entities but are bound together by standardized or proprietary technologies (e.g., cloud bursting for load balancing between clouds) that enable data and application portability.

[0192] A cloud computing environment is a service oriented environment that emphasizes statelessness, low coupling, modularity, semantic interoperability, or a combination thereof. At the core of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0193] Additionally, the non-limiting system 100 and / or exemplary operating environment 1300 may be associated with and / or included in a data analysis system, a data processing system, a graph analysis system, a graph processing system, a big data system, a social network system, a speech recognition system, an image recognition system, a graphical modeling system, a bioinformatics system, a data compression system, an artificial intelligence system, an authentication system, a syntactic pattern recognition system, a medical system, a health monitoring system, a network system, a computer network system, a communication system, a router system, a server system, a high availability server system (e.g., a Telecom server system), a web server system, a file server system, a data server system, a disk array system, a power insertion board system, a cloud-based system, and / or the like. Accordingly, the non-limiting system 100 and / or exemplary operating environment 1300 may be utilized to solve problems using hardware and / or software that are not abstract and / or highly technical in nature and cannot be performed as a set of human mental activities.

[0194] Referring now to details of one or more aspects shown in FIG. 14 , an exemplary cloud computing environment 1450 is illustrated. As shown, the cloud computing environment 1450 includes one or more cloud computing nodes 1410 with which local computing devices used by cloud consumers may communicate, such as, for example, a personal digital assistant (PDA) or mobile phone 1454A, a desktop computer 1454B, a laptop computer 1454C, an automobile computer system 1454N, or a combination thereof. Although not shown in FIG. 14 , the cloud computing nodes 1410 may further include a quantum platform (e.g., a quantum computer, quantum hardware, quantum software, the like, or a combination thereof) with which local computing devices used by cloud consumers may communicate. The cloud computing nodes 1410 may communicate with each other. They may be physically or virtually grouped (not shown) in one or more networks, such as a private cloud, a community cloud, a public cloud, or a hybrid cloud, or a combination thereof, as described above. This allows the cloud computing environment 1450 to provide infrastructure, platform, and / or software as a service for which cloud consumers are not required to maintain resources on their local computing devices. It should be understood that the types of computing devices 1454A-N shown in Figure 14 are intended to be exemplary only, and that the cloud computing node 1410 and the cloud computing environment 1450 may communicate (e.g., using a web browser) with any type of computerized device over any type of network, network-addressable connection, or combination thereof.

[0195] Referring now to details of one or more aspects illustrated in FIG. 15 , a set of functional abstraction layers 1500, such as those provided by cloud computing environment 1450 ( FIG. 14 ), is illustrated. One or more embodiments described herein may be associated with (e.g., accessible through) one or more functional abstraction layers described below with reference to FIG. 15 (e.g., hardware and software layer 1560, virtualization layer 1570, management layer 1580, workload layer 1590, or a combination thereof). It should be understood in advance that the components, layers, functions, or combinations thereof illustrated in FIG. 15 are intended to be illustrative only, and the embodiments described herein are not limited thereto. As illustrated, the following layers, corresponding functions, or combinations thereof are provided:

[0196] Hardware and software layer 1560 may include hardware and software components. Examples of hardware components include mainframe 1561, RISC (minimum instruction set computer) architecture-based server 1562, server 1563, blade server 1564, storage device 1565, network, networking component 1566, or any combination thereof. In one or more embodiments, software components may include network application server software 1567, quantum platform routing software 1568, quantum software (not shown in FIG. 15), or any combination thereof.

[0197] The virtualization layer 1570 may provide an abstraction layer from which the following examples of virtual entities may be provided: virtual servers 1571, virtual storage 1572, virtual networks including virtual private networks 1573, virtual applications, operating systems 1574, or a combination thereof, virtual clients 1575, or a combination thereof.

[0198] In one example, management layer 1580 may provide the functions described below. Resource provisioning 1581 may provide dynamic procurement of computing and other resources that can be utilized to execute tasks within the cloud computing environment. Metering and pricing 1582 may provide cost tracking as resources are used within the cloud computing environment, charging, billing for the consumption of these resources, or a combination thereof. In one example, these resources may include one or more application software licenses. Security may provide identity verification for cloud consumers, tasks, or a combination thereof, and protection for data, other resources, or a combination thereof. User (or entity) portal 1583 may provide access to the cloud computing environment for consumers and system administrators. Service level management 1584 may provide cloud computing resource allocation, management, or a combination thereof, so that required service levels are met. Service level agreement (SLA) planning and fulfillment 1585 may provide advance arrangements and procurement for cloud computing resources that anticipate future requirements according to SLAs.

[0199] Workload tier 1590 may provide examples of functionality for which a cloud computing environment may be utilized. Non-limiting examples of workloads and functions that may be provided from this tier include mapping and navigation 1591, software development and lifecycle management 1592, virtual classroom instructional delivery 1593, data analytics processing 1594, transaction processing 1595, application transformation software 1596, or a combination thereof.

[0200] The embodiments described herein may relate to one or more of a system, a method, an apparatus, a computer program product, or a combination thereof at any possible level of technical detail of integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to perform aspects of one or more embodiments described herein. A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. Computer-readable storage media may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, superconducting storage devices, and / or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may also include portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or raised structures in grooves with instructions recorded thereon, or any suitable combination of the above. Computer-readable storage media as used herein should not be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves or a combination thereof, electromagnetic waves propagated through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable) or a combination thereof, or electrical signals transmitted through wires or a combination thereof.

[0201] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or storage device, or a combination thereof, over a network, such as the Internet, a local area network, a wide area network, or a wireless network. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing / processing device. The computer readable program instructions for carrying out the operations of one or more embodiments described herein may be source code, object code, or a combination thereof written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, an object-oriented programming language, e.g., Smalltalk, C++, or the like, a procedural programming language such as the "C" programming language, a similar programming language, or a combination thereof. The computer readable program instructions may be executed entirely on the computer, partially on the computer, as a stand-alone software package, partially on the computer, partially on a remote computer, or a combination thereof, or entirely on a remote computer, a server, or a combination thereof.In the latter scenario, the remote computer may be connected to the computer through any type of network, including a local area network (LAN), a wide area network (WAN), or a combination thereof, may be connected to the external computer (e.g., over the Internet using an Internet service provider), or a combination thereof. In one or more embodiments, an electronic circuit, including, for example, a programmable logic circuit, a field programmable gate array (FPGA), a programmable logic array (PLA), or a combination thereof, may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuit to perform aspects of one or more embodiments described herein.

[0202] Aspects of one or more embodiments described herein will be described with reference to flowchart diagrams, block diagrams, or combinations thereof of methods, apparatus (systems), and computer program products according to one or more embodiments described herein. It will be understood that each block of the flowchart diagrams and / or block diagrams, and combinations of blocks in the flowchart diagrams and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, or combinations thereof, to create a machine. The instructions, executed by the processor of the computer or other programmable data processing apparatus, may thereby form means for implementing the function / acts specified in a block or blocks of the flowchart or block diagram, or combinations thereof. These computer-readable program instructions may also be stored on a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, or other device, or combinations thereof, to function in a particular manner. A computer-readable storage medium having instructions stored thereon may thereby comprise an article of manufacture including instructions that can implement an aspect of the function / acts specified in a block or blocks of the flowchart or block diagram, or combinations thereof. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, other device, or combination thereof, to cause a series of operational acts to be performed on the computer, other programmable apparatus, other device, or combination thereof, creating a computer-implemented process, whereby the instructions executing on the computer, other programmable apparatus, other device, or combination thereof, implement the function / acts specified in a block or blocks of the flowchart or block diagram, or combination thereof.

[0203] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, operation, or combination thereof of possible implementations of a system, computer-implementable method, computer program product, or combination thereof according to one or more embodiments described herein. In this regard, each block in a flowchart or block diagram may represent a module, segment, portion of instructions, or combination thereof, comprising one or more executable instructions for implementing the specified logical function(s). In one or more alternative implementations, the functions described in the blocks may occur out of the order depicted in the figures. For example, two blocks shown in succession may be executed substantially simultaneously, depending on the functionality involved, or the blocks may possibly be executed in the reverse order, or a combination thereof. It is also noted that each block of a block diagram, flowchart diagram, or combination thereof, or combination of blocks in a block diagram, flowchart diagram, or combination thereof, may be implemented by a special-purpose hardware-based system that may perform the specified functions, actions, or combinations thereof, and that may execute one or more combinations of instructions of special-purpose hardware, a computer, or combinations thereof.

[0204] While the subject matter has been described above in the general context of computer-executable instructions for a computer program product executing on a computer, multiple computers, or combinations thereof, those skilled in the art will recognize that one or more embodiments herein can also be implemented in combination with one or more other program modules. Generally, program modules include routines, programs, components, data structures, the like, or combinations thereof that perform particular tasks, implement particular abstract data types, or combinations thereof. Additionally, the computer-implemented methods described above can be practiced with single-processor and / or multiprocessor computer systems, minicomputing devices, mainframe computers, and other computer system configurations, including computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer and / or industrial electronics, and / or the like. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. However, one or more aspects, if not all, of one or more embodiments described herein can be practiced on a stand-alone computer. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

[0205] As used herein, terms such as “component,” “system,” “platform,” “interface,” and combinations thereof may refer to, include, or be a combination of computer-related entities or entities related to an operating machine having one or more specific functionalities. The entities described herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer, or combinations thereof. By way of illustration, both an application running on a server and the server may be a component. One or more components may reside in a process, thread of execution, or combinations thereof; a component may be localized on one computer, distributed between two or more computers, or combinations thereof. In another example, each component may execute from various computer-readable media having various data structures stored thereon. Components may communicate via local, remote, or a combination thereof processes, such as according to signals comprising one or more data packets (e.g., data from one component interacting with another component in a local system, a distributed system, or a network such as the Internet with other systems or combinations thereof via signals). As another example, a component may be a device having inherent functionality provided by mechanical parts operated by electrical or electronic circuits operated by software, firmware applications, or combinations thereof executed by a processor. In such cases, the processor may be internal, external, or a combination thereof to the device and may execute at least a portion of the software, firmware applications, or combinations thereof.As yet another example, a component may be a device that provides its inherent functionality without mechanical parts through electronic components, which may include a processor, other means, or combination thereof, for executing software, firmware, or a combination thereof that provides at least a portion of the functionality of the electronic component. In some aspects, a component may emulate the electronic component via, for example, a virtual machine in a cloud computing system.

[0206] Additionally, the term "or" is intended to mean an inclusive "or," rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X utilizes A or B" is intended to mean any of the natural inclusive permutations. That is, in any of the foregoing examples, "X utilizes A or B" is satisfied when X utilizes A, when X utilizes B, or when X utilizes both A and B. Also, as used in this specification and the accompanying drawings, the articles "a" and "an" should generally be construed to mean "one or more" unless otherwise specified or clear from the context to refer to the singular form. As used herein, the terms "example" and / or "exemplary" are used to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter described herein is not limited to such examples. Additionally, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0207] The term "processor" as used herein may refer to virtually any computing processing unit, device, or combination thereof, including, but not limited to, a single-core processor, a single processor with software multithreading execution capabilities, a multi-core processor, a multi-core processor with software multithreading execution capabilities, a multi-core processor with hardware multithreading technology, a parallel platform, a parallel platform with distributed shared memory, or a combination thereof. Additionally, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, gates, or combinations thereof, to optimize space utilization or enhance performance of associated equipment, or a combination thereof. A processor may be implemented as a combination of computing processing units.

[0208] As used herein, terms such as “store,” “storage,” “data store,” “data storage,” “database,” and substantially any other information storage component associated with the operation and functionality of a component are used to refer to a “memory” or a “memory component” entity embodied in a component that includes memory. The memory and / or memory components described herein may be either volatile or nonvolatile memory, or may include both volatile and nonvolatile memory. By way of example and not limitation, nonvolatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)), or combinations thereof. Volatile memory may include RAM, which may act as external cache memory, for example. By way of example, and not limitation, RAM may be available in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), Rambus dynamic RAM (RDRAM), or combinations thereof. Additionally, the described memory components of systems and / or computer-implemented methods herein are intended to include, but are not limited to, these and / or any other suitable types of memory.

[0209] What has been described above includes only example systems and computer-implemented methods. Of course, for purposes of describing one or more embodiments, it is not possible to describe every conceivable combination of components, computer-implemented methods, or combinations thereof; however, one of ordinary skill in the art may recognize that many additional combinations, permutations, or combinations thereof of one or more embodiments are possible. Furthermore, when the terms "including," "having," "comprising," and the like are used in the detailed description, claims, appendices, and / or drawings, such terms are intended to be inclusive in the same manner as the term "comprising" is interpreted when used as a transitional phrase in the claims.

[0210] The description of one or more embodiments is presented for illustrative purposes and is not intended to be exhaustive or limited to the embodiments described herein. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, technical improvements over techniques found in the industry, or combinations thereof, or to allow those skilled in the art to understand the embodiments described herein, or for such combinations.

Claims

1. a tunable first coupler coupled to the first qubit; a tunable second coupler coupled to the second qubit; and a junction that couples the first coupler and the second coupler wherein the first coupler and the second coupler are parametrically excitable.

2. The electronic device of claim 1 , wherein the first coupler and the second coupler comprise superconducting quantum interference devices or Josephson junctions.

3. 10. The electronic device of claim 1, wherein the junction has a central hub or node separately coupled to the first coupler and the second coupler.

4. The electronic device of claim 3 , wherein the junction has a central hub, the central hub including a loop of series-coupled inductors.

5. a third coupler coupled to the third qubit 10. The electronic device of claim 9, further comprising: a junction coupling the first coupler, the second coupler, and the third coupler, the third coupler being parametrically excitable; and the junction being separately coupled to the first coupler, the second coupler, and the third coupler.

6. 10. The electronic device of claim 1, wherein the junction provides a unique coupling between the first qubit and the second qubit.

7. 10. The electronic device of claim 1, wherein the first coupler and the second coupler are configured to capacitively or inductively couple the first qubit and the second qubit to one another, and wherein the electronic device is configured to perform a controlled-Z (CZ) gate utilizing the first qubit and the second qubit.

8. 10. The electronic device of claim 1, wherein the first coupler and the second coupler are configured to capacitively or inductively couple the first qubit and the second qubit to one another, and wherein the electronic device is configured to perform an iSWAP gate utilizing the first qubit and the second qubit.

9. 1. A method of performing a quantum gate operation, comprising: applying, by a system operably coupled to the processor, a first bias and a first parametric excitation to a first coupler coupled to the first qubit; applying, by the system, a second bias and a second parametric excitation to a second coupler coupled to a second qubit and to the first coupler; and performing a parametric gate operation using the first qubit and the second qubit with the system. A method for providing

10. applying, by the system, the first parametric excitation and the second parametric excitation at respective frequencies that are a difference between the respective frequencies of the first qubit and the second qubit. The method of claim 9 further comprising:

11. applying, with the system, the first parametric excitation and the second parametric excitation when the first qubit is in a respective excited state and when the second qubit is in a respective excited state. The method of claim 10 further comprising:

12. applying, by the system, the first parametric excitation and the second parametric excitation at respective frequencies that are the difference between the respective frequencies of the first qubit and the second qubit, plus or minus anharmonicity of the first and second qubits.

12. The method of any one of claims 9 to 11, further comprising:

13. applying, with the system, the first parametric excitation and the second parametric excitation when one of the first qubit or the second qubit is in a respective excited state and the other of the first qubit or the second qubit is in a respective ground state. The method of claim 12 further comprising:

14. and inductively coupling the first coupler and the second coupler by a pair of radio frequency superconducting quantum interference devices of the first coupler and the second coupler.

14. The method of any one of claims 9 to 13, further comprising:

15. capacitively coupling the first coupler and the second coupler by a single coupling node using the system.

15. The method of any one of claims 9 to 14, further comprising:

16. applying, by the system, a third bias and a third parametric excitation to a third coupler coupled to a third qubit; applying, by the system, a fourth bias and a fourth parametric excitation to a fourth coupler coupled to a fourth qubit; and performing, with the system, a second parametric gate operation utilizing the third qubit and the fourth qubit in parallel with the parametric gate operation. Furthermore, 16. The method of any one of claims 9 to 15, wherein the first coupler, the second coupler, the third coupler, and the fourth coupler are coupled to each other by a single junction.

17. a plurality of tunable couplers each having a superconducting quantum interference device, each coupled to a respective qubit; and a junction for coupling the plurality of adjustable couplers together by an all-to-all coupling; wherein the first coupler and the second coupler are parametrically excitable.

18. 20. The electronic device of claim 17, wherein the junction has a central hub, the central hub including a loop of series-coupled inductors, the number of series-coupled inductors equal to the number of tunable couplers in the plurality of tunable couplers.

19. 19. The electronic device of any one of claims 17 to 18, wherein the plurality of tunable couplers are configured to capacitively or inductively couple the respective pairs of qubits to one another, and to utilize the respective pairs of qubits to perform a Controlled-Z (CZ) gate or an iSWAP gate.

20. 20. The electronic device of any one of claims 17 to 19, wherein the plurality of tunable couplers and the junction are collectively configured to perform a first parametric gate operation using a pair of tunable couplers from the plurality of tunable couplers, and to perform a second parametric gate operation using a different pair of tunable couplers from the plurality of tunable couplers in parallel with the first parametric gate operation.

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