Systems and methods for active noise compensation of qubits

Abstract

A quantum processor is described having a flux compensation circuit communicatively coupled to a first quantum bit. The flux compensation circuit includes a quantum flux parametron (QFP) flux pump circuit having a first QFP in communication with the first quantum bit, and a storage circuit including a second Josephson junction and a storage loop coupled in series with the QFP flux pump circuit. Communication between the QFP flux pump circuit and the storage loop is mediated by the second Josephson junction. A first control line is in communication with the first Josephson junction, and a second control line is in communication with the second Josephson junction. During use, a flux stored in the storage loop acts against the first quantum bit.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent claims priority to U.S. Patent Application No. 63 / 403,513, filed September 2, 2022, the entire disclosure of which is incorporated herein by reference for all purposes.

[0002] Field The present disclosure relates generally to active noise compensation of qubits, and particularly to active flux noise compensation in quantum processors. [Background technology]

[0003] background quantum devices Quantum devices are structures in which quantum mechanical effects are observable. Quantum devices include circuits in which current transport is governed by quantum mechanical effects. Such devices include spintronics and superconducting circuits. Both spin and superconductivity are quantum mechanical phenomena. Quantum devices can be used in measurement equipment in computing machinery and the like.

[0004] quantum computing A quantum computer is a system that directly exploits at least one quantum mechanical phenomenon, such as superposition, tunneling, or entanglement, to perform operations on data. The elements of a quantum computer are qubits. Quantum computers can provide speedups for some classes of computational problems, such as those that simulate quantum physics.

[0005] Superconducting qubit A superconducting qubit is a solid-state quantum bit based on a circuit of superconducting material. The operation of a superconducting qubit is based on the fundamental principles of flux quantization and Josephson tunneling. The superconducting effect can exist in various configurations and can give rise to various types of superconducting qubits, including flux, phase, charge, and hybrid qubits. The various configurations can vary in the topology of the loop, the placement of the Josephson junctions, and the physical parameters of the superconducting circuit elements (such as inductance, capacitance, and Josephson junction critical current).

[0006] quantum processor The quantum processor may take the form of a superconducting quantum processor, which may include many superconducting qubits and associated local bias devices, and may also include coupling devices (also known as couplers) that selectively provide communicative coupling between the qubits.

[0007] In one implementation, a superconducting qubit includes a superconducting loop interrupted by a Josephson junction. The inductance and critical current can be selected, adjusted, or tuned to increase the ratio of the inductance of the Josephson junction to the geometric inductance of the superconducting loop and to enable the qubit to operate as a bistable device. In some implementations, the ratio of the inductance of the Josephson junction to the geometric inductance of the qubit's superconducting loop is approximately equal to 3.

[0008] In one implementation, the superconducting coupler includes a superconducting loop interrupted by a Josephson junction. The inductance and critical current can be selected, adjusted, or tuned to reduce the ratio of the inductance of the Josephson junction to the geometric inductance of the superconducting loop and to enable the coupler to operate as a monostable device. In some implementations, the ratio of the inductance of the Josephson junction to the geometric inductance of the superconducting loop of the coupler is approximately equal to or less than one.

[0009] Further details and embodiments of exemplary quantum processors that may be used in conjunction with the present systems and devices are described, for example, in U.S. Patent Nos. 7,533,068, 8,008,942, 8,195,596, 8,190,548, and 8,421,053.

[0010] The foregoing examples of the related art and limitations associated therewith are intended to be illustrative and therefore not exhaustive. Other limitations of the related art will become apparent to those skilled in the art upon reading this specification and studying the accompanying drawings. Summary of the Invention [Means for solving the problem]

[0011] overview According to one aspect, there is provided a quantum processor including a first quantum bit and a flux compensation circuit communicatively coupled to the first quantum bit, the flux compensation circuit comprising: a quantum flux parametron (QFP) flux pump circuit including a first QFP in communication with the first quantum bit, the first QFP including a first Josephson junction; a quantum flux parametron flux pump circuit; a memory circuit including a second Josephson junction and a memory loop coupled in series with the QFP flux pump circuit, wherein communication between the QFP flux pump circuit and the memory loop is mediated by the second Josephson junction; a first control line in communication with the first Josephson junction; and a second control line in communication with the second Josephson junction, the memory loop being communicatively coupled to the first quantum bit such that, in use, a magnetic flux stored in the memory loop counteracts the first quantum bit.

[0012] According to another aspect, the storage loop may be communicatively coupled to the first qubit through a first QFP, the first Josephson junction and the second Josephson junction may each include a compound Josephson junction, the QFP flux pump circuit may include a second QFP coupled in series with the first QFP, the second QFP including a third Josephson junction, the first QFP and the second QFP connected by an inductor, and the QFP flux pump circuit may include a third QFP coupled in series with the second QFP, the coupling between the second QFP and the third QFP being a fourth Josephson junction. The quantum processor may further include a third control line in communication with the third Josephson junction and a fourth control line in communication with the fourth Josephson junction, the third Josephson junction and the fourth Josephson junction may each include a compound Josephson junction, the quantum processor may include a set of qubits, the first qubit is one of the set of qubits, each qubit of the set of qubits may be coupled to a respective flux compensation circuit, and the memory loop may include a high kinetic inductance material.

[0013] According to one aspect, there is provided a flux compensation circuit including a quantum flux parametron (QFP) flux pump circuit, the quantum flux parametron (QFP) flux pump circuit comprising: a first QFP including a first Josephson junction; a second QFP connected in series with the first QFP and including a third Josephson junction, the first QFP and the second QFP being connected by an inductor; a third QFP connected in series with the second QFP, the connection between the second QFP and the third QFP being a fourth Josephson junction; a memory circuit including a third QFP, a second Josephson junction connected in series with the QFP flux pump circuit, and a memory loop, the connection between the QFP flux pump circuit and the memory loop being mediated by the second Josephson junction; a first control line in communication with the first Josephson junction, a second control line in communication with the second Josephson junction, a third control line in communication with the third Josephson junction, and a fourth control line in communication with the fourth Josephson junction.

[0014] According to another embodiment, each of the first, second, third and fourth Josephson junctions may include a compound Josephson junction, and the storage loop may include a high dynamic inductance material.

[0015] According to one aspect, a method for correcting flux noise in a quantum bit is provided, the method including iteratively performing the following until an exit condition is satisfied: projecting information about the flux state of the quantum bit into a quantum flux parametron (QFP) flux pump circuit; replicating the information about the flux state of the quantum bit as a directional current through the QFP flux pump circuit; activating a Josephson junction coupled in series with the QFP flux pump circuit to store flux in a storage loop connected to the Josephson junction based on the directional current; evaluating the exit condition; and transferring the flux stored in the storage loop to the quantum bit to reduce the flux state of the quantum bit.

[0016] According to other aspects, projecting information regarding the flux state of the qubit into a QFP flux pump circuit may include annealing the qubit in the presence of ambient flux noise, and projecting information regarding the flux state of the qubit into a QFP flux pump circuit may include annealing a first QFP in communication with the qubit in the presence of ambient flux noise, and replicating information regarding the flux state of the qubit as a directional current through the QFP flux pump circuit may include: inducing a current into the first QFP including a first Josephson junction based on the projected information regarding the flux state; activating the first Josephson junction to latch the first QFP; and inducing a current into a second QFP including a second Josephson junction based on the current in the latched first QFP. P and activating the second Josephson junction to latch the second QFP; replicating the information regarding the flux state of the qubit as a directional current via the QFP flux pump circuit may further include: inducing a current in a third QFP including a third Josephson junction based on the current in the latched second QFP, and activating the third Josephson junction to latch the third QFP; evaluating the exit condition may include incrementing a counter until a certain number of iterations have occurred; and the method may further include deactivating a bias device in communication with the qubit to isolate the qubit prior to projecting the information regarding the flux state of the qubit.

[0017] According to one aspect, there is provided a method of correcting flux noise in a quantum processor including a plurality of qubits, the method comprising performing any of the methods described herein for each qubit in the quantum processor.

[0018] Described herein are error suppression techniques for reducing on-chip flux noise on a per-qubit basis. As used herein, "on-chip" refers to being part of the same processor as the qubits being compensated. A quantum processor typically includes not only qubits and couplers, but also control devices and other on-chip circuitry, as discussed with respect to FIG. 2 . The compensation circuitry described herein provides compensation for those qubits in situ or as part of the quantum processor. In particular, many quantum processors are maintained in an isolated environment, such as a cryogenic refrigerator, and thus on-chip flux noise compensation can occur without the need for information to be read out to a separate circuit or processor outside the isolated environment or at room temperature. On-chip circuitry is provided for capturing and aggregating information about qubit flux offsets due to noise, which can be used to correct for the offsets. The above methods and devices may advantageously enable flux noise compensation without the need to bring information about qubit states off-chip or to reprogram on-chip digital-to-analog converters (DACs). This may advantageously enable faster and more effective compensation of low-frequency flux noise. Thus, reducing the flux noise present within each qubit can reduce problem misspecification and dephasing, improving the performance of quantum processors. Reducing flux noise can also simplify the requirements for error correction mechanisms in gate-model quantum computing.

[0019] In other aspects, the above-described features may be combined together in any reasonable combination as would be understood by one of ordinary skill in the art.

[0020] A brief description of some of the figures in the drawing In the accompanying drawings, like reference numbers identify similar elements or acts. The dimensions and relative positions of elements in the accompanying drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve the readability of the drawings. Furthermore, the particular shapes of the elements as depicted are not necessarily intended to convey any information regarding the actual shape of the particular elements, and may have been selected solely for ease of recognition in the accompanying drawings. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a schematic diagram of a hybrid computing system including a digital computer coupled to an analog computer in accordance with present systems, devices and methods; [Figure 2] 1 is a schematic diagram of a portion of an exemplary superconducting quantum processor that may be employed in accordance with the present systems, devices, and methods. [Figure 3] FIG. 1 is a schematic diagram of an exemplary fluxonium qubit that may be employed in accordance with the present systems, devices, and methods. [Figure 4] 1 is a schematic diagram of an exemplary noise compensation circuit that may be employed in accordance with the present systems, devices, and methods. [Figure 5] 4 is a graph of an exemplary signal pattern for a noise compensation circuit that may be employed in accordance with the present systems, devices, and methods. [Figure 6A] 1A-1C are schematic diagrams of an exemplary noise compensation circuit at successive stages of a noise compensation cycle that may be employed in accordance with the present systems, devices, and methods. [Figure 6B] 1A-1C are schematic diagrams of an exemplary noise compensation circuit at successive stages of a noise compensation cycle that may be employed in accordance with the present systems, devices, and methods. [Figure 6C] 1A-1C are schematic diagrams of an exemplary noise compensation circuit at successive stages of a noise compensation cycle that may be employed in accordance with the present systems, devices, and methods. [Figure 6D]1A-1C are schematic diagrams of an exemplary noise compensation circuit at successive stages of a noise compensation cycle that may be employed in accordance with the present systems, devices, and methods. [Figure 6E] 1A-1C are schematic diagrams of an exemplary noise compensation circuit at successive stages of a noise compensation cycle that may be employed in accordance with the present systems, devices, and methods. [Figure 6F] 1A-1C are schematic diagrams of an exemplary noise compensation circuit at successive stages of a noise compensation cycle that may be employed in accordance with the present systems, devices, and methods. [Figure 6G] 1A-1C are schematic diagrams of an exemplary noise compensation circuit at successive stages of a noise compensation cycle that may be employed in accordance with the present systems, devices, and methods. [Figure 6H] 1A-1C are schematic diagrams of an exemplary noise compensation circuit at successive stages of a noise compensation cycle that may be employed in accordance with the present systems, devices, and methods. [Figure 6I] 1A-1C are schematic diagrams of an exemplary noise compensation circuit at successive stages of a noise compensation cycle that may be employed in accordance with the present systems, devices, and methods. [Figure 6J] 1A-1C are schematic diagrams of an exemplary noise compensation circuit at successive stages of a noise compensation cycle that may be employed in accordance with the present systems, devices, and methods. [Figure 6K] 1A-1C are schematic diagrams of an exemplary noise compensation circuit at successive stages of a noise compensation cycle that may be employed in accordance with the present systems, devices, and methods. [Figure 7] 1 is a graph of an exemplary probability distribution of qubit states that may be employed in accordance with the present systems, devices, and methods. [Figure 8] 1 is a flowchart of a method for correcting magnetic flux noise that may be employed in accordance with the present systems, devices, and methods. DETAILED DESCRIPTION OF THE INVENTION

[0022] Detailed Description In the following description, some specific details are set forth to provide a thorough understanding of various disclosed implementations. However, those skilled in the art will recognize that some implementations may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures related to computer systems, server computers, and / or communication networks have not been shown or described in order to avoid unnecessarily obscuring the description of the implementations.

[0023] Unless the context requires otherwise, throughout the following specification and claims, the term "comprising" is synonymous with "including" and is inclusive or open-ended (i.e., does not exclude additional, unrecited elements or method acts).

[0024] References throughout this specification to "one implementation" or "an implementation" mean that a particular feature, structure, or characteristic described in connection with that implementation is included in at least one implementation. Thus, the appearances of the phrase "in one implementation" or "in an implementation" in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations.

[0025] As used in this specification and the appended claims, the singular articles "a," "an," and "the" include plural references unless the context clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and / or" unless the context clearly dictates otherwise. The disclosure titles and abstracts provided herein are for convenience only and do not interpret the scope or meaning of the implementations.

[0026] Exemplary Hybrid Computing System 1 shows a computing system 100 that includes a digital computer 102. The digital computer 102 includes one or more digital processors 106 that can be used to perform classical digital processing tasks. The digital computer 102 can also include at least one system memory 122 and at least one system bus 120 that couples various system components, including the system memory 122, to the digital processor 106. The system memory 122 can store one or more sets of processor-executable instructions, which can be referred to as modules 124.

[0027] Digital processor 106 may be any logical processing unit or circuit configuration (e.g., integrated circuit), such as one or more central processing units ("CPUs"), graphics processing units ("GPUs"), digital signal processors ("DSPs"), application specific integrated circuits ("ASICs"), programmable gate arrays ("FPGAs"), programmable logic controllers ("PLCs"), etc., and / or combinations thereof.

[0028] In some implementations, computing system 100 includes analog computer 104, which may include one or more quantum processors 126. Quantum processor 126 may include at least one superconducting integrated circuit. Digital computer 102 may communicate with analog computer 104, for example, via controller 118. Some calculations may be performed by analog computer 104 at the direction of digital computer 102, as described in more detail herein.

[0029] The digital computer 102 may include a user input / output subsystem 108. In some implementations, the user input / output subsystem 108 includes one or more user input / output components, such as a display 110, a mouse 112, and / or a keyboard 114.

[0030] The system bus 120 may employ any known bus structure or architecture, including a memory bus with a memory controller, a peripheral bus, and a local bus. The system memory 122 may include read-only memory ("ROM"), static random access memory ("SRAM"), non-volatile memory such as flash NAND, and volatile memory (not shown), such as random access memory ("RAM").

[0031] The digital computer 102 may also include other non-transitory computer- or processor-readable storage media or non-volatile memory 116. The non-volatile memory 116 may take a variety of forms, including a hard disk drive for reading from and writing to a hard disk (e.g., a magnetic disk), an optical disk device for reading from and writing to a removable optical disk, and / or a solid-state drive (SSD) for reading from and writing to solid-state media (e.g., NAND-based flash memory). The non-volatile memory 116 may communicate with the digital processor via a system bus 120 and may include an appropriate interface or controller 118 coupled to the system bus 120. The non-volatile memory 116 may serve as long-term storage (sometimes referred to as a program module or program modules 124) for the digital computer 102's processor or computer-readable instructions, data structures, or other data.

[0032] Although the digital computer 102 has been described as employing hard disks, optical disks, and / or solid-state storage media, those skilled in the art will recognize that other types of non-transitory, non-volatile computer-readable media may be employed. Those skilled in the art will understand that some computer architectures employ non-transitory, volatile memory and non-transitory, non-volatile memory. For example, data in volatile memory may be cached to non-volatile memory or to a solid-state disk that employs integrated circuits to provide the non-volatile memory.

[0033] Various processor- or computer-readable and / or executable instructions, data structures, or other data may be stored in system memory 122. For example, system memory 122 may store instructions for communicating with remote customers and for scheduling the use of resources, including resources on digital computer 102 and analog computer 104. Also, for example, system memory 122 may store at least one of processor-executable instructions or data that, when executed by at least one processor, cause the at least one processor to perform various algorithms for executing instructions. In some implementations, system memory 122 may store processor- or computer-readable computational instructions and / or data for pre-processing, co-processing, and post-processing for analog computer 104. System memory 122 may store a set of analog computer interface instructions for interacting with analog computer 104. For example, system memory 122 may store processor- or computer-readable instructions, data structures, or other data that, when executed by a processor or computer, cause the processor or computer to perform one or more or all of the acts of method 800 (FIG. 8).

[0034] Analog computer 104 may include at least one analog processor, such as quantum processor 126. Analog computer 104 may be provided in an isolated environment (e.g., an isolated environment that shields the internal components of the analog computer from heat, magnetic fields, and other external noise). The isolated environment may include a refrigerator (e.g., a dilution refrigerator) operable to cryogenically cool the analog processor (e.g., to temperatures below about 1 K).

[0035] Analog computer 104 may be a quantum processor and may include programmable elements (also referred to herein as controllable devices) such as qubits, couplers, and other devices. Qubits may be read out via readout control system 128. The readout results may be transmitted to other computer-readable instructions or processor-readable instructions in digital computer 102. Qubits may be controlled via qubit control system 130. Qubit control system 130 may include on-chip digital-to-analog converters (DACs) and analog lines operable to apply biases to target devices. Couplers coupling qubits may be controlled via coupler control system 132. Coupler control system 132 may include tuning elements such as on-chip DACs and analog lines. Qubit control system 130 and coupler control system 132 may be used to implement quantum annealing schedules as described herein on analog computer 104. The programmable elements may be included within quantum processor 126 in the form of an integrated circuit. The qubits and couplers may be located in a layer of the integrated circuit comprising a first material. Other devices, such as devices of readout control system 128, may be located in other layers of the integrated circuit comprising a second material. According to this disclosure, quantum processors, such as quantum processor 126, may be designed to perform quantum annealing and / or adiabatic quantum computing. Examples of quantum processors are described in U.S. Patent No. 7,533,068.

[0036] Quantum processors can perform two general types of quantum computation. The first (quantum annealing and / or adiabatic quantum computing) generally relies on the physical evolution of quantum systems. Gate (or circuit) model quantum computing relies on the use of quantum gate operations to perform computations using data. Surface code refers to a specific implementation of error-correcting gate or circuit quantum computing (QC) in which logical qubits are encoded into several portions or patches of a square lattice of physical qubits using a two-dimensional low-density parity-check scheme. Other implementations of gate model quantum computing are known in the art.

[0037] Exemplary Superconducting Quantum Processor Figure 2 is a schematic diagram of a portion of an example superconducting quantum processor 200 according to at least one implementation. The portion of superconducting quantum processor 200 shown in Figure 2 includes two superconducting qubits 201 and 202. Also shown is tunable coupling (i.e., providing a 2-local interaction) between qubits 201 and 202 via coupler 210. Although the portion of quantum processor 200 shown in Figure 2 includes only two qubits 201, 202 and one coupler 210, those skilled in the art will understand that quantum processor 200 may include any number of qubits and any number of coupler coupling information therebetween.

[0038] Quantum processor 200 includes multiple interfaces 221, 222, 223, 224, and 225 that are used to configure and control the state of quantum processor 200. Each of interfaces 221-225 may be implemented by a respective inductively coupled structure, as shown as part of the programming and / or evolution subsystems. Alternatively, or in addition, interfaces 221-225 may be implemented by a galvanically coupled structure. In some implementations, one or more of interfaces 221-225 may be driven by one or more DACs. Such programming and / or evolution subsystems may be separate from quantum processor 200 or may be included locally (i.e., on-chip with quantum processor 200).

[0039] In operation of quantum processor 200, interfaces 221 and 224 may each be used to couple flux signals into compound Josephson junctions 231 and 232 of qubits 201 and 202, respectively, thereby introducing a tunable tunneling term (Δ i This coupling realizes the off-diagonal σ xterms, and these flux signals are examples of “delocalized signals.” Examples of Hamiltonians (and their terms) used in quantum computing are described in more detail in, for example, U.S. Patent No. 9,424,526.

[0040] Similarly, interfaces 222 and 223 can each be used to apply a flux signal into the qubit loop of qubits 201 and 202, respectively, thereby changing the h i This coupling realizes the diagonal σ z Additionally, interface 225 can be used to couple the flux signal into coupler 210, thereby providing a J ij This coupling realizes the diagonal σ i z σ j z Provide a term.

[0041] In Figure 2, the contribution of each interface 221-225 to the system Hamiltonian is indicated within dashed boxes 221a, 222a, 223a, 224a, and 225a. As shown in the example of Figure 2, dashed boxes 221a-225a are elements of a time-varying Hamiltonian for quantum annealing and / or adiabatic quantum computation.

[0042] While quantum processor 200 is one example of a quantum annealing processor, it will be understood that the methods described herein may also be applied to other types of quantum processors, such as gate or circuit model quantum processors. Throughout this specification and the appended claims, the term "quantum processor" is used to generally describe a collection of physical qubits (e.g., qubits 201 and 202) and qubit couplers (e.g., coupler 210). Physical qubits 201 and 202 and coupler 210 are referred to as "controllable devices" of quantum processor 200, and their corresponding parameters (e.g., qubit h i Value and coupler J ij The controllable parameters (values) are referred to as the "controllable parameters" of the quantum processor. In the context of quantum processors, the term "programming subsystem" is used generally to describe the interfaces (e.g., programming interfaces 222, 223, and 225) used to apply the controllable parameters to the controllable devices and other associated control circuitry and / or instructions of quantum processor 200. In some implementations, programming interfaces 222, 223, and 225 may include DACs. DACs may also be programmable devices used to control controllable devices such as qubits, couplers, and parameter tuning devices.

[0043] As previously described, the programming interface of the programming subsystem may communicate with other subsystems, which may be separate from the quantum processor or may be included locally on the processor. The programming subsystem may be configured to receive programming instructions in machine language for the quantum processor and to execute the programming instructions to program the programmable and controllable devices in accordance with the programming instructions. Similarly, in the context of a quantum processor, the term "evolution subsystem" generally includes interfaces (e.g., evolution interfaces 221 and 224) used to evolve devices such as qubits of quantum processor 200 and other associated control circuitry and / or instructions. For example, the evolution subsystem may include annealing signal lines to qubits 201 and 202 and their corresponding interfaces 221, 224. Evolution may refer to performing quantum annealing or other types of quantum computation.

[0044] Quantum processor 200 also includes readout devices 251 and 252, where readout device 251 is associated with qubit 201 and readout device 252 is associated with qubit 202. In the exemplary implementation shown in FIG. 2 , readout devices 251 and 252 each include a direct current superconducting quantum interference device (DC-SQUID) inductively coupled to a corresponding qubit. In the context of quantum processor 200, the term “readout subsystem” is used to generally describe readout devices 251 and 252 used to read out the final states of qubits (e.g., qubits 201 and 202) in quantum processor 200 to generate a bit string. The readout subsystem may also include other elements such as routing circuitry (e.g., latch elements, shift registers, or multiplexer circuits) and / or may be arranged in alternative configurations (e.g., an XY-addressable array, an XYZ-addressable array, etc.), any of which may include a DAC. Qubit readout can also be performed using alternative circuitry such as that described in US Pat. No. 8,854,074.

[0045] 2 shows only two physical qubits 201, 202, one coupler 210, and two readout devices 251, 252, a quantum processor (e.g., quantum processor 200) may employ any number of qubits and couplers, and / or readout devices (including large numbers (e.g., hundreds, thousands, or more) of qubits, couplers, and / or readout devices). Application of the present teachings to processors having different numbers (e.g., large numbers) of computer components should be readily apparent to one of ordinary skill in the art.

[0046] Examples of superconducting qubits include superconducting flux qubits, superconducting charge qubits, etc. In superconducting flux qubits, the Josephson energy dominates or is equal to the charge energy. In charge qubits, this is the opposite. Examples of flux qubits that can be used include radio frequency superconducting quantum interference devices (rf-SQUIDs), which include a superconducting loop interrupted by one Josephson junction, persistent current qubits, which include a superconducting loop interrupted by three Josephson junctions, etc.

[0047] 3 is a schematic diagram of an example implementation of a superconducting qubit 300. The fluxonium qubit has a large body inductance (E J / E L ≫1 and E C / E L>>1). For a discussion of fluxonium qubits, see Manucharyan, VE, et al., 2009, Science 326(5949), 113 and U.S. Provisional Patent Application No. 63 / 223,686. Superconducting qubit 300 is similar to a fluxonium qubit and replaces the Josephson junction array of the fluxonium qubit with a kinetic inductor. Superconducting qubit 300 includes a Josephson junction structure 301 and a kinetic inductor 302. In this exemplary implementation, Josephson junction structure 301 includes two Josephson junctions 304 and 305 to form a compound Josephson junction (CJJ). Those skilled in the art will appreciate that Josephson junction structure 301 may include only one Josephson junction or may include a compound-compound Josephson junction (CCJJ) where one or both of the parallel paths of the CJJ are themselves CJJs, and in some implementations, Josephson junction structure 301 may include other structures, such as inductors electrically in series with Josephson junctions 304 and 305. Kinetic inductor 302 may include niobium nitride (NbN), niobium titanium nitride (NbTiN), or titanium nitride (TiN).

[0048] Kinetic Inductance Electric current flowing through a metallic material principally stores energy both in the magnetic field of the metal and in the kinetic energy of the charge carriers (e.g., electrons or Cooper pairs). In non-superconducting metals, charge carriers frequently collide with the lattice and lose their kinetic energy as Joule heating. This is also called scattering, and the energy is rapidly released. However, in superconducting materials, scattering is greatly reduced because the charge carriers are Cooper pairs, which are protected from dissipation through scattering. This allows superconducting materials to store energy in the form of kinetic inductance. This phenomenon allows kinetic inductance to efficiently store energy in superconducting metals. Kinetic inductance is determined at least in part by the inertial mass of the charge carriers in a given material and increases as carrier density decreases. As charge carrier density decreases, fewer charge carriers must have proportionally greater velocity to generate the same current. Materials with high kinetic inductance per given area (as defined below) are called "kinetic inductance materials" or "high kinetic inductance materials."

[0049] Kinetic inductance materials are materials with high normal state resistivity and / or small superconducting energy gaps, resulting in a larger kinetic inductance per unit area. Generally, the total inductance L of a superconducting material is L = L K +L G where L G is the geometric inductance, and L K is the kinetic inductance. The kinetic inductance of a superconducting film at temperatures close to zero is the effective penetration depth λ eff In particular, for a film with a given thickness t, the kinetic inductance of the film is proportional to the ratio of the film's length L to its width W, where length is the direction of current flow and width is orthogonal to length (note that both width and length are orthogonal to the dimension in which thickness is measured). That is, for a superconducting film with a given thickness

number

number

[0050] magnetic flux noise A qubit (e.g., 201, 202, 300) is an example of a noise-vulnerable device in a quantum processor. A coupler (e.g., 210) is another example. Herein, the phrases “noise-vulnerable superconducting device” or “device with high noise vulnerability” are used to describe superconducting devices that are noise-vulnerable, since a noise-free operating environment is highly desirable for the performance of superconducting integrated circuits, such as quantum processors. Poor performance of a noise-vulnerable device can result in the quantum processor producing an inaccurate or suboptimal solution to a problem (e.g., an inaccurate or suboptimal result of quantum annealing or gate model calculation). Note that the phrases “noise-vulnerable” and “vulnerable to noise” do not necessarily imply that the device itself is physically more or less sensitive to noise compared to other devices not described as noise-vulnerable. Instead, “noise vulnerability” is used to refer to the sensitivity of processor performance to noise within a given device. The sensitivity of processor performance to noise is higher in noise-vulnerable devices than in devices described as less noise-vulnerable or as “devices with low noise vulnerability.” Sources of noise in quantum processors can include, but are not limited to, magnetic flux noise, charge noise, magnetic fields, and high frequency photons.

[0051] Low-frequency magnetic flux noise is one example of noise that can cause problem misspecification in quantum processors and decoherence in qubits, both of which can result in quantum computing errors. Magnetic flux noise can degrade the performance of both quantum annealing and gate-model processors. Magnetic flux noise can originate in the materials that make up superconducting circuits; for example, magnetic flux noise can be intrinsic-to-microscopic stoquastic fluctuations of magnetic defects in the materials that make up quantum processors. These fluctuations can be driven by thermal and quantum fluctuations, and some magnetic flux noise can be independent of actions taken by the quantum processor.

[0052] However, flux noise can also be affected by actions taken by the quantum processor (such as performing operations involved in problem solving). For example, spin bath polarization resulting from quantum computations can manipulate the state of these magnetic defects and affect the subsequent operation of the quantum processor. Although spin bath polarization within a quantum processor decays over time, strong spin bath influences can provide flux noise that, if persisted between quantum computations, can cause problem misspecification.

[0053] Fabrication techniques can be beneficially applied to provide circuits with lower intrinsic magnetic flux noise. In gate-model processors, dynamic decoupling can be used in which pulse sequences reduce or reverse the effects of low-frequency magnetic flux noise. To significantly affect low-frequency magnetic flux noise, it may be beneficial to measure and compensate on time scales set by the spectrum of low-frequency magnetic flux noise fluctuations (which may be significantly shorter than 1 second) to achieve significant improvements.

[0054] U.S. Pat. No. 10,552,755 describes one method of reducing flux noise by repeatedly measuring the qubit offset and reprogramming the qubit flux bias DAC to compensate for the measured flux. This compensation method is limited by the repetition rate because the flux offset changes over time, and significant processor time is required to read the qubit and then reprogram the flux bias DAC. Because occupying the quantum processor to perform this compensation reduces the time available for quantum computation, reducing the time used in compensation is beneficial. However, lower repetition rates provide poorer compensation for flux noise due to noise variations over time. As discussed in U.S. Pat. No. 10,552,755, on-chip flux noise has an inherent time correlation, and it is necessary to estimate the most likely flux offset within a given qubit at a given time based on the time elapsed since the measurement was taken. A model characterizing the relationship between the population of qubit states and the control parameter offset can be formed by a hyperbolic tangent function determined by the Boltzmann distribution, parameterized by a width related to the qubit energy scale and physical temperature. This solution requires intermittent measurements and predictive estimation of the magnetic flux over time between measurements to apply to the qubit during problem solving. Furthermore, static shims can only significantly reduce these offsets for a short time after compensation because the magnetic flux noise occurs in a stoichiometric manner.

[0055] Provided herein is an on-chip device for capturing qubit flux offset information and compensating for those offsets without taking the information off-chip or reprogramming the qubit flux bias DAC. This can advantageously allow for faster and therefore more effective compensation of these flux biases. Providing an on-chip device advantageously allows for more frequent measurements because it is not required to perform readouts on one or more devices in a room temperature environment. In the circuits described below, the direction of the flux bias determines the direction of flux loading into the storage loop based on circuit parameters, and the flux loading is self-limiting in response to compensation for flux noise. No signal is required from a device located in a room temperature environment to provide the direction of flux loading based on a room temperature readout.

[0056] 4 is an exemplary implementation of a circuit 400 forming part of a quantum processor, which may form part of, for example, analog computer 104 or quantum processor 200 of FIG. 1 . Circuit 400 provides on-chip flux noise compensation for each qubit. A portion of qubit 402, which may be one of qubits 201, 202, 300 discussed with respect to FIGS. 2 and 3 or another type of flux qubit as known in the art, is communicatively coupled to flux compensation circuit 404. The portion of qubit 402 represents the length of the body of qubit 201, 202, or 300, and has additional structure not shown, such as Josephson junctions, interfaces with control devices, and interfaces with couplers. In the exemplary implementation of FIG. 2 , the portion of qubit 402 may be the length of the body loop of qubit 201 that is not in communication with other devices, such as coupler 210 or readout device 251. Flux compensation circuit 404 includes a quantum flux parametron (QFP) flux pump circuit 434 and a storage circuit 436. QFP flux pump circuit 434 includes a first QFP 406 communicatively coupled to qubit 402. In the example implementation of FIG. 4 , first QFP 406 is inductively coupled to qubit 402 at interface 412. In other implementations, the coupling between first QFP 406 and qubit 402 may be galvanic, and first QFP 406 and qubit 402 may share an inductor, or the coupling between first QFP 406 and qubit 402 may be a combination of partially galvanic and partially inductive. QFP devices can be used to replicate qubit states for readout as well as for replicating states for programming and other applications. QFP devices such as QFP shift registers are further described in U.S. Pat. No. 10,528,886 and International (PCT) Patent Application No. WO2022155140.

[0057] The first QFP 406 has a first Josephson junction 408 in communication with a first control line 410. As used herein, "in communication" refers to electrical communication or coupling. In the example implementations of FIGS. 4 and 6A-6K, "in communication" refers to inductive coupling. However, it will be understood that in other implementations, capacitive, galvanic, or other known communication coupling types may be used. In the example implementation of FIG. 4, the first Josephson junction 408 is a compound Josephson junction (CJJ) and may also be referred to as the "first CJJ 408." In other implementations, the first CJJ 408 may be a compound-compound Josephson junction (CCJJ). As used herein, a compound-compound Josephson junction (CCJJ) refers to a Josephson junction in which one or more of the junctions in the compound Josephson junction are themselves compound Josephson junctions. It will be understood that all of the Josephson junctions discussed below can be single Josephson junctions, compound Josephson junctions, or compound-compound Josephson junctions.

[0058] In the exemplary implementation of FIG. 4 , first control line 410 is inductively coupled to first CJJ 408. QFP flux pump circuit 434 is electrically coupled in series with a storage circuit 436 having second Josephson junction 430 and storage loop 428. Second Josephson junction 430 may also be a CJJ or CCJJ and may also be referred to as “second CJJ 430.” Communication between QFP flux pump circuit 434 and storage loop 428 is mediated by second CJJ 430. Second control line 432 is in communication with second CJJ 430. As discussed in more detail below, storage loop 428 is communicatively coupled to qubit 402 such that, in use, magnetic flux stored in storage loop 428 acts on qubit 402 to cancel at least a portion of the magnetic flux noise acting on qubit 402. The storage loop 428 counteracts through the flux pump circuit 434, and a counteracting current induced by the magnetic flux in the storage loop 428 will flow in the opposite direction of the magnetic flux bias on the qubit due to magnetic flux noise. In this exemplary implementation, the storage loop 428 is communicatively coupled to the qubit 402 through the first QFP 406. However, in other implementations, the storage loop 428 may be directly inductively coupled to the qubit 402. In some implementations, the storage loop 428 may be formed from a high kinetic inductance material. In some implementations, the entire length of the storage loop 428 may be formed from a high kinetic inductance material. In other implementations, only the inductor portion of the storage loop 428 may be a high kinetic inductor material.

[0059] While the inductor is depicted as a discrete structure in the exemplary implementation of FIG. 4 , it will be understood that the inductor may also be part of the storage loop 428 where coupling occurs and therefore may not be a discrete structure. In other implementations, the storage circuit 436, including the second CJJ 430, may be formed entirely of a high-dynamic inductance material. In the exemplary implementation of FIG. 4 , the second QFP 414 is electrically coupled in series to the first QFP 406. The superconducting loops of the first QFP 406 and the second QFP 414 are electrically coupled by the inductor 416. While the inductor is depicted as a discrete structure in the exemplary implementation of FIG. 4 , it will be understood that the coupling may occur in a portion of the qubit or QFP body, designated only by being where the coupling occurs, and may not be a separate structure. The second QFP 414 has a third Josephson junction 418 (which may be a CJJ or a CCJJ and may also be referred to as the "third CJJ 418") in communication with a third control line 420. The third QFP 422 is serially coupled to the second QFP loop 414. The superconducting loops of the second QFP 414 and the third QFP 422 are coupled by a fourth Josephson junction 424 (which may be a CJJ or a CCJJ and may also be referred to as the "fourth CJJ 424") in communication with a fourth control line 426. The third QFP 422 is serially coupled to a storage circuit 436 by a second CJJ 430 in communication with a second control line 432, as discussed above. 4 has three QFPs (406, 414, 422) in series, it will be understood that the number of QFPs in QFP flux pump circuit 434 can be varied so long as the relationship between the direction of the flux stored in storage loop 428 and the flux noise in qubit 402 is maintained. In addition, the duplication of states from first QFP 406 into second QFP 414, discussed in more detail below, beneficially provides at least partial isolation between the rest of the circuit and qubit 402. Furthermore, this duplication allows for the evolution of circuit parameters that are favorable to the operation of circuit 400.

[0060] Two implementations of exemplary parameter values ​​for circuit 400 are provided below. It will be understood that the parameter values ​​provided are only examples, and therefore other parameter values ​​can be used depending on the requirements of the circuit. In the table below, the parameter values ​​for the QFP Josephson junction are represented as the number "2x" because the given value is for each junction of the two-junction compound Josephson junction (CJJ). The storage inductance value provided by storage loop 428 is significantly larger than the other inductance values ​​in circuit 400. This larger storage inductance value can be provided by a high-dynamic inductance material.

[0061] [Table 1]

[0062] FIG. 5 provides an example time series plot 500 of signals that may be applied to circuit 600 (discussed below) to achieve a reduction in flux bias in qubit 602. The signals may be applied, for example, to control lines similar to control lines 221 and 222 in FIG. 2 and may be provided by a control system similar to control systems 128, 130, and 132 in FIG. 1. The signals shown provide relative amplitudes and, while unitless in this example, may be provided, for example, in terms of relative flux quanta. Legend 502 provides the correspondence between signals, control lines, and qubits shown in FIGS. 6A-6K (i.e., control lines 610, 620, 626, and 632, and qubit 602). Time is shown in integer increments. It will be understood that this may relate to a time value (e.g., a number of nanoseconds), or that the time step may not be an integer number of times, but rather may be some preferred time interval. The increments provided are also an example, and thus the intervals between signal changes need not be spaced as shown. The sequence of signals will be explained in more detail below with reference to Figures 6A-6K.

[0063] FIG. 6A shows circuit 600a at time t=0 in time series plot 500, with no signals applied. Circuit 600a has a portion of qubit 602 coupled to flux compensation circuit 604. In FIGS. 6A-6K, discussed below, open circles represent inactive CJJs, while filled circles represent CJJs activated by their respective signal lines. Throughout FIGS. 6A-6K, similar reference numbers as used in FIG. 4 are used for similar components (e.g., qubits 402 and 602), and similar values ​​as provided in exemplary implementations 1 and 2 discussed above may apply to elements of FIGS. 6A-6K. At t=0, no signals are applied to qubit 602 or via control lines (610, 620, 626, 632), and all CJJs (608, 618, 624, 630) are in a "low" state. The values ​​at nodes (634, 636, 638, 640, 642, 644, 646) are also zero. In the following discussion, the units of the values ​​at nodes (634, 636, 638, 640, 642, 644, 646) will be given in flux quanta. These numbers represent the phase at various points in the circuit in the exemplary implementation being discussed and can be multiplied by 2π to convert to phase units. For example, if the difference in value between two nodes is 0.5, this means a π phase difference between those nodes.

[0064] FIG. 6B shows circuit 600b at time t=1, when a signal is provided by qubit 602. Qubit 602 is annealed in the presence of magnetic flux noise such that the state of the qubit after annealing is statistically determined by the magnetic flux noise. The resulting qubit state (which may be represented by labels such as "spin up" or "spin down," or by a "0" or a "1") provides information about the direction of the magnetic flux noise. For example, in the presence of magnetic flux noise that biases the qubit toward a "spin up" state, the qubit will be found in that "spin up" state more frequently upon annealing, thus providing information about the current state of the qubit (i.e., a 1-bit of information). To counteract the effects of this magnetic flux noise, magnetic flux is loaded into the storage loop to counteract the qubit to reduce the bias. Qubit 602 is inductively coupled to first QFP 606 via interface 612. The current in qubit 602 induces a bias in first QFP 606. 6B shows arrows indicating the direction of this induced current. It will be understood that the direction of these arrows would be reversed if the state of qubit 602 were reversed. In example implementation 1 outlined above, when a 10 mPhi0 bias is applied by qubit 602, the induced current through first CJJ 608 and inductance 616 is 0.1 μA, and the relative flux quanta at nodes 634, 636, and 638 are 0.01, while the relative flux quanta at nodes 640, 642, 644, and 646 are 0.0. The flux quantum at node 646 remains zero throughout the processes described below and is therefore not called out in the examples.

[0065] FIG. 6C shows circuit 600c at time t=2, when a signal is applied via signal line 610 in communication with the first CJJ 608, placing the CJJ 608 in a “high” state (one flux quantum). This latches the first QFP 606, causing it to enter a circulating current state. This reverses the direction of the current in the first QFP 606 and generates a current in the second QFP 614. Although the signal from the qubit 602 may be small, this coupling action amplifies the current. In exemplary implementation 1, the current through the first CJJ 608 is 5.3 μA, and the current through the inductance 616 is 4.1 μA. The current through the second CJJ 618 is 1.2 μA, the current through the third CJJ 624 is 1.0 μA, and the current through the fourth CJJ 630 is 0.2 μA. The relative flux quantum at each of nodes 634, 636, 638, 640, 642 and 644 is measured to be -0.3.

[0066] In example implementation 1, in addition to the first QFP 606, the flux compensation circuit 604 also has a series-coupled second QFP 614 and a third QFP 622. As discussed above, the coupled signal from the qubit 602 into the first QFP 606 generates a current in the second QFP 614.

[0067] Providing a QFP flux pump circuit with multiple QFPs coupled in series beneficially amplifies the signal from the qubit 602. While it would be desirable to eliminate the flux offset in the first QFP 606 so that the process starts with zero flux bias in all components of the flux compensation circuit 604, in practical implementations, some non-zero offset may be present from stray fields, junction asymmetry, and other similar factors. The replication of states into each successive QFP loop becomes more robust due to the amplification. The state replicated into each QFP will oppose the direction of current flow in the CJJ before the QFP is latched. An odd number of QFP loops results in the final state replicated into the storage loop being in the opposite direction relative to the qubit, so that the counter-acting flux through the QFP circuit or direct coupling of the storage loop to the qubit relieves at least a portion of the flux bias on the qubit. Prior to latching the CJJ, the energetically favorable state (i.e., the lowest energy state) is where the phase difference across the junction is zero. When the junction is latched, the energetically favorable state is where the phase difference is π. By passing a directional current through the QFP flux pump circuit, the phase difference is established and ultimately stored in the storage inductance in a way that counteracts the qubit and cancels at least a portion of the flux noise.

[0068] In the exemplary implementations of FIGS. 4 and 6A-K, where communication between the storage loop and the qubit is mediated by QFP stages, the number of QFP stages will be set by the current direction relationship. In this case, more QFP stages may be added, but an odd number of QFP stages must be maintained, resulting in the need to add two stages at a time. That is, one aspect of designing multiple QFP loops and coupling configurations will be the requirement that the net back-action from the magnetic flux stored in the storage loop cancels the magnetic flux in the qubit rather than adding to it. This feedback needs to have the opposite sign to the noise or be in the opposite direction to the noise. The direction of the back-action will be determined by the number of replication operations and the configuration of the QFP loop. In some implementations where direct coupling is provided from the storage loop to the qubit rather than using back-action via a QFP stage, various numbers of QFPs may be included, and the sign relationship may be set based on the coupling to the qubit.

[0069] 6D shows circuit 600d at time t=3 when a signal is applied to control line 620 to cause CJJ 618 to go to a “high” state and latch the second QFP 614 into a circulating current state, replicating the state from the first QFP 606. This causes a reversal of the direction of the current in the second QFP 614 due to the sign of the coupling between the two QFPs (first QFP 606 and second QFP 614). In example implementation 1, the current through the first CJJ 608 is 4.2 μA, the current through inductance 616 is 8.2 μA, the current through the second CJJ 618 is 4.1 μA, the current through the third CJJ 624 is 3.5 μA, and the current through the fourth CJJ 630 is 0.6 μA. Measurements taken at the nodes within the flux quantum are: −0.4 at node 634, −0.2 at node 640, and 0.0 at the remaining nodes (636, 638, 642, 644, 646). The difference in flux between node 634 and node 640 provides the phase difference across inductance 616.

[0070] 6E shows circuit 600e at time t=4 when a signal is applied to control line 626 to cause third CJJ 624 to go to a “high” state and latch third QFP 622 into a circulating current state, replicating the state from second QFP 614. This causes a reversal of the direction of current in third QFP 622 and further amplification of the current. Third QFP 622 is defined by CJJ 624 and also communicates with fourth CJJ 630 of storage circuit 628. In exemplary implementation 1, the current through first CJJ 608 is 5.1 μA, the current through inductance 616 is 4.7 μA, the current through second CJJ 618 is 0.4 μA, the current through third CJJ 624 is 14 μA, and the current through fourth CJJ 630 is 13.6 μA. Measurements taken at the nodes within the flux quantum are: −0.4 at node 634, 0.2 at node 636, 0.2 at node 638, −0.2 at node 640, −0.3 at node 642, and 0.1 at node 644. This provides a π phase difference across CJJ 624.

[0071] 6F shows circuit 600f at time t=5 when a signal is applied to control line 632 to cause fourth CJJ 630 to go to a “high” state and latch storage circuit 628 into a circulating current state, replicating the state from third QFP 622. This again causes a reversal of the direction of current in storage circuit 628. In example implementation 1, the current through first CJJ 608 is 5.3 μA, the current through inductance 616 is 4.1 μA, the current through second CJJ 618 is 1.2 μA, the current through third CJJ 624 is 1.2 μA, and the current through fourth CJJ 630 is 0.2 μA. Measurements taken at nodes within the flux quantum are: −0.3 at node 634, 0.2 at node 636, 0.2 at node 638, −0.3 at node 640, −0.3 at node 642, and −0.3 at node 644. The difference in flux quantum between the top and bottom of the fourth CJJ 630 is 0.5 flux quanta, or in phase units, this provides a π phase difference across the fourth CJJ 630, and the flux quantum will be replicated into the storage inductance of the storage circuit 628.

[0072] FIG. 6G shows the circuit 600g at time t=6. The state of the first QFP 606 is the same as it was at t=2, with a current flowing in the opposite direction to that induced by qubit 602. This can be used to provide an additional flux quantum to the storage circuit 628. Thus, by repeating a similar process, another flux quantum can be replicated from the first QFP 606. At t=6, the signal from control line 620 is removed, forcing the second CJJ 618 to a "low" state and reversing the direction of the current through the second QFP 614. Removing the latch bias changes the current direction and also increases the current amplitude. In example implementation 1, the current through the first CJJ 608 is 4.2 μA, the current through the inductance 616 is 8.2 μA, the current through the second CJJ 618 is 4.1 μA, the current through the third CJJ 624 is 3.5 μA, and the current through the fourth CJJ 630 is 0.5 μA. Measurements taken at nodes within the flux quantum are as follows: −0.4 at node 634, 0.5 at node 636, 0.5 at node 638, −0.2 at node 640, 0.0 at node 642, and 0.0 at node 644.

[0073] 6H shows circuit 600h at time t=8, where the latch is removed from the third QFP 622 by removing the signal from the third CJJ 624. Removing the latch from the third QFP 622 increases the phase difference across the fourth CJJ 630. In example implementation 1, the current through the first CJJ 608 is 5.1 μA, the current through the inductance 616 is 4.7 μA, the current through the second CJJ 618 is 0.4 μA, the current through the third CJJ 624 is 13.8 μA, and the current through the fourth CJJ 630 is 13.3 μA. Measurements taken at nodes within the flux quantum are: −0.3 at node 634, 0.7 at node 636, 0.7 at node 638, −0.2 at node 640, −0.3 at node 642, and 0.1 at node 644. The difference across the fourth CJJ 630 in this exemplary implementation has now increased from 0.5 to 0.6 flux quanta.

[0074] FIG. 6I shows circuit 600i at time t=11, where the signal to the fourth CJJ 630 is lowered and the latch is removed from the storage circuit 628. This increases the phase difference across the fourth CJJ 630 relative to FIG. 6H. In exemplary implementation 1, the current through the first CJJ 608 is 5.3 μA, the current through the inductance 616 is 4.1 μA, the current through the second CJJ 618 is 1.2 μA, the current through the third CJJ 624 is 1.0 μA, and the current through the fourth CJJ 630 is 0.3 μA. Measurements taken at nodes within the flux quantum are as follows: −0.3 at node 634, 0.7 at node 636, 0.7 at node 638, −0.3 at node 640, −0.3 at node 642, and −0.3 at node 644. The difference across the fourth CJJ 630 in this exemplary implementation has now increased from 0.6 to 1.0 flux quanta so that the magnetic flux is now stored in the storage inductance of the storage circuit 628 .

[0075] FIG. 6J shows circuit 600j at time t=14, where the feedback circuit has gone to a quiescent state. The signal to the first CJJ 608 has been removed, and the latch on the first QFP 606 has been removed. In exemplary implementation 1, the current through the first CJJ 608 is 0.0 μA, the current through the inductance 616 is 0.0 μA, the current through the second CJJ 618 is 0.0 μA, the current through the third CJJ 624 is 0.0 μA, and the current through the fourth CJJ 630 is 0.1 μA. Measurements taken at nodes within the flux quantum are as follows: 0.0 at node 634, 1.0 at node 636, 1.0 at node 638, 0.0 at node 640, 0.0 at node 642, and 0.0 at node 644. One flux quantum is now stored in storage circuit 628.

[0076] The high phase nodes 636 and 638 are effectively isolated from the rest of the circuit by either the CJJ or the inductance in each direction. This blocks the high phase nodes from the low phase side of the circuit. The current through the inductors is proportional to the phase difference and inversely proportional to the inductance. Because the current is sinusoidal in phase with respect to the CJJ, for each integer multiple of 2π (or one flux quantum), the phase difference across the CJJ has no effect on the current. That is, the periodicity of the junction allows for isolation of the high phase nodes. Note that in the above discussion, various numbers of QFPs can be used. If the third QFP 622, and especially the third CJJ 624, were removed from circuits 600a-600k, the high phase nodes would still be isolated by the second CJJ 618 and the fourth CJJ 630.

[0077] 6K shows circuit 600k at time t=28, where the second cycle has been performed as described above. In exemplary implementation 1, this results in the following: the flux quanta at nodes 636 and 638 increase to 2.0, and the current through fourth CJJ 630 increases to 0.2, while the flux quanta in the rest of circuit 600k remain at 0.0. The flux stored in storage circuit (e.g., loop) 628 can cause the CJJ biases of all of the loops in QFPs 606, 614, and 622 to be zero, effectively causing the loops in QFPs 606, 614, and 622 to act like couplers, coupling the flux stored in the loops in storage circuit 628 back to qubit 602 (but in the opposite direction to the original state of qubit 602). This reverse action results in cancellation of at least a portion of the flux noise acting on qubit 602.

[0078] 7 shows an example probability distribution for the state of a qubit, such as qubit 402 or 602, after being readout or detected. Graph 700 shows an ideal distribution 702 (dashed line) for an ideal qubit not experiencing any flux noise. If a first state of the qubit is represented by the value "0" and a second state of the qubit is represented by the value "1," the ideal qubit would have an equal probability of being found in either state, and therefore the probability distribution would be centered around the value "0.5," as shown in 704. In other implementations, such as when the qubit states are represented by "-1" and "1," the distribution would be centered around "0" in 704. In the presence of flux noise, this probability distribution will shift, and the qubit is more likely to be found in the 1 state than in other states. 7, the qubit is biased to be more likely to be in the "1" state than the "0" state (or the "1" state than the "-1" state), and the probability distribution 706 is centered around value 708. This shift is represented by distance 710.

[0079] In an exemplary implementation of a quantum annealing processor, such as quantum processor 126 or circuit 200, qubits can be annealed to determine their state and provide this probability distribution. During the first anneal, in the presence of magnetic flux noise creating distance 710, the qubit is more likely to be found in the “1” state. A qubit in the “1” state will cause a magnetic flux load into the active noise compensation circuit (e.g., circuits 400 and 600a-600k). During subsequent anneals of the qubit, the distribution will shift toward the ideal distribution thanks to compensation from the active noise compensation circuit. However, the qubit is still more likely to be found in the “1” state, and the magnetic flux will be loaded in the same direction as after the first anneal, providing a larger compensation signal from the active noise compensation circuit and shifting the distribution closer to the ideal distribution. Over many anneals, the magnetic flux loaded into the active noise compensation circuit will bring the qubit's actual distribution into alignment with the ideal distribution. At this stage, the qubit is equally likely to be found in the "0" state or the "1" state, and no further flux is applied to the active noise compensation circuit. That is, it is equally likely that flux is applied in the first direction or the second direction during each iteration, resulting in a net zero change. As each cycle adds a positive or negative flux quantum, the feedback flux from the storage loop will fluctuate because the loading described above is a stoichiometric process. However, on average, if the flux noise changes, the active noise compensation circuit will load to reduce any imbalance in the population of qubits.

[0080] For ambient flux noise to determine the direction of current, the qubit must be isolated from the source of flux bias provided by the processor, allowing the flux noise to determine the qubit's state. In an exemplary implementation of a quantum annealing processor, qubits can be annealed at nominally zero flux by deactivating a control line. The qubit anneal line can be activated for a given qubit while other qubits in the processor are held at a suppressed point. In other implementations, it may be sufficient to suppress only neighboring qubits. In some implementations, anneal lines can be shared between non-neighboring qubits. A qubit can be suppressed by applying an anneal waveform to one shared qubit anneal line at a time while setting the other shared anneal lines to their suppressed values. This suppresses each qubit's neighbors from annealing. In this implementation, all qubits and flux compensation circuits associated with a given shared qubit anneal line can be operated simultaneously. The persistent current in a suppressed qubit becomes zero, effectively decoupling the qubit. This also eliminates the need for the coupler to be reprogrammed, since the coupler has no effect on the qubit when decoupled.

[0081] 8 is a flow diagram of an exemplary method 800 for correcting flux noise in a qubit that may be employed in accordance with the present systems, devices, and methods. In at least some implementations, method 800 may be performed on a hybrid computing system that includes at least one digital or classical processor and at least one quantum processor, such as computing system 100 that includes digital processor 106 and quantum processor 126. The digital or classical processor may provide control signals or instructions to the quantum processor to perform the method.

[0082] Although method 800 includes acts 802-810, one skilled in the art will understand that many of the acts shown are examples and that in some implementations, some acts may be omitted, other acts may be added, and / or the order of the acts may be changed.

[0083] At 802, information about the flux state of a qubit is projected into a quantum flux parametron (QFP) flux pump circuit. In some implementations, such as those using a quantum annealing processor, projecting information about the flux state of a qubit into a QFP flux pump circuit may involve annealing the qubit in the presence of ambient flux noise. For example, in a quantum processor with multiple qubits, information about the flux state of each qubit may be provided by annealing the qubits one by one via coupled CJJ control lines, such that as a given qubit is annealed, its neighboring qubits are suppressed. In addition, other sources of flux bias are deactivated so that it can be assumed that the flux within a given qubit is nominally zero, aside from compensated flux noise. Unlike when performing computations with a quantum processor, it is beneficial to set up the environment so that each qubit is effectively isolated.

[0084] In some implementations, a qubit may be exposed to a different flux offset during flux noise compensation (e.g., method 800) compared to the flux offset during problem solving. For example, crosstalk may occur within a quantum processor (between the qubit CJJ anneal lines (e.g., lines 221 in FIG. 2 ) and the qubit body). This crosstalk may provide a different flux offset during problem solving than during flux noise compensation because some of the CJJ anneal lines will be suppressed during flux noise compensation as described above. Compensation devices may be coupled to ensure that flux noise compensation occurs due to flux noise rather than a combination of flux noise and flux offset within the processor, which may be achieved by providing the ability to null out qubit flux offset shifts present during flux noise compensation to ensure that flux compensation circuits (such as flux compensation circuits 404 and 604 discussed above) are acting on pure flux noise. Additional compensation devices may be provided, for example, on a per-qubit basis to account for this flux offset. U.S. Patent No. 9,015,215 describes several examples of persistent current compensation devices that provide per-qubit programmable h-bias. Similar devices can be used to provide per-qubit flux offset compensation. For example, a similar compensation device can be provided for each qubit, and a global shared analog control line can be coupled to the compensation devices. Each compensation device can be coupled to a qubit by a per-qubit tunable coupling to provide per-qubit flux offset compensation.

[0085] As discussed above with respect to FIG. 2, in a quantum annealing processor, bias lines are provided to generate the h and J values ​​of a quantum Hamiltonian. Referring to FIG. 2, to isolate a qubit, such as qubit 201, it is beneficial to zero out a global waveform provided by the Hamiltonian and defined throughout the processor. The waveform providing the h bias of the Hamiltonian is generated through one or more analog lines, and these lines can be turned off. For example, in FIG. 2, bias line 222, which provides the h bias, can be turned off, and bias line 223 can be turned off. This effectively isolates qubit 201 from qubit 202 (and any other qubits on the processor). Furthermore, this means that couplers, such as coupler 210, do not need to be turned off or reprogrammed. That is, bias line 225, which provides the J value, does not need to be changed. In some implementations, coupler CJJ can be biased by a combination of analog control lines and a coupler flux DAC. Reprogramming the coupler can involve changing the state of the DAC. It may be beneficial to maintain both the state of the coupler DAC and the bias contributions provided by the coupler analog lines. These contributions may shift the qubit offsets, and therefore it may be beneficial to correct for qubit flux noise in the presence of these offsets as they will be present during problem solving. In some implementations, analog control lines may be shared between some or all of the couplers, and the bias required to suppress the couplers may vary from coupler to coupler, necessitating DAC reprogramming. As discussed above, the methods described herein advantageously enable flux noise compensation within individual qubits without reprogramming the couplers. Annealing can then be performed on a per-qubit basis (or per set of qubit biases if the lines are shared as discussed above) by using one qubit CJJ line at a time, such as line 221 in FIG. 2 .

[0086] In other implementations, the systems, methods, and devices described herein may be used for gate-model quantum computing. In those implementations, the gate-model qubit may be measured by a similar annealing process or by other compatible measurement processes. In one exemplary embodiment, projecting information about the flux state of a qubit into a QFP flux-pump circuit may involve annealing a first QFP while the first QFP is in communication with a gate-model qubit. Annealing the first QFP causes the first QFP to reflect the state of a coupled qubit without directly annealing the qubit. The first QFP may be coupled to detect the flux state of the qubit, and upon annealing, adopts a state that reflects the flux state of the qubit, thereby providing information about the flux bias on the qubit itself. In some examples, such as gate-model flux qubits, projecting information about the flux state of a qubit into a QFP flux-pump circuit may involve annealing a first QFP in communication with the qubit in the presence of ambient flux noise. In some examples, this may include deactivating a bias device in communication with the qubit to isolate the qubit prior to projecting information about the flux state of the qubit.

[0087] In some implementations, the flux compensation circuits described herein can also be coupled to couplers, such as coupler 210 in FIG. 2, to compensate for flux noise in the coupler. Couplers can also experience flux noise, which can affect the coupled qubit. In the systems, methods, and devices described herein, flux noise acting on the coupler and therefore on the qubit will be compensated for by the flux compensation circuit coupled to the qubit because the coupler is active during compensation. However, flux noise in the coupler can also be compensated for directly. Couplers can be annealed with analog lines coupled to the coupler Josephson junctions. In some systems, couplers can be designed with CCJJs, and these couplers can be directly compensated for by the flux compensation circuit. However, as discussed above, the effect of coupler flux noise on the qubit can be compensated for via the qubit flux compensation circuit.

[0088] At 804, information about the qubit's flux state is replicated as a directional current through the QFP flux pump circuitry. In some implementations, such as the example implementation of FIG. 4, replicating information about the qubit's flux state as a directional current through the QFP flux pump circuitry may include the acts outlined above with respect to FIGS. 6A-6K. These acts may include inducing a current into a first QFP including a first Josephson junction based on the projected information about the flux state, activating the first Josephson junction to latch the first QFP, inducing a current into a second QFP including a second Josephson junction based on the current in the latched first QFP, and activating the second Josephson junction to latch the second QFP. These acts may further include inducing a current into a third QFP including a third Josephson junction based on the current in the latched second QFP, and activating the third Josephson junction to latch the third QFP.

[0089] At 806, a Josephson junction coupled in series with the QFP flux pump circuit is activated to store magnetic flux in a storage loop connected to the Josephson junction based on a directional current.

[0090] At 808, an exit condition is evaluated. If the exit condition is satisfied, control proceeds to act 810. If the exit condition is not satisfied, control returns to act 802, and acts 802 through 808 are repeated iteratively until the exit condition is satisfied. In some implementations, the exit condition can be the number of iterations of performing acts 802 through 808. In other implementations, the exit condition can be based on measurements of flux noise in the qubit or on the direction of the flux added to the QFP flux pump circuitry at each stage. If the direction of the added flux has approximately equal probability of being one way or the other, the qubit is likely sufficiently compensated.

[0091] At 810, the flux stored in the storage loop is communicated to the qubit to reduce the flux state of the qubit. As discussed above, in the example implementations of Figures 4 and 6A-K, the state stored in the storage loop may be coupled to the qubit via a quiescent state QFP flux pump circuit to compensate for flux noise acting on the qubit.

[0092] After 810, the method 800 ends, for example, until invoked again.

[0093] In some implementations, such as when a quantum processor includes multiple qubits, method 800 may be repeated sequentially for each qubit in the quantum processor to correct for flux noise throughout the quantum processor. In other implementations, such as when several sets of qubits in different neighborhoods (i.e., no two qubits in a set are connected by a coupler) share a control line, method 800 may be performed simultaneously for a first set of qubits and then repeated sequentially for each set of qubits. All of the qubits in each set of qubits share an annealing control line (such as anneal line 221 in FIG. 2 ) and are in different neighborhoods. When method 800 is performed for one set of qubits, all other sets of qubits are suppressed as discussed above. Once all of the qubits have been corrected, the processor may be used for problem solving. It may be beneficial to repeat the method for all qubits between each problem to be solved or at set intervals to compensate for changes in flux noise. Method 800 may be performed for each qubit anneal line in a quantum processor between each problem anneal. After each qubit is corrected, the processor may be used to solve the quantum annealing problem. Performing flux noise compensation prior to each anneal may beneficially reduce flux bias drift on a per-qubit basis just before any anneal is performed.

[0094] It will be understood that performing method 800 by using one anneal line at a time can follow a wide variety of schedules. For example, method 800 can be performed such that acts 802-808 are repeated n times for all of the qubits on a first anneal line (such as anneal line 221 in FIG. 2 ) and then acts 802-808 are performed n times for all of the qubits on the next anneal line (until n cycles have been performed for all qubits on the processor). Alternatively, method 800 can be performed such that one cycle 802-808 is performed for all of the qubits on one anneal line, then one cycle is performed for all qubits on another anneal line, etc., until all of the qubits have performed one cycle, and then this can be repeated until n cycles 802-808 have been performed for all qubits on the processor. Typically, the same number, n, of cycles will be performed for each qubit, but it will be understood that the number of cycles can vary in some circumstances. For example, in some implementations, it may be known that more noise occurs consistently in a given region of a quantum processor, and therefore more cycles may be performed on the qubits in that region.

[0095] Acts 802 through 808 are performed iteratively to load enough flux quanta to correct for the flux noise in the qubit. The number of flux quanta that can be loaded into the storage loop determines the maximum value of the flux bias on the qubit that the correction circuit can correct. The target value can be determined by the typical flux bias value multiplied by a factor. Amplification of the current through the QFP flux pump circuit can favorably affect the number of flux quanta that can be loaded into the storage loop before the QFP flux pump circuit saturates. The step size (which determines the minimum change in flux bias that can be corrected) is determined by the change resulting from a single loaded flux quantum. It is also beneficial to perform these iterations rapidly to continuously update the qubit flux noise compensation as the flux bias on the qubit varies over time.

[0096] Thus, there are three parameters associated with the flux compensation circuit that must be balanced: step size, maximum value, and the rate at which acts 802-808 are cycled. The rate at which a given change in qubit flux can be corrected depends on the step size and the rate at which the cycle (acts 802-808) can be executed. A smaller step size will require more steps or iterations to correct a given change, but the size of the change that can be corrected will be more precise. That is, the minimum change in flux bias that can be corrected will be smaller with a smaller step size. A target value can be determined by estimating the maximum change in flux bias that will not affect the results produced by the quantum processor during problem solving. To provide compensation for the flux noise of a given qubit, the sign or direction of the current flowing through the QFP is determined by the qubit state. However, eventually, the current flowing through the QFP will reach a maximum value for the circuit (where the back-action from the stored flux overcomes the bias from the qubit). This provides an upper bound on the amount of flux bias that can be corrected by a given circuit.

[0097] Generally, when replicating states between QFPs, the current flowing through the CJJ of a QFP can affect the accuracy of the state replication. The process of transferring signals as discussed above can amplify the signal through the QFP's latch, resulting in a more robust replication operation at each successive CJJ. After the process of replicating the first flux quantum through the QFP and into the storage inductance, successive flux quanta are loaded. As the number of flux quanta loaded into the storage inductance increases, these loaded flux quanta begin to counteract adjacent QFPs, reducing the current through the CJJ of the adjacent QFP. This process ultimately limits how much flux can be loaded into the storage inductance. Therefore, signal amplification to provide a large current is beneficial for providing a wide range of device operation.

[0098] The method 800 discussed above allows for compensation of flux noise in qubits to be performed entirely on-chip. That is, the state of the qubit does not need to be read out to a device at room temperature, nor is any other information required to pass from on-chip to a device at room temperature and back again. The qubit can be annealed, and the flux quanta copied into storage circuitry without the need for an external processor or user to observe the qubit state. Providing flux noise compensation without reading out any information to a device at room temperature advantageously allows flux noise compensation to be performed more quickly.

[0099] Described herein are error suppression techniques for reducing on-chip flux noise on a per-qubit basis. As used herein, "on-chip" refers to being part of the same processor as the qubits being compensated. A quantum processor typically includes not only qubits and couplers, but also control devices and other on-chip circuitry, as discussed with respect to FIG. 2 . The compensation circuitry described herein provides compensation for those qubits in situ or as part of the quantum processor. In particular, many quantum processors are maintained in isolated environments, such as cryogenic refrigerators, and on-chip flux noise compensation can occur without the need for information to be read out to a separate circuit or processor outside the isolated environment or at room temperature. On-chip circuitry is provided for capturing and aggregating information about qubit flux offsets due to noise and can be used to correct for the offsets. The above methods and devices may advantageously enable flux noise compensation without the need to bring information about qubit states off-chip or to reprogram on-chip DACs. This may advantageously enable faster and more effective compensation of low-frequency flux noise. Thus, reducing the flux noise present within each qubit can reduce problem misspecification and phase relaxation, improving the performance of quantum processors. Flux noise reduction can also ease the requirements for error correction mechanisms in gate-model quantum computing.

[0100] The methods, processes, or techniques described above may be implemented by a series of processor-readable instructions stored on one or more non-transitory processor-readable media. Some example methods, processes, or techniques described above are performed in part by a specialized device or system (e.g., a computer including at least one digital processor), such as an adiabatic quantum computer or quantum annealer, that programs or otherwise controls its operations. While the methods, processes, or techniques described above may include various acts, those skilled in the art will recognize that some acts may be omitted and / or additional acts may be added in alternative embodiments. Those skilled in the art will recognize that the depicted order of acts is for illustrative purposes only and may vary in alternative embodiments. Some of the example acts or operations of the methods, processes, or techniques described above are performed iteratively. Some of the methods, processes, or techniques described above may be performed during each iteration, after multiple iterations, or at the end of all iterations.

[0101] The above descriptions of illustrated implementations, including those described in the Summary of the Invention, are not intended to be exhaustive or to limit implementations to the precise forms disclosed. Specific implementations and examples are described herein for illustrative purposes; however, those skilled in the art will recognize that various equivalent modifications may be made without departing from the spirit and scope of the present disclosure. The teachings provided herein of various implementations do not necessarily apply to the exemplary method of quantum computing generally described above, but may also be applied to other methods of quantum computing.

[0102] The various implementations described above may be combined to provide further implementations. All commonly assigned U.S. patent application publications, U.S. patent applications, foreign patents, and foreign patent applications referenced herein and / or listed within the Application Data Sheets are hereby incorporated by reference in their entirety, including but not limited to the following patents: U.S. Patent No. 7,533,068; U.S. Patent No. 8,008,942; U.S. Patent No. 8,195,596; U.S. Patent No. 8,190,548; U.S. Patent No. 8,421,053; U.S. Patent No. 8,854,074; U.S. Patent No. 9,015,215; U.S. Patent No. 9,424,526; U.S. Patent No. 10,528,886; U.S. Patent No. 10,552,755. International (PCT) Patent Application No. WO2022155140. U.S. Provisional Patent Application No. 63 / 223,686.

[0103] These and other changes can be made to the above implementations in light of the above detailed description. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific implementations disclosed in the specification and claims, but should be construed to include all possible implementations, along with the full range of equivalents to which such claims are entitled. Accordingly, the scope of the claims is not limited by this disclosure.

Claims

1. a first qubit; and 1. A quantum processor comprising: a flux compensation circuit communicatively coupled to the first qubit, the flux compensation circuit comprising: a quantum flux parametron (QFP) flux pump circuit including a first QFP in communication with the first qubit, the first QFP including a first Josephson junction; a memory circuit including a second Josephson junction and a memory loop coupled in series with the QFP flux pump circuit, wherein communication between the QFP flux pump circuit and the memory loop is mediated by the second Josephson junction; a first control line in communication with the first Josephson junction; and a second control line in communication with the second Josephson junction; A quantum processor, wherein the storage loop is communicatively coupled to the first quantum bit such that, in use, magnetic flux stored in the storage loop acts against the first quantum bit.

2. The quantum processor of claim 1 , wherein the storage loop is communicatively coupled to the first qubit via the first QFP.

3. The quantum processor of claim 1 , wherein the first Josephson junction and the second Josephson junction each comprise a compound Josephson junction.

4. 2. The quantum processor of claim 1, wherein the QFP flux pump circuit includes a second QFP coupled in series with the first QFP, the second QFP including a third Josephson junction, and the first QFP and the second QFP connected by an inductor.

5. 5. The quantum processor of claim 4, wherein the QFP flux pump circuit includes a third QFP coupled in series with the second QFP, and the coupling between the second QFP and the third QFP is mediated by a fourth Josephson junction.

6. 6. The quantum processor of claim 5, further comprising a third control line in communication with the third Josephson junction and a fourth control line in communication with the fourth Josephson junction.

7. The quantum processor of claim 6 , wherein the third Josephson junction and the fourth Josephson junction each comprise a compound Josephson junction.

8. 10. The quantum processor of claim 1, wherein the quantum processor includes a set of qubits, the first qubit being one of the qubits of the set of qubits, and each qubit of the set of qubits being coupled to a respective flux compensation circuit.

9. The quantum processor of claim 1 , wherein the storage loop comprises a high kinetic inductance material.

10. 1. A flux compensation circuit including a quantum flux parametron (QFP) flux pump circuit, the quantum flux parametron (QFP) flux pump circuit comprising: a first QFP, the first QFP including a first Josephson junction; a second QFP connected in series with the first QFP, the second QFP including a third Josephson junction, the first QFP and the second QFP being connected by an inductor; a third QFP connected in series with the second QFP, the connection between the second QFP and the third QFP being mediated by a fourth Josephson junction; a storage circuit including a second Josephson junction and a storage loop connected in series with the QFP flux pump circuit, the connection between the QFP flux pump circuit and the storage loop being mediated by the second Josephson junction; a first control line in communication with the first Josephson junction; a second control line in communication with the second Josephson junction; a third control line in communication with the third Josephson junction; and a flux compensation circuit including a fourth control line in communication with the fourth Josephson junction;

11. 11. The flux compensation circuit of claim 10, wherein each of the first, second, third and fourth Josephson junctions comprises a compound Josephson junction.

12. The flux compensation circuit of claim 10 , wherein the storage loop comprises a high dynamic inductance material.

13. 1. A method of correcting flux noise in a qubit, comprising: projecting information about the flux state of the qubit into a quantum flux parametron (QFP) flux pump circuit; replicating the information regarding the flux state of the qubit as a directional current through the QFP flux pump circuit; activating a Josephson junction coupled in series with the QFP flux pump circuit to store magnetic flux in a storage loop connected to the Josephson junction based on the directional current; evaluating the exit condition; and transferring the magnetic flux stored in the storage loop to the qubit to reduce the magnetic flux state of the qubit; The method includes repeatedly performing the steps.

14. 14. The method of claim 13, wherein projecting information about the flux state of the qubit into a QFP flux pump circuit comprises annealing the qubit in the presence of ambient flux noise.

15. 14. The method of claim 13, wherein projecting information about the flux state of the qubit into the QFP flux pump circuit comprises annealing a first QFP in communication with the qubit in the presence of ambient flux noise.

16. Replicating information about the flux state of the qubit as a directional current through the QFP flux pump circuit includes: inducing a current in a first QFP including a first Josephson junction based on the projected information regarding the magnetic flux state; activating the first Josephson junction to latch the first QFP; inducing a current in a second QFP including a second Josephson junction based on the current in the latched first QFP; and activating the second Josephson junction to latch the second QFP.

14. The method of claim 13, comprising:

17. Replicating information about the flux state of the qubit as a directional current through the QFP flux pump circuit further includes: inducing a current in a third QFP including a third Josephson junction based on the current in the latched second QFP; and activating the third Josephson junction to latch the third QFP; 17. The method of claim 16, comprising:

18. 14. The method of claim 13, wherein evaluating the exit condition comprises incrementing a counter until a fixed number of iterations have occurred.

19. 14. The method of claim 13, further comprising deactivating a bias device in communication with the qubit to isolate the qubit prior to projecting information about the flux state of the qubit.

20. 20. A method of correcting flux noise in a quantum processor comprising a plurality of qubits, comprising performing the method of any one of claims 13 to 19 for each qubit in the quantum processor.

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