Parallel processing for three-dimensional semiconductor manufacturing

Abstract

Described herein are various techniques for electrochemical etching of semiconductors controlled by lasers that emit light having an energy lower than the bandgap energy of the semiconductor.

Description

[Technical Field]

[0001] TECHNICAL FIELD This disclosure relates to semiconductor manufacturing through the use of lasers. [Background technology]

[0002] Microfabrication refers to various techniques used to manufacture integrated circuits (ICs) and microelectromechanical systems (MEMS). ICs and MEMS manufactured by conventional microfabrication techniques have feature sizes on the order of microns or nanometers. Traditionally, microfabrication of ICs and MEMS is a layer-by-layer process in which layers of semiconductors (and various other materials) are deposited, patterned using lithography tools, and then etched to define portions of the final shape. Generally, these conventional microfabrication techniques are limited to creating structures with shapes similar to two-dimensional extruded shapes, sometimes referred to as 2.5D.

[0003] Furthermore, these conventional microfabrication techniques are complex, time-consuming, and costly. In one example, fabrication of one layer of a device may include the steps of 1) depositing a thin film on a substrate or wafer, 2) coating the thin film with a photoresist masking layer, 3) photolithographically patterning the photoresist masking layer, 4) etching the thin film layer through the photoresist masking layer, 5) stripping the photoresist masking layer, and 6) thoroughly cleaning the substrate or wafer before similarly depositing and patterning subsequent layers. Summary of the Invention

[0004] The following is a brief summary of subject matter described in more detail herein. This summary is not intended to be limiting on the scope of the claims.

[0005] Described herein are various techniques related to the fabrication of structures in semiconductors by selective etching of the semiconductor. These techniques are suitable for fabricating various three-dimensional (3D) structures (e.g., three-dimensional voids) in semiconductors. Furthermore, these techniques are suitable for etching structures in semiconductors having smaller feature sizes than are typically possible with conventional selective etching techniques.

[0006] In various exemplary embodiments, a semiconductor is etched by an electrochemical reaction at the surface of the semiconductor exposed to an etchant solution. The exposed surface of the semiconductor is selectively etched based on the controlled generation of holes (i.e., the absence of electrons in the lattice, which are commonly modeled as positively charged particles called holes) in the atomic lattice of the semiconductor. In the etching reaction, the holes in the exposed surface of the semiconductor cause oxidation of the semiconductor, which is then etched by the etchant solution. The holes are selectively generated by irradiating the semiconductor with an illumination source (e.g., a laser) having energy lower than the bandgap energy of the semiconductor. A single photon below the bandgap energy does not have enough energy to move an electron in the semiconductor from the valence band to the conduction band. Therefore, light below the bandgap energy typically cannot create holes in the atomic lattice of the semiconductor. The light below the bandgap energy emitted by the illumination source is focused to a sufficiently strong focus to cause multiphoton absorption (MPA) in the semiconductor. When this occurs, the photon energies of multiple photons combine to exceed the bandgap energy of the semiconductor, exciting electrons from the valence band to the conduction band, thereby creating holes in the atomic lattice of the semiconductor at the focal point of the illumination source. By selectively creating holes in the region near the focal point of the illumination source where etching is desired to occur, etching can be limited to the region near the focal point.

[0007] The semiconductor is transparent to the light emitted by the illumination source because the light emitted is below the bandgap energy and does not undergo linear absorption. By moving the focal point of the illumination source within the semiconductor body, etching of the semiconductor can be selectively controlled to occur at locations that cannot be etched using conventional semiconductor etching methods. Thus, three-dimensional features that are not easily created using conventional microfabrication techniques can be etched into the semiconductor body. In an exemplary embodiment, the illumination source can be positioned facing a second surface (e.g., backside) of the semiconductor opposite the surface exposed to the etchant solution. In this embodiment, the illumination source emits light toward the second surface of the semiconductor, through the semiconductor, and to a focal point within the semiconductor body. Illuminating the semiconductor through the second surface opposite the etching surface avoids the possibility of scattering of the emitted light, which could cause undesired etching of the semiconductor or reduce the achievable resolution of the semiconductor features.

[0008] In another exemplary embodiment, the illumination source is controlled by a computing device incorporating a physical model of charge carrier transport within a semiconductor. Generally, holes generated at a first location within a semiconductor can move within the semiconductor due to various forces caused by electric fields, carrier diffusion, etc. Therefore, in some cases, holes generated at a first location within the semiconductor may move to a location within the semiconductor other than the desired location for etching. By incorporating a physical model of charge carrier transport, the computing device can control the illumination source so that holes are generated by radiation at a location where they will ultimately move to the desired etching location. As an example, the computing device is provided with a desired etching location within the semiconductor. The computing device outputs a prediction based on the physical model, indicating that holes generated at the first location are expected to move to the desired etching location. The physical model can output a prediction based on charge carrier diffusion within the semiconductor, an electric field applied to the semiconductor (e.g., by a bias voltage), and a current within an electrochemical cell driving the etching reaction. The computing device then controls the output of the illumination source to cause the illumination source to illuminate the semiconductor at a focal point of the illumination source at the first location predicted by the physical model.

[0009] The above summary presents a simplified overview to provide a basic understanding of some aspects of the systems and / or methods discussed herein. This summary is not an extensive overview of the systems and / or methods discussed herein. It is not intended to identify key / critical elements or to delineate the scope of such systems and / or methods. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later. [Brief explanation of the drawings]

[0010] [Figure 1]FIG. 1 is a diagram of an exemplary system that facilitates selective etching of semiconductors controlled by below-bandgap energy lasers. [Figure 2] 1 is a conceptual diagram of an MPA near the focal point of an illumination source below the bandgap energy. [Figure 3] 1 is a conceptual diagram of hole drift under the influence of an induced electric field. [Figure 4] FIG. 1 is a conceptual diagram illustrating the generation and movement of holes in a semiconductor. [Figure 5] FIG. 1 is a conceptual diagram illustrating the electric field concentration effect on the movement of holes in a semiconductor. [Figure 6] 1A-1C are diagrams of exemplary subsurface semiconductor etching. [Figure 7] FIG. 7 is a three-dimensional view of the subsurface semiconductor etch shown in FIG. 6. [Figure 8] FIG. 1 is a diagram of another exemplary system that facilitates selective etching of semiconductors controlled by lasers below multiple bandgap energies. [Figure 9] FIG. 1 is a diagram illustrating the generation of charge carriers in the overlap region of two laser beams. [Figure 10] FIG. 1 is a diagram of an exemplary series of illumination positions. [Figure 11] FIG. 1 is a diagram illustrating a dispersive and condensing system. [Figure 12] FIG. 1 is a flow diagram illustrating an exemplary method for sub-bandgap laser controlled selective semiconductor etching. [Figure 13] 1 is an exemplary computing system. DETAILED DESCRIPTION OF THE INVENTION

[0011] Various techniques relating to light-controlled selective semiconductor etching will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following specification, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. However, it will be apparent that such aspects may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate description of one or more aspects. Furthermore, it will be understood that functions described as being performed by a particular system component may be performed by multiple components. Similarly, for example, a component may be configured to perform functions described as being performed by multiple components.

[0012] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, the phrase "X uses A or B" is intended to mean any of the natural inclusive permutations. That is, the phrase "X uses A or B" is satisfied by any of the following examples: X uses A; X uses B; or X uses both A and B. Furthermore, the articles "a" and "an," as used in this application and the appended claims, should generally be construed to mean "one or more," unless otherwise specified or clear from the context that the singular form is intended.

[0013] Furthermore, as used herein, the terms "component" and "system" are intended to encompass computer-readable data storage configured with computer-executable instructions that, when executed by a processor, cause a particular function to be performed. The computer-executable instructions may include routines, functions, etc. It should also be understood that a component or system may be localized on a single device or distributed across several devices. Furthermore, as used herein, the term "exemplary" is intended to mean serving as an example or instance of something and is not intended to indicate preference.

[0014] As used herein, it should be understood that a "hole" in a semiconductor lattice refers to the absence of an electron at a location within the semiconductor lattice. While various actions and occurrences are referred to herein in relation to holes as tangible entities, it should be understood that such descriptions are intended merely to facilitate understanding of various aspects and may reflect some inaccuracy in the underlying physical processes. For example, while reference is made herein to an electric field exerting a force on holes, causing their movement, it should be understood that the electric field actually exerts a force on electrons in the semiconductor lattice, causing their movement, but that the results of such movement can be properly explained by conceptualizing the hole as a virtual particle. Such reference to holes is made for ease of understanding and is consistent with descriptions commonly used in the art of semiconductor fabrication.

[0015] Referring to FIG. 1 , an exemplary system 100 for facilitating selectively controlled semiconductor etching is shown. The system 100 includes an etching chamber 102, a laser 104, and a computing device 106 that controls the laser 104. The etching chamber 102 includes a semiconductor element 108 desired to be etched and an etching solution 110 that selectively oxidizes and etches the semiconductor 108 at locations where holes exist in the atomic lattice of the semiconductor 108. The laser 104 emits a light beam 109 at the semiconductor 108 based on a control signal received from the computing device 106 to generate holes in specific regions within the semiconductor 108. The semiconductor 108 is then etched by the etching solution 110 at locations where the generated holes migrate to a first surface 112 of the semiconductor 108 exposed to the etching solution 110. Thus, the laser 104 is controlled to etch the semiconductor 108 at the desired locations based on where the laser 104 generates holes within the semiconductor 108.

[0016] The composition of the etching solution 110 is selected based on the chemical makeup of the semiconductor 108. By way of example and not limitation, in applications where the semiconductor 108 includes silicon or other carbon-family elements (e.g., silicon, carbon, germanium, etc.), the etching solution 110 can include hydrofluoric acid (HF). For example, the etching solution 110 can be a 1% to 30% HF solution. In other embodiments, other chemicals that provide fluorine atoms for reaction, such as ammonium hydroxide / ammonium fluoride, can also be used. In various embodiments, the etching solution 110 can include a surfactant (e.g., ethanol, dimethylformamide, acetonitrile, etc.) that can promote wetting of the etching solution 110 to the surface 112 of the semiconductor 108 and facilitate removal of etching gases from the surface 112 of the semiconductor 108. In yet another example, the etching solution 110 can include at least one of sodium hydroxide, acetic acid, sulfuric acid, propionic acid, perchloric acid, potassium sulfate, or peroxydisulfuric acid. It should be understood that the methods and systems described herein are suitable for selectively etching a variety of semiconductors. In some exemplary embodiments, the semiconductor 108 comprises an intrinsic elemental semiconductor, such as silicon, carbon (diamond, graphene, carbon nanotubes, etc.), germanium, etc. In other exemplary embodiments, the semiconductor 108 comprises a III-V semiconductor (e.g., gallium arsenide, indium phosphide, etc.), a III nitride (e.g., gallium nitride, indium gallium nitride, etc.), a II-VI semiconductor (e.g., zinc oxide, cadmium telluride, etc.), or other semiconductor compounds (e.g., silicon carbide, silicon germanium, indium gallium arsenide, indium gallium phosphide, mercury cadmium telluride, etc.). The composition of the etching solution 110 can be selected to facilitate etching of the semiconductor to be desirably etched.

[0017] Various details regarding the construction and operation of system 100 will now be described with respect to selective etching of semiconductor elements 108. Etch chamber 102 includes a first containment vessel 114 and a second containment vessel 116. First containment vessel 114 contains an etching solution 110. The vessels 114, 116 are joined by a seal 118 (e.g., an O-ring if vessels 114, 116 are annular) that prevents escape of etching solution 110 from etching chamber 102. Semiconductor 108 is disposed within second containment vessel 116 such that a first surface 112 of semiconductor 108 is exposed to etching solution 110.

[0018] The system 100 further includes a voltage source 120 that establishes an electric field within the semiconductor 108 that promotes an etching reaction at the surface 112 of the semiconductor 108. The voltage source 120 is connected at its positive and negative terminals to an anode electrode 122 and a cathode electrode 124, respectively. The anode electrode 122 is disposed within the second containment vessel 116 in contact with a conductive material 126. The conductive material 126 contacts a second surface 128 of the semiconductor 108 opposite the surface 112 exposed to the etching solution 110. When a voltage is applied to the electrodes 122, 124 by the voltage source 120, an electric field is established within the semiconductor 108 that can be used to direct charge carriers to desired locations within the semiconductor 108. For example, the voltage source 120 can be controlled to establish an electric field within the semiconductor 108 that tends to move positive charge carriers, such as holes, toward the etching surface 112.

[0019] The second containment vessel 116 further includes a window 130 disposed on an outer surface 132 of the vessel 116 and extending through the surface 132 to face the backside 128 of the semiconductor 108 (i.e., the surface opposite the surface to be etched). The window 130 is transparent to the beam 109 emitted by the laser 104. The laser 104 is disposed facing the window 130 and emits the beam 109 through the window 130 toward the backside 128 of the semiconductor 108. The conductive material 126 is selected or configured to be transparent to the beam 109 of light emitted by the laser 104. By way of example and not limitation, the conductive material 126 may be salt water, an acid, a base, a transparent conductive oxide, an extremely thin metal film (e.g., 10-50 nm), a metal mesh, graphene, carbon nanotubes, a transparent conductive polymer, or the like. In another exemplary embodiment, the conductive material 126 may be a weak HF solution. When the etching solution 110 includes HF, using an HF solution as the conductive material 126 can suppress undesired reactions between the etching solution 110 and the conductive material 126 when they come into contact. The system 100 can further include a focusing system 134 (e.g., comprising an objective lens or a custom optical focusing element) that receives the beam 109 from the laser 104 and focuses the beam 109 through the window 130 to a focal point within the semiconductor element 108. Although the beam 109 is considered to become a converging cone after exiting the focusing system 134, for purposes of simplicity and explanation, the beam 109 (and in several subsequent figures) is shown as a straight beam until it reaches its focal point 144.

[0020] The computing device 106 comprises a processor 136, a memory 138 operatively connected to the processor 136, and a data storage unit 140 operatively connected to the processor 136. The memory 138 contains instructions that, when executed by the processor 136, cause the processor 136 to perform various functions. A process control component 142 controls various aspects of the process for selectively etching the semiconductor 108. For example, the process control component 142 controls the orientation and positioning of the laser 104 and / or the focusing system 134 with respect to irradiating specific locations within the semiconductor 108. Additionally, the process control component 142 can be configured to control other etching input variables, such as the intensity of the beam 109, the bias voltage applied by the voltage source 102, the temperature of the etching solution 110, etc.

[0021] The operation of the system 100 with respect to selective etching of the semiconductor 108 will now be described. Etching of the semiconductor 108 by the etching solution 110 occurs based on a series of chemical reactions that take place at the etching surface 112 of the semiconductor 108 in the presence of holes in the atomic lattice at the surface 112. For example, in an exemplary embodiment in which the semiconductor 108 comprises silicon and the etching solution 110 comprises hydrofluoric acid, the etching reaction is the following two-step electrochemical reaction:

[0022] Si+2F - +2h + →SiF2(1)

[0023] SiF2+2HF→SiF4+H2(2)

[0024] In the chemical reaction shown in Equation 1, positively charged holes on the surface of a silicon semiconductor promote a reaction between negatively charged fluorine ions and neutral silicon, producing SiF2 on the surface. The chemical reaction shown in Equation 2 is the etching reaction, in which an HF etching solution reacts with SiF2 to produce SiF4 and H2 gas. Therefore, the electrochemical etching reactions represented by Equations 1 and 2 can be controlled by controlling the amount and location of holes within the semiconductor. Where holes are present, etching can occur, and where holes are absent, etching does not occur. Alternative chemical reaction equations for silicon electrochemical etching of silicon with an intermediate silicon oxide stage have also been proposed. In general, the various proposed reaction equations and experimental results indicate that holes are necessary for etching to occur.

[0025] In the exemplary system 100, holes are generated by irradiating the semiconductor 108 with a laser 104. Because the electrochemical etching reaction between the etching solution 110 and the semiconductor 108 is facilitated by the presence of holes, etching of the semiconductor 108 can be controlled based on irradiating the semiconductor 108 with the laser 104. To generate holes in a semiconductor, electrons in the semiconductor lattice must be given sufficient energy to allow the electrons to cross the semiconductor's bandgap from the valence band to the conduction band. Therefore, holes have traditionally been generated in semiconductors using lasers whose photons each have an energy greater than the semiconductor's bandgap energy.

[0026] In contrast, laser 104 is a laser that emits light whose photon energy is less than the bandgap energy of semiconductor 108. Light below the bandgap energy is not normally absorbed by semiconductor 108, and therefore semiconductor 108 is typically transparent to beam 109 emitted by laser 104. Light collection system 134 is configured to focus beam 109 to a strong focal point 144 within semiconductor 108. Normally, light below the bandgap energy does not impart enough energy to electrons to free them from their positions in the semiconductor lattice (thereby creating holes); however, when light collection system 134 focuses the beam to strong focal point 144, MPA occurs, where multiple photons can impart energy to an electron substantially simultaneously. When an electron absorbs multiple photons, each with energy less than the bandgap energy, sufficient energy can be imparted to move the electron from the valence band to the conduction band, thereby creating holes.

[0027] By way of example, referring now to Figure 2, a conceptual diagram of the creation of holes in the atomic lattice of a semiconductor is shown. While certain aspects relating to electrons, photons, and holes are illustrated and described with respect to Figure 2, it should be understood that such aspects are intended only as conceptual illustrations to facilitate understanding of the underlying physical processes, and are not intended as entirely accurate depictions of subatomic physical processes. Figure 2 illustrates the creation of multiple electrons e - 2 shows a snapshot view of a semiconductor 200 containing electrons e - is constrained to lie in either the valence band of semiconductor 200 or the conduction band of semiconductor 200. Figure 2 further illustrates a beam of light 202 emitted, for example, by a laser. As shown in Figure 2, beam 202 includes multiple photons p, each photon p having an energy less than the band gap energy of semiconductor 200.

[0028] Initially, the beam 202 is not focused in region 204. In the unfocused region 204, the likelihood of two or more photons simultaneously energizing an electron is low, making it unlikely that the beam 202 will provide enough energy to the electron to cross the band gap from the valence band to the conduction band. The beam 202 then focuses to a focal point 206 within the semiconductor 200. At the focal point 206, the fluence (i.e., energy per unit area) of the beam 202 increases compared to the unfocused region 204. Thus, at the focal point 206, it is more likely that two or more photons will substantially simultaneously energize an electron. MPA occurs at the focal point 206 of the beam 202. For example, as shown in FIG. 2, two photons 208 and 210 simultaneously reach the electron 212. The photons 208 and 210 provide enough energy to displace the electron 212 from its position within the atomic lattice of the semiconductor 200, as indicated by the arrow extending from the electron 212. In contrast, at the snapshot in time shown in Figure 2, only a single photon 214 reaches another electron 216. Because photon p of beam 202 has energy below the band gap, the single photon 214 is insufficient to provide electron 216 with enough energy to displace it from its position in the lattice, so photon 214 is not absorbed and electron 216 remains in the valence band. - leaves its location in the semiconductor lattice, a positively charged hole h + For example, an electron 218 is shown moving away from its position in the lattice, while a hole 220 remains in its place.

[0029] 1 , the MPA of light below the bandgap energy of beam 109 causes electrons in the atomic lattice of semiconductor 108 at focal point 144 to create holes at focal point 144. The holes created at focal point 144 can migrate to etching surface 112, causing oxidation and subsequent etching of semiconductor 108 at the location of the holes at surface 112. By way of example, semiconductor 108 includes etched feature 146 that extends from surface 112 into semiconductor 108. As the holes created at focal point 144 migrate to bottom surface 148 of etched feature 146, etching solution 110 oxidizes and etches bottom surface 148 of feature 146, extending feature 146 further into the body of semiconductor 108.

[0030] The process control component 142 can control various parameters of the electrochemical etching of the semiconductor 108 by the etching solution 110 in the etching chamber 102 to facilitate etching of desired features. In one example, an electric field can be established and variably controlled to affect the size or shape of features etched into the semiconductor 108. In the system 100, the computing device 106 is in communication with the voltage source 120, and the process control system 142 is configured to control the output of the voltage source 120. The process control system 142 can control the voltage source 120 to establish an electric field within the semiconductor 108. The electric field can be maintained to sweep holes toward the etching surface 112, as described above. Establishing an electric field within the semiconductor 108 by the voltage source 120 facilitates selective etching of the surface 112 of the semiconductor 108 by directing the holes to desired locations within the semiconductor lattice. Various internal electric fields within the semiconductor 108 (not due to the voltage source 120) can exert forces on the holes in the semiconductor 108, causing semiconductor drift. Additionally, holes diffuse from regions of higher concentration to regions of lower concentration through the semiconductor 108. By using the voltage source 120 to establish an electric field within the semiconductor 108, the effect of other electric fields and carrier diffusion on the final location of the holes at the surface 112 of the semiconductor 108 can be reduced by shortening the time between the generation of the holes at the focal point 144 of the laser 104 and their arrival at the surface 112.

[0031] By way of example, referring now to FIG. 3, a diagram illustrating the movement of holes under the influence of two different electric fields is shown. FIG. 3 shows a semiconductor element 300 including a first surface 302 exposed to an etching solution 304 and a second surface 306 opposite the first surface 302, where a beam of light 308 of below-bandgap energy enters the semiconductor 300 through the second surface 306. The beam 308 generates a plurality of holes 310-314 at a focal point 316 of the beam 308 located within the semiconductor 300. The holes 310-314 migrate toward the etching surface 302 of the semiconductor 300 under the influence of an electric field E. At a first strength of the electric field E, the holes 310-314 migrate to respective locations 318-322. When the electric field E is increased to a second, greater strength (e.g., by increasing the voltage output of the voltage source 120 of the system 100), the holes 310-314 may be swept more rapidly toward the etching surface 302. As shown in Figure 3, under the influence of the second, greater strength electric field, the holes 310, 314 move to their respective positions 324, 326, which are closer to each other than positions 318, 322. Thus, the size (e.g., diameter) of the etched feature for a given set of irradiation parameters (e.g., laser focal spot size, position, intensity) can be increased by decreasing the strength of the electric field E, or decreased by increasing the strength of the electric field E.

[0032] Still other parameters of the system 100 may be controlled by the process control component 142 in connection with etching the desired features within the semiconductor 108. In an exemplary embodiment, the process control component 142 outputs control signals to the laser 104 and / or the focusing system 134 to adjust the size, intensity, or position of the focal spot 144 within the semiconductor 108 by the laser 104 and / or the focusing system 134 to affect the resulting etching.

[0033] By way of example, referring now to FIG. 4, a diagram illustrating the difference in hole migration within a semiconductor for various focal spot sizes and locations is shown. FIG. 4 illustrates a semiconductor element 400 including a first surface 402 exposed to an etching solution 404 and a second backside surface 406 opposite the first surface 402. Beams 408-412 of below-bandgap energy light are shown entering the semiconductor 400 through the backside surface 406. Each of the beams 408-412 has a different combination of focal spot size and location relative to the etching surface 402. Beam 408 has a focal spot 414 with a focal width fw1 located at a depth d1 from the etching surface 402. Holes 416 and 418 are initially shown separated by a maximum distance fw1 at the focal spot 414. Due to carrier diffusion, internal or induced electric fields, or various other forces, the holes 416 and 418 migrate to locations 420 and 422 on the etching surface 402 of the semiconductor 400. The locations 420, 422 are spaced apart by a width w1, where the value of w1 depends on various etching parameters described herein. Similarly, the beam 410 has a focal point 424. The focal point 424 of the beam 410 has the same focal width fw1 as the focal point 414 of the first beam 408, but the focal point 424 is located at a depth d2 that is shallower than the depth d1 of the first focal point 414. As a result, all else being equal, holes 426, 428 generated at the focal point 424 a maximum distance fw1 apart travel to respective second locations 430, 432 at the etching surface 420 that are spaced apart by a width w2 that is smaller than the width w1. For the same size focal point, the size of the etched features at the etching surface of the semiconductor can be increased by increasing the distance between the focal point and the etching surface.

[0034] The width of the focal point can also affect the width of the resulting etched feature. Still referring to FIG. 4 , the third beam 412 has a focal point 434 located at the same depth d2 as the focal point 424 of the second beam 410. Furthermore, the focal point 434 of the third beam 412 has a focal width fw2 that is greater than the focal width fw1 of the second beam 410. Holes 436, 438 are shown as being generated at the focal point 434, spaced a maximum distance fw2 apart. The holes 436, 438 are shown moving to respective second locations 440, 442 on the etched surface 402, the locations 440, 442 being spaced apart by a width w3. The width w3 is greater than the width w2, indicating that, all else being equal, a larger focal width fw2 results in a larger etched feature width w3.

[0035] Additionally, the position of the focal point 144 of the laser 104 can be controlled relative to the position of an existing etched feature in the semiconductor 108 to affect the resulting size or shape of the etched feature. For example, the focal point 144 can be positioned proximate to the surface of the etched feature in the semiconductor 108 (e.g., from within 10 nanometers of the surface of the feature to within 10-200 microns of the surface of the feature, or more, depending on the carrier diffusion length of the particular semiconductor) to alter the motion of holes generated at the focal point 144 by the internal electric field established by the geometry of the etched feature. In one non-limiting example, referring now to FIG. 5 , an illustration of an exemplary etch of a semiconductor 500 is shown, in which holes are generated proximate to an existing etched feature to reduce the size of the etch. The semiconductor comprises a front surface 502 exposed to an etching solution 504 and a back surface 506 through which a beam of light 508 of below-bandgap energy enters the semiconductor 500. The semiconductor 500 includes a feature 510 etched into the surface 502 of the semiconductor 500. The feature 510 has an initial width w i In an exemplary embodiment, the initial width w iis based on the width of the focal point 512 of the beam 508, the strength of the electric field E induced within the semiconductor 500, the relative difference in the concentration of charge carriers between the surface 502 and the location of the focal point 512, etc. As the feature 510 extends into the semiconductor 500, the width of the feature 510 decreases to a smaller final width w due to the electric field focusing of the charge carriers at the tip 514 of the feature 510. f It tapers off to.

[0036] Illustratively, a plurality of holes 516-520 are generated at a focal point 512 of the beam 508. Under the influence of the induced electric field E, the holes 516-520 migrate from the focal point 512 of the beam 508 toward the etched surface 502 of the semiconductor 500. If no pre-existing features exist, the minimum width of the etched feature at the surface 502 may be limited by the focal size of the beam 508. For example, for the initial etching of a feature 510 at the surface 502 of the semiconductor 500, an initial width w i may be the width of the focal point 512. As the feature 510 is etched into the semiconductor, the surfaces of the feature 510 (e.g., inner surfaces 522, 524) bend the electric field lines (not shown) from the surface 506 toward the feature 510, particularly toward the tip 514 of the feature 510. This change in the electric field due to the feature 510 exerts a force on the holes as they move through the semiconductor 500. Thus, holes 516-520 created at the focal point 512 of the beam 508 swell toward the tip 514 of the feature 510 with a width w f In the absence of feature 510, holes 516-520 may spread as they move toward surface 502 (e.g., due to diffusion of charge carriers within semiconductor 500), while the surface of feature 510 attracts holes toward the surface of feature 510.

[0037] In the exemplary embodiment, the final width w of feature 510 fis smaller than the width of the focal spot 512. Thus, referring back to Figure 1, by positioning the focal spot 144 of the laser 104 near the feature to be etched in the semiconductor 108, features having sizes smaller than the resolution limit of the laser 104 and the focusing system 134 can be etched in the semiconductor 108. In one illustrative example, if the laser 104 has a minimum focal spot size of 500 nanometers, the process control component 142 can control the laser 104 to etch features having dimensions as small as 10 nanometers using electric field focusing.

[0038] Because light below the bandgap energy is not absorbed by the semiconductor 108 except at the focal point 144 of the laser 104, the focal point 144 can be located anywhere within the three-dimensional body of the semiconductor 108. This allows three-dimensional features to be etched into the semiconductor 108 without requiring a direct, straight path to the etching surface 112 of the semiconductor 108, as is typically required in conventional photomask-based etching.

[0039] For example, referring now to FIG. 6 , an exemplary etch of a semiconductor 600 is shown in which a cavity 602 is formed within the body of the semiconductor 600. As shown in FIG. 6 , the semiconductor 600 comprises a front surface 604 exposed to an etching solution 606 and a back surface 608 through which a beam of light 610 of below-bandgap energy enters the semiconductor 600. The cavity 602 is not formed on the surface of the semiconductor 600 but is disposed within the bulk of the semiconductor 600. Because the semiconductor 600 is transparent to the beam 608 except at a focal point 612 of the beam 610, the focal point 612 can be positioned to generate holes anywhere within the body of the semiconductor 600. In conjunction with the etching of the cavity 602, additional channel features 614, 616 are etched prior to etching the cavity 602. The location of etching by the etching solution 606 can be controlled by using the beam 608 to control the generation of holes within the semiconductor 600; however, the etching solution 606 must be able to reach the features in order to etch them. Thus, a first channel feature 614 is etched from the front surface 604 into the bulk of the semiconductor 600. Because the etching solution 606 can reach the second channel feature 616 through the first channel feature 614, the second channel feature 616 is etched following the first channel feature 614. The cavity 602 can then be etched because the etching solution 606 can reach the cavity 602 through the already etched channel features 614, 616.

[0040] For ease of understanding, various aspects related to etched features are shown in two-dimensional format in the figures; however, it should be understood that the techniques described herein are suitable for etching features of virtually any shape in three dimensions. Referring now to FIG. 7 , a three-dimensional representation 700 of the etched features 602, 614, and 616 shown in FIG. 6 is shown. In the three-dimensional representation 700, the semiconductor device 600 is shown to have a rectangular parallelepiped shape. The first channel feature 614 is a rectangular channel feature extending from the front surface 604 into the body of the semiconductor device 600. The second channel feature 616 is also a rectangular channel feature, extending horizontally outward from the first channel feature 614 within the body of the semiconductor device 600. The cavity 602 is shown as a cubic cavity that connects with the second channel feature 616 and, therefore, connects to the front surface 604 of the semiconductor device 600 via the two channel features 614 and 616.

[0041] 1 , the process control component 142 can further control the temperature and composition of the etching solution 110 to maintain desired etching parameters. The system 100 further includes a composition controller 150 and a temperature controller 152 in communication with the computing device 106. The composition controller 150 is connected to the interior of the first confinement vessel 114 through an opening 154 in the confinement vessel 114. The composition controller 150 can be controlled by the process control component 142 to remove by-products of the etching reaction from the first confinement vessel 114 and / or introduce additional etching solution to maintain a target composition of the etching solution 110 within the confinement vessel 114. The temperature controller 152 is connected to a heating / cooling device 156 disposed within the confinement vessel 114. In response to receiving a control signal from the computing device 106, the temperature controller 152 controls the heating / cooling device 156 to heat or cool the etching solution 110 within the containment vessel 114 to maintain a target temperature of the etching solution 110 (e.g., as indicated in the control signal sent by the computing device 106 to the temperature controller 152).

[0042] It should be understood that any or all of the various forces, parameters, and variables described herein can affect the movement of holes within the semiconductor 108. Thus, it will be true that holes generated at one location may migrate to another location under the influence of numerous variable physical parameters (e.g., temperature, voltage between the electrodes 122, 124, size, strength, and position of the focal spot 144, composition of the semiconductor 108, etc.). To facilitate etching of the semiconductor 108 according to the desired etch pattern, the memory 138 includes an etch modeling component 158 ​​that outputs etch control instructions to the process control component 142 based on an etch definition entered into the computing device 106. Additionally, feedback can be introduced into the control algorithm by monitoring the current I flowing through the electrochemical etching cell (related to the rate of etching occurring), the current temperature of the etching solution 110, products resulting from the etching process (e.g., as identified by the composition controller 150), or images of the etched surface as etching progresses.

[0043] An exemplary operation of the etch modeling component 158 ​​and the process control component 142 with respect to etching the semiconductor 108 according to a desired pattern will now be described. An etch definition is provided to the etch modeling component 158, the etch definition representing the locations and dimensions of various features desired to be etched in the semiconductor 108. In other words, the etch definition indicates multiple locations where etching of the semiconductor 108 is desired (e.g., by an operator of the system 100), which collectively define the structure of one or more features to be etched. In an exemplary embodiment, the etch definition includes a computer-aided design (CAD) file representing the dimensions of the semiconductor and the respective locations and dimensions of one or more etched features within the semiconductor. The etch definition input to the etch modeling component 158 ​​can further include one or more desired parameters of the etch. By way of example and not limitation, the etch definition can include data representing the composition of the semiconductor 108, the locations of existing etched features within the semiconductor 108, desired operating parameters of the laser 104 and / or voltage source 120, etc.

[0044] The etch modeling component 158 ​​is configured to output etch control instructions to the process control component 142 based on the etch definition. The etch control instructions define control parameters for various aspects of the system 100 used by the process control component 142 in connection with performing the desired etch described in the etch definition. In an exemplary embodiment, the etch control instructions include multiple positions of the focal point 144 of the laser 104. In other examples, the etch control instructions may include data representing the composition of the etch solution 110, the temperature of the etch solution 110, the voltage output of the voltage source 120, etc.

[0045] In the exemplary system 100, the beam 109 is emitted toward the backside 128 of the semiconductor 108 to avoid scattering of the beam 109 by previously etched features in the semiconductor 108, such as feature 146. Scattering of the beam 109 by previously etched features in the semiconductor 108 can typically be avoided by irradiating the semiconductor 108 with the laser 104 from the backside 128, etching features closest to the etching surface 112 first, followed by features further from the etching surface 112. However, for more complex three-dimensional structures, it may be necessary to etch the features in a different order to avoid scattering of the beam 109. The etch modeling component 158 ​​can be configured to generate etch control instructions to minimize the chance that the beam 109 crosses previously etched features in the semiconductor 108.

[0046] In an exemplary embodiment, the etch modeling component 158 ​​generates the etch control instructions based on a physics model 160 configured to output a prediction of hole movement within the semiconductor 108. In one example, a desired etch location is provided to the physics model 160 (e.g., as indicated in an etch definition provided to the etch modeling component 158), and the physics model 160 outputs a prediction that includes an irradiation location, where the prediction indicates that holes generated at the irradiation location are expected to move to the desired etch location. In other words, the physics model 160 receives the desired etch location of the semiconductor 108 and outputs a prediction of where the focal point 144 of the laser 104 can be placed to produce the desired etch.

[0047] The physical model 160 generates irradiation location predictions for desired etch locations based on various parameters that affect the movement of holes within the semiconductor 108. Such physical effects include, but are not limited to, charge carrier diffusion, an electric field induced within the semiconductor 108 (e.g., caused by a voltage established between the electrodes 122, 124), a current I through an electrochemical cell including the conductive material 126, the semiconductor 108, the etching solution 110, the electrodes 122, 124, and the voltage source 120, etc. In connection with generating the irradiation location predictions, the physical model 160 can further model the effects of these parameters based on other underlying data that may affect the modeled physical processes. For example, the physical model 160 can model the effects of charge carrier diffusion based on the composition of the semiconductor 108 and the concentration of dopants or other impurities within the semiconductor 108. In another example, the physical model 160 can model the effects of an electric field induced based on a voltage applied between the electrodes 122, 124.

[0048] In addition to receiving data regarding desired etch parameters (e.g., as specified in an etch definition presented to etch modeling component 158), physics model 160 also receives data regarding the current state of one or more operating parameters of system 100. For example, process control component 142 can output data to physics model 160 in real time, where the data represents a current current I, which in turn represents a reaction rate of an etch reaction (e.g., the reaction represented by Equations 1 and 2 above). Thus, physics model 160 can continuously generate updated predictions of irradiation locations for desired etched features based on data regarding the current state of system 100. Etch modeling component 158 ​​can generate updated control commands based on the predictions and send the updated control commands to process control component 142 to facilitate process control component 142's control of system 100 based on the most current information regarding the system state.

[0049] In another exemplary embodiment, the physics model 160 can be configured to generate irradiation position predictions based on the simulation results 162 stored in the data storage 140. In one embodiment, the simulation results 162 include results of a large number (e.g., hundreds or thousands or more) of simulated etches of semiconductors with various etching parameters. The physics model 160 can be configured to run a machine learning algorithm on the simulation results 162 to identify simulated etches that exhibit an etch pattern similar to the desired etch indicated in the etch definition received by the etch modeling component 158. The physics model 160 can then output irradiation position predictions based on the identified results.

[0050] While specific examples of physical effects modeled by the physical model 160 are described herein, it is contemplated that the physical model 160 can model virtually any physical process that can affect the etching location resulting from holes generated by the focal point 144 of the laser 104 at the irradiation location.

[0051] It should be understood that the systems and methods for selective electrochemical etching of various semiconductors are suitable for etching features of various sizes. For example, features can be etched according to the techniques described herein to have sizes on the order of 10 nanometers to 1 micron, or on the order of 10 microns to 1 millimeter, or features of any larger size can be etched.

[0052] While various aspects of an exemplary system 100 operable in connection with selective etching of a semiconductor are described in detail above, it should be understood that other configurations are possible and are considered within the scope of the present disclosure. Referring now to FIG. 8 , another exemplary system 800 is shown in which a semiconductor 108 is contained in an etching chamber 802 configured for frontside illumination by multiple sub-bandgap energy lasers 804-808. The etching chamber 802 comprises a first containment vessel 810 containing an etching solution 110 and a second containment vessel 812 containing the semiconductor 108 and a conductive element 814. The first containment vessel 810 further comprises a window 816 through which beams 818-822 emitted by the respective lasers 804-808 are focused by respective focusing systems 824-828 toward the frontside etching surface 112 of the semiconductor 108. It should be appreciated that as the beams 818-822 are emitted toward the front surface 112 of the semiconductor 108, the beams 818-822 may be focused to respective focal points within the body of the semiconductor 108 and below the surface 112. In the exemplary system 800, a voltage source 120 is connected between a conductive element 814 in electrical contact with the back surface 128 of the semiconductor 108 and an electrode 830 disposed within the first containment vessel 810.

[0053] The process control component 142 of the computing device 106 can be configured to independently control multiple lasers 804-808 to facilitate faster etching of the semiconductor 108. For example, because etching of the semiconductor 108 by the etching solution 110 is driven by holes that drive the etching reaction, the lasers 804-808 can simultaneously generate holes at multiple locations within the semiconductor 108, allowing several features to be etched simultaneously. It should be understood that virtually any number of lasers may be included in a system for selective electrochemical etching of a semiconductor and controlled by the process control component 142. In other examples, it may be desirable for the process control component 142 to control multiple lasers to operate in parallel so that the same feature can be simultaneously etched multiple times within the semiconductor 108.

[0054] In some embodiments, the system 100 can include multiple lasers 104, 164, 166 to facilitate parallel etching of the semiconductor 108 at multiple locations. The lasers 164, 166 can have respective focusing systems 168, 170. The lasers 164, 166 emit respective beams 172, 174. The multiple beams 109, 172, 174 stimulate charge carriers by the MPA at multiple locations simultaneously within the semiconductor 108. As these stimulated carriers migrate to the surface 112 of the semiconductor 108, the etchant solution 110 reacts with portions of the semiconductor 108 that have been oxidized by the carriers, causing etching of the semiconductor 108 at multiple locations. However, overlapping of the beams 109, 172, 174 within the semiconductor 108 can generate charge carriers at unintended locations within the semiconductor 108. The migration of these unintended charge carriers to the surface 112 of the semiconductor 108 can result in etching of the semiconductor 108 at undesired locations.

[0055] 9, a cross-sectional view 900 of a semiconductor element 902 is shown in which a first laser beam 904 and a second laser beam 906 overlap within the semiconductor 902. The first laser beam 904 has a focal point 908 where holes 910 are generated by the MPA. The second laser beam 906 has a focal point 912 where holes 914 are generated by the MPA. These holes 910, 914 travel to corresponding etching locations 916, 918 on a surface 920 of the semiconductor 902 that is exposed to an etchant solution 922.

[0056] Laser beams 904, 906 overlap at region 924 within the bulk of semiconductor 902. While beams 904, 906 may not individually have sufficient intensity to generate charge carriers via MPA except at their respective focal points 908, 912, the overlap of beams 904, 906 may provide sufficient intensity for MPA to occur in region 924. Thus, although it may be desirable for charge carriers (e.g., holes) to be generated only near focal points 908, 912, holes 926 may also be generated in overlap region 924 of beams 904, 906. These holes 926 may migrate to etching location 928 on surface 920 of semiconductor 902, potentially causing etching of semiconductor 902 at unintended locations.

[0057] To avoid unintended generation of charge carriers within the bulk of the semiconductor 108, the process control component 142 can be configured to control the lasers 104, 164, and 166 so that the beams 109, 172, and 174 do not overlap within the semiconductor 108. In an exemplary embodiment, the process control component 142 receives an etch definition (e.g., as input to the computing device 106) that defines the location of features desired to be etched into the semiconductor 108. The process control component 142 can generate etch instructions based on the etch definition, where the etch instructions indicate the irradiation positions of each of the lasers 104, 164, and 166. The irradiation positions of the lasers 104, 164, and 166 are configured so that the charge carriers generated by the lasers 104, 164, and 166 collectively cause etching (by the etchant solution 110) of the entire feature specified by the etch definition. The process control component 142 can generate the etch instructions so that the beams 109, 172, and 174 simultaneously irradiate the semiconductor 108 without overlapping. For example, the etching instructions may specify that a first laser 104 is to irradiate a location within a first region of the semiconductor 108, and a second laser 164 is to irradiate a location within a second region of the semiconductor 108 that does not overlap the first region.

[0058] In a further example, the process control component 142 can be configured to control the lasers 104, 164, 166 based on the geometry of the beams 109, 172, 174. For example, the process control component 142 can control the lasers 104, 164, 166 to direct the beams 109, 172, 174 to positions that are a distance away at least as large as the maximum width of the beams 109, 172, 174 within the semiconductor 108. In a non-limiting illustrative example, the beam 109 can be the widest of the beams 109, 172, 174 and can have a maximum width x1 within the semiconductor 108. The process control component 142 can be configured so that none of the other beams 172, 174 simultaneously illuminates a position within the distance x1 of the beam 109. The width of each of the beams 109, 172, 174 within the semiconductor 108 can depend on the depth of focus of each of the beams 109, 172, 174 within the semiconductor 108. Generally, a beam having a greater depth within the semiconductor 108 (i.e., a focal point closer to the front surface 112 of the semiconductor) will have a greater width across the semiconductor 108 than a similarly shaped beam at a shallower depth within the semiconductor 108.

[0059] While in some embodiments, the system 100 includes multiple lasers 104, 164, 166 that simultaneously irradiate the semiconductor 108 to facilitate simultaneous etching of multiple features within the semiconductor 108, in some embodiments, a single laser (e.g., laser 104) can be used to generate charge carriers (e.g., holes) that can be used to facilitate etching of the semiconductor 108 at multiple locations simultaneously. As an example, the process control component 142 can be configured to control the laser 104 according to an etch definition so that multiple features are simultaneously etched within the semiconductor 108. The population of charge carriers stimulated by the laser 104 persists within the semiconductor 108 for a lifetime that can depend on the configuration of the semiconductor 108. Thus, after the beam 109 stimulates charge carriers via the MPA, the charge carriers may persist within the semiconductor 108 even when the beam 109 is turned off. A single laser 104 can be used to control the parallel etching of multiple etching locations within the semiconductor 108 by sequentially irradiating the multiple irradiation locations within the semiconductor 108 and repeating this sequence until etching at the multiple etching locations is complete.

[0060] In an exemplary embodiment, the laser 104 is a pulsed laser. The focusing system 134 can be configured to sequentially move the focal point 144 of the laser 104 to a plurality of irradiation positions associated with a respective plurality of etching positions (e.g., defined by an etching definition). In a non-limiting example, referring now to FIG. 10 , an exemplary surface 1000 of a semiconductor element 1002 is shown, depicting a plurality of irradiation positions 1004-1008. The focusing system 134 can move the focal point 144 to the first irradiation position 1004 at a first time, to the second irradiation position 1006 at a second time, and to the third irradiation position 1008 at a third time. When the focal point 144 is at the first irradiation position 1004, a first pulse of the beam 109 generates charge carriers in the semiconductor 1002 near the first irradiation position 1004. When the focal point 144 moves to the second irradiation location 1006, the second pulse of the beam 109 creates charge carriers in the semiconductor 1002 near the second irradiation location 1006. However, if the time between pulses is shorter than the lifetime of the charge carriers in the semiconductor 1002, some charge carriers remain near the first irradiation location 1004 and are available to enable etching of the semiconductor 1002 at the etching location corresponding to the first irradiation location 1004. Similarly, when the focal point 144 moves to the third irradiation location 1008, the third pulse of the beam 109 creates charge carriers near the third irradiation location 1008. Again, some charge carriers remain near each of the first irradiation location 1004 and the second irradiation location 1008. Thus, the remaining charge carriers at the three irradiation locations 1004-1008 are available to enable continued etching of the semiconductor at the etching locations corresponding to the irradiation locations 1004-1008 for a period of time after the laser 104 has moved away from the irradiation locations 1004-1008.

[0061] 1 , once the final illumination location in the sequence of illumination locations has been illuminated by the focal point 144, the process control component 142 can control the laser and / or focusing system 134 to begin the sequence again. In other words, the process control component 142 controls the laser 104 to repeatedly illuminate the sequence of illumination locations. It should be understood that in some embodiments, the illumination location in the sequence of illumination locations may vary over time (i.e., in subsequent repetitions of the sequence) to facilitate etching of non-vertical features in the semiconductor 108.

[0062] The number of parallel etch locations that can be supported by a single laser 104 may depend on the lifetime of charge carriers in the semiconductor 108, the pulse repetition frequency of the laser 104, and / or the number of charge carriers generated in the semiconductor 108 in a single pulse of the laser 104. The pulse repetition frequency of the laser 104 may be an inherent property of the laser 104. In other embodiments, the pulse repetition frequency of the laser 104 may be controllable. In such embodiments, the pulse repetition frequency of the laser 104 may be selected depending on the desired number of parallel etch locations. In various embodiments, the pulse repetition frequency of the laser 104 may be 250 kHz or greater, 1 MHz or greater, 10 MHz or greater, or 100 MHz or greater.

[0063] In connection with controlling etching of a semiconductor 108 using a single laser 104, the collection system 134 can include various components that can be controlled (e.g., by process control components 142) to move the focal point 144 of the beam 109 from one irradiation position to the next. These components can include micromirrors, electro-optic deflectors, positioning goniometers, etc. In some embodiments, the components of the collection system 134 are selected according to the desired pulse repetition frequency of the laser 104. By way of example and not limitation, the components of the collection system 134 can be selected such that the collection system 134 can change the position of the focal point 144 of the laser 104 within a time between pulses determined by the pulse repetition frequency of the laser 104.

[0064] In some embodiments, the repetition of the pulse sequence described above with respect to a single laser 104 can be used in systems including multiple lasers. By way of example, the process control component 142 can be configured to control the lasers 104, 164, 166 and the collection systems 134, 168, 170 so that each of the lasers 104, 164, 166 repeatedly illuminates a respective sequence of illumination locations over time. In these embodiments, the process control component 142 can control the multiple lasers 104, 164, 166 and the collection systems 134, 168, 170 so that none of the lasers 104, 164, 166 overlap within the semiconductor 108 at each stage of the sequence.

[0065] In some embodiments, the collection systems 134, 168, 170 can be configured to use optical dispersion to reduce the instantaneous intensity of the beams 109, 172, 174 within the bulk of the semiconductor 108 before the beams reach their respective focal points. By way of example, the lasers 104, 164, 166 may be picosecond or femtosecond lasers that generate extremely short pulses. Such lasers are characterized by broadband optical output spectra. The collection systems 134, 168, 170 are configured to temporally broaden and then recompress the pulses output by the lasers 104, 164, 166. By way of example, and referring now to FIG. 11 , an exemplary collection system 1100 is shown. The collection system 1100 includes a dispersive element 1102 and an objective lens 1104. The dispersive element 1102 receives the optical pulses from the laser 1106 and directs the pulses toward the objective lens 1104. The objective lens 1104 then focuses the pulse to a focal point 1108 within the semiconductor 1110. In an exemplary embodiment, the dispersive element 1102 may be or include any of a variety of diffraction gratings, such as a micromirror array, a blazed grating, or the like. The dispersive element 1102 is configured to exhibit an optical dispersive effect, which temporally broadens the optical pulse received from the laser 1106. The temporal broadening of the optical pulse reduces the instantaneous intensity of the pulse. The objective lens 1104 exhibits a negative dispersive effect, which temporally compresses the optical pulse, which was temporally broadened by the dispersive element 1102, as the pulse propagates toward the focal point 1108. The pulse reaches a peak intensity at the focal point 1108. At the output of the laser 1106, the pulse may be sufficiently intense to reliably induce MPA within the semiconductor 1110. The dispersive element 1102 may be configured such that the temporal spreading reduces the intensity of the pulse, increasing the probability of inducing MPA before it reaches the focal point 1108. Thus, referring again to FIG. 1, the light collection systems 134, 168, 170 may include dispersive elements similar to those described with respect to FIG.Due to the reduced intensity of the pulsed beams 109, 172, 174 output from the collection systems 134, 168, 170 caused by the temporal spreading of the beams 109, 172, 174, the overlapping regions of the beams 109, 172, 174 still have insufficient optical intensity to cause frequent MPA within the bulk of the semiconductor 108. Thus, by incorporating dispersive elements into the collection systems 134, 168, 170, MPA can be limited to regions near the focal points of the beams 109, 172, 174, respectively.

[0066] 12 illustrates an exemplary method 1200 for selective semiconductor etching driven by irradiation below the bandgap energy of the semiconductor. While the method is illustrated and described as a series of operations performed in sequence, it should be understood and appreciated that the method is not limited by the order of the sequence. For example, some operations may occur in a different order than described herein. Additionally, some operations may occur simultaneously with other operations. Furthermore, in some cases, not all operations may be required to implement a method described herein.

[0067] Furthermore, the operations described herein may be computer-executable instructions executable by one or more processors and / or storable on one or more computer-readable media. Computer-executable instructions may include routines, subroutines, programs, threads of execution, etc. Still further, results of the operations of the methods may be stored on a computer-readable medium, displayed on a display device, etc.

[0068] The method 1200 facilitates selective etching of a semiconductor by irradiation below the bandgap energy of the semiconductor. The method 1200 begins at 1202, and at 1204, a voltage is applied between a first surface of the semiconductor and a second surface of the semiconductor. By way of example, the voltage can be applied between the first and second surfaces by applying a voltage between electrodes (e.g., electrodes 122, 124 shown in the exemplary system 100) immersed in a conductive solution that contacts the first and second surfaces, respectively. At 1206, the semiconductor is irradiated at a first location with a laser that emits light having an energy lower than the bandgap energy of the semiconductor. The laser is focused sufficiently strongly to generate holes in the semiconductor at the first location, and etching of the semiconductor occurs at a second location based on the holes generated at the first location. The method then ends at 1208.

[0069] Referring now to FIG. 13 , a high-level diagram of an exemplary computing device 1300 that can be used in accordance with the systems and methods disclosed herein is shown. For example, the computing device 1300 can be used in a system that controls the operation of a system (e.g., system 100, system 800) for selective semiconductor etching. As another example, the computing device 1300 can be used in a system that performs a simulation of charge carrier movement in a semiconductor based on a physical model. The computing device 1300 includes at least one processor 1302 that executes instructions stored in memory 1304. The instructions may be, for example, instructions for performing functions described as being performed by one or more components described above or instructions for implementing one or more of the methods described above. The processor 1302 can access the memory 1304 via a system bus 1306. In addition to storing executable instructions, the memory 1304 can also store simulation results, etch definitions, the status of various process parameters of the selective etching system, etc.

[0070] Computing device 1300 further includes a data storage unit 1308 that can be accessed by processor 1302 via system bus 1306. Data storage unit 1308 can include executable instructions, simulation results, etc. Computing device 1300 further includes an input interface 1310 that allows external devices to communicate with computing device 1300. For example, input interface 1310 can be used to receive instructions from an external computer device, a user, etc. Furthermore, computing device 1300 further includes an output interface 1312 that allows computing device 1300 to interact with one or more external devices. For example, computing device 1300 can display text, images, etc. via output interface 1312.

[0071] It is contemplated that external devices communicating with computing device 1300 via input interface 1310 and output interface 1312 may be included in an environment providing virtually any type of user interface that enables interaction with a user. Example types of user interfaces include graphical user interfaces, natural user interfaces, etc. For example, a graphical user interface may accept input from a user using an input device such as a keyboard, mouse, remote control, etc., and provide output to an output device such as a display. Furthermore, a natural user interface may allow a user to interact with computing device 1300 in a manner free from the constraints imposed by input devices such as a keyboard, mouse, remote control, etc. Rather, a natural user interface may rely on voice recognition, touch and stylus recognition, gesture recognition both on and adjacent to the screen, air gestures, head and eye tracking, voice and speech, vision, touch, gestures, machine intelligence, etc.

[0072] Furthermore, while computing device 1300 is shown as a single system, it should be understood that it may be a distributed system, such that, for example, several devices may communicate over network connections and collectively perform the tasks described as being performed by computing device 1300.

[0073] The various functions described herein can be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. A computer-readable medium includes a computer-readable storage medium. A computer-readable storage medium may be any available storage medium that can be accessed by a computer. By way of example and not limitation, such computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk and disc include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs (BDs), where disks typically reproduce data magnetically and discs typically reproduce data optically using lasers. Furthermore, propagated signals are not included within the scope of computer-readable storage media. Computer-readable media also includes communication media, which includes any medium that facilitates transfer of a computer program from one place to another. A connection, for example, may be a communications medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of communications media. Combinations of the above should also be included within the scope of computer-readable media.

[0074] Alternatively, or in addition, the functionality described herein may be performed, at least in part, by one or more hardware logic components, such as, but not limited to, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0075] What has been described above includes some examples of one or more embodiments. Of course, it is not possible to describe every conceivable modification and variation of the above-described devices or methods for the purpose of describing the foregoing aspects, but those skilled in the art will recognize that numerous further modifications and permutations of the various aspects are possible. Accordingly, the above-described aspects are intended to encompass all such changes, modifications, and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent the term "includes" is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term "comprising" when "comprising" is interpreted when used as a transitional term in a claim.

Claims

1. A laser, a computing device in communication with the laser and controlling operation of the laser; The system includes: a laser emitting light toward a semiconductor, the light having a focus within the semiconductor, the photon energy of the light being less than a band gap energy of the semiconductor, and the semiconductor being etched based on the light emitted by the laser.

2. The system of claim 1 , further comprising a focusing system that focuses the light emitted by the laser so that the light has the focal point within the semiconductor.

3. 10. The system of claim 1, further comprising an etching chamber containing the semiconductor and an etching solution, wherein a surface of the semiconductor is exposed to the etching solution, and wherein the etching solution oxidizes and etches the semiconductor where holes exist in the atomic lattice of the semiconductor.

4. 4. The system of claim 3, wherein the semiconductor comprises at least one of silicon, carbon, germanium, diamond, gallium arsenide, indium gallium arsenide, indium phosphide, indium gallium phosphide, gallium nitride, indium gallium nitride, zinc oxide, cadmium telluride, cadmium mercury telluride, silicon carbide, or silicon germanium.

5. 4. The system of claim 3, wherein the etching solution comprises at least one of hydrofluoric acid, ammonium hydroxide, ammonium fluoride, sodium hydroxide, ethanol, dimethylformamide, acetic acid, sulfuric acid, propionic acid, perchloric acid, potassium sulfate, peroxydisulfuric acid, or acetonitrile.

6. The etching chamber comprises: a first containment vessel; a second containment vessel, wherein the first containment vessel holds the etching solution, the semiconductor is located within the second containment vessel, and the first and second containment vessels are joined by a seal that prevents the etching solution from leaking out of the etching chamber. The system of claim 3.

7. The system of claim 1 , further comprising a voltage source applying a voltage to an electrode to establish an electric field within the semiconductor, wherein the semiconductor is etched based on the electric field within the semiconductor.

8. The system of claim 1 , wherein an interior region of the semiconductor is etched based on the light emitted by the laser.

9. 10. The system of claim 1, further comprising: a second laser, wherein the computing device is in communication with and controls the second laser, the second laser emitting a second light toward the semiconductor simultaneously with the laser emitting the light toward the semiconductor, the second light having a second focal point within the semiconductor, and a photon energy of the second light less than the band gap energy of the semiconductor, and further wherein the semiconductor is etched simultaneously at multiple locations based on the light emitted by the laser and the second light emitted by the second laser.

10. The system of claim 1 , wherein the laser is a pulsed laser.

11. 1. A method for etching a semiconductor, comprising: emitting light from a laser having a photon energy less than the band gap energy of the semiconductor; focusing the light emitted from the laser so that the light has a focal point within the semiconductor, generating holes in the semiconductor due to the focusing of the light within the semiconductor; and etching the semiconductor at locations within the semiconductor based on the holes created within the semiconductor.

12. The method of claim 11 , wherein the light is directed through a back surface of the semiconductor to reach the focal point.

13. The method of claim 11 , wherein the light is directed through a front surface of the semiconductor to reach the focal point.

14. 12. The method of claim 11, further comprising applying a voltage between a first surface of the semiconductor and a second surface of the semiconductor to form an electric field within the semiconductor, wherein the semiconductor is etched at the location based on the electric field formed within the semiconductor.

15. emitting second light from a second laser at a second photon energy less than the band gap energy of the semiconductor; simultaneously focusing the second light emitted from the second laser within the semiconductor such that the second light has a second focal point within the semiconductor, and generating second holes within the semiconductor due to the focusing of the second light within the semiconductor; etching the semiconductor at a second location within the semiconductor based on the second holes generated within the semiconductor. The method of claim 11.

Images