Decoder, decoding method, memory controller, and memory system

Abstract

Examples of the present disclosure provide a decoder, a decoding method, a memory controller, and a memory system. The decoder includes a cache module and a flip instruction module. The cache module is configured to cache soft data related to a codeword to be decoded. The flip instruction module is configured to retrieve the soft data from the cache module and, when performing hard-decision decoding on the codeword to be decoded, determine, with the help of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded, at least in a first flip iteration.

Description

[Technical Field]

[0001] The present disclosure relates to the field of memory technology, and more particularly to a decoder, a decoding method, a memory controller, and a memory system. [Background technology]

[0002] As storage technology advances, 3D NAND flash memory (Flash) has evolved from single-level cell (SLC) memory, which can store one bit of information, and double-level cell (DLC) memory, which can store two bits of information, to triple-level cell (TLC) memory, which can store three bits of information, and even to quad-level cell (QLC) memory, which can store four bits of information. The number of stacked layers has also increased. Memory devices with more layers and memory bits typically employ low-density parity check (LDPC) for error correction when reading data to improve the reliability of the data stored within the memory device. However, 3D NAND flash memory has a complex structure, and as the amount of data stored increases, the types of errors it contains become increasingly complex. Current error correction methods suffer from slow and inefficient error correction speeds, which severely impact read speeds. Summary of the Invention [Problem to be solved by the invention]

[0003] In view of this, examples of the present disclosure provide a decoder, a decoding method, a memory controller, and a memory system.

[0004] To achieve the above objectives, the technical solutions of the present disclosure are achieved as follows: [Means for solving the problem]

[0005] In a first aspect, an example of the present disclosure provides a decoder including a cache module and a flip indication module; the cache module is configured to cache soft data related to the codeword to be decoded; The flip instruction module is configured to retrieve the soft data from the cache module and, when performing hard-decision decoding on the codeword to be decoded, determine, at least in a first flip iteration, with the aid of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded.

[0006] In the above solution, the flip instruction module: determining an initial error bit indicator vector corresponding to a codeword to be decoded; determining, with the aid of soft data in combination with the initial error bit indicator vector, the number of parity checks not satisfied by bits in the codeword to be decoded; The device is further configured to:

[0007] In the above solution, the decoder further comprises a variable node module and a check node module connected to form a variable-check connection network according to a pre-constructed parity check matrix; the variable node module is configured to receive hard-read data, generate a codeword to be decoded according to the hard-read data, send the codeword to be decoded to the check node module, and send the codeword to be decoded and the hard-read data to the flip indication module; the check node module is configured to receive a codeword to be decoded, determine a checksum vector according to the codeword to be decoded and a check matrix, and send the checksum vector to the flip instruction module; The flip indication module is further configured to receive the codeword to be decoded and hard read data sent by the variable node module, receive the checksum vector sent by the check node module, obtain the check matrix and soft data, and determine an initial error bit indication vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector, and the check matrix.

[0008] In the above solution, the flip instruction module: determining a soft data vector corresponding to the soft data; performing a summation operation on the soft data vector and the initial error bit indicator vector to obtain a target error bit indicator vector; determining the number of parity checks not satisfied by each bit in the codeword to be decoded according to the target error bit indication vector; further configured to: Each element of the target error bit indication vector corresponds to the number of parity checks that are not satisfied by a single bit.

[0009] In the above solution, the flip instruction module: performing a summation operation on the hard read data and the codeword to be decoded, and then performing a modulo operation on the summation to obtain a first bit vector; multiplying the transpose of the checksum vector by a parity check matrix to obtain a second bit vector; performing a summation operation on the first bit vector and the second bit vector to obtain an initial error bit indicator vector; The device is further configured to:

[0010] In the above solution, the flip instruction module: further configured to generate a flip direction vector according to the number of unsatisfied parity checks and a flipping criterion, the flip direction vector including determined bits that need to be flipped in the codeword to be decoded; The variable node module is further configured to receive a flip direction vector and flip bits that need to be flipped in the codeword to be decoded according to the flip direction vector.

[0011] In the above solution, the flipping criteria are: flipping bits in the codeword to be decoded that has the largest number of unsatisfied parity checks, or Flipping bits in the codeword to be decoded for which the number of unsatisfied parity checks is equal to or exceeds a preset threshold. Includes.

[0012] In the above solution, the decoder further includes a counting module and a termination determination module; the counting module is configured to count the number of hard-decision decoding iterations performed on the codeword to be decoded; The termination determination module is configured to determine whether the number of iterations has reached a maximum number of iterations, determine whether the checksum vector is a zero vector, and output a first decoding stop signal when the number of iterations has reached the maximum number of iterations and the checksum vector is a non-zero vector, wherein the first decoding stop signal is configured to indicate that hard-decision decoding of the codeword to be decoded has failed.

[0013] In the above solution, the decoder further comprises a rearrangement configuration module; The termination determination module is further configured to output a second decryption stop signal when the checksum vector is determined to be a zero vector; The rearrangement configuration module is configured to, in response to the second decoding stop signal, perform a rearrangement configuration process on the codewords to be decoded and output the codewords to be decoded in the correct order.

[0014] In the above solution, the termination determination module is further configured to output a continue decoding signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations, and the continue decoding signal is configured to instruct the variable node module, the check node module, and the flip indication module to continue performing hard-decision decoding operations on the codeword to be decoded.

[0015] In a second aspect, an example of the present disclosure provides a decoding method, the decoding method comprising: obtaining soft data corresponding to a codeword to be decoded; determining, at least in a first flip iteration, with the aid of soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded when performing hard-decision decoding on the codeword to be decoded; Includes.

[0016] In the above solution, determining the number of parity checks not satisfied by bits in the codeword to be decoded with the help of soft data is determining an initial error bit indicator vector corresponding to a codeword to be decoded; determining, with the aid of soft data in combination with the initial error bit indicator vector, the number of parity checks not satisfied by bits in the codeword to be decoded; Includes.

[0017] In the above solution, determining the number of parity checks not satisfied by bits in the codeword to be decoded with the help of soft data in combination with the initial error bit indicator vector is determining a soft data vector corresponding to the soft data; performing a summation operation on the soft data vector and the initial error bit indicator vector to obtain a target error bit indicator vector; determining the number of parity checks not satisfied by each bit in the codeword to be decoded according to the target error bit indication vector; Including, Each element of the target error bit indication vector corresponds to the number of parity checks that are not satisfied by a single bit.

[0018] In the above solution, determining the initial error bit indicator vector corresponding to the codeword to be decoded includes: receiving hard read data and generating a codeword to be decoded according to the hard read data; determining a checksum vector according to a codeword to be decoded and a pre-constructed check matrix; determining an initial error bit indication vector corresponding to the code word to be decoded according to the hard read data, the code word to be decoded, the checksum vector, and the check matrix; Includes.

[0019] In the above solution, determining an initial error bit indication vector corresponding to the code word to be decoded according to the hard read data, the code word to be decoded, the checksum vector, and the parity check matrix includes: performing a summation operation on the hard read data and the codeword to be decoded, and then performing a modulo operation on the summation to obtain a first bit vector; multiplying the transpose of the checksum vector by a parity check matrix to obtain a second bit vector; performing a summation operation on the first bit vector and the second bit vector to obtain an initial error bit indicator vector; Includes.

[0020] In the above solution, the method is: generating a flip direction vector according to the number of unsatisfied parity checks and a flipping criterion, the flip direction vector including determined bits that need to be flipped in the codeword to be decoded; flipping bits that need to be flipped in the codeword to be decoded according to the flip instruction vector; Further includes:

[0021] In the above solution, the method is: generating a flip direction vector according to the number of unsatisfied parity checks and a flipping criterion, the flip direction vector including determined bits that need to be flipped in the codeword to be decoded; flipping bits that need to be flipped in the codeword to be decoded according to the flip instruction vector; Further includes:

[0022] In the above solution, the flipping criteria are: flipping bits in the codeword to be decoded that has the largest number of unsatisfied parity checks, or Flipping bits in the codeword to be decoded for which the number of unsatisfied parity checks is equal to or exceeds a preset threshold. Includes.

[0023] In the above solution, the method is: counting the number of hard decision decoding iterations performed on the codeword to be decoded; determining whether the number of iterations has reached a maximum number of iterations and whether the checksum vector is a zero vector; outputting a first decoding stop signal when the number of iterations reaches a maximum number of iterations and the checksum vector is a non-zero vector, the first decoding stop signal being configured to indicate that hard-decision decoding of the codeword to be decoded has failed; Further includes:

[0024] In the above solution, the method is: determining whether the checksum vector is a zero vector, and outputting a second decoding stop signal when the checksum vector is determined to be a zero vector; in response to a second decoding stop signal, performing a rearrangement configuration process on the code words to be decoded and outputting the code words to be decoded in the correct order; Further includes:

[0025] In the above solution, the method is: The method further includes outputting a continue decoding signal when the checksum vector is not a zero vector and the number of iterations has not reached a maximum number of iterations, wherein the continue decoding signal is configured to instruct performing a hard-decision decoding operation on the codeword to be decoded.

[0026] In a third aspect, an example of the present disclosure further provides a memory controller, the memory controller comprising: a processor; and a decoder according to any one of the above aspects, wherein the processor is configured to read soft data corresponding to a codeword to be decoded from a memory device; The decoder is configured to cache the soft data and, when performing hard-decision decoding on the codeword to be decoded, determine, at least in a first flip iteration, with the aid of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded.

[0027] In a fourth aspect, an example of the present disclosure provides a memory system, the memory system comprising: a memory device configured to store data; a memory controller coupled to the memory device and comprising a processor and a decoder, the processor configured to read soft data corresponding to a codeword to be decoded from the memory device; Equipped with The decoder is configured to cache the soft data and, when performing hard-decision decoding on the codeword to be decoded, determine, at least in a first flip iteration, with the aid of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded.

[0028] In the above solution, the processor is further configured to read the hard read data from the memory device and send the hard read data to the decoder; The decoder is further configured to receive the hard read data and generate a codeword to be decoded according to the hard read data.

[0029] In the above solution, the decoder comprises a cache module, a variable node module, a check node module, and a flip indication module; the cache module is configured to cache soft data read by the processor; the variable node module is configured to receive the hard read data read by the processor, generate a code word to be decoded according to the hard read data, and send the code word to be decoded to the check node module; The check node module is configured to receive the codeword to be decoded sent by the variable node module, determine a checksum vector according to the codeword to be decoded and a pre-constructed check matrix, and send the checksum vector to the flip instruction module; The flip indication module is configured to receive the hard read data and the codeword to be decoded sent by the variable node module, receive the checksum vector sent by the check node module, obtain the check matrix and soft data, determine an initial error bit indication vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector, and the check matrix, and determine the number of parity checks that are not satisfied by bits in the codeword to be decoded with the help of the soft data combined with the initial error bit indication vector.

[0030] Examples of the present disclosure provide a decoder, a decoding method, a memory controller, and a memory system. The decoder includes a cache module and a flip instruction module. The cache module is configured to cache soft data related to a codeword to be decoded. The flip instruction module is configured to retrieve the soft data from the cache module and, when performing hard-decision decoding on the codeword to be decoded, determine, with the help of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded, at least in a first flip iteration. The decoder provided by examples of the present disclosure caches the soft data related to the codeword to be decoded through an included buffer module, and then, when performing hard-decision decoding on the codeword to be decoded, the flip instruction module determines, with the help of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded, in one or more iterations. In this way, the soft data is used to assist flipping decisions in hard-decision decoding, thereby enabling high processing power and low power consumption in hard-decision decoding and significantly improving the error correction capability of hard-decision decoding.

[0031] In the drawings, which are not necessarily to scale, like reference numerals may describe like components in different figures. The same numerals with different subscripts may indicate different instances of like components. The drawings illustrate generally, by way of example, and not by way of limitation, various examples described in the present specification. [Brief explanation of the drawings]

[0032] [Figure 1] 1 is a schematic diagram of an exemplary system having a memory system according to an example of the present disclosure. [Figure 2a] 1 is a schematic diagram of an exemplary memory card having a memory system according to an example of the present disclosure. [Figure 2b]FIG. 1 is a schematic diagram of an exemplary solid-state drive having a memory system according to an example of the present disclosure. [Figure 3] FIG. 2 is a schematic structural diagram of a memory controller according to an example of the present disclosure. [Figure 4] FIG. 1 is a schematic diagram of an exemplary memory device including peripheral circuitry according to an example of the present disclosure. [Figure 5] 1 is a schematic cross-sectional view of a memory array including a NAND memory string according to an example of the present disclosure. [Figure 6] 1 is a schematic diagram of an exemplary memory device including a memory array and peripheral circuitry according to an example of the present disclosure. [Figure 7] FIG. 2 is a schematic structural diagram of a decoder according to an example of the present disclosure. [Figure 8] FIG. 2 is an exemplary schematic diagram of acquiring soft data and hard read data according to an example of the present disclosure. [Figure 9] FIG. 10 is a schematic structural diagram of a decoder according to another example of the present disclosure. [Figure 10] FIG. 1 is a schematic diagram of a Tanner graph according to an example of the present disclosure. [Figure 11] FIG. 1 is a schematic diagram of a Tanner graph according to an example of the present disclosure. [Figure 12] FIG. 10 is a schematic structural diagram of a decoder according to another example of the present disclosure. [Figure 13] FIG. 10 is a schematic structural diagram of a decoder according to another example of the present disclosure. [Figure 14] FIG. 1 is a schematic diagram of a decoder workflow according to an example of the present disclosure. [Figure 15] 1 is a schematic flowchart of a decoding method according to an example of the present disclosure. [Figure 16] FIG. 2 is a schematic structural diagram of a memory controller according to an example of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0033] Various examples of the present disclosure are described in more detail below with reference to the accompanying drawings. Other examples, which are variations of any disclosed example, may be formed by configuring or arranging the elements and features of the examples of the present disclosure differently. Therefore, the examples of the present disclosure are not limited to the examples described herein. Rather, the described examples are provided so that the disclosed examples will be exhaustive and complete, and will fully convey the scope of the disclosed examples to those skilled in the art to which the examples of the present disclosure pertain. It should be noted that references to "one example," "another example," and similar references do not necessarily mean only one example, and different references to such phrases are not necessarily to the same example. While terms such as "first," "second," and "third" may be used herein to identify various elements, it should be understood that these elements should not be limited by these terms. These terms are used to distinguish one element from other elements having the same or similar names. Thus, a first element in one example may be referred to as a second or third element in another example without departing from the spirit and scope of the examples of the present disclosure.

[0034] The drawings are not necessarily to scale, and in some cases, the dimensions of the examples may be exaggerated to clearly illustrate the features of the examples. When an element is referred to as being connected or coupled to another element, it should be understood that the former may be directly connected or coupled to the latter, or may be electrically connected or coupled to the latter through one or more intervening elements. Additionally, when an element is referred to as being "between" two elements, it is also understood that the element may be the only element between the two elements, or that there may also be one or more intervening elements.

[0035] The terms used herein are intended to describe specific examples only and are not intended to limit the scope of the present disclosure. As used in the original English text of the present disclosure, the singular form "a" or "an" is intended to include the plural unless the context clearly indicates otherwise. Unless otherwise specified or clearly understood as singular from the context, the articles "a" and / or "an" used in the examples of the present disclosure and the appended claims in the original English text shall be interpreted collectively to mean "one or more." It should be further understood that the terms "comprise," "comprising," "include," and "including" used in the examples of the present disclosure specify the presence of the stated elements and do not exclude the presence or addition of one or more other elements. The term "at least one" used in the examples of the present disclosure includes any combination of one or more of the associated listed items. Unless otherwise defined, all terms, including technical and scientific terms, used in the examples of this disclosure have the same meaning as commonly understood by a person skilled in the art to which this disclosure belongs in light of the examples of this disclosure. It should be further understood that unless expressly defined by the examples of this disclosure, words as defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the examples of this disclosure and the relevant technology, and should not be interpreted in an idealized or overly formalized manner.

[0036] In the following description, numerous specific details are set forth to provide a comprehensive understanding of the present disclosure; however, the present disclosure may be practiced without some or all of these specific details. In other instances, at least one well-known processing structure or process has not been described in detail to avoid unnecessarily obscuring the present disclosure. In some instances, unless otherwise specified, it should also be understood that features or elements described with respect to one example may be used alone or in combination with other features or elements of other examples, as would be apparent to one skilled in the art, unless otherwise specified. Various examples of the present disclosure are described in detail below with reference to the accompanying drawings. The following description focuses on details that will facilitate an understanding of the examples of the present disclosure. Well-known technical details may be omitted so as not to obscure the features and aspects of the examples of the present disclosure.

[0037] In order to allow a more detailed understanding of the characteristics and technical contents of examples of the present disclosure, examples of the present disclosure are described in detail below in conjunction with the accompanying drawings, which are provided for reference and explanation only and are not intended to limit the examples of the present application.

[0038] A memory device is a memory device used to store information in modern information technology. As a typical non-volatile memory device, 3D NAND (Not-And) memory devices have become a mainstream product in the storage market due to their high storage density, controllable production costs, favorable programming and erasing speeds, and retention characteristics. As the number of memory bits and the number of stacked layers in memory cells increase, the types of errors that occur during read operations of memory devices become increasingly complex. In this case, when LDPC hard-decision decoding in a decoder is used to decode the codeword to be decoded (data read from a memory device), the decoding time becomes longer and the error correction ability becomes weaker, which seriously affects the read speed.

[0039] Based on one or more of the above problems, one example of the present disclosure provides a decoder that utilizes soft data to assist flip decisions in hard-decision decoding, thereby achieving the high processing power and low power consumption characteristics of hard-decision decoding and thereby significantly improving the error correction capability of hard-decision decoding.

[0040] Examples of the disclosure are described in further detail below in conjunction with the accompanying drawings and specific examples.

[0041] FIG. 1 is a schematic diagram of an exemplary system having a memory system according to one example of the present disclosure. In FIG. 1, system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory system therein. As shown in FIG. 1, system 100 may include a host 108 and a memory system 102. Host 108 may include a processor such as a central processing unit (CPU) or a system-on-chip (SoC). The SoC may be, for example, an application processor (AP). Host 108 further includes at least one operating system (OS) that can generally manage and control functions and operations performed on host 108. The OS may enable interoperability between host 108 coupled to memory system 102 and users who require and use memory system 102. The OS may support functions and operations corresponding to user requests. For example, without limitation, depending on whether the type of host 102 is a removable host, the OS may be categorized as a general-purpose operating system and a mobile operating system. A general-purpose operating system may be a personal operating system, which may be an operating system used to support general-purpose services, including Windows and Chrome, and an enterprise operating system, which may be an operating system specifically designed to ensure and support high performance, including Windows Server, Linux, Unix, etc. A mobile operating system may refer to an operating system for mobility services or functions (e.g., power saving functions). Generally, a mobile operating system may be an operating system such as Android, iOS, and Windows Mobile. In some examples, the host 108 may include multiple OSs.Correspondingly, host 108 may execute multiple operating systems related to memory system 102. In other examples, host 108 translates a user request into one or more commands and transmits the one or more commands to memory system 102, which then performs the operations related to the one or more commands.

[0042] The memory system 102 can operate or perform specific functions in response to requests from the host 108 or perform various internal operations. In some examples, the memory system 102 can store data accessed by the host 108. The memory system 102 can function as a primary or secondary memory system for the host 108. The memory system 102 and the host 108 can be electrically coupled and communicate according to corresponding protocols. The memory system 102 can be implemented and packaged in different types of end electronic products, including, but not limited to, solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), reduced-size MMCs (RSMMCs), micro MMCs, secure digital (SD) cards, mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash (CF) cards, smart media (SM) cards, and memory sticks.

[0043] In some examples, the memory system 102 may also be configured as part of, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured by a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured by a home network, one of various electronic devices configured by a computer network, one of various electronic devices configured by a telematics network, a radio frequency identification (RFID) device, or one of various components configured by a computing system.

[0044] Referring again to FIG. 1 , the memory system 102 may include one or more memory devices 104 and a memory controller 106. The memory controller 106 can respond to requests from the host 108 and then control the memory device 104. For example, the memory controller 106 can read data from the memory device 104 and transmit the read data to the host 108. Furthermore, the memory controller 106 can receive data to be stored from the host 108 and store the data to be stored in the memory device 104. That is, the memory controller 106 can control write (or program) operations, read operations, erase operations, background operations, and similar operations of the memory device 104. Furthermore, the memory system 102 can be implemented and packaged in different types of end electronic products. In one example, as shown in FIG. 2 a, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may further include a memory card connector 204 that couples the memory card 202 to a host (e.g., host 108 in FIG. 1 ). In another example, as shown in FIG. 2b , the memory controller 206 and the multiple memory devices 104 may be integrated into an SSD 206. The SSD 206 may further include an SSD connector 208 that couples the SSD 206 to a host (e.g., host 108 in FIG. 1 ). In some examples, at least one of the storage capacity or operating speed of the SSD 206 is greater than that of the memory card 202.

[0045] 3, memory controller 106 may include a host I / F (or front-end interface) 301, a memory I / F (or back-end interface) 302, a processor 303, and a memory 304. The above-mentioned components 301, 302, 303, and 304 of memory controller 106 may share transmission signals inside memory controller 106 through an internal bus. In some examples, host I / F 301 may interface host 108 with memory system 102 in response to a protocol of host 108, and host I / F 301 exchanges transfer commands and data operations between host 108 and memory system 102. The host I / F 301 can process commands and data sent by the host 108 and can include at least one of a Universal Serial Bus (USB), a Multimedia Card (MMC), a Peripheral Component Interconnect Express (PCI-e or PCIe), a Small Computer System Interface (SCSI), a Serial SCSI (SAS), a Serial Advanced Technology Attachment (SATA), a Parallel Advanced Technology Attachment (PATA), a Small Computer System Interface (SCSI), an Enhanced Small Disk Drive Interface (ESDI), and an Electronic Integrated Drive (IDE). In some examples, the host I / F 301 is a component of the memory system 102 used to exchange data with the host 108 and can be implemented by firmware called a host interface layer (HIL).

[0046] The memory I / F 302 may be an interface for commands and data transferred between the memory controller 106 and the memory device 104, allowing the memory controller 106 to control the memory device 104 in response to requests communicated from the host 108. The memory I / F 302 may generate control signals for controlling the memory device 104. In some examples, if the memory device 104 is a NAND flash memory, the memory I / F 302 may write data to or read data from the memory device 104 under the control of the processor 303. The memory I / F 302 may process commands and data between the memory controller 106 and the memory device 104, for example, and may handle operations of the NAND flash interface, particularly operations between the memory controller 106 and the memory device 104. According to one example, the memory I / F 302 may be implemented as a component for exchanging data with the memory device 104 by firmware called a flash interface layer (FIL).

[0047] The processor 303 may be implemented by a microprocessor or a central processing unit (CPU). The memory system 102 may include one or more processors 303. The processor 303 may control the overall operation of the memory system 102. By way of example, and not limitation, the processor 303 may control program operations or read operations of the memory device 104 in response to write or read requests from the host 108. According to one example, the processor 303 may use or execute firmware to control the overall operation of the memory system 102. In this disclosure, the firmware may be referred to as a flash translation layer (FTL). The FTL may act as an interface between the host 108 and the memory device 104. The host 108 may transmit requests related to write and read operations to the memory device 104 through the FTL. For example, the memory controller 106 uses the processor 303 when executing operations requested by the host 108 on the memory device 104. A processor 303 coupled to the memory device 104 may process instructions or commands related to commands from the host 108. The memory controller 106 may perform foreground operations such as command operations corresponding to command input from the host 108, e.g., program operations corresponding to write commands, read operations corresponding to read commands, and erase / discard operations corresponding to erase / discard commands, as well as parameter setting operations corresponding to parameter setting commands or feature setting commands with setting commands.

[0048] As another example, the memory controller 106 may execute background operations on the memory device 104 via the processor 303. By way of example, and not limitation, the background operations may include a garbage collection (GC) operation, a wear leveling (WL) operation, a map clear operation, and a bad block management operation that checks for or searches for bad blocks. A garbage collection operation may include an operation that copies and processes data stored in a particular memory block in the memory device 104 to another memory block. A wear leveling operation may include an operation that swaps and processes data stored between memory blocks of the memory device 104. A map clear operation may include an operation that stores map data stored in the memory controller 106 in a memory block of the memory device 104. A bad block management operation may include an operation that checks for and processes bad blocks in a memory block of the memory device 104. The memory controller 106 may respond to operations that access the memory blocks of the memory device 104. An operation that accesses a memory block of memory device 104 may include a foreground or background operation performed on a memory block of memory device 104.

[0049] The memory 304 may be a working memory of the memory controller 106 and is configured to store data used to drive the memory controller 106. More specifically, when the memory controller 106 controls the memory device 104 in response to a request from the host 108, the memory 304 can store firmware driven by the processor 303 and data (e.g., metadata) necessary to drive the firmware. The memory 304 may be a buffer memory of the memory controller 106 and is configured to temporarily store write data transferred from the host 108 to the memory device 104 and read data transferred from the memory device 104 to the host 108. The memory 304 may include a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, and a map buffer / cache for storing write data and read data. The memory 304 may be implemented using volatile memory. The memory 304 may be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both.

[0050] 3 shows memory 304 included in memory controller 106, the disclosure is not limited thereto. In one example, memory 304 may be external to memory controller 106, and memory controller 106 may input data to and output data from memory 304 via a separate memory interface (not shown).

[0051] The error correction (ECC) module 305 includes an encoding section 3051 and a decoding section 3052. The encoding section 3051 can perform an encoding operation, such as LDPC, on data to be programmed into the semiconductor memory device 104 and output data including additional parity check bits. The parity check bits can be stored in the semiconductor memory device 104. The decoding section 3052 can perform error correction decoding on data read from the semiconductor memory device 104, determine whether the error correction decoding is successful, output a command signal based on the determination result, and correct error bits in the data using the parity check bits generated by the LDPC encoding operation.

[0052] 3 illustrates the error correction module 305 being included in the memory controller 106, the present disclosure is not limited thereto. In one example, the error correction module 305 may be external to the memory controller 106, and the memory controller 106 may be in data communication with the error correction module 305 via a separate interface (not shown).

[0053] Referring again to FIG. 1 , memory device 104 may include non-volatile memory that retains data stored therein even when power is not applied. Memory device 104 may further include volatile storage memory. Device 104 can store data provided by host 108 through write operations. Memory device 104 can also provide stored data to host 108 through read operations. In examples of the present disclosure, memory device 104 may include any of the disclosed memories, for example, volatile memory devices such as dynamic random access memory (DRAM) and static RAM (SRAM), or volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM®), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), and flash memory (e.g., 3D NAND flash memory).

[0054] The memory device is illustrated by taking a 3D NAND flash memory as an example. Referring to FIG. 4, a schematic circuit diagram of an exemplary memory device 400 including peripheral circuits according to some embodiments of the present disclosure is shown. The memory device 400 may be an example of the memory device 104 in FIG. 1. The memory device 400 may include a memory array 401 and peripheral circuits 402 coupled to the memory array 401. The memory array 401 is illustrated by taking a 3D NAND memory array as an example. The memory cells 406 are provided in the form of an array of NAND memory strings 408 each extending vertically above a substrate (not shown). In some examples, each NAND memory string 408 includes multiple memory cells 406 coupled in series and stacked vertically. Each memory cell 406 can hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the memory cell 406. Each memory cell 406 can be either a floating-gate memory cell including a floating-gate transistor or a charge-trapping memory cell including a charge-trapping transistor.

[0055] In some examples, each memory cell 406 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first range of voltages, and a second memory state "1" can correspond to a second range of voltages. In some examples, each memory cell 406 is a multi-level cell (MLC) that can store more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also called a triple-level cell (TLC)), four bits per cell (also called a quad-level cell (QLC)), or five bits per cell (also called a penta-level cell (PLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value may be used for the erased state.

[0056] As shown in FIG. 4 , each NAND memory string 408 can include a bottom selective gate (BSG) 410 at its source end and a top selective gate (TSG) 412 at its drain end. The BSG 410 and TSG 412 can be configured to activate a selected NAND memory string 408 during read and program operations. In some examples, the sources of the NAND memory strings 408 in the same block 404 are coupled through the same source line (SL) 414, e.g., a common SL. In other words, according to some examples, all NAND memory strings 408 in the same block 404 have an array common source (ACS). According to some examples, the TSG 412 of each NAND memory string 408 is coupled to a respective bit line (BL) 416 from which data can be read or written via an output bus (not shown). In some examples, each NAND memory string 408 is configured to be selected or deselected by at least one of applying a select voltage (e.g., above the threshold voltage of the transistor comprising the TSG 412) or a deselect voltage (e.g., 0V) to the respective TSG 412 through one or more TSG lines 413, or applying a select voltage (e.g., above the threshold voltage of the transistor comprising the BSG 410) or a deselect voltage (e.g., 0V) to the respective BSG 410 through one or more BSG lines 415.

[0057] As shown in FIG. 4 , NAND memory strings 408 may be organized into multiple blocks 404, each of which may have a common source line 414, for example, coupled to ground. In some examples, each block 404 is the basic data unit for an erase operation, i.e., all memory cells 406 in the same block 404 are erased simultaneously. To erase memory cells 406 in a selected block 404, the source line 414 coupled to the selected block 404, as well as unselected blocks 404 in the same plane as the selected block 404, may be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20 V or greater). It will be understood that in some examples, erase operations may be performed at a half-block level, a quarter-block level, or a level having any suitable number of blocks or any suitable fraction of a block. Memory cells 406 of adjacent NAND memory strings 408 may be coupled through word lines 418 that select which rows of memory cells 406 are affected by read and program operations.

[0058] 5 shows a schematic cross-sectional view of an example memory array 401 including a NAND memory string 408 according to some embodiments of the present disclosure. As shown in FIG. 5, the NAND memory string 408 may include a stacked structure 510 including multiple gate layers 511 and multiple insulating layers 512 stacked in alternating order, and the memory string 408 vertically passing through the gate layers 511 and insulating layers 512. The gate layers 511 and insulating layers 512 may be stacked alternately, with two adjacent gate layers 511 separated by the insulating layer 512. The number of pairs of gate layers 511 and insulating layers 512 in the stacked structure 510 can determine the number of memory cells included in the memory array 401.

[0059] The constituent material of the gate layer 511 may include a conductive material. The conductive material may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some examples, each gate layer 511 may include a metal layer, such as a tungsten layer. In some examples, each gate layer 511 includes a doped polysilicon layer. Each gate layer 511 may include a control gate surrounding a memory cell. The gate layer 511 on top of the stacked structure 510 may extend laterally as a top selective gate line, the gate layer 511 at the bottom of the stacked structure 510 may extend laterally as a bottom selective gate line, and the gate layer 511 extending laterally between the top selective gate line and the bottom selective gate line may be used as a word line layer 503.

[0060] In some examples, the stacked structure 510 may be disposed on a substrate 501. The substrate 501 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0061] In some examples, the NAND memory string 408 includes a channel structure extending vertically through the stack structure 510. In some examples, the channel structure includes a channel hole filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). In some examples, the semiconductor channel includes silicon, e.g., polysilicon. In some examples, the memory film is a composite dielectric layer including a tunnel layer, a storage layer (also referred to as a "charge trap / storage layer"), and a blocking layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some examples, the semiconductor channel, the tunnel layer, the storage layer, and the blocking layer are radially arranged in this order from the center of the pillar toward the outer surface of the pillar. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0062] 4, peripheral circuitry 402 may be coupled to memory array 401 through bit lines 416, word lines 418, source lines 414, BSG lines 415, and TSG lines 413. Peripheral circuitry 402 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 401 by applying and sensing voltage and / or current signals to and from each target memory cell 406 through bit lines 416, word lines 418, source lines 414, BSG lines 415, and TSG lines 413. Peripheral circuitry 402 may include various types of circuits formed using metal-oxide-semiconductor (MOS) technology. 6 illustrates some exemplary peripheral circuits, where peripheral circuits 402 include a page buffer / sense amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, control logic 612, registers 614, an interface 616, and a data bus 618. It will be understood that in some examples, additional peripheral circuits not shown in FIG. 6 may be included as well.

[0063] The page buffer / sense amplifier 604 may be configured to read data from and program (write) data into the memory array 401 according to control signals from the control logic 612. In one example, the page buffer / sense amplifier 604 may store program data (write data) to be programmed into the memory array 401. In another example, the page buffer / sense amplifier 604 may perform a program verify operation to confirm that data has been properly programmed into the memory cells 406 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 604 may also sense low-power signals from the bit lines 416 representing data bits stored in the memory cells 406 and amplify small voltage swings to recognizable logic levels in a read operation. The column decoder / bit line driver 606 may be controlled by the control logic 612 and configured to select one or more NAND memory strings 408 by applying bit line voltages generated from a voltage generator 610.

[0064] The row decoder / word line driver 608 may be controlled by the control logic 612 and configured to select / deselect a block 404 of the memory array 401 and to select / deselect a word line 418 of the block 404. The row decoder / word line driver 608 may be further configured to drive the word line 418 using a word line voltage generated from the voltage generator 610. In some examples, the row decoder / word line driver 608 may also select / deselect and drive the BSG line 415 and the TSG line 413 as well. The row decoder / word line driver 608 is configured to perform a program operation on the memory cell 406 coupled to the selected word line 418. The voltage generator 610 may be controlled by the control logic 612 and configured to generate word line voltages (e.g., read voltages, program voltages, pass voltages, channel boost voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory array 401.

[0065] The control logic 612 may be coupled to each peripheral circuit described above, such as the voltage generator 610 and the row decoder / word line driver 608, and configured to control the operation of each peripheral circuit. The registers 614 are coupled to the control logic 612 and may include a status register, a command register, and an address register that store status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 616 is coupled to the control logic 612 and may operate as a control buffer that buffers and relays control commands received from a host (not shown) to the control logic 612 and buffers and relays status information received from the control logic 612 to the host. The interface 616 is further coupled to the column decoder / bit line driver 606 via a data bus 618 and may operate as a data I / O interface and data buffer that buffers and relays data from or to the memory array 401.

[0066] Among 3D NAND memory devices, single-level cell (SLC) has occupied a certain share of the memory market due to its advantages such as fast read and write speeds, high reliability, and long service life, while multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC) have become the development trend in the memory market due to their high memory density and large memory capacity.

[0067] However, as the number of memory bits in a memory cell increases and the number of stacked layers increases, the types of errors involved become more and more complex. When performing a read operation on a memory device, LDPC hard-decision decoding is used to decode the codeword to be decoded, which increases the decoding time and weakens the error correction ability, seriously affecting the read speed.

[0068] Based on the memory device and memory system described above, in order to solve one or more of the above-mentioned problems, reference is made to Figure 7, which is a schematic structural diagram of a decoder according to an example of the present disclosure.

[0069] In some examples, the decoder 700 includes a cache module 701 and a flip indication module 702; a cache module 701 configured to cache soft data related to a codeword to be decoded; The flip instruction module 702 is configured to retrieve the soft data from the cache module 701 and, when performing hard-decision decoding on the codeword to be decoded, determine, at least in a first flip iteration, with the help of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded.

[0070] It should be noted that the decoder provided by the example of the present disclosure can be applied to the aforementioned memory system, and the decoder 700 can be set in the decoding section of the memory controller as shown in FIG. 3 and configured to perform a decoding operation on a codeword to be decoded. Here, the codeword to be decoded can refer to hard read data that can be read from the memory device by the memory controller according to a hard read voltage, or the codeword to be decoded can also be a codeword flipped at a specific iteration during decoding. Whether the codeword to be decoded is hard read data or a codeword flipped at a specific iteration will be described in detail later and will not be repeated here.

[0071] Here, the hard read voltage may be an initial read voltage, which is a default read voltage preset by the memory system. The default read voltage may be the same as a reference voltage in a read retry table (RRT) or may have a specific offset from the reference voltage, where the offset is included in the RRT. Alternatively, the hard read voltage may be an optimal read voltage. A method for obtaining the optimal read voltage includes, but is not limited to, determining the optimal read voltage according to the use of the memory device and the RRT. A specific process includes traversing the RRT and determining a voltage offset within the RRT with a minimum error when reading the memory device in this use case, and then obtaining the optimal read voltage based on the reference voltage and the determined voltage offset.

[0072] It should be noted that the RRT is a table containing multiple voltage offsets, each of which is relative to a reference voltage. These voltage offsets can be realized by a hardware circuit in a memory. For example, these voltage offsets can be set through a register included in the memory. In other words, the required voltage offsets for all read voltages are obtained based on the RRT table, and then superimposed with the reference voltage (including sign superimposition, i.e., if the voltage offset is negative, the final read voltage is lower than the reference voltage), thereby obtaining the required voltage value, which is then applied to the corresponding word line.

[0073] Regarding RRT, for example, as shown in Table 1, this is the RRT corresponding to a TLC-type memory cell according to an example of the present disclosure. Each column in Table 1 represents a set of voltage offsets, Rd1 through Rd7, that distinguish adjacent programming states relative to the corresponding reference voltage. Note that a TLC-type memory cell has eight data states, which can be distinguished by using seven read voltages, i.e., there are seven columns in Table 1.

[0074] The set of voltage offsets described above may include positive offsets that increase above the reference voltage and negative offsets that decrease below the reference voltage. For example, in Rd7, +V1, +V2, +V3, and +V4 are positive offsets, with V1, V2, V3, and V4 increasing in value, while −V5 to −V11 are negative offsets, with V5 to V11 decreasing in value.

[0075] [Table 1]

[0076] Referring back to the decoder shown in Figure 7, the soft data used in the decoder may be a kind of probability information used to measure the reliability of specific read data (such as the hard read data in the example of this disclosure) and may be represented by a log-likelihood ratio (LLR). Thus, the read data serves as a benchmark for measuring the reliability of the soft data.

[0077] For the soft data, see FIG. 8 . In FIG. 8 , it is assumed that the hard read data read at an optimal read voltage is 1100, and the data read at a first re-read voltage is 1000, where the first re-read voltage is to the left of the optimal read voltage and deviates from the optimal read voltage by a certain offset represented as −Δ. The data read at a second re-read voltage is 1110, where the second re-read voltage is to the right of the optimal read voltage and deviates from the optimal read voltage by a certain offset represented as +Δ. Correspondingly, the soft data may be 0110. In this case, the soft data may be used to determine the reliability of the hard read data 1100 / 1000 / 1110. In some examples, the soft data is used to determine the reliability of the hard read data, and a “0” bit in the soft data indicates a relatively high reliability of the bit in the hard read data. In other words, the bit is determined to be closer to truth. A “1” bit in the soft data indicates a weak reliability of the bit in the hard read data. 8, the reliability of the hard read data 1100 is determined by using the soft data 0110, where the leftmost bit of the hard read data 1100 is "1" and the number corresponding to that bit in the soft data is "0", so the reliability of that bit is relatively high, i.e., a strong "1". By analogy, the middle two bits in the hard read data 1100 correspond to "1" in the soft data, so the reliability of the middle two bits is weak, i.e., a weak "1" or "0", and the rightmost bit of the hard read data 1100 is a strong "0".

[0078] In some examples, the method for obtaining the soft data may include directly reading the soft data from the NAND memory device, as shown in Figure 8. In some examples, the memory controller may send a command to the memory device to read the soft data, and the memory device feeds the soft data back to the memory controller. In some other examples, the soft data may be based on an XOR result of two adjacent hard read data that are pre-cached in the memory of the memory controller.

[0079] When performing hard-decision decoding on a codeword to be decoded, the decoder provided by the example of the present disclosure obtains soft data related to the codeword to be decoded, which is buffered by a buffer module within the decoder, and then determines the number of parity checks that are not satisfied by bits in the codeword to be decoded with the help of the soft data. The hard-decision decoding may be LDPC bit-flip decoding. In LDPC bit-flip decoding, fast-read soft data is used to assist LDPC bit-flip decoding in at least the first flip iteration, thereby significantly improving the correction capability of LDPC bit-flip decoding. Using soft data to assist bit-flip decisions in at least the first flip iteration may be performed only in the first flip iteration, or in the first and second flip iterations, or in multiple flip iterations, etc.

[0080] Here, an unsatisfied parity check may mean that after the codeword to be decoded is checked once by the check matrix, each non-zero element in the generated checksum vector corresponds to an unsatisfied parity check equation involving bits in the codeword to be decoded. The number of parity checks that are unsatisfied by bits in the codeword to be decoded may refer to the number of parity check equations involving bits in the codeword to be decoded that are non-zero elements.

[0081] As an example, suppose the codeword to be decoded is C1C2C3C4C5C6C8C9C10C11C12, then the checksum vector that is filled in one check is

[0082]

number

[0083] This becomes:

[0084] In this case, the number of parity checks not satisfied by bits in the codeword are C1:2, C2:2, C3:0, C4:1, C5:2, C6:1, C7:1, C8:0, C9:0, C10:1, C11:0, and C12:1, respectively.

[0085] In some examples, the flip instruction module 702: determining an initial error bit indicator vector corresponding to a codeword to be decoded; determining, with the aid of soft data in combination with the initial error bit indicator vector, the number of parity checks not satisfied by bits in the codeword to be decoded; The device may be further configured to:

[0086] Note that in some examples, this operation is to use soft data to assist in determining the number of parity checks that are not satisfied by bits in the codeword to be decoded. In some examples, an initial error bit indication vector for the codeword to be decoded is first determined. The initial error bit indication vector may refer to the number of parity checks that are not satisfied by bits in the codeword to be decoded when only LDPC bit flip decoding is performed without the aid of soft data. Then, the number of parity checks that are not satisfied by bits in the codeword to be decoded is determined with the aid of the soft data in combination with the initial error bit indication vector.

[0087] In some examples, the flip instruction module 702: determining a soft data vector corresponding to the soft data; performing a summation operation on the soft data vector and the initial error bit indicator vector to obtain a target error bit indicator vector; determining the number of parity checks not satisfied by each bit in the codeword to be decoded according to the target error bit indication vector; further configured to: Each element of the target error bit indication vector corresponds to the number of parity checks that are not satisfied by a single bit.

[0088] Please note that the following describes how to determine the number of parity checks that are not satisfied by bits in a codeword to be decoded with the help of soft data combined with an initial error bit indicator vector.In some examples, the soft data is first represented in the form of a soft data vector.Then, a summation operation is performed on the soft data vector and the initial error bit indicator vector to obtain a target error bit indicator vector, and each element of the target error bit indicator vector corresponds to the number of parity checks that are not satisfied by one bit.

[0089] For example, suppose the initial error bit vector is {0, 1, 1, 0}, then the soft data vector corresponding to the soft data is {0, 1, 1, 0}, and the target error bit vector is {0, 2, 2, 0}, where the number of parity checks unsatisfied by the first bit in the codeword to be decoded is 0, the number of parity checks unsatisfied by the second bit in the codeword to be decoded is 2, the number of parity checks unsatisfied by the third bit in the codeword to be decoded is 2, and the number of parity checks unsatisfied by the fourth bit in the codeword to be decoded is 0.

[0090] According to an example of the present disclosure, as shown in Figure 9, to obtain an initial error bit indication vector in some examples, the decoder 700 further includes a variable node module 703 and a check node module 704. The node module and the check node module are connected to form a variable check connection network according to a pre-constructed check matrix; the variable node module 703 is configured to receive the hard read data, generate a codeword to be decoded according to the hard read data, send the codeword to be decoded to the check node module, and send the codeword to be decoded and the hard read data to the flip indication module; the check node module 704 is configured to receive a codeword to be decoded, determine a checksum vector according to the codeword to be decoded and a check matrix, and send the checksum vector to the flip instruction module; The flip indication module 702 is further configured to receive the codeword to be decoded and hard read data sent by the variable node module, receive the checksum vector sent by the check node module, obtain the check matrix and soft data, and determine an initial error bit indication vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector, and the check matrix.

[0091] It should be noted that the decoder shown in Figure 7 only discloses the main structure related to the inventive concept of the example of this disclosure. In LDPC bit flip decoding, the decoder can further include a variable node module and a check node module. Furthermore, the variable node module can include multiple variable node units, and the check node module can include multiple check node units. The multiple variable node units and the multiple check node units are connected to form a variable check connection network according to a pre-constructed check matrix. Here, the pre-constructed check matrix refers to an LDPC check matrix, which can also be called an H matrix.

[0092] In practical applications, the variable check connection network formed above can also be called a Tanner graph, as shown in Figure 10. In Figure 10, the Tanner graph includes check nodes 1001, variable nodes 1002, and edges 1003 connecting the check nodes and the variable nodes. The values ​​transferred from the check nodes to the variable nodes after the check node processing are called check node information 1004A. The values ​​transferred from the variable nodes to the check nodes after the variable node processing are called variable node information 1004B.

[0093] 11, as an example, a Tanner graph includes five check nodes 1001 of a parity check equation of an H matrix, ten variable nodes 1002 representing code symbols, and edges 1003 representing relationships between the check nodes and the variable nodes. The edges 1003 connect each check node to a variable node corresponding to a code symbol included in the parity check equation represented by the check node. FIG. 11 shows a Tanner graph formed by an H matrix in which the number of variable nodes connected to each check node is fixed at 4, and the number of check nodes connected to each variable node is fixed at 2. The initial values ​​of the variable nodes can be hard read data.

[0094] 9, the variable node module can receive hard read data, generate a codeword to be decoded according to the hard read data, send the codeword to be decoded to the check node module, and send the codeword to be decoded and the hard read data to the flip instruction module. The check node module can receive the codeword to be decoded, determine a checksum vector according to the codeword to be decoded and the aforementioned check matrix, and send the checksum vector to the flip instruction module. The flip instruction module can receive the aforementioned codeword to be decoded, hard read data, and checksum vector, obtain the check matrix, and then obtain an initial error bit indication vector according to the codeword to be decoded, hard read data, checksum vector, and check matrix.

[0095] Based on the above description, it should be noted that the decoder can be located within the decoding section of the memory controller. Therefore, the hard read data received by the variable node module can be a read command corresponding to the processor. In this case, the read data fed back by the memory device through the memory I / F is directly transmitted to the variable node module via the bus. Alternatively, the hard read data received by the variable node module can be a read command corresponding to the processor. In this case, the read data fed back by the memory device through the memory I / F is temporarily stored in the memory, and the hard read data is retrieved from the memory by the processor and transmitted to the variable node module. Any other process that can retrieve the hard read data is also possible. Generally, the decoder is located within the memory controller and is coupled with other components, such as the processor, via the bus. Therefore, the variable node module can receive the hard read data from outside the decoder. After the variable node module receives the hard read data, the value of each bit of the hard read data is assigned to a corresponding variable node unit to generate a codeword to be decoded.

[0096] Determining the checksum vector according to the codeword to be decoded and the aforementioned check matrix may be implemented by multiplying the check matrix with the transpose of the codeword to be decoded to obtain the checksum vector.

[0097] For a codeword to be decoded, hard read data, a checksum vector, and an initial error bit indication vector obtained using a parity check matrix, in some examples, the flip indication module 702 may: performing a summation operation on the hard read data and the codeword to be decoded, and then performing a modulo operation on the summation to obtain a first bit vector; multiplying the transpose of the checksum vector by a parity check matrix to obtain a second bit vector; performing a summation operation on the first bit vector and the second bit vector to obtain an initial error bit indicator vector; The device is further configured to:

[0098] It should be noted that the specific operation described here is how to obtain an initial error bit indicator vector by using a codeword to be decoded, hard read data, a checksum vector, and a parity check matrix. In some examples, a first bit vector is obtained by performing a summation operation on the hard read data (the codeword to be decoded in the first iteration flip) and the codeword to be decoded, and then performing a modulo operation on the summation, a second bit vector is obtained by multiplying the transpose of the checksum vector by the parity check matrix, and then the initial error bit indicator vector is obtained by performing a summation operation on the first bit vector and the second bit vector. Here, the number of elements in the first bit vector and the second bit vector is the same as the number of bits in the codeword to be decoded.

[0099] In some examples, the above calculation process may be carried out using the following formula: f1=(y+y0) mod2 + s'H and f1 is the initial error bit indication vector, each element of which corresponds to a bit in the codeword to be decoded, y is the codeword to be decoded, y0 is the hard read data, s' is the transpose of the checksum vector, and H is the check matrix.

[0100] Note that in the first flip iteration, y = y0, i.e., in the first flip iteration, the codeword to be decoded is the hard read data, and in the remaining flip iterations, the codeword to be decoded is the hard read data after bit flipping.

[0101] Based on this, in the example of the present disclosure, the target error bit indication vector is calculated by the following formula: f2=(y+y0) mod2 + s'H + R It can be expressed as f2 is the target error bit indication vector and R is the soft data.

[0102] In some examples, the flip instruction module 702: further configured to generate a flip instruction vector according to the number of unsatisfied parity checks and a flipping criterion, the flip instruction vector including the determined bits that need to be flipped in the codeword to be decoded; The variable node module is further configured to receive a flip direction vector and flip bits that need to be flipped in the codeword to be decoded according to the flip direction vector.

[0103] Here, the flipping criterion is flipping bits in the codeword to be decoded that has the largest number of unsatisfied parity checks, or Flipping bits in the codeword to be decoded for which the number of unsatisfied parity checks is equal to or exceeds a preset threshold. may include:

[0104] It should be noted that after the target error bit indication vector is obtained, the number of parity checks not satisfied by each bit in the codeword to be decoded is obtained. Then, the flip indication module obtains a flip indication vector according to the obtained number of parity checks not satisfied by each bit and a flipping criterion. Then, the variable node module flips the bits to be flipped in the codeword to be decoded according to the flip indication vector. Here, the flipping criterion includes, but is not limited to, flipping the bits in the codeword to be decoded that have the largest number of unsatisfied parity checks, and flipping the bits in the codeword to be decoded that have the number of unsatisfied parity checks equal to or greater than a preset threshold. In the above description, only the bits corresponding to the largest data in f2 are flipped, or alternatively, the bits whose data in f2 are equal to or greater than T (i.e., a preset threshold) are flipped.

[0105] In some examples, as shown in FIG. 12 , the decoder 700 further includes a counting module 704 and a termination determination module 705; the counting module 704 is configured to count the number of hard-decision decoding iterations performed on the codeword to be decoded; The termination determination module 705 is configured to determine whether the number of iterations has reached a maximum number of iterations, determine whether the checksum vector is a zero vector, and output a first decoding stop signal when the number of iterations has reached the maximum number of iterations and the checksum vector is a non-zero vector, where the first decoding stop signal is configured to indicate that hard-decision decoding of the codeword to be decoded has failed.

[0106] It should be noted that in hard-decision decoding, the number of flipping iterations is limited. The number of flipping iterations can be counted by the counting module 704, i.e., the number of iterations is counted by the counting module. Then, the termination determination module 705 determines whether the counted number of iterations reaches the maximum iteration number and whether the checksum vector is a zero vector. When the maximum iteration number is reached and the checksum vector is a non-zero vector, a first decoding stop signal is output. The first decoding stop signal is used to indicate that the hard-decision decoding of the codeword to be decoded has failed.

[0107] In some examples, the decoder 700 further comprises a rearrangement configuration module 706, the termination determination module 705 is further configured to output a second decoding stop signal when the checksum vector is determined to be a zero vector, the second decoding stop signal being configured to indicate that hard-decision decoding of the codeword to be decoded has been successful; The rearrangement configuration module 706 is configured to, in response to the second decoding stop signal, perform rearrangement configuration on the codewords to be decoded and output the codewords to be decoded in the correct order.

[0108] It should be noted that the termination determination module 705 outputs a second decoding stop signal, and the rearrangement configuration module performs a rearrangement configuration process on the codewords to be decoded in response to the second decoding stop signal, and outputs the codewords to be decoded in the correct order, thereby completing the decoding of the hard-read data.

[0109] In some examples, the termination determination module 705 is further configured to output a continue decoding signal when the checksum vector is not a zero vector and the number of iterations has not reached a maximum number of iterations, and the continue decoding signal is configured to instruct the variable node module, the check node module, and the flip indication module to continue performing hard-decision decoding operations on the codeword to be decoded.

[0110] It should be noted that these operations may here refer to an end determination module that outputs a continue decoding signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations. The continue decoding signal is configured to instruct the aforementioned variable node module, check node module, and flip indication module to continue performing hard-decision decoding operations on the codeword to be decoded, thereby determining whether the decoding of the codeword to be decoded is successful or unsuccessful.

[0111] Based on the above description, as shown in Figure 13, which illustrates a schematic structural diagram of a decoder according to an example of the present disclosure. Note that in Figure 13, d represents hard read data, v represents a codeword to be decoded, S represents a checksum vector, I represents a flip indication vector, and stop represents a decoding stop signal, including a first decoding stop signal and a second decoding stop signal. Here, the first sub-connection network and the second sub-connection network together form a variable check node connection network.

[0112] Based on the decoder shown in Figure 13, a decoding workflow provided by an example of this disclosure may be shown in Figure 14. In some examples, a possible decoding workflow may be as follows.

[0113] S1401: Obtain hard read data y0 and soft data R, assign the hard read data to the codeword y (y=y0) to be decoded, and cache the soft data. The number of iterations is 0, where y0 is d in FIG. 13 and y is v in FIG. 13.

[0114] S1402: Generate a checksum vector by using the parity check matrix and the codeword to be decoded, and determine whether the checksum vector is a zero vector (i.e., H*y T =0?), if yes, execute S1403, otherwise execute S1404.

[0115] S1403: The codeword to be decoded that has been successfully decoded is output, and the process ends.

[0116] S1404: Determine whether the number of iterations has reached the maximum number of iterations; if yes, execute S1305; if not, execute S1406.

[0117] S1405: A decoding failure indication signal, for example, a first decoding stop signal, is output.

[0118] S1406: Calculate the number of parity checks not satisfied by bits in the codeword to be decoded using the f2 formula.

[0119] S1407: Determine the bits that need to be flipped in the codeword to be decoded according to the number of unsatisfied parity checks and the flipping criterion.

[0120] S1408: The iteration number is increased by 1, and the next iteration is continued, and steps S1402 to S1408 are continued to be executed sequentially, and this process ends when the decoding is successful or fails.

[0121] It should be noted that the method for obtaining the hard read data and soft data in operation S1401 has been described above. That is, the hard read data may be obtained by directly receiving feedback from the memory of the memory device or the memory controller. The soft data may be cached in a cache module of the decoder and then obtained from the cache module. The above-mentioned operations are only one way of implementing the decoding workflow. The execution order of each operation may be adjusted according to actual circumstances. For example, S1404 may be executed before S1402, in which case it is first determined whether the number of iterations has reached the maximum number of iterations. If the maximum number of iterations has not been reached, a checksum vector is generated by using the check matrix and the codeword to be decoded; otherwise, a decoding failure indication signal is output to terminate the process.

[0122] According to the decoder provided by the example of the present disclosure, the soft data is applied to LDPC bit-flipping (i.e., hard-decision) decoding. The strong error correction ability of the soft data is utilized to speed up the LDPC bit-flipping decoding, thereby reducing the power consumed by the LDPC bit-flipping decoding and improving the error correction processing ability of the decoder.

[0123] An example of the present disclosure also provides a decoding method, as shown in FIG. 15, which includes:

[0124] S1501: Obtain soft data corresponding to a codeword to be decoded.

[0125] S1502: When performing hard-decision decoding on the codeword to be decoded, at least in the first flip iteration, with the help of soft data, determine the number of parity checks that are not satisfied by bits in the codeword to be decoded.

[0126] In some examples, determining the number of parity checks not satisfied by bits in a codeword to be decoded with the aid of soft data may include: determining an initial error bit indicator vector corresponding to a codeword to be decoded; determining, with the aid of soft data in combination with the initial error bit indicator vector, the number of parity checks not satisfied by bits in the codeword to be decoded; Includes.

[0127] In some examples, determining the number of parity checks not satisfied by bits in a codeword to be decoded with the aid of soft data in combination with an initial error bit indicator vector may include: determining a soft data vector corresponding to the soft data; performing a summation operation on the soft data vector and the initial error bit indicator vector to obtain a target error bit indicator vector; determining the number of parity checks not satisfied by each bit in the codeword to be decoded according to the target error bit indication vector; Including, Each element of the target error bit indication vector corresponds to the number of parity checks that are not satisfied by a 1 bit.

[0128] In some examples, determining an initial error bit indicator vector corresponding to a codeword to be decoded may include: receiving hard read data and generating a codeword to be decoded according to the hard read data; determining a checksum vector according to a codeword to be decoded and a pre-reconstructed check matrix; determining an initial error bit indication vector corresponding to the code word to be decoded according to the hard read data, the code word to be decoded, the checksum vector, and the check matrix; Includes.

[0129] In some examples, determining an initial error bit indication vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector, and the parity check matrix includes: performing a summation operation on the hard read data and the codeword to be decoded, and then performing a modulo operation on the summation to obtain a first bit vector; multiplying the transpose of the checksum vector by a parity check matrix to obtain a second bit vector; performing a summation operation on the first bit vector and the second bit vector to obtain an initial error bit indicator vector; Includes.

[0130] In some examples, the method comprises: generating a flip direction vector according to the number of unsatisfied parity checks and a flipping criterion, the flip direction vector including determined bits that need to be flipped in the codeword to be decoded; flipping bits that need to be flipped in the codeword to be decoded according to the flip instruction vector; Further includes:

[0131] In some examples, the flipping criteria are: flipping bits in the codeword to be decoded that has the largest number of unsatisfied parity checks, or Flipping bits in the codeword to be decoded for which the number of unsatisfied parity checks is equal to or exceeds a preset threshold. Includes.

[0132] In some examples, the method comprises: counting the number of hard decision decoding iterations performed on the codeword to be decoded; determining whether the number of iterations has reached a maximum number of iterations and whether the checksum vector is a zero vector; outputting a first decoding stop signal when the number of iterations reaches a maximum number of iterations and the checksum vector is a non-zero vector, the first decoding stop signal being configured to indicate that hard-decision decoding of the codeword to be decoded has failed; Further includes:

[0133] In some examples, the method comprises: determining whether the checksum vector is a zero vector, and outputting a second decoding stop signal when the checksum vector is determined to be a zero vector; in response to a second decoding stop signal, performing a rearrangement configuration process on the code words to be decoded and outputting the code words to be decoded in the correct order; Further includes:

[0134] In some examples, the method comprises: The method further includes outputting a continue decoding signal when the checksum vector is not a zero vector and the number of iterations has not reached a maximum number of iterations, wherein the continue decoding signal is configured to instruct performing a hard-decision decoding operation on the codeword to be decoded.

[0135] It should be noted that the decoding method provided by the example of the present disclosure is actually the working process of the decoder presented above. The working process of the decoder has been described in detail above, and the terms and features appearing in this specification may refer to the above description, and will not be repeated here.

[0136] An example of the present disclosure further provides, as shown in FIG. 16 , a memory controller 1600, wherein the memory controller 1600 includes a processor 1601 and the decoder 700 described in any one of the above aspects, wherein the processor 1601 is configured to read soft data corresponding to a codeword to be decoded from a memory device; The decoder is configured to cache the soft data and, when performing hard-decision decoding on the codeword to be decoded, determine, at least in a first flip iteration, with the aid of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded.

[0137] It should be noted that the memory controller provided by the examples of the present disclosure includes the aforementioned decoder, and therefore the terminology and features of the decoder have been described in detail above and will not be repeated here.

[0138] An example of the present disclosure further provides a memory system, the memory system comprising: a memory device configured to store data; a memory controller coupled to the memory device and comprising a processor and a decoder, the processor configured to read soft data corresponding to a codeword to be decoded from the memory device; Equipped with The decoder is configured to cache the soft data and, when performing hard-decision decoding on the codeword to be decoded, determine, at least in a first flip iteration, with the aid of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded.

[0139] In some examples, the processor is further configured to read the hard read data from the memory device and send the hard read data to the decoder; The decoder is further configured to receive the hard read data and generate a codeword to be decoded according to the hard read data.

[0140] In some examples, the decoder comprises a cache module, a variable node module, a check node module, and a flip indication module; the cache module is configured to cache soft data read by the processor; the variable node module is configured to receive the hard read data read by the processor, generate a code word to be decoded according to the hard read data, and send the code word to be decoded to the check node module; The check node module is configured to receive the codeword to be decoded sent by the variable node module, determine a checksum vector according to the codeword to be decoded and a pre-constructed check matrix, and send the checksum vector to the flip instruction module; The flip indication module is configured to receive the hard read data and the codeword to be decoded sent by the variable node module, receive the checksum vector sent by the check node module, obtain the check matrix and soft data, determine an initial error bit indication vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector, and the check matrix, and determine the number of parity checks that are not satisfied by bits in the codeword to be decoded with the help of the soft data combined with the initial error bit indication vector.

[0141] It should be noted that the memory system provided by the example of the present disclosure includes the memory controller described above and a decoder included in the memory controller. Therefore, for terms and features appearing in this specification, reference may be made to the above descriptions, and they will not be repeated here.

[0142] The above description is merely a specific example of the present disclosure, and the protection scope of the present disclosure is not limited thereto. Those skilled in the art can easily come up with modifications or replacements within the technical scope of the present disclosure, which will fall within the protection scope of the present disclosure. [Explanation of symbols]

[0143] 100 systems 102 Memory System 104 Memory Devices 106 Memory Controller 108 Host 202 Memory Card 204 memory card connector 206 SSD 208 SSD connector 301 Host I / F (or Front-end Interface) 302 Memory I / F (or back-end interface) 303 processor 304 memory 305 Error Correction (ECC) Module 400 memory devices 401 Memory Array 402 Peripheral Circuit 404 Block 406 memory cells 408 NAND memory strings 410 Bottom Selective Gate (BSG) 412 Top Selective Gate (TSG) 413 TSG Line 414 Source Line (SL) 415 BSG line 416 bit lines (BL) 418 Word Line 501 PCB 510 Laminated structure 511 Gate Layer 512 Insulation layer 604 Page Buffer / Sense Amplifier 606 Column Decoder / Bit Line Driver 608 Row Decoder / Word Line Driver 610 Voltage Generator 612 Control Logic 614 registers 616 Interface 618 Data Bus 700 Decoder 701 Cache Module 702 Flip Instruction Module 703 Variable Node Module 704 Check Node Module 704 Counting Module 705 End Judgment Module 706 Relocation Configuration Module 1001 check nodes 1002 Variable Nodes 1003 Edge 1004A Inspection node information 1004B Variable node information 1600 memory controller 1601 processor 3051 Encoding Section 3052 Decoding Section

Claims

1. 1. A cache module, comprising: a cache module configured to cache soft data related to a codeword to be decoded; a flip instruction module, retrieving the soft data from the cache module; determining, at least in a first flip iteration, with the aid of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded when performing hard-decision decoding on the codeword to be decoded; a flip instruction module configured to A decoder comprising:

2. The flip instruction module includes: determining an initial error bit indicator vector corresponding to the codeword to be decoded; determining, with the aid of the soft data in combination with the initial error bit indicator vector, the number of parity checks not satisfied by the bits in the codeword to be decoded; The decoder of claim 1 , further configured to:

3. The decoder A variable node module, receiving hard read data and generating the codeword to be decoded according to the hard read data; sending the codeword to be decoded to a check node module; sending the codeword to be decoded and the hard read data to the flip indication module; a variable node module configured to: the check node module; the variable node module and the check node module are connected to form a variable check connection network according to a pre-constructed parity check matrix, and the check node module receiving the codeword to be decoded; determining a checksum vector according to the codeword to be decoded and the check matrix; sending the checksum vector to the flip instruction module; configured to The flip instruction module includes: receiving the codeword to be decoded and the hard read data transmitted by the variable node module; receiving the checksum vector transmitted by the check node module; obtaining the check matrix and the soft data; determining the initial error bit indication vector corresponding to the code word to be decoded according to the hard read data, the code word to be decoded, the checksum vector, and the parity check matrix; 3. The decoder of claim 2, further configured to:

4. The flip instruction module includes: determining a soft data vector corresponding to the soft data; performing a summation operation on the soft data vector and the initial error bit indicator vector to obtain a target error bit indicator vector; determining the number of parity checks not satisfied by each bit in the codeword to be decoded according to the target error bit indication vector; further configured to:

3. The decoder of claim 2, wherein each element in the target error bit indication vector corresponds to the number of parity checks that are not satisfied by one bit.

5. The flip instruction module includes: performing a summation operation on the hard read data and the codeword to be decoded, and then performing a modulo operation on the summation to obtain a first bit vector; multiplying the transpose of the checksum vector by the parity check matrix to obtain a second bit vector; performing a summation operation on the first bit vector and the second bit vector to obtain the initial error bit indicator vector; 4. The decoder of claim 3, further configured to:

6. The flip instruction module includes: further configured to generate a flip direction vector according to the number of unsatisfied parity checks and a flipping criterion, the flip direction vector including determined bits that need to be flipped in the codeword to be decoded; The variable node module: The decoder of claim 3 , further configured to receive the flip direction vector and flip the bits that need to be flipped in the codeword to be decoded according to the flip direction vector.

7. The flipping criteria are: flipping the bit in the codeword to be decoded that has the largest number of unsatisfied parity checks; or flipping the bits in the codeword to be decoded for which the number of unsatisfied parity checks is greater than or equal to a preset threshold.

7. The decoder of claim 6, comprising:

8. The decoder A counting module, a counting module configured to count the number of hard-decision decoding iterations performed on the codeword to be decoded; A termination determination module, determining whether the number of iterations has reached a maximum number of iterations and whether the checksum vector is a zero vector; outputting a first decoding stop signal when the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, the first decoding stop signal being configured to indicate that the hard-decision decoding of the codeword to be decoded has failed; a termination determination module configured to The decoder of claim 3 further comprising:

9. the decoder further comprises a rearrangement configuration module; The termination decision module is further configured to output a second decryption stop signal when the checksum vector is determined to be a zero vector; The relocation configuration module: performing a rearrangement configuration process on the codeword to be decoded in response to the second decoding stop signal; Outputting the codewords to be decoded in the correct order 9. The decoder of claim 8, configured to:

10. The termination determination module further configured to output a continue decoding signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations; The decoding continuation signal is 10. The decoder of claim 9, configured to instruct the variable node module, the check node module, and the flip indication module to continue performing hard-decision decoding operations on the codeword to be decoded.

11. obtaining soft data corresponding to a codeword to be decoded; determining, at least in a first flip iteration, with the aid of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded when performing hard-decision decoding on the codeword to be decoded; A decoding method comprising:

12. said step of determining, with the aid of said soft data, the number of parity checks not satisfied by said bits in said codeword to be decoded, determining an initial error bit indicator vector corresponding to the codeword to be decoded; determining, with the aid of the soft data in combination with the initial error bit indicator vector, the number of parity checks not satisfied by the bits in the codeword to be decoded; 12. The decoding method of claim 11, comprising:

13. determining the number of parity checks not satisfied by the bits in the codeword to be decoded with the aid of the soft data in combination with the initial error bit indicator vector, determining a soft data vector corresponding to said soft data; performing a summation operation on the soft data vector and the initial error bit indicator vector to obtain a target error bit indicator vector; determining the number of parity checks not satisfied by each bit in the codeword to be decoded according to the target error bit indication vector; Including, 13. The method of decoding of claim 12, wherein each element in the target error bit indication vector corresponds to the number of parity checks that are not satisfied by one bit.

14. The step of determining the initial error bit indicator vector corresponding to the codeword to be decoded comprises: receiving hard read data and generating the codeword to be decoded according to the hard read data; determining a checksum vector according to the codeword to be decoded and a pre-constructed check matrix; determining the initial error bit indication vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector, and the parity check matrix; 13. The decoding method of claim 12, comprising:

15. The step of determining the initial error bit indication vector corresponding to the code word to be decoded according to the hard read data, the code word to be decoded, the checksum vector, and the parity check matrix includes: performing a summation operation on the hard read data and the codeword to be decoded, and then performing a modulo operation on the summation to obtain a first bit vector; multiplying the transpose of the checksum vector by the parity check matrix to obtain a second bit vector; performing a summation operation on the first bit vector and the second bit vector to obtain the initial error bit indicator vector; 15. The decoding method of claim 14, comprising:

16. generating a flip direction vector according to the number of unsatisfied parity checks and a flipping criterion, wherein the flip direction vector includes determined bits that need to be flipped in the codeword to be decoded; flipping the bits that need to be flipped in the codeword to be decoded according to the flip instruction vector; The decoding method of claim 11 further comprising:

17. The flipping criteria are: flipping the bit in the codeword to be decoded that has the largest number of unsatisfied parity checks; or flipping the bits in the codeword to be decoded for which the number of unsatisfied parity checks is greater than or equal to a preset threshold.

17. The decoding method of claim 16, comprising:

18. counting the number of hard-decision decoding iterations performed on the codeword to be decoded; determining whether the number of iterations has reached a maximum number of iterations and whether the checksum vector is a zero vector; outputting a first decoding stop signal when the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, the first decoding stop signal being configured to indicate that the hard-decision decoding of the codeword to be decoded has failed; 14. The decoding method of claim 13, further comprising:

19. determining whether the checksum vector is a zero vector, and outputting a second decryption stop signal when the checksum vector is determined to be a zero vector; performing a rearrangement configuration process on the codeword to be decoded in response to the second decoding stop signal; outputting the codewords to be decoded in the correct order; 20. The decoding method of claim 18, further comprising:

20. 20. The decoding method of claim 19, further comprising: when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations, outputting a continue decoding signal, the continue decoding signal being configured to instruct performing a hard-decision decoding operation on the codeword to be decoded.

21. 1. A processor, comprising: a processor configured to read soft data corresponding to a codeword to be decoded from a memory device; A decoder according to any one of claims 1 to 10, caching the soft data; and determining, at least in a first flip iteration, with the aid of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded when performing hard-decision decoding on the codeword to be decoded; a decoder configured to A memory controller comprising:

22. a memory device configured to store data; a memory controller coupled to the memory device; The memory controller comprises:

1. A processor, comprising: a processor configured to read soft data corresponding to a codeword to be decoded from the memory device; and 1. A decoder comprising: caching the soft data; and determining, at least in a first flip iteration, with the aid of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded when performing hard-decision decoding on the codeword to be decoded; a decoder configured to A memory system comprising:

23. The processor: reading hard read data from the memory device; transmitting the hard read data to the decoder; further configured to: The decoder 23. The memory system of claim 22, further configured to receive the hard read data and generate the codeword to be decoded according to the hard read data.

24. The decoder 1. A cache module, comprising: a cache module configured to cache the soft data read by the processor; A variable node module, receiving the hard read data read by the processor and generating the codeword to be decoded according to the hard read data; transmitting the codeword to be decoded to a check node module; a variable node module configured to: The check node module, receiving the codeword to be decoded transmitted by the variable node module; determining a checksum vector according to the codeword to be decoded and a pre-constructed check matrix; sending the checksum vector to a flip instruction module; the check node module configured to: The flip instruction module, receiving the hard read data transmitted by the variable node module and the codeword to be decoded; receiving the checksum vector transmitted by the check node module; obtaining the check matrix and the soft data; determining an initial error bit indication vector corresponding to the code word to be decoded according to the hard read data, the code word to be decoded, the checksum vector, and the parity check matrix; determining, with the aid of the soft data in combination with the initial error bit indicator vector, the number of parity checks not satisfied by bits in the codeword to be decoded; the flip instruction module configured to 24. The memory system of claim 23, comprising:

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