Edge capacitive coupling for quantum chips

Abstract

A quantum computing chip device provides edge-based capacitive intra-chip connections. A first chip includes a first signal line having a distal end located near or on an edge of the first chip and a proximal end located away from the edge of the first chip. A second chip includes a second signal line having a distal end located near or on the edge of the second chip and a proximal end located away from the edge of the second chip. The first and second signal lines are configured to carry signals. The second signal line of the second chip is aligned for capacitive bus connection to the first signal line of the first chip. (Figure 1)

Description

[Technical Field]

[0001] The present disclosure relates generally to electrical devices, and more particularly to edge capacitive coupling for quantum chips. [Background technology]

[0002] Quantum computing chips are generally larger than those used in conventional CMOS electronics. At some point, the ability to create and deliver increasingly larger quantum chips becomes challenging. At this point, in order to increase the size of quantum devices, it becomes desirable to connect individual quantum chips together to effectively form larger devices. When connecting two qubits together, there is a requirement that the qubit state be maintained between the two qubits. However, the qubit circuitry is highly susceptible to picking up interference or some other undesired signal from the environment. In addition, the connection between the qubits should have low loss. "Loss" in this context is generally characterized by the frequency range of the qubits and associated with the resonant structure on the qubit chip, which may be, for example, on the order of several gigahertz.

[0003] In electrical connections where a dielectric is present, the loss tangents of commonly used dielectric materials are typically so irreversible in nature that their use in quantum computing systems would destroy the quantum states in the qubit chains. For example, 1×10 -3 A dielectric material with a loss tangent of 100 s and intimately connected to the qubits and resonators present on quantum devices operating in the gigahertz range essentially limits the operation of the device to approximately microseconds before energy dissipates and the qubit state is lost across the qubit connections. Practically speaking, suitable dielectric materials have a loss tangent of 100 s so that they can be used in qubit connections. -6 or 10 -7However, such dielectric materials are inadequate, making their availability and use impractical. Accordingly, there are limited choices of materials available for constructing the electrical connections of qubits. Summary of the Invention

[0004] According to an embodiment of the present disclosure, a quantum computing chip device is provided. The quantum computing chip device includes a first chip. The first chip includes a first signal line. The first signal line has a distal end located near or on an edge of the first chip and a proximal end located away from the edge of the first chip. The quantum computing chip device also includes a second chip. The second chip includes a second signal line. The second signal line has a distal end located near or on an edge of the second chip and a proximal end located away from the edge of the second chip. The second signal line of the second chip is aligned and positioned for capacitive bus connection to the first signal line of the first chip. The first signal line and the second signal line are configured to transmit signals. The alignment of the first signal line of the first chip with the second signal line of the second chip provides improved chip-to-chip coupling in the quantum computing device. By using edge-based coupling, an indirect signal connection is made via a capacitive field generated by the first signal line and the second signal line. The edge-based capacitive coupling arrangement increases the number of qubits transmitted between quantum computing elements in a system, which increases the quantum computing efficiency of the system.

[0005] In one embodiment that may be combined with the preceding embodiments, the distal end of the first signal line is spaced from the edge of the first chip by substrate material. By allowing some substrate material between the signal line and the edge of the chip, guaranteed spacing is provided between signal lines of cooperating chips that form capacitive-based coupling. The physical spacing prevents unintended galvanic coupling between chips, which could lose qubits in intra-chip connections.

[0006] According to an embodiment of the present disclosure, a quantum computing chip is provided. The quantum computing chip includes a substrate. The substrate includes a first end and a second end. The quantum computing chip also includes a first superconducting metal signal line. The first superconducting metal line has a first end located intermediate the first end of the substrate and the second end of the substrate. The second end of the superconducting metal line is located at an edge of the second end of the substrate. The quantum computing chip also includes a second superconducting metal signal line. The second superconducting metal signal line has a first end located intermediate the first end of the substrate and the second end of the substrate. The second end of the second superconducting metal signal line is located proximate to an edge of the second end of the substrate. The first and second superconducting metal signal lines are configured to generate a capacitive field. Embodiments improve intra-chip connections in quantum computing applications by generating an edge-based capacitive field for transmitting signals. Edge-based capacitance signaling allows adjacent chips to send signals to each other even when the chips are part of typically incompatible technologies that do not traditionally connect to each other at the intra-chip level.

[0007] In one embodiment that may be combined with the preceding embodiments, the second end of the first superconducting metal signal wire and the second end of the second superconducting metal signal wire are located on a route that extends from a top surface of the substrate, over the edge of the second end of the substrate, and over a sidewall of the second end of the substrate by routing a signal.

[0008] According to an embodiment of the present disclosure, a method for fabricating a quantum computing device is provided. The method includes forming a chip substrate. One or more signal lines of superconducting metal are formed on a top surface of a first chip substrate proximate to or in contact with an edge of the top surface of the first chip substrate. A second chip substrate is formed. One or more signal lines of superconducting metal are formed on a top surface of a second chip substrate proximate to or in contact with an edge of a second top surface of the second chip substrate. A first distal end of the first signal line(s) is positioned proximate to a second distal end of the second signal line(s). The first signal line(s) and the second signal line(s) form a capacitive-based bus connection when a signal passes through either the first signal line(s) or the second signal line(s). The method represents an improvement over current fabrication methods, as other methods are typically designed for galvanic connections, the yield of which is a challenge for testing before cutting the chip die. Discontinuities and other defects in galvanic-based lines cannot be tested until the chip is diced. The capacitive-based signal lines formed in the above embodiments can be pre-tested before dicing the chip because the integrity of the signal lines is independent of other signal lines.

[0009] In one embodiment that may be combined with the preceding embodiments, a method includes forming a first conductive bump on a first one or more signal lines and forming a second conductive bump on a second one or more signal lines. The first and second conductive bumps form a capacitive-based bus connection. Typically, the bumps only function as physical connection points for wires or traces or as spacers to create gaps between different layers of material. As can be appreciated, the bumps of the instant disclosure can provide a dual function as spacers to adjacent modules while providing edge-based capacitive connections.

[0010] The techniques described herein may be implemented in numerous ways. Exemplary implementations are provided below with reference to the following figures. [Brief explanation of the drawings]

[0011] The drawings are of exemplary embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for a more efficient illustration. Some embodiments may be practiced with additional components or steps and / or without all of the components or steps illustrated. When the same numeral appears in different drawings, it refers to the same or similar components or steps.

[0012] [Figure 1] 1 is a schematic side view of a quantum computing device having edge-based capacitive connections between a pair of quantum computing modules according to an embodiment.

[0013] [Figure 2A] FIG. 1 illustrates a side top perspective view of an interposer having an edge-based capacitor according to an embodiment for use in a quantum computing device.

[0014] [Figure 2B] FIG. 2B is a top view of the interposer of FIG. 2A.

[0015] [Figure 3A] FIG. 10 is a side top perspective view of an interposer having an edge-based capacitor according to another embodiment for use in a quantum computing device.

[0016] [Figure 3B] FIG. 3B is a top view of the interposer of FIG. 3A.

[0017] [Figure 3C]FIG. 3C is a top view of the interposer of FIG. 3B, where the capacitor plates are cut in half by the formation of trenches according to one embodiment of a manufacturing process.

[0018] [Figure 4A] FIG. 1 illustrates a side top perspective view of an edge-based capacitor interposer according to an embodiment for use in a quantum computing device.

[0019] [Figure 4B] FIG. 4B is a top view of the interposer of FIG. 4A.

[0020] [Figure 5A] FIG. 1 is a side top perspective view of an interposer with edge-based capacitors and standoffs according to an embodiment for use in a quantum computing device.

[0021] [Figure 5B] FIG. 5B is a top view of a quantum computing device connection using two of the interposers shown in FIG. 5A.

[0022] [Figure 6A] FIG. 1 is a side top perspective view of an interposer having edge-based capacitors and capacitive bumps according to an embodiment for use in a quantum computing device.

[0023] [Figure 6B] FIG. 6B is a top view of a quantum computing device connection using two of the interposers shown in FIG. 6A.

[0024] [Figure 7A] FIG. 1 is a side top perspective view of an interposer with an edge-based capacitor and a coupled chip according to an embodiment for use in a quantum computing device.

[0025] [Figure 7B]FIG. 7B is a top view of a quantum computing device connection using two of the interposers shown in FIG. 7A. DETAILED DESCRIPTION OF THE INVENTION

[0026] [overview] In the following detailed description, numerous specific details are set forth, by way of example, in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and / or circuits have been described relatively broadly and without detail in order to avoid unnecessarily obscuring aspects of the present teachings.

[0027] In one aspect, spatial terms such as "front," "back," "top," "bottom," "beneath," "below," "lower," "above," "upper," "side," "left," "right," and the like, are used with reference to the orientation of the illustrated figures. Because components of the embodiments of the present disclosure may be positioned in many different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It will therefore be understood that the spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, for example, the term "below" can encompass both an orientation of above as well as below. The device may be oriented differently (rotated 90 degrees or viewed or referenced in other directions) and the spatially related descriptors used herein should be interpreted accordingly.

[0028] As used herein, the terms "lateral," "planar," and "horizontal" describe an orientation parallel to a first surface of a chip or substrate.

[0029] As used herein, the term "vertical" describes an orientation that is disposed perpendicular to a first surface of a chip, chip carrier, chip substrate, or semiconductor body.

[0030] As used herein, the terms "coupled" and / or "electrically coupled" are not intended to imply that elements must be directly coupled together - intervening elements may be provided between "coupled" or "electrically coupled" elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present. The term "electrically connected" refers to a low ohmic electrical connection between the elements electrically connected together.

[0031] Although terms such as first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as the first element, without departing from the scope of the exemplary embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of regions of a device and are not limiting in scope. It should be understood that the figures and / or drawings accompanying this disclosure are illustrative and non-limiting, and are not necessarily drawn to scale.

[0033] It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the spirit and scope as defined by the claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0034] Referring to the figures, embodiments of the subject technology provide electrical connections in quantum computing circuits. The subject electrical structures maintain qubit states as signals propagate along readout chains in quantum computing circuits. In exemplary embodiments, quantum computing devices of the subject technology use capacitive coupling to the edges of chips or modules in the circuit to provide bus connections between different circuit elements. The capacitor structures disclosed herein may use superconducting wires located near or on the edge surfaces of adjacent chips or modules. When placed near each other, superconducting wires from one chip create a capacitive relationship with the superconducting wires of an adjacent chip. As will be appreciated, the dielectric features in this structure provide the quality factor necessary to transmit quantum bit outputs between circuit elements while maintaining the integrity of the qubit states at the output.

[0035] Referring now to FIG. 1 , a pair of quantum computing modules 100 are shown that are exemplary of the subject technology. Quantum computing modules 100 may be part of a larger quantum computing system (not shown) and, in some embodiments, may represent quantum computing devices, in that there may be circuitry formed between computing elements on one module 100 whose output is transmitted to a second module 100. In a general embodiment, quantum computing module 100 includes an interposer chip 110, a quantum processing unit (QPU) or central processing unit (CPU) 120. In a QPU, there may be multiple interconnected qubits. QPU / CPU 120 may be coupled to interposer chip 110. Signals from QPU / CPU 120 may be transmitted to interposer chip 110 via connection layer 130. Interposer chip 110 includes a substrate 140. In some embodiments, substrate 140 may be, for example, silicon, sapphire, magnesium oxide, or quartz; however, other materials may be used depending on the application. One or more signal lines 150 are located on or near the edge of one substrate 140, aligned with signal lines 150 of (also located on or near) the edge of the second substrate 140, to create a shared capacitive bus connection between the first interposer and the second interposer 110. The signal lines 150 define the capacitor elements of each cooperating interposer 140. Typically, the signal lines 150 use superconducting metal to form superconducting capacitors. In some embodiments, the signal lines 150 of each module 100 can be separated by air, providing a vacuum gap. The capacitive bus connection of a quantum computing device has a low loss tangent because it avoids the use of dielectrics with poor quality factors. Thus, a signal from one QPU / CPU 120 can be transmitted to a second QPU / CPU 120 with the qubit states intact.

[0036] 2A / B through 7A / B illustrate various contemplated embodiments providing edge-based capacitive connections between quantum computing modules 100. Similar elements use the same reference numerals, updated serially relative to the figure numbers. For example, chip 110 is labeled by numeral "210" in FIGS. 2A / B, "310" in FIGS. 3A / B, and so on. Similarly, substrate 140 in FIG. 1 is labeled by numeral "240" in FIGS. 2A / B, "340" in FIGS. 3A / B, and so on. Unless otherwise noted, elements illustrated in one embodiment and figure may be the same element having the same structure in subsequent figures, even if they use different reference numerals relative to the illustrated embodiment. Therefore, some elements that are common between different embodiments may not be repeatedly described or referenced. Additionally, references to a "proximal end" should be considered to be the side of the structure away from the mating surface or edge (and the like) of substrate 140. References to "distal" should be considered to be the end closest to the mating surface in the structure shown.

[0037] 2A and 2B, an interposer chip 210 according to an embodiment is shown. The interposer chip 210 may include a trench etched from the substrate 240 and lined with superconducting metal that defines elements of the capacitor signal line 250. The superconducting metal fills the trench and extends inwardly below the top surface of the substrate 240. In some embodiments, the trench may be filled with a dielectric, if necessary. In the illustrated embodiment, the trench may be positioned so that the signal line 250 terminates adjacent to, but spaced apart from, an edge 285 of an end face 280 of the substrate 240. The end face 280 may be on a sidewall of the chip 210. The end face 280 may be considered herein as a mating surface that would face toward the opposing mating surface of an adjacent interposer chip 210. FIG. 1 may be referenced as an example showing mating surfaces of opposing chips 110 facing each other to provide a capacitive connection. The chip 210 is diced and then optionally polished to position the trench near the edge 285 of the substrate 240. In some embodiments, the substrate 240 can be a high-quality single-crystal material. Some substrate material can remain to buffer the distal end of the trench from the mating surface 280 and provide some guaranteed spacing of the distal end of the trench relative to the edge 285. In some embodiments, capacitor pads 255 can be formed on the distal end of the trench using a superconducting metal. The capacitor pads 255 can be formed by a liner in the trench, with the exterior of the liner positioned to face the mating surface 280 of the adjacent chip 210. Substrate material can be present between the capacitor pads 285 and the mating surface 280. Placing two chips 210 close to each other with the capacitor pads 285 (or the distal ends of the capacitor 250 lines if they are not present) facing each other leaves double the gap of substrate material between the pads. In this embodiment, the substrate 240 material serves as a dielectric feature.

[0038] Referring now to Figures 3A, 3B, and 3C, an interposer chip 310 according to an embodiment is shown. The interposer chip 310 is similar to the interposer chip 210, except that a different signal line 350 capacitor structure is used. As shown in Figure 3C, the embodiment shows a chip structure fabricated by creating a trench in the chip die with capacitor pads 355 formed therein and then cutting through the middle of the trench. The capacitor is then formed by pressing two chip modules together, with the spacing between the capacitor pads 355 defined by the width of the trench. Figure 3B does not show the trench formed along the lines of the capacitor pads 355.

[0039] The interposer chip 310 includes signal lines 350 that extend toward or protrude through the mating surface 380, so that the superconducting metal can be exposed through the mating surface 380. In embodiments including capacitor pads 355, the capacitor pads 355 can be flush with or protrude from the mating surface 380. In this embodiment, fabrication is the same as the structure disclosed in FIGS. 2A and 2B, except that singulation of the chip 310 can occur through trenches, so that the final capacitor pads 355 are formed by liners on the inner walls of the trenches. Chip singulation from the wafer can be performed by mechanical dicing or laser dicing. Dicing can pass through the trenches, cutting the metal liner of the trench in half, with the inner coating serving as the capacitor pads 355. Thus, cutting occurs through the trenches, where the interior of the liner is the "active surface" of the capacitor.

[0040] 4A and 4B show an embodiment similar to that shown in Figures 3A and 3B, except that there are no trenches used in forming signal lines 450. In this embodiment, metal is deposited as a layer on the top surface of substrate 440 and patterned onto edge 485 of chip 410, covering a portion of mating surface 480, so that the metallization on the top surface connects to the metallization on the edge and mating surface.

[0041] 5A and 5B illustrate an embodiment similar to that shown in FIGS. 4A and 4B. The interposer chip 510 includes superconducting metal signal lines 550 on its top surface and edge 585. The illustrated interposer chip 510 also includes one or more standoffs 560 located on its mating surface 580. When the interposer chip 510 is placed in a capacitor circuit connecting separate modules, the standoffs 560 define a separation gap between the chip substrates 540. Embodiments may include standoffs 560 on only one of the interposers 510 or on both interposers 510. If both interposers 510 include standoffs 560, the standoffs 560 from each substrate 540 are aligned with one another, so that the length of the standoffs 560 from each interposer 510 can be considered when designing the separation between the substrates 540 and the capacitance of the resulting connection.

[0042] 6A and 6B, an interposer 610 is shown that is similar to interposers 310, 410, and 510, except that metallization for signal lines 650 may be deposited only on the top surface of substrate 640 (and not on edge 685 or mating surface 680). Interposer 610 may include bumps 660 located on the top surface of substrate 640. Bumps 660 may be metallic (e.g., solder bumps). Bumps 660 are electrically connected to signal lines 650. Bumps 660 may be located on or proximate to the distal ends of signal lines 650. When opposing interposers 610 are located near each other, bumps 660 cooperate to form a capacitive field.

[0043] 7A and 7B show another embodiment of an interposer 710 similar to interposer 610, except that instead of using bumps 660, a coupling chip 770 on the top surface of substrate 740 may bridge signal lines 750. Coupling chip 770 may be made of metal. The distal end of coupling chip 770 may protrude beyond edge 785 of substrate 740. When the pair of interposers 710 are positioned for electrical connection, the distal end of each coupling chip 770 forms a capacitive-based coupling from one interposer 710 to the other interposer 710.

[0044] [Conclusion] The description of various embodiments of the present teachings is presented for purposes of illustration and is not intended to be exhaustive or limiting to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0045] While the foregoing describes what is considered to be best mode and / or other examples, it is understood that various modifications may be made thereto and that the subject matter disclosed herein may be implemented in various configurations and examples, and that the teachings may be applied in numerous applications, only some of which are described herein. It is intended by the following claims to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0046] The components, steps, features, objects, benefits, and advantages described herein are exemplary only. Neither their description nor their context is intended to limit the scope of protection. While various advantages have been described herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, estimates, positions, dimensions, sizes, and other specifications described herein and included in the following claims are approximate and not exact. They are intended to have a reasonable range consistent with the function they relate to and that which is customary in the art to which they pertain.

[0047] Numerous other embodiments are contemplated, including embodiments having fewer, additional, and / or different components, steps, features, objects, benefits, and advantages, as well as embodiments in which the components and / or steps are arranged and / or ordered differently.

[0048] While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term "exemplary" is intended as an example only, not as best or optimal. Except as immediately noted, nothing described or illustrated is intended or should be construed as conferring upon the public any component, step, feature, object, benefit, advantage, or equivalent, whether claimed or not.

[0049] Terms and expressions used herein will be understood to have the ordinary meanings ascribed to such terms and expressions relative to their corresponding respective fields of study and research, unless a specific meaning is otherwise stated herein. Relationship terms such as first, second, and the like may be used solely to distinguish one entity or operation from another, without necessarily requiring or implying any actual relationship or order between such entities or operations. The terms "comprises," "comprising," or any other variation thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that includes a list of elements may include not only those elements, but also other elements not expressly listed or inherent in such process, method, article, or apparatus. An element preceded by "a" or "an" does not, without further constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0050] The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, various features may be found grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. a first chip including a first signal line having a distal end located near or on an edge of the first chip and a proximal end located away from the edge of the first chip; and a second chip including a second signal line having a distal end located near or on an edge of the second chip and a proximal end located away from the edge of the second chip; Equipped with the second signal lines of the second chip are aligned and positioned for capacitive bus connection to the first signal lines of the first chip; The first signal line and the second signal line are configured to transmit signals. Quantum computing chip device.

2. The quantum computing chip device of claim 1 , wherein the distal end of the first signal line is spaced from the edge of the first chip by substrate material.

3. 10. The quantum computing chip device of claim 1, wherein the first signal line is located on a top surface of the first chip, over the edge of the first chip, and on a sidewall mating surface of the first interposer.

4. 10. The quantum computing chip device of any preceding claim, further comprising a trench in a substrate of the first chip, the first signal line being embedded in the trench.

5. 10. The quantum computing chip device of any preceding claim, further comprising a capacitor pad on a distal end of the first signal line and adjacent the edge of the first chip.

6. 6. The quantum computing chip device of claim 5, wherein the capacitor pads are embedded in a substrate of the first chip and spaced from the edge of the first chip.

7. 10. The quantum computing chip device of claim 1, further comprising a front surface of the distal end of the first signal line, the front surface of the distal end of the first signal line being exposed through a sidewall of the first chip.

8. The quantum computing chip device of claim 7 , wherein the front surface of the distal end of the first signal line is flush with the sidewall of the first chip.

9. 10. The quantum computing chip device of any preceding claim, further comprising standoffs on sidewalls of the first chip.

10. 10. The quantum computing chip device of any preceding claim, further comprising a bump on a top surface of the first chip.

11. 10. The quantum computing chip device of any preceding claim, further comprising a first bump coupled to the first signal line and positioned to provide capacitance in cooperation with a second bump located on the second signal line.

12. 10. The quantum computing chip device of any preceding claim, further comprising a metallic chip coupled to the first signal line, the metallic chip protruding beyond the edge of the first chip and positioned to provide capacitance in cooperation with a second metallic chip coupled to the second signal line.

13. a substrate having a first end and a second end; a first end located intermediate the first end of the substrate and the second end of the substrate; and a second end located on an edge of the second end of the substrate; a first superconducting metal signal line having: a first end located intermediate the first end of the substrate and the second end of the substrate; and a second end located adjacent an edge of the second end of the substrate; wherein the first superconducting metal signal line and the second superconducting metal signal line are configured to generate a capacitive field. A quantum computing chip comprising:

14. 14. The quantum computing chip of claim 13, wherein the second end of the first superconducting metal signal wire and the second end of the second superconducting metal signal wire are located at routes extending from a top surface of the substrate, over the edge of the second end of the substrate, and over a sidewall of the second end of the substrate.

15. 15. The quantum computing chip of any of claims 13 to 14, wherein the second end of the first superconducting metal signal wire and the second end of the second superconducting metal signal wire are exposed through the second end of the substrate.

16. 16. The quantum computing chip of any preceding claim 13 to 15, wherein the first superconducting metal signal line and the second superconducting metal signal line are embedded in the substrate.

17. 17. The quantum computing chip of any preceding claim 13 to 16, further comprising one or more standoffs located on a sidewall of the second end of the substrate.

18. 20. The quantum computing chip of claim 17, wherein the one or more standoffs are configured to provide spacing based on a target capacitance for coupling using the quantum computing chip.

19. 19. The quantum computing chip of any of claims 13 to 18, further comprising a first conductive bump located on the first superconducting metal signal line and a second conductive bump located on the second superconducting metal signal line, wherein the capacitive field is formed between the first conductive bump and the second first conductive bump.

20. 20. The quantum computing chip of any of claims 13 to 19, further comprising a metallic tip coupled to the first superconducting metallic signal line and to the second end of the second superconducting metallic signal line, one end of the metallic tip protruding beyond the second end of the substrate.

21. forming a first chip substrate; forming a first one or more signal lines of superconducting metal on a top surface of the first chip substrate adjacent to or contacting an edge of the top surface of the first chip substrate; forming a second chip substrate; forming one or more signal lines of the superconducting metal on a top surface of the second chip substrate adjacent to or contacting an edge of the top surface of the second chip substrate; and forming a capacitive-based bus connection between a first distal end of the first one or more signal lines and a second distal end of the second one or more signal lines and upon determining that a signal passes through either the first one or more signal lines or the second one or more signal lines.

1. A method for manufacturing a quantum computing device, comprising:

22. 22. The method of claim 21 , further comprising forming trenches in the first substrate and depositing the superconducting metal in the trenches, the trenches and the deposited superconducting metal defining the first one or more signal lines.

23. depositing a layer of the superconducting metal on the top surface of the first substrate; and depositing the superconducting metal on an edge of the first substrate and on a mating surface of the first substrate; 23. The method of any of the preceding claims 21-22, further comprising:

24. forming a first conductive bump on the first one or more signal lines; and forming a second conductive bump on the second one or more signal lines, the first conductive bump and the second conductive bump forming the capacitive-based bus connection.

24. The method of any of the preceding claims 21 to 23, further comprising:

25. forming a first conductive tip connected to the first one or more signal lines and projecting beyond the edge of the top surface of the first chip substrate; and forming a second conductive tip connected to the second one or more signal lines and protruding beyond the edge of the top surface of the second chip substrate, the first conductive tip and the second conductive tip forming the capacitive-based bus connection.

25. The method of any of the preceding claims 21 to 24, further comprising:

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