Structures for forming high-voltage FinFET I / O devices and integrating them with nanosheet logic devices

Abstract

The semiconductor device includes a substrate having a first region and a second region spaced a distance from the first region to define a space therebetween. The first semiconductor device, including a gate dielectric, is on the first region. The first semiconductor device may implement a FinFET-based input / output (I / O) device in the first region. The second semiconductor device, excluding the gate dielectric, is on the second region. The second semiconductor device may implement a nanosheet-based logic device in the second region (FIG. 1).

Description

[Background technology]

[0001] The present invention relates generally to methods for fabricating semiconductor devices and resulting structures, and more particularly to methods for integrating high voltage input / output devices into nanosheet logic devices and resulting semiconductor devices.

[0002] Gate-all-around (GAA) field-effect transistors (FETs), such as nanosheet-based transistors (often referred to as nanosheet FETs), offer better electrostatic control. Therefore, GAA device architectures help meet the requirements of more aggressive device scaling. The ongoing trend to reduce the footprint of FET devices has increased the available area for integrating additional semiconductor devices with GAA FETs on a common semiconductor substrate.

[0003] Many circuit designs implement input / output (I / O) devices in devices that utilize logic devices, such as logic gates, that do not need to process input / output signals directly. Therefore, a recent trend in semiconductor device manufacturing and design is to integrate FinFET-based I / O devices with nanosheet-based logic devices on a common substrate, taking advantage of the increased available substrate area provided by reduced FET footprints. These devices that integrate FinFET-based devices and nanosheet-based devices on a common substrate are sometimes referred to as "hybrid transistor devices."

[0004] Traditionally, FinFETs embedded in I / O devices employ gate dielectrics formed by thermal oxidation of silicon to accommodate the higher operating voltages of the I / O devices, which in some applications may be similar to the external voltage (voltage level of external / peripheral circuits). However, the corresponding nanosheet FETs used to implement logic devices on the same substrate often lack sufficient space for growing the dielectric layer. Furthermore, designing the nanosheet FET to provide space to accommodate the dielectric layer when forming the gate dielectric layer of the I / O device FinFET results in the formation of the gate dielectric in the logic nanosheet FET, which can degrade the performance of the logic device. Summary of the Invention

[0005] Embodiments of the present invention relate to fabrication methods and resulting semiconductor devices that implement source / drain placeholder elements that improve epitaxial growth uniformity. According to non-limiting embodiments of the present invention, a method for fabricating a semiconductor device includes designating a first region and a second region on a substrate, the second region being spaced apart from the first region by a distance to define a space therebetween. The method further includes forming a first semiconductor device on the first region and a second semiconductor device on the second region. The first semiconductor device includes a gate dielectric, while the second semiconductor device excludes the gate dielectric. As a result, the method facilitates the formation of semiconductor devices that integrate I / O devices capable of handling higher operating voltages into nanosheet logic devices, avoiding performance losses caused by gate dielectrics.

[0006] In addition to or in the alternative to one or more of the features described herein, a further embodiment of forming a first semiconductor device comprises forming a fin field effect transistor (FinFET) in the first region and forming a nanosheet transistor in the second region.

[0007] In addition to or in the alternative to one or more of the features described herein, further embodiments of the method include forming one or more semiconductor fins in a first region, forming one or more semiconductor nanosheets in a second region, forming an oxide layer on the one or more semiconductor fins and the one or more semiconductor nanosheets, and removing the oxide layer from the one or more semiconductor nanosheets while maintaining the oxide layer on the one or more semiconductor fins to form a gate dielectric.

[0008] In addition to or alternative to one or more of the features described herein, a further embodiment of forming one or more semiconductor fins comprises forming a bottom dielectric insulator (BDI) layer on an upper surface of a substrate; forming a first nanosheet stack on the BDI layer in a first region, the first nanosheet stack comprising an alternating arrangement of sacrificial nanosheets and active nanosheets; forming a second nanosheet stack on the BDI layer in a second region, the second nanosheet stack comprising an alternating arrangement of sacrificial nanosheets and active nanosheets; and replacing the sacrificial nanosheets of the first nanosheet stack with a semiconductor material while maintaining the sacrificial nanosheets of the second nanosheets to form one or more semiconductor fins.

[0009] In addition to or in the alternative to one or more of the features described herein, further embodiments include depositing a high-k dielectric on the one or more semiconductor fins and the one or more semiconductor nanosheets after removing the dielectric layer from the one or more nanosheets.

[0010] In addition to or in the alternative to one or more of the features described herein, further embodiments include forming a dielectric layer interposed between the one or more semiconductor fins and the high-k dielectric layer.

[0011] In addition to or in the alternative to one or more of the features described herein, further embodiments include forming a high-k dielectric layer, included in a FinFET, directly on one or more semiconductor fins, and forming a high-k dielectric layer, included in a nanosheet transistor, directly on one or more semiconductor nanosheets.

[0012] According to another non-limiting embodiment of the present invention, a method for fabricating a hybrid transistor device includes designating a first region and a second region on a substrate, the second region being spaced apart from the first region by a distance to define a space therebetween. The method further includes forming a fin field effect transistor (FinFET) on the first region, the finFET including a gate dielectric, and forming a nanosheet transistor on the second region, excluding the gate dielectric. As a result, the method forms a hybrid transistor device that integrates I / O devices capable of handling higher operating voltages with nanosheet logic devices that avoid performance losses caused by the gate dielectric.

[0013] In addition to or in the alternative to one or more of the features described herein, further embodiments of the method include forming one or more semiconductor fins in a first region, forming one or more semiconductor nanosheets in a second region, forming an oxide layer on the one or more semiconductor fins and the one or more semiconductor nanosheets, and removing the oxide layer from the one or more semiconductor nanosheets while maintaining the oxide layer on the one or more semiconductor fins to form a gate dielectric of a FinFET.

[0014] In addition to or in the alternative to one or more of the features described herein, a further embodiment of forming one or more semiconductor fins comprises forming a first nanosheet stack in a first region, the first nanosheet stack comprising an alternating arrangement of sacrificial nanosheets and active nanosheets; forming a second nanosheet stack in a second region, the second nanosheet stack comprising an alternating arrangement of sacrificial nanosheets and active nanosheets; and replacing the sacrificial nanosheets of the first nanosheet stack with a semiconductor material while maintaining the sacrificial nanosheets of the second nanosheets to form one or more semiconductor fins.

[0015] In addition to or in place of one or more of the features described herein, further embodiments of the method include forming active sacrificial nanosheets from silicon germanium (SiGe) and forming semiconductor material from silicon (Si) to facilitate the formation of strained heterostructure semiconductor fins that improve hole mobility through I / O FinFETs. In this manner, performance of I / O devices and logic devices may be improved.

[0016] In addition to or in the alternative to one or more of the features described herein, further embodiments of the method include depositing a high-k dielectric on the one or more semiconductor fins and the one or more semiconductor nanosheets after removing the dielectric layer from the one or more nanosheets.

[0017] In addition to or in the alternative to one or more of the features described herein, further embodiments of the method include forming a dielectric layer interposed between the one or more semiconductor fins and the high-k dielectric layer.

[0018] In addition to or in the alternative to one or more of the features described herein, further embodiments of the method include forming a high-k dielectric layer included in a FinFET directly on one or more semiconductor fins, and forming a high-k dielectric layer included in a nanosheet transistor directly on one or more semiconductor nanosheets.

[0019] The semiconductor device includes a substrate having a first region and a second region spaced apart from the first region by a distance to define a space therebetween. A first semiconductor device including a gate dielectric is on the first region. The first semiconductor device may implement a FinFET-based input / output (I / O) device in the first region. A second semiconductor device, excluding the gate dielectric, is on the second region. The second semiconductor device may implement a nanosheet-based logic device in the second region. As a result, a semiconductor device is provided that integrates an I / O device capable of handling higher operating voltages with a nanosheet logic device that avoids the performance loss caused by the gate dielectric.

[0020] In addition to or in the alternative to one or more of the features described herein, further embodiments of the semiconductor device include an input / output (I / O) device on the first region that includes a first semiconductor device, and a logic device on the second region that includes a second semiconductor device.

[0021] In addition to or in the alternative to one or more of the features described herein, further embodiments of the semiconductor device provide the first semiconductor device as a fin field effect transistor (FinFET) including one or more semiconductor fins and the second semiconductor device as a nanosheet transistor including one or more semiconductor nanosheets.

[0022] In addition to or in the alternative to one or more of the features described herein, further embodiments of the semiconductor device include a first high-k dielectric layer formed directly on the gate dielectric such that the gate dielectric is interposed between the first high-k dielectric layer and the one or more semiconductor fins, and a second high-k dielectric layer formed directly on the one or more semiconductor nanosheets.

[0023] In addition to or in the alternative to one or more of the features described herein, further embodiments of the semiconductor device provide a logic device including a semiconductor material defining a fin body that extends continuously from a top surface of the semiconductor fin to a base formed on a top surface of a substrate.

[0024] In addition to or in the alternative to one or more of the features described herein, further embodiments of the semiconductor device provide a logic device including a semiconductor fin with alternating layers of silicon germanium (SiGe) and silicon (Si), the alternating layers extending continuously from a top surface of the semiconductor fin to a base formed on a top surface of a substrate.

[0025] Other embodiments of the present invention implement features of the above-described devices / structures in methods and / or implement features of the methods in devices / structures. Additional technical features and advantages are realized through the techniques of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, reference is made to the detailed description and drawings. [Brief explanation of the drawings]

[0026] The details of the exclusive rights set forth herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings presented herein.

[0027] 1-14 show a series of diagrams illustrating a method of forming a semiconductor device according to an exemplary embodiment of the present teachings.

[0028] [Figure 1] 1 illustrates a starting semiconductor structure for forming a hybrid semiconductor device according to a non-limiting embodiment of the invention.

[0029] [Figure 2]1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0030] [Figure 3] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0031] [Figure 4] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0032] [Figure 5] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0033] [Figure 6] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0034] [Figure 7] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0035] [Figure 8] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0036] [Figure 9] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0037] [Figure 10] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0038] [Figure 11]1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0039] [Figure 12] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0040] [Figure 13] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0041] [Figure 14] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0042] [Figure 15] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0043] [Figure 16] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0044] [Figure 17] 1 illustrates a starting semiconductor structure after one or more semiconductor fabrication steps, according to one or more non-limiting embodiments.

[0045] In the accompanying figures and the following detailed description of the illustrated embodiments, various elements shown in the figures are provided with two or three digit reference numerals. With few exceptions, the left-most digit(s) of each reference numeral corresponds to the figure in which the element is first shown. DETAILED DESCRIPTION OF THE INVENTION

[0046] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternative embodiments may be devised without departing from the scope of the present invention. It should be noted that in the following description and in the drawings, various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are described. These connections and / or positional relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, coupling between entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. As an example of an indirect positional relationship, references in this description to forming layer "A" on layer "B" include situations in which one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," so long as the relevant properties and functions of layer "A" and layer "B" are not substantially altered by the intermediate layers.

[0047] The following definitions and abbreviations will be used in interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover non-exclusive inclusions. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent in such composition, mixture, process, method, article, or device.

[0048] Additionally, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "plurality" is understood to include any integer greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "coupled" can include indirect and direct "coupled."

[0049] References herein to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed to be within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0050] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall refer to the structures and methods described as oriented in the drawing figures. The terms "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is above a second element, such as a second structure, where there may be intervening elements, such as interfacial structures, between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layers at the interface between the two elements. It should be noted that the term "selective to," such as "a first element selective to a second element," means that the first element can be etched and the second element can act as an etch stop.

[0051] For the sake of brevity, conventional techniques associated with the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Moreover, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functionality not described in detail herein. In particular, because the various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps will only be briefly described herein or will be omitted entirely without providing well-known process details. For example, descriptions of substrates and / or semiconductor devices following various lithography and patterning operations to form various features (e.g., cavities, openings, trenches, holes, etc.) may include various well-known deposition, lithography, photoresist, and etching processes and techniques.

[0052] As explained above, nanosheet FETs used to implement logic devices on the same substrate often lack sufficient space for growing dielectric layers. Furthermore, designing nanosheet FETs to provide space to accommodate the dielectric layers when forming the gate dielectric layers of I / O device FinFETs can result in the formation of gate dielectrics in the logic nanosheet FETs, which can degrade the performance of the logic device. One or more non-limiting embodiments of the present invention address the shortcomings of conventional hybrid transistor devices by providing a semiconductor device (e.g., a hybrid transistor device) that includes one or more FinFET-based devices that implement gate dielectrics and one or more nanosheet-based devices that omit the gate dielectric. Thus, a hybrid transistor device is provided that integrates I / O devices capable of handling higher operating voltages with a nanosheet logic device that avoids the performance loss caused by the gate dielectric.

[0053] Referring now to FIG. 1 , a semiconductor structure 100 is shown that serves as a starting point for fabricating a hybrid transistor device according to a non-limiting embodiment of the present invention. The semiconductor structure 100 includes a semiconductor substrate 102 having a first region 104 and a second region 106 spaced a distance from the first region 104. The first region 104 is designated to support a first semiconductor device, while the second region 106 is designated to support a second semiconductor device. According to one or more non-limiting embodiments, the first region 104 is designated to support input / output (I / O) devices, while the second region 106 is designated to support logic devices. According to one or more non-limiting embodiments of the present invention, I / O devices may be referred to as devices that handle input and / or output voltages / currents and, therefore, must be able to withstand larger amounts of voltage or current swings than logic devices. In some non-limiting embodiments of the present invention, logic devices include core devices that do not need to directly handle input / output voltages / currents. For example, the logic devices may include various logic gates such as NAND, NOR, INVERTER, etc. In some embodiments, the core devices may include an SRAM (Static Random Access Memory) region. It should be understood that first region 104 and second region 106 may each support other types of semiconductor devices without departing from the scope of the present invention.

[0054] With continued reference to FIG. 1 , the semiconductor structure 100 further includes a first semiconductor stack 108 and a second semiconductor stack 109. The first semiconductor stack 108 is formed on the top surface of the substrate 102 in a first region 104, while the second semiconductor stack 109 is formed on the top surface of the substrate in a second region 106. Each of the first and second semiconductor stacks 108 and 109 may have a length (e.g., along the X-axis direction) ranging from about 35 nanometers (nm) to about 45 nm, for example. In one or more non-limiting embodiments, a bottom dielectric insulation (BDI) layer (not shown in FIG. 1 ) may be formed between the substrate 102 and the first and second semiconductor stacks 108 and 109. The BDI layer may improve subthreshold characteristics and increase process and electrical stability of NSFET devices formed on the substrate 102. The BDI layer may also provide improved immunity to sub-channel leakage due to process variations caused by parasitic “fat fins” or “wide fins” inherent in nanosheet structures.

[0055] A space 101 or void 101 exists between the first semiconductor stack 108 and the semiconductor stack 109 due to the distance between the first region 104 and the second region 106. The space 101 or void 101 allows various manufacturing steps (e.g., patterning, etching, deposition, etc.) to be performed on one of the semiconductor stacks without processing or damaging the other semiconductor stack. For example, one or more manufacturing steps can be performed in the first region 104 to pattern, etch, deposit material, etc. on the first semiconductor stack 108 without extending the manufacturing step to the second region 106 and processing or damaging the second semiconductor stack 109, or vice versa.

[0056] The first semiconductor stack 108 includes an alternating stack of sacrificial nanosheets 110 and active nanosheets 112. The sacrificial nanosheets 110 can be formed from a first semiconductor material, while the active nanosheets 112 can be formed from a second semiconductor material that is different from the first semiconductor material. According to one or more non-limiting embodiments of the present invention, the sacrificial nanosheets 110 are formed from silicon germanium (SiGe), while the active nanosheets 112 are formed from silicon (Si). According to non-limiting embodiments of the present invention, the lowest-stack sacrificial nanosheets 110 included in the first semiconductor stack 108 are formed on the top surface of the semiconductor substrate 102 in the first region 104. As a result, the lowest-stack active nanosheets 110 included in the first semiconductor stack 108 are formed on the top surface of the lowest-stack sacrificial nanosheets 110.

[0057] Similarly, the second semiconductor stack 109 includes an alternating stack of sacrificial nanosheets 111 and active nanosheets 113. The sacrificial nanosheets 111 can be formed of a first semiconductor material, while the active nanosheets 113 can be formed of a second semiconductor material different from the first semiconductor material. According to one or more non-limiting embodiments of the present invention, the sacrificial nanosheets 111 are formed of silicon germanium (SiGe), while the active nanosheets 113 are formed of silicon (Si). The thickness (e.g., in the Z-axis direction) of the sacrificial nanosheets 110 can be, for example, in the range of about 7 nm to about 11 nm, and the thickness of the active nanosheets 112 can be, for example, in the range of about 8 nanometers (nm) to about 12 nm. In one or more non-limiting embodiments of the present invention, the lowest-stack sacrificial nanosheet 111 included in the second semiconductor stack 109 is formed on the top surface of the semiconductor substrate 102 in the second region 106. As a result, the lowest stack active nanosheet 113 included in the second semiconductor stack 109 is formed on top of the lowest stack sacrificial nanosheet 111 .

[0058] 2, semiconductor structure 100 is shown after depositing masking layer 103 on top of first semiconductor stack 108 and second semiconductor stack 109. According to one or more non-limiting embodiments, masking layer 103 is formed from various masking materials, including, but not limited to, polysilicon material, silicon oxide (SiO), and silicon nitride (SiN). As a result, masking layer 103 can function as a hard mask when performing various semiconductor fabrication and patterning processes described herein.

[0059] 3 , semiconductor structure 100 is shown after selective removal of sacrificial nanosheets 110 and 111 relative to active nanosheets 112 and 113. In one or more non-limiting embodiments of the present invention, a wet or dry etching process having an etchant chemistry selected to attack the material of sacrificial nanosheets 110 and 111 (e.g., SiGe) without attacking or substantially attacking active nanosheets 112 and 113 (e.g., Si) may be performed to selectively remove sacrificial nanosheets 110 and 111. In this manner, active nanosheets 112 and 113 may be “released,” forming voids 120 and 121 between active nanosheets 112 and 113. Released active nanosheets 112 and 113 may function as channels (e.g., N-channel or P-channel) of respective semiconductor devices, as described herein.

[0060] 4, semiconductor structure 100 is shown after filling disposed voids 120 and 121 with sacrificial material 122. According to one or more non-limiting embodiments, sacrificial material 122 may be formed from a dielectric material, including, but not limited to, polysilicon, silicon oxide (SiO), and silicon nitride (SiN). Although not shown, a masking layer may be deposited on top of the sacrificial material to expose first region 104 while covering second region 106.

[0061] 5 , the semiconductor structure 100 is shown after selectively removing the sacrificial material 122 disposed in the first region 104 while preserving the sacrificial material 122 and the active nanosheets 113 disposed in the second region 106. According to one or more non-limiting embodiments of the present invention, the etching process employs an etchant chemistry that attacks the material of the sacrificial material 122 without attacking the material of the active nanosheets 112. In this manner, the sacrificial material 122 may be selectively removed relative to the active nanosheets 112, forming voids 120 between the active nanosheets 112. As described herein, the active nanosheets 113 disposed in the second region 106 may be prevented from being removed due to the space 101 separating them from the first region 104 and / or the masking layer maintained in the second region 106.

[0062] 6, the semiconductor structure 100 is shown after performing an epitaxy process in the first region 104. The epitaxy process involves growing epitaxial material from a surface of the semiconductor material exposed to a gas or liquid precursor. The space 101 separating the second region 106 from the first region 104 and / or the dielectric sacrificial material 123 prevents epitaxy growth on the active nanosheets 113 disposed in the second region 106.

[0063] According to one or more non-limiting embodiments of the present invention, the epitaxy process may employ vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes to facilitate epitaxy material growth. The epitaxial silicon, silicon germanium, and / or carbon-doped silicon (Si:C) silicon may be doped during deposition (in-situ doping) by adding dopants, for example, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor.

[0064] The terms "epitaxial growth and / or deposition" and "epitaxially forming and / or growing" refer to the growth of a semiconductor material (crystalline material) on the deposition surface of another semiconductor material (crystalline material), where the growing semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material (seed material) on the deposition surface. In an epitaxial deposition process, chemical reactants provided by source gases are controlled, and system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around the surface and orient themselves relative to the crystalline arrangement of atoms on the deposition surface. Thus, the epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which it is formed. For example, epitaxially grown semiconductor material deposited on a {100}-oriented crystalline surface will have a {100} orientation. In some embodiments of the present invention, the epitaxial growth and / or deposition process is selective to formation on semiconductor surfaces and generally does not deposit material on non-crystalline surfaces such as silicon dioxide or silicon nitride.

[0065] In some embodiments of the present invention, the gas source for deposition of epitaxial semiconductor materials includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial Si layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Combinations of such gas sources can be used to form epitaxial silicon-germanium alloy layers. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0066] With continued reference to FIG. 6 , the epitaxy process can be continued until the void 120 is filled to form an integral, fully solid semiconductor “fin” 114. For example, the semiconductor fin 114 includes a semiconductor material defining a fin body that extends continuously from a top surface of the semiconductor fin to a base formed on the top surface of the semiconductor substrate 102. In one or non-limiting embodiments, the fin body is formed entirely from a single semiconductor material, such as silicon (Si). As a result, the semiconductor fin 114 can extend from a fin base formed on the top surface of the substrate 102 to an opposite upper fin surface. While a single semiconductor fin 114 is shown, it should be understood that additional semiconductor fins 114 (e.g., two, three, etc.) can be included in the semiconductor device 100 (e.g., in the first region 104) for use with logic devices.

[0067] In one or more non-limiting embodiments of the present invention, the upper fin surface is aligned with or extends above the top surface of the sacrificial material 122 disposed in the second region 106. In this scenario, as shown in Figure 7, a portion of the semiconductor material can be recessed such that its height is aligned or substantially aligned with the top surface (indicated by dotted line 124) of the uppermost active nanosheet 102. According to one or more non-limiting embodiments, a reactive ion etching (RIE) process or a chemical mechanical planarization (CMP) process can be performed to recess the height of the semiconductor fin 114.

[0068] 8, the semiconductor structure 100 is shown after selective removal of the sacrificial material 122 relative to the active nanosheets 113. In one or more non-limiting embodiments of the present invention, a wet or dry etching process can be performed to selectively remove the sacrificial material 122. The etching process employs an etchant chemistry selected to attack the sacrificial material without attacking or substantially attacking the active nanosheets 113. The released active nanosheets 113 can function as channels (e.g., N-channel or P-channel) of the nanosheet semiconductor devices formed in the second region 106 described herein.

[0069] 9, the semiconductor device 100 is shown following deposition of an oxide layer 118 / 118' in the first region 104 and the second region 106. The oxide layer 118 / 118' may be deposited using a variety of deposition processes, including, but not limited to, atomic layer deposition (ALD) and plasma-enhanced ALD (PEALD). As a result, the oxide layer 118 / 118' may conform to the exposed surface of the semiconductor fin 114, the exposed surface of the active nanosheet 113, and the exposed surface of the semiconductor substrate 102. The oxide layer 118 / 118' may be formed from a variety of oxide materials, including, but not limited to, SiO2, and may be deposited in the first and second regions 104 and 106 using a single deposition process or separate deposition processes.

[0070] According to one or more non-limiting embodiments, the thickness of oxide layer 118 / 118' can be selected based, at least in part, on the target thickness of the gate dielectric to be formed on semiconductor fin 114. For example, the thickness of oxide layer 118 / 118' can be, for example, in the range of about 2 nm to about 5 nm.

[0071] 10 , a semiconductor device is shown after selective removal of oxide layer 118′ from nanosheet 113 located in second region 106 while maintaining oxide layer 118 on semiconductor fin 114 located in first region 104. According to one or more non-limiting embodiments of the present invention, the etching process employs an etchant chemistry that attacks the material of oxide layer 118′ without attacking the material of the underlying active nanosheet 112. As described herein, oxide layer 118 located in first region 104 may be prevented from being removed due to space 101 separating it from second region 106 and / or due to a masking layer (not shown in FIG. 10 ) covering semiconductor fin 114.

[0072] As described herein, the remaining gate oxide layer 118 formed on the semiconductor fin 114 may function as a gate dielectric 118 for a corresponding semiconductor device (e.g., an I / O device) according to one or more non-limiting embodiments of the present invention. Thus, unlike conventional hybrid transistor devices, a semiconductor FinFET 114 formed in a first region 104 designated to support a first semiconductor device (e.g., an I / O device) may include the oxide layer 118 (e.g., gate dielectric), while a second semiconductor device (e.g., a nanosheet-based logic device) formed in a second region 106 designated to support a second semiconductor device (e.g., an I / O device) may omit the gate oxide 118 (e.g., gate dielectric). Removing the oxide layer 118′ not only allows for improved performance of the completed logic device formed in the second region 106, but also allows for an increase in the thickness of the oxide layer 118 used as a gate dielectric for the FinFET 114 implementing the I / O device formed in the first region 104 without having to consider spatial limitations associated with the nanosheets 113 used to form the nanosheet-based logic device in the second region. As a result, the I / O devices can be formed with thicker gate dielectrics 118 compared to conventional hybrid transistor devices that integrate I / O devices and nanosheet-based logic devices on a common substrate.

[0073] 11 , the semiconductor device 100 is shown following deposition of the high-k dielectric layer 126 / 126′ in the first region 104 and the second region 106. The high-k dielectric layer 126 / 126′ can be deposited using a variety of deposition processes, including, but not limited to, atomic layer deposition (ALD) and plasma-enhanced ALD (PEALD). As a result, the high-k dielectric layer 126 / 126′ can conform to the exposed surface of the oxide layer 118 (i.e., gate dielectric 118), the exposed surface of the active nanosheet 113, and the exposed surface of the semiconductor substrate 102. The high-k dielectric layer 126 / 126′ can be formed from a variety of high-k dielectric materials (e.g., materials with a higher dielectric constant compared to SiO) and can be deposited in the first and second regions 104 and 106 using a single deposition process or separate deposition processes. In one or more non-limiting embodiments, the high-k dielectric material includes, but is not limited to, hafnium silicate (HfSiO), zirconium silicate (ZrSiO), hafnium dioxide (HfO), and zirconium dioxide (ZrO).

[0074] As described herein, various non-limiting embodiments of the invention described herein provide a process flow for fabricating a semiconductor device 100 (e.g., a hybrid transistor device) shown in Figure 11 that includes a fin field effect transistor (FinFET) 150 for implementing an I / O device with a common source / drain, along with an integrated nanosheet transistor 151 for implementing a logic device. The resulting semiconductor device 100 enables the I / O device to operate at increased voltages (e.g., from about 1.2 V to about 3.5 V) while omitting the formation of a gate dielectric on the nanosheets, which can result in degradation of the logic device's performance.

[0075] In accordance with one or more non-limiting embodiments of the present invention, the process flows described herein can be utilized to introduce strain into a logic device's FinFET 114. The strained FinFET 114 provides a hybrid architecture that provides a strained heterostructure FinFET that promotes hole mobility therethrough and improves the operational performance of corresponding I / O and logic devices.

[0076] 12, for example, shows semiconductor structure 100 after selectively removing sacrificial Si nanosheets located in first region 104 to release SiGe nanosheets 110 while preserving sacrificial material 122 and active nanosheets 113 located in second region 106 (a process similar to that used in FIG. 5 can be performed to achieve semiconductor substrate 100 shown in FIG. 12). As a result, voids 120 expose the surface of SiGe nanosheets 110.

[0077] 13, the semiconductor device 100 is shown following an epitaxy step that grows Si material 128 from the exposed surfaces of the SiGe nanosheets 110. As a result, the SiGe nanosheets 110 induce strain in the epitaxied Si material 128, thereby resulting in a strained heterostructure FinFET 130 having one or more highly strained Si layers 128 that promote hole mobility therethrough.

[0078] 14 shows semiconductor device 100 after completing the various fabrication steps shown in FIGS. 6-11 to provide semiconductor device 100 (e.g., a hybrid transistor device) that integrates strained heterostructure semiconductor fin 130 for implementing FinFET 150 included in an I / O device having a gate dielectric with nanosheet transistor 151 for implementing a logic device excluding the gate dielectric. While a single strained heterostructure semiconductor fin 130 is shown, it should be understood that additional strained heterostructure semiconductor fins 130 may be included in semiconductor device 100 (e.g., in first region 104) for use with a logic device without departing from the scope of the present invention.

[0079] As described herein, semiconductor device 100 may also include additional semiconductor fins 114 (e.g., in first region 104) used with logic devices, along with a BDI layer formed between substrate 102 and I / O devices 150 and / or logic devices 151. Referring to FIG. 15 , for example, a semiconductor structure 100 used to form multiple semiconductor fins in I / O region 104 is shown, according to a non-limiting embodiment. Semiconductor structure 100 includes a BDI layer 105 interposed between semiconductor substrate 102, a first semiconductor stack 108 (e.g., I / O semiconductor stack 108), and a second semiconductor stack 109 (e.g., logic semiconductor stack 109). BDI layer 105 may be formed from any dielectric material, including, for example, an oxide material or a nitride material.

[0080] 15, a patterned masking layer 103 is formed on top of the first semiconductor stack 108 and the second semiconductor stack 109. In this example, the masking layer 103 is patterned in a manner to form a plurality of semiconductor fins in the I / O region 104, as described herein.

[0081] 16, semiconductor structure 100 is shown after the masking patterning defined by masking layer 103 has been transferred to first semiconductor stack 108. As a result, multiple individual I / O semiconductor stacks 108a and 108b are formed on top of BDI layer 105, which is located in I / O region 104.

[0082] Following the formation of the individual I / O semiconductor stacks 108 and 108, various fabrication operations may be performed according to the process flow described herein to form multiple FinFETs 150a and 150b as shown in Figure 17. As a result, multiple FinFETs 150a and 150b, including gate oxide layer 118 (e.g., gate dielectric 118), along with an integrated nanosheet transistor 151 excluding the gate dielectric, may implement an I / O device with a common source / drain and implement a logic device formed on a common substrate 102.

[0083] As described herein, various non-limiting embodiments of the present invention provide semiconductor devices (e.g., hybrid transistor devices) that include one or more FinFET-based devices that implement a gate dielectric and one or more nanosheet-based devices that omit the gate dielectric. Thus, semiconductor devices are provided that integrate I / O devices capable of handling higher operating voltages with nanosheet logic devices that avoid the performance loss caused by the gate dielectric.

[0084] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternative embodiments may be devised without departing from the scope of the present invention. While the following description and drawings describe various connections and relationships between elements (e.g., above, below, adjacent, etc.), those skilled in the art will recognize that many of the relationships described herein are independent of orientation, provided that the described functionality is maintained even when the orientation is changed. These connections and / or relationships may be direct or indirect, unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, a connection between entities may refer to a direct or indirect connection, and a relationship between entities may be a direct or indirect relationship. As an example of an indirect relationship, reference in this description to forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") are between layers "A" and "B," as long as the relative properties and functionality of layers "A" and "B" are not substantially altered by the intermediate layer(s).

[0085] The phrase "selective to," such as "a first element selective to a second element," means that the first element can be etched and the second element can act as an etch stop.

[0086] As previously discussed herein, for the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. However, by way of background, a more general description of semiconductor device manufacturing processes that may be utilized in implementing one or more embodiments of the present invention is now provided. While the specific manufacturing operations used in implementing one or more embodiments of the present invention may be individually known, the combination of the described operations and / or resulting structures of the present invention are unique. Thus, the unique combination of operations described in connection with manufacturing semiconductor devices in accordance with the present invention utilizes various individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs.

[0087] Generally, the various processes used to form microchips to be packaged into ICs fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. Removal / etching is any process that removes material from the wafer. Examples include etching processes (wet or dry) and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping the source and drain of transistors, for example, typically by diffusion and / or ion implantation. These doping steps are followed by furnace annealing or rapid thermal annealing (RTA). The annealing serves to activate the implanted dopants. Films, both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.), are used to connect and separate transistors and their components. Selective doping of various regions of a semiconductor substrate makes it possible to change the conductivity of the substrate with the application of a voltage. By fabricating structures of these various components, millions of transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices.

[0088] As described above, atomic layer etching processes can be used in the present invention to remove residues such as those caused by via misalignment. Atomic layer etching processes provide precise etching of metals using plasma-based or electrochemical approaches. Atomic layer etching processes are generally defined by two well-defined, sequential, independently controllable, self-limiting reaction steps. The process generally involves selective removal of passivation followed by passivation, and can be used to remove thin metal layers on the order of nanometers. An exemplary plasma-based approach generally involves a two-step process that generally involves exposing a metal, such as copper, to chlorine and hydrogen plasma at low temperatures (below 20°C). This process produces volatile etching products that minimize surface contamination. In another example, cyclic exposure to an oxidizing agent and hexafluoroacetylacetone (Hhfac) at elevated temperatures, such as 275°C, can be used to selectively etch metals, such as copper. An exemplary electrochemical approach can also involve two steps. The first step involves surface-limited sulfurization of a metal, such as copper, to form a metal sulfide, e.g., CuS, followed by selective wet etching of the metal sulfide, e.g., etching CuS in HCl. Atomic layer etching is a relatively recent technology, and optimization for a particular metal is within the skill of one in the art. Reaction at the surface provides high selectivity, minimizing or eliminating attack of exposed dielectric surfaces.

[0089] Semiconductor lithography is the creation of three-dimensional relief images or patterns on a semiconductor substrate for subsequent transfer of the pattern to a substrate. In semiconductor lithography, the pattern is formed with a light-sensitive polymer called photoresist. The lithography and etching pattern transfer steps are repeated multiple times to build the complex structures that make up transistors and the many wires that connect a circuit's millions of transistors. Each pattern printed on the wafer is aligned with previously formed patterns, and conductors, insulators, and selectively doped regions are slowly built up to form the final device.

[0090] The photoresist may be formed using conventional deposition techniques such as chemical vapor deposition, plasma vapor deposition, sputtering, dip coating, spin-on coating, brushing, spraying, and other similar deposition techniques. Following formation of the photoresist, the photoresist is exposed to a desired pattern of radiation, such as x-ray radiation, extreme ultraviolet (EUV) radiation, electron beam radiation, or the like. The exposed photoresist is then developed using a conventional resist development process.

[0091] After the development step, an etching step may be performed to transfer the pattern from the patterned photoresist to the interlayer dielectric. The etching step used in forming the at least one opening may include a dry etching process (including, for example, reactive ion etching, ion beam etching, plasma etching, or laser ablation), a wet chemical etching process, or any combination thereof.

[0092] For the sake of brevity, conventional techniques related to making and using aspects of the present invention may or may not be described in detail herein. Accordingly, for the sake of brevity, many conventional implementation details are mentioned only briefly herein or are omitted entirely without providing details of well-known systems and / or processes. For example, a description of patterning a substrate to form various features (e.g., cavities, openings, trenches, holes, etc.) may include the deposition, lithography, photoresist, and etching processes and techniques described above. Accordingly, for the sake of brevity, references to patterned substrates and / or patterned semiconductor devices at one or more stages of a process flow may omit full details of the deposition, lithography, photoresist, and / or etching processes and techniques described above.

[0093] In some embodiments, various functions or operations may be performed at a given location and / or in conjunction with the operation of one or more devices or systems. In some embodiments, a portion of a given function or operation may be performed at a first device or location, and the remaining function or operation may be performed at one or more additional devices or locations.

[0094] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should be further understood that the terms "comprises" and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, and / or elementary components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elementary components, and / or groups thereof.

[0095] In the following claims, the corresponding structure, material, acts, and equivalents of any means-plus-function or step-plus-function element are intended to include any structure, material, or acts for performing the function in combination with other claimed elements as specifically claimed. This disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the disclosure. The embodiments were chosen and described to best explain the principles and practical applications of the disclosure and to enable those skilled in the art to understand the disclosure in various embodiments with various modifications suited to the particular uses contemplated.

[0096] The diagrams shown herein are exemplary. There may be many variations in the diagrams or steps (or operations) described therein without departing from the scope of the present disclosure. For example, operations may be performed in a different order, or operations may be added, deleted, or modified. Also, the term "coupled" indicates that there is a signal path between two elements and does not imply a direct connection between elements with no intervening elements / connections between them. All of these variations are considered part of the present disclosure.

[0097] The following definitions and abbreviations will be used in interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to encompass a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent in such composition, mixture, process, method, article, or device.

[0098] Moreover, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "plurality" is understood to include any integer greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connected" can include both an indirect "connected" and a direct "connected."

[0099] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on the equipment available at the time of filing. For example, "about" can include a range of ±8%, or 5%, or 2% of a given value.

[0100] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0101] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions, that implement the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0102] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the market, or to enable others skilled in the art to understand the embodiments described herein.

Claims

1. 1. A method of manufacturing a semiconductor device, comprising: designating a first region on a substrate and a second region spaced a distance from the first region defining a space therebetween; forming a first semiconductor device on the first region, the first semiconductor device including a gate dielectric; and forming a second semiconductor device on the second region, the second semiconductor device excluding a gate dielectric; A method for providing

2. 10. The method of claim 1, wherein forming the first semiconductor device comprises forming a fin field effect transistor (FinFET) in the first region and forming a nanosheet transistor in the second region.

3. forming one or more semiconductor fins in the first region; forming one or more semiconductor nanosheets in the second region; forming an oxide layer on the one or more semiconductor fins and the one or more semiconductor nanosheets; and removing the oxide layer from the one or more semiconductor nanosheets while maintaining the oxide layer on the one or more semiconductor fins to form the gate dielectric. The method of claim 2 further comprising:

4. Forming the one or more semiconductor fins comprises: forming a bottom dielectric insulation (BDI) layer on an upper surface of the substrate; forming a first nanosheet stack on the BDI layer in the first region, the first nanosheet stack including an alternating arrangement of sacrificial nanosheets and active nanosheets; forming a second nanosheet stack on the BDI layer in the second region, the second nanosheet stack comprising an alternating arrangement of sacrificial nanosheets and active nanosheets; and replacing the sacrificial nanosheets of the first nanosheet stack with a semiconductor material while maintaining the sacrificial nanosheets of the second nanosheet stack to form the one or more semiconductor fins. The method of claim 3, comprising:

5. 4. The method of claim 3, further comprising depositing a high-k dielectric layer on the one or more semiconductor fins and the one or more semiconductor nanosheets after removing the oxide layer from the one or more semiconductor nanosheets.

6. 6. The method of claim 5, wherein the oxide layer is interposed between the one or more semiconductor fins and the high-k dielectric layer.

7. 7. The method of claim 6, wherein the high-k dielectric layer included in the FinFET is formed directly on the oxide layer, and the high-k dielectric layer included in the nanosheet transistor is formed directly on the one or more semiconductor nanosheets.

8. designating a first region on a substrate and a second region spaced a distance from the first region defining a space therebetween; forming a fin field effect transistor (FinFET) including a gate dielectric on the first region; and forming a nanosheet transistor on the second region, excluding a gate dielectric; 1. A method for fabricating a hybrid transistor device, comprising:

9. forming one or more semiconductor fins in the first region; forming one or more semiconductor nanosheets in the second region; forming an oxide layer on the one or more semiconductor fins and the one or more semiconductor nanosheets; and removing the oxide layer from the one or more semiconductor nanosheets while maintaining the oxide layer on the one or more semiconductor fins to form the gate dielectric of the FinFET. The method of claim 8 further comprising:

10. Forming the one or more semiconductor fins comprises: forming a first nanosheet stack in the first region, the first nanosheet stack including an alternating arrangement of sacrificial nanosheets and active nanosheets; forming a second nanosheet stack in the second region, the second nanosheet stack comprising an alternating arrangement of sacrificial nanosheets and active nanosheets; and replacing the sacrificial nanosheets of the first nanosheet stack with a semiconductor material while maintaining the sacrificial nanosheets of the second nanosheet stack to form the one or more semiconductor fins. The method of claim 9 comprising:

11. 11. The method of claim 10, wherein the active sacrificial nanosheets comprise silicon germanium (SiGe) and the semiconductor material comprises silicon (Si), forming a strained heterostructure semiconductor fin.

12. 11. The method of claim 10, further comprising depositing a high-k dielectric on the one or more semiconductor fins and the one or more semiconductor nanosheets after removing the oxide layer from the one or more semiconductor nanosheets.

13. 13. The method of claim 12, wherein the gate dielectric is interposed between the one or more semiconductor fins and the high-k dielectric layer.

14. The method of claim 13, wherein the high-k dielectric layer included in the FinFET is formed directly on the gate dielectric, and the high-k dielectric layer included in the nanosheet transistor is formed directly on the one or more semiconductor nanosheets.

15. a substrate including a first region and a second region spaced a distance from the first region to define a space therebetween; a first semiconductor device on the first region, the first semiconductor device including a gate dielectric; and a second semiconductor device on the second region, the second semiconductor device excluding a gate dielectric; A semiconductor device comprising:

16. an input / output (I / O) device on the first region that includes the first semiconductor device; and a logic device on the second region that includes the second semiconductor device; The semiconductor device of claim 15 further comprising:

17. 17. The semiconductor device of claim 16, wherein the first semiconductor device is a fin field effect transistor (FinFET) including one or more semiconductor fins, and the second semiconductor device is a nanosheet transistor including one or more semiconductor nanosheets.

18. a first high-k dielectric layer formed directly on the gate dielectric such that the gate dielectric is interposed between the first high-k dielectric layer and the one or more semiconductor fins; and a second high-k dielectric layer formed directly on the one or more semiconductor nanosheets; 20. The semiconductor device of claim 17, further comprising:

19. 20. The semiconductor fin of claim 18, wherein the semiconductor fin comprises silicon (Si) extending continuously from a top surface of the semiconductor fin to a base of the semiconductor fin formed on a top surface of the substrate.

20. 20. The semiconductor fin of claim 18, wherein the semiconductor fin comprises alternating layers of silicon germanium (SiGe) and silicon (Si), the alternating layers extending continuously from a top surface of the semiconductor fin to a base of the semiconductor fin formed on a top surface of the substrate.

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