Global curvature correction during stress management

Abstract

Embodiments of the present disclosure relate to techniques and apparatus for reducing out-of-plane distortion (OPD) in a substrate, and to controlling the effects of OPD and the impact that modifications made to the substrate to correct for OPD have on subsequent substrate processing operations performed on the substrate. The present embodiments employ novel techniques for reducing the OPD of a substrate without adding or modifying portions of the substrate to cause problems in subsequent substrate manufacturing processes.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] The present disclosure relates generally to stress control in substrates, and more particularly to stress compensation to reduce out-of-plane distortion in substrates. [Background technology]

[0002]

[0002] Memory devices are essential components of currently developed digital electronic devices. Advances in today's technology have created a need for increasing memory capacity in most electronic devices. At the same time, there is a demand for smaller memory devices to meet market demands for smaller electronic devices incorporating memory devices.

[0003] In recent years, conventional (2D) NAND memory devices have faced many challenges, including voltage drop-related issues (e.g., continued scaling of cell size leads to a shortage of electrons in the current-carrying elements), retention loss, and overall reliability. To address these challenges arising from the scaling of planar (2D) NAND memory devices and achieve higher density while reducing the cost per bit, ultra-high-density three-dimensional (3D) stacked memory structures have been introduced. Such 3D memory structures, sometimes referred to as bit-cost scalable (BiCS) architectures, contain vertically integrated strings of memory cells. Typically, the vertically aligned memory cells are formed from an array of alternating conductive and insulating layers, with the conductive layers corresponding to the word lines of the memory structure.

[0004]

[0004] As the number of vertically stacked memory cells in 3D NAND devices increases (e.g., as chip density increases), stresses within the stacked memory cells increase, leading to increased substrate warpage and numerous performance issues. Local variations in material composition within vertically stacked memory cells can create stresses that deform or bend the semiconductor substrate on which the structures are formed. Substrate flatness or warpage has a significant impact on semiconductor device manufacturing because it can affect the ability of photolithography systems to effectively form device patterns on the substrate's surface. Even moderate variations in surface topography within the photolithography exposure area can alter device feature patterns and ultimately lead to reduced die yield. To accurately form device patterns, it is important that the substrate remains relatively flat or planar when forming the pattern on the substrate. Substrate warpage is also important for other related manufacturing processes, as substrate deformation or bending can also cause problems in subsequent processing steps, such as chip bonding and packaging.

[0005]

[0005] One common concern when fabricating such devices and structures on a substrate is the occurrence of in-plane distortion (IPD), which affects the overlay of a layer relative to an underlying reference layer. IPD is a complex quantity that is affected by both the out-of-plane distortion (OPD) of the substrate and the alignment scheme used in photolithography. OPD is a fundamental substrate quantity, and residual OPD characteristics formed in the substrate due to stress are important to the achievable overlay. For example, a commonly encountered type of OPD is global substrate bowing, which can occur in many cases of processing due to stress accumulation in the substrate as a result of processing operations.

[0006]

[0006] Therefore, there is a need for an improved memory device structure and method for forming the same that addresses the above problems. Summary of the Invention

[0007]

[0007] An embodiment of the present disclosure provides a substrate including a semiconductor device. The substrate including the semiconductor device includes: a plurality of semiconductor device layers formed on a front surface of the substrate, the semiconductor device layers including at least one layer including a compressive stress or a tensile stress that causes an out-of-plane strain in the substrate; and a strain compensation structure formed on a back surface of the substrate, the strain compensation layer including a first material having an as-deposited compressive stress or tensile stress on the back surface and having a thickness; and implanted ions disposed across the back surface of the substrate, the thickness and compressive stress or tensile stress formed in the as-deposited first material cannot compensate for all of the out-of-plane strain formed in the substrate, the implanted ions including a uniform dose of implanted ions provided at a first ion energy, and a combination of the as-deposited first material and the addition of implanted ions into the first material configured to compensate for the out-of-plane strain formed in the substrate.

[0008]

[0008] Embodiments of the present disclosure also provide a method for forming a three-dimensional memory device, the method including: measuring out-of-plane strain formed in a substrate including multiple semiconductor device layers formed on a front side of the substrate; determining at least one strain compensation parameter used to form a strain compensation structure formed on a back side of the substrate; forming a strain compensation layer of the strain compensation structure on the back side of the substrate, the strain compensation layer including a first material having a compressive or tensile stress as-deposited on the back side and having a thickness; and performing an ion implantation process to uniformly implant ions throughout the back side of the first material deposited on the back side of the substrate, wherein the thickness and the compressive or tensile stress formed in the as-deposited first material cannot compensate for all of the out-of-plane strain formed in the substrate, the implanted ions including a uniform dose of implanted ions delivered at a first ion energy, wherein a combination of the as-deposited first material and the addition of implanted ions into the first material is configured to compensate for the out-of-plane strain formed in the substrate.

[0009]

[0009] Embodiments of the present disclosure further provide a method of forming a strain compensation structure, the method including: depositing a strain compensation layer on a backside of a substrate that includes a plurality of semiconductor device layers on a frontside of the substrate, at least one of the plurality of semiconductor device layers having compressive or tensile stress that induces an out-of-plane strain in the substrate; and performing an ion implantation process that exposes the as-deposited strain compensation layer to a uniform dose of implanted ions.

[0010]

[0010] So that the above features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments and are therefore not intended to limit the scope of the present disclosure, which may admit of other embodiments that are equally effective. [Brief explanation of the drawings]

[0011] [Figure 1] 1 shows a substrate containing out-of-plane strain. [Figure 2] 2 shows the substrate shown in FIG. 1 after a conventional stress compensation layer has been added to the backside of the substrate. [Figure 3] 1 illustrates a method of forming a distortion compensation structure according to one or more embodiments described herein. [Figure 4] 2 illustrates a portion of a distortion compensation structure formation process performed on the substrate shown in FIG. 1 according to one or more embodiments described herein. [Figure 5] 2 illustrates a portion of a distortion compensation structure formation process performed on the substrate shown in FIG. 1 according to one or more embodiments described herein. [Figure 6] 10 is a graph illustrating the effect of increasing the amount of uniform implant dose provided to a strain correction layer of a strain correction structure according to one or more embodiments described herein. [Figure 7] 7-9 illustrate the effect of different uniform implant dose levels on out-of-plane distortion according to one or more embodiments described herein. [Figure 8] 7-9 illustrate the effect of different uniform implant dose levels on out-of-plane distortion according to one or more embodiments described herein. [Figure 9] 7-9 illustrate the effect of different uniform implant dose levels on out-of-plane distortion according to one or more embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0017] To facilitate understanding, the same reference numerals have been used wherever possible to indicate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0013]

[0018] In the following description, details are given by way of example to facilitate understanding of the disclosed subject matter. However, it should be apparent to those skilled in the art that the disclosed embodiments are illustrative and do not encompass all possible embodiments. Therefore, it should be understood that reference to the described examples is not intended to limit the scope of the present disclosure. Any changes and further modifications to the described devices, apparatus, and methods, and further applications of the principles of the present disclosure, are fully contemplated as would normally occur to one skilled in the art to which the present disclosure pertains. In particular, it is fully contemplated that features, components, and / or steps described with respect to one embodiment can be combined with features, components, and / or steps described with respect to other embodiments of the present disclosure. As used herein, the term "about" may refer to a + / - 10% variation from the nominal value. It is understood that any value provided herein may include such variations.

[0014]

[0019] The embodiments described herein relate to techniques and apparatus for reducing out-of-plane distortion (OPD) in a substrate, and to controlling the effects of OPD and the effect that modifications made to the substrate to correct for OPD have on subsequent substrate processing operations performed on the substrate. The embodiments employ novel techniques for reducing the OPD of a substrate without adding or modifying portions of the substrate to cause problems in subsequent substrate manufacturing processes.

[0015]

[0020] As mentioned above, in one application, as the number of vertically stacked memory cells in a 3D NAND device increases (e.g., as chip density increases), the stresses induced within the stacked memory cells increase, thereby increasing the OPD of the substrate and, therefore, what is referred to as "wafer bow" or "substrate warpage." To compensate for global substrate bow, i.e., bowing across the entire substrate surface, it has been common practice to deposit a stress compensation layer on the surface of the substrate to a desired thickness so that the intrinsic and extrinsic stresses in the deposited stress compensation layer tend to counteract the global substrate bow caused by previous substrate processing steps. Thus, as the global substrate bow increases, the deposited stress compensation layer must be thicker to counteract the larger substrate bow. For metal contamination reasons, the deposited stress compensation layer is typically made of silicon oxide (SiO x Typically, the dielectric film layer includes a dielectric film layer such as silicon nitride (SiN), carbon, or a combination thereof.

[0016]

[0021] However, in the fabrication of most semiconductor devices, it is common to process substrates multiple times using one or more plasma processes, such as physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), reactive ion etching (RIE), plasma-enhanced atomic layer deposition (PEALD), or other similar processing techniques, to form device layers on the substrate. In most plasma processes, it is desirable to electrostatically chuck the substrate to the surface of a substrate support to ensure good temperature control. The act of electrostatically chucking the substrate to the surface of the substrate support causes charge to migrate and accumulate on the underside of the substrate during processing. Before the substrate can be removed from the surface of the substrate support, the accumulated charge must be discharged, often referred to as the substrate dechucking process. However, as the thickness of the stress compensation layer deposited on the backside of the substrate increases, it becomes increasingly difficult to completely discharge all of the accumulated charge on the backside of the substrate, or to discharge it within a reasonable time. Failure to discharge the accumulated charge also significantly increases the likelihood of damaging or breaking the substrate when the substrate lift mechanism is used to separate the substrate from the substrate support surface, often resulting in particle generation and chamber downtime to remove the damaged or broken substrate.

[0017] Stress Compensation Process

[0022] To eliminate or minimize the complex distortion shapes formed in the deformed substrate, distortion compensation structures and process sequences for forming the same have been developed and are disclosed herein.

[0018]

[0023] 1 is a cross-sectional side view of a substrate having significant global substrate bow caused by large OPD. The amount of displacement caused by the OPD can be measured at the center or neutral axis of the substrate 101. In one example, the substrate 101 includes semiconductor device layers formed on a front surface 102 of the substrate 101 that are used to form a 3D memory device. At least one layer of the semiconductor device layers has compressive or tensile stress that causes out-of-plane distortion (OPD) in the substrate 101.

[0019]

[0024] 2 is a side cross-sectional view of the substrate 101 after a conventional stress compensation layer 201 has been formed on the backside 103 of the substrate 101. The conventional stress compensation layer 201 has a thickness T CON The stress compensation layer 201 typically comprises a dielectric material. However, as discussed above, the thickness of the conventional stress compensation layer 201 must be large, and the dielectric film properties can cause significant problems in many subsequent processes performed on the substrate. In one example, a conventional stress compensation layer containing silicon nitride (SiN) deposited on the backside 103 of the substrate 101 and having a thickness of, for example, greater than 5,000 angstroms (Å) has been found to have an undesirably high breakage rate when used in typical processes that employ electrostatic chucks. In some cases, the conventional stress compensation layer can have a thickness of approximately 1 μm per approximately 5 μm to approximately 8 μm of warp or bow, as described in U.S. Patent Application Publication No. 20170178891 A1.

[0020]

[0025] 3 illustrates a method 300 used to form a distortion compensation structure 502 used to compensate for OPD found in a substrate 101, according to one or more embodiments described herein. FIGS. 4 and 5 are schematic cross-sectional side views of the substrate 101 at various stages of the distortion compensation structure 502 formation process shown in FIG. 3, according to one or more embodiments described herein. In general, the distortion compensation structure 502 formation process involves forming a substrate 101 with a thickness T DCL and then exposing the deposited strain correction layer 501 formed on the backside 103 of the substrate 101 to a uniform implant dose to correct for OPD in the substrate 101.

[0021]

[0026] Method 300 begins with activity 302, where the OPD of substrate 101 is measured using conventional substrate bow metrology techniques. The conventional metrology techniques can be performed using a WaferSight™ tool available from KLA Corporation of Milpitas, California, a metrology system available from MTI Instruments, Inc. of Albany, New York, or other similar substrate bow metrology tools.

[0022]

[0027] In activity 304, a system controller (not shown) within the one or more distortion correction structure processing tools determines the desired amount of distortion correction required for one or more of the various portions of the distortion correction structure 502 to be formed on the backside of the substrate 101. The determined required amount of correction is based on data collected during activity 302. The system controller includes a programmable central processing unit (CPU) operable with memory (e.g., non-volatile memory) and support circuits. The support circuits are conventionally coupled to the CPU and include cache, clock circuits, input / output subsystems, etc., combinations of which are coupled to and facilitate the control of various components within the one or more distortion correction structure processing tools. The CPU is one of any form of general-purpose computer processor used in industrial environments to control various components and sub-processors of processing systems. Typically, the memory is in the form of a non-transitory computer-readable storage medium (e.g., non-volatile memory) containing instructions that, when executed by the CPU, facilitate the operation of the one or more distortion correction structure processing tools. The computer instructions in the memory are in the form of a program product, such as a program, that implements one or more portions of the methods of the present disclosure.

[0023]

[0028] In activity 306, an as-deposited strain correction layer 501 is formed on the backside of the substrate 101. The process of forming the as-deposited strain correction layer 501 may include depositing a dielectric-containing layer on the backside 103 using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or any other useful deposition process. The thickness T of the as-deposited strain correction layer 501 is DCLis selected using a pre-activity to be less than the thickness required to fully compensate for the OPD of the substrate 101 and to ensure that the distortion correction layer 501 will not cause problems in subsequent manufacturing processes. In one example, the as-deposited distortion correction layer 501 may comprise a silicon nitride (Si3N4)-containing layer formed by a PVD or CVD process. In some embodiments, the system controller determines the required thickness T of the as-deposited distortion correction layer 501 based on the data collected during activity 302. DCL Determine the thickness T DCL can be selected based on the implant dose to be provided during activity 308, and thus the thickness T of the as-deposited strain correction layer 501. DCL is adjusted based on the implant dose parameters used during activity 308. In some cases, it may be desirable to set the thickness of the as-deposited strain correction layer 501 to be thick enough so that implant ions provided during the ion implantation process performed during activity 308 do not implant into the backside of the substrate 101. In some non-limiting examples, the as-deposited strain correction layer 501 has a thickness T DCL Silicon nitride (Si) having a thickness of less than 4,000 Å, for example less than 2,000 Å, or between 1,000 Å and 2,000 Å. x N y ) membrane layer.

[0024]

[0029] In activity 308, an ion implantation process is performed in which the as-deposited strain correction layer 501 is exposed to a dose of implanted ions (also referred to as an "implant dose"), and the modified as-deposited strain correction layer 501, referred to herein as strain correction layer 503, corrects the OPD, as shown in FIG. 5. In some embodiments, the implanted ion dose comprises a spatially uniform ion dose. Suitable implanted ions provided from the ion beam can include any ion species capable of inducing stress changes after implantation with appropriate ion energy, and according to some non-limiting embodiments, include ions such as argon (Ar), phosphorus (P), silicon (Si), carbon (C), boron (B), nitrogen (N), krypton (Kr), indium (In), or fluorine (BF), with the ion energy adjusted depending on the ion species used. A dose of implanted ions is applied to the as-deposited strain correction layer 501 using an ion implantation energy source to correct OPD and reduce or minimize in-plane distortion (IPD) that impacts device fabrication and other device patterning procedures. Non-limiting examples of ion implantation energy sources include an ion beam that can be scanned relative to the backside 103 of the substrate 101. In various embodiments, the ion implantation energy source can deliver a dose into the substrate that involves a uniform direct-write process. In this context, a "direct-write" process, including a direct-write implantation process, can refer to a process that utilizes relative movement of an ion beam or other beam used to generate a uniform dose across the substrate surface. In some embodiments, a direct-write process using an ion implantation energy source can involve exposure to electrons, such as an electron beam, or photons, such as a laser beam, to globally adjust stress in the as-deposited strain correction layer 501 to adjust the substrate curvature and, therefore, the substrate OPD. In some embodiments of activity 308, the system controller determines the ion energy (keV), dose (atoms / cm), and / or the thickness of the as-deposited distortion correction layer 501 based on the data collected during activity 302 and the thickness of the as-deposited distortion correction layer 501. 2), and / or ion species. In some embodiments, method 300 is complete after performing activity 308, and substrate 101 is ready for transfer to one or more subsequent processing steps, such as additional 3D memory device (e.g., 3D NAND device) processing steps. In one non-limiting example, the ion implantation process involves implanting a silicon nitride (Si) layer having a thickness of approximately 1,300 Å. x N y ) to the as-deposited distortion correction layer with a constant energy such as 65 keV and 1x10 12 ~1x10 16 atoms / cm 2 In another non-limiting example, the ion implantation process includes implanting argon (Ar) ions at a dose of about 1000 Å to a thickness of about 2,000 Å to correct for an OPD of about 300 μm. x N y The method involves implanting argon (Ar) ions at a constant energy, such as 70 keV, into the as-deposited strain correction layer.

[0025]

[0030] However, in some embodiments of method 300, activities 310-314 are additionally performed to further adjust the OPD found in substrate 101 after activity steps 302-308 are performed. In activity 310, after performing activities 302-308, the OPD of substrate 101 is again measured to determine whether further OPD correction is necessary. In activity 312, a system controller (not shown) determines a second desired distortion correction amount necessary to correct the OPD found in substrate 101. The determined second distortion correction amount is based on data collected during activity 310. In activity 314, an ion implantation process is performed, a second uniform dose of implanted ions is calculated based on activities 310 and 312, the distortion correction layer 503 formed during activity 308 is exposed to the second uniform dose of implanted ions, and the remaining OPD is corrected by the modified distortion correction layer 503.

[0026]

[0031] In another embodiment of method 300, the dose of implant ions is calculated during activity 308, but the ion implantation process is not performed during activity 308. In this case, the ion implantation process is performed during activity 314, and the ion implantation dose includes providing a total implantation dose that includes the ion implantation dose calculated during activity 308 and the second implantation dose determined during activity 314. Thus, in activity 314, the system controller determines the ion energy (keV), dose (atoms / cm), and the thickness of the as-deposited distortion correction layer based on the data collected during activities 302 and 310. 2 ), and / or ion species, necessary to deliver the total implant dose.

[0027] Example

[0032] 6 is a graph illustrating the effect of increasing the amount of uniform implant dose provided to the strain correction layer of the strain correction structure. The graph was generated using a fixed ion energy level applied to the entire backside of the substrate 101. It can be seen that as the implanted ion dose increases, the global substrate bow 601 decreases.

[0028]

[0033] Figures 7-9 show the effect of different uniform implant dose levels on out-of-plane distortion using a distortion compensation structure including a silicon nitride layer. Figure 7 shows OPD data for an example substrate before and after ion implantation at a low uniform implant dose. Figure 8 shows OPD data for an example substrate before and after ion implantation at a medium uniform implant dose. Figure 9 shows example OPD data for a substrate before and after an ion implantation process at a high uniform implant dose. As shown in Figure 7, at a low uniform implant dose, the substrate bow is slightly compensated (e.g., a global substrate bow of 40 μm is compensated to 36 μm). As shown in Figures 8 and 9, at a medium and high uniform implant dose, the substrate bow is overcompensated (e.g., a global substrate bow of 16 μm and 26 μm is compensated to -19 μm and -37 μm, respectively).

[0029]

[0034] Applications of the disclosures provided herein can be used during the formation of 2D NAND, 3D NAND, 2D DRAM, 3D DRAM, and logic devices. Applications of the disclosures provided herein can also be used in various device packaging applications, such as hybrid wafer bonding and other similar packaging processes.

[0030]

[0035] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, which scope is determined by the appended claims.

Claims

1. A substrate including a semiconductor device, a plurality of semiconductor device layers formed on a front side of a substrate, the semiconductor device layers including at least one layer that contains compressive or tensile stress that causes an out-of-plane strain in the substrate; a distortion correction structure formed on a rear surface of the substrate, the distortion correction structure including a distortion correction layer; The distortion correction layer comprises: a first material having a compressive or tensile stress immediately after deposition on the backside surface and having a thickness; implanted ions uniformly distributed across the back surface of the first material disposed across the back surface of the substrate; Including, the thickness and the compressive or tensile stress formed in the as-deposited first material cannot compensate for all of the out-of-plane strain formed in the substrate; the implanted ions include a uniform dose of implanted ions delivered at a first ion energy; the combination of the as-deposited first material and the addition of the implanted ions into the first material is configured to correct the out-of-plane distortion formed in the substrate. substrate.

2. 2. The substrate of claim 1, wherein the thickness of the as-deposited first material and parameters of the ion implantation process used to implant ions are selected such that the implanted ions are not implanted into the backside of the substrate.

3. The substrate of claim 2 , wherein the implanted ions comprise argon (Ar), phosphorus (P), silicon (Si), or carbon (C).

4. The substrate of claim 1 , wherein the plurality of semiconductor device layers are configured to form at least a portion of a 3D memory device.

5. 1. A method of forming a three-dimensional memory device, comprising: measuring out-of-plane strain formed in a substrate having a plurality of semiconductor device layers formed on a front side of the substrate; determining at least one distortion compensation parameter used to form a distortion compensation structure formed on the backside of the substrate; forming a strain correction layer of the strain correction structure on the back surface of the substrate, the strain correction layer comprising a first material having a compressive stress or a tensile stress immediately after deposition on the back surface and having a thickness; performing an ion implantation process to uniformly implant ions across the back surface of the first material deposited on the back surface of the substrate; Including, the thickness and the compressive or tensile stress formed in the as-deposited first material cannot compensate for all of the out-of-plane strain formed in the substrate; the implanted ions include a uniform dose of implant ions delivered at a first ion energy; the combination of the as-deposited first material and the addition of the implanted ions into the first material is configured to correct the out-of-plane distortion formed in the substrate. method.

6. 6. The method of claim 5, wherein the thickness of the as-deposited first material and parameters of the ion implantation process used to implant the implanted ions are selected such that the implanted ions are not implanted into the backside of the substrate.

7. 7. The method of claim 6, wherein the implanted ions include argon (Ar), phosphorus (P), silicon (Si), or carbon (C).

8. 8. The method of claim 7, wherein the plurality of semiconductor device layers are configured to form at least a portion of a 3D memory device.

9. 6. The method of claim 5, wherein the at least one distortion correction parameter comprises at least one of the thickness of the as-deposited first material, ion energy, dose, and ion species required during the ion implantation process.

10. The method of claim 5 , wherein determining the at least one distortion correction parameter is performed by a system controller after receiving information regarding a measurement of the out-of-plane distortion formed in the substrate.

11. 11. The method of claim 10, wherein the system controller is further configured to control the thickness, ion energy, dose, and ion species of the as-deposited first material during the ion implantation process after determining the at least one distortion correction parameter.

12. 1. A method of forming a distortion compensation structure, comprising: depositing a strain compensation layer on a backside of a substrate having a plurality of semiconductor device layers on a frontside of the substrate, at least one of the plurality of semiconductor device layers having a compressive or tensile stress that induces an out-of-plane strain in the substrate; performing an ion implantation process to expose the as-deposited strain compensation layer to a uniform dose of implanted ions; A method comprising:

13. The distortion correction layer is made of silicon nitride (Si ３ N ４ 13. The method of claim 12, comprising a )-containing layer.

14. The method of claim 12, wherein the thickness of the distortion correction layer is between 1,000 Å and 2,000 Å.

15. 13. The method of claim 12, wherein the implanted ions include phosphorus, boron, argon, nitrogen, krypton, indium, or boron fluorine.

16. The ion implantation process is performed at a constant energy of 65 keV to 70 keV and 1×10 １２ ~1 x 10 １６ atoms / cm ２ 13. The method of claim 12, comprising implanting argon (Ar) ions into the as-deposited strain compensation layer at a dose of .

17. Prior to depositing the distortion compensation layer, measuring the out-of-plane strain of the substrate; determining at least one distortion correction parameter used to form the distortion correction layer; The method of claim 12 further comprising:

18. 20. The method of claim 17, wherein the at least one distortion correction parameter comprises at least one of a thickness of the distortion correction layer, an ion energy, a dose, and an ion species required during the ion implantation process.

19. After the ion implantation process, measuring out-of-plane strain found in the substrate; determining at least one distortion correction parameter to be used to form the additional distortion correction layer; The method of claim 12 further comprising:

20. depositing the additional distortion correction layer on the backside of the substrate; performing an ion implantation process to expose the as-deposited additional strain compensation layer to a uniform dose of implanted ions; 20. The method of claim 19, further comprising:

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