Direct backside self-aligned contact

Abstract

A semiconductor structure is provided that includes a backside source / drain contact structure in contact with the source / drain regions of a transistor and overlapping a portion of a triple-layer bottom dielectric isolation structure located on the backside of the transistor. The presence of the triple-layer bottom dielectric isolation structure prevents shorts between the transistor's gate structure and the backside source / drain contact structure, thus improving process margins.

Description

[Technical Field]

[0001] This application relates to semiconductor technology, and more particularly to semiconductor structures with self-aligned backside source / drain contact structures and methods for forming the same. [Background technology]

[0002] Integrated circuits continue to scale to smaller feature dimensions and higher transistor densities. Three-dimensional (3D) integration increases transistor density by leveraging the Z dimension and building up in the X and Y dimensions as well as building laterally outward. Another development that can be used for increasingly densely packed semiconductor devices is establishing electrical connections between semiconductor devices using both front-side and back-side connections. Whether an integrated circuit includes one device layer (or, equivalently, a "device region") or multiple device layers, the use of back-side connections can improve various aspects of the configuration and performance of semiconductor devices, especially with respect to density constraints. Summary of the Invention

[0003] A semiconductor structure is provided that includes a backside source / drain contact structure in contact with the source / drain regions of a transistor and overlapping a portion of a triple-layer bottom dielectric isolation structure located on the backside of the transistor. The backside source / drain contact is self-aligned. The presence of the triple-layer bottom dielectric isolation structure prevents shorts between the transistor's gate structure and the backside source / drain contact structure, thus improving process margins.

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment, the semiconductor structure includes a transistor including a gate structure and a first source / drain region located on a first side of the gate structure and a second source / drain region located on a second side of the gate structure. The structure further includes a triple-layer bottom dielectric isolation structure located below the transistor, a backside power rail located below the triple-layer bottom dielectric isolation structure and spaced apart from the triple-layer bottom dielectric isolation structure, and a backside source / drain contact structure connecting the backside power rail to the first source / drain region of the transistor. According to the present application, the backside source / drain contact structure overlaps (i.e., vertically) at least a portion of the triple-layer bottom dielectric isolation structure. The presence of the triple-layer bottom dielectric isolation structure provides a thick dielectric cap that prevents the backside source / drain contact structure from shorting the gate structure. In prior art, the bottom isolation structure is a thin structure, typically less than 10 nm thick, and therefore a short circuit may occur between the gate structure and the backside source / drain contact structure.

[0005] In an embodiment of the present application, the three-layer bottom dielectric insulating structure includes a first bottom dielectric insulating layer, a second bottom dielectric insulating layer, and a third bottom dielectric insulating layer, where the first and third bottom dielectric insulating layers are both composed of a first dielectric material, and the second bottom dielectric insulating layer is composed of a second dielectric material that is compositionally different from the first dielectric material. In this application, the second bottom dielectric insulating layer is sandwiched between the first and third bottom dielectric insulating layers. The different dielectric materials provide etch selectivity to the structure, allowing the etch used to form the backside source / drain contact openings that accommodate the backside source / drain contact structures to stop on the second bottom dielectric insulating layer, thus preventing exposure of the gate structure.

[0006] In embodiments of the present application, the first dielectric material comprises a low-k spacer dielectric material (i.e., a dielectric constant of less than 5.5) and the second dielectric material comprises a high-k gate dielectric material (i.e., a dielectric constant of 4.0 or greater), which provides the etch selectivity described above.

[0007] In an embodiment of the present application, the structure further comprises a gate spacer located on a sidewall of the gate structure, wherein the gate spacer is composed of a first dielectric material. This aspect of the present application relates to a process in which the gate spacer, the first bottom dielectric insulating layer, and the third bottom dielectric insulating layer are simultaneously formed.

[0008] In an embodiment of the present application, the gate structure includes a gate dielectric material layer, where the gate dielectric material layer is composed of a second dielectric material. This aspect of the present application relates to a process in which the gate dielectric material layer and the second bottom dielectric insulating layer are formed simultaneously.

[0009] In the present embodiment, the backside source / drain contact structure contacts the sidewalls of the first bottom dielectric insulating layer, the horizontal and sidewall surfaces of the second bottom dielectric insulating layer, and the sidewalls of the third bottom dielectric insulating layer, which is a result of the different dielectric materials used in forming the three-layer bottom dielectric insulating structure, and as a result, short circuits between the gate structure and the backside source / drain contact structure are avoided.

[0010] In an embodiment of the present application, the structure further comprises a semiconductor buffer layer located on a surface of the first source / drain region, wherein the semiconductor buffer layer embeds a portion of the backside source / drain contact structure, and serves as a growth surface for the source / drain region, enabling the formation of high-quality source / drain regions as defined later in the present application.

[0011] In an embodiment of the present application, the structure further comprises a multi-layer backside interlayer dielectric material structure embedding another portion of the backside source / drain contact structure, wherein the multi-layer backside interlayer dielectric material structure further embeds a backside power rail.

[0012] In an embodiment of the present application, the structure further comprises a backside power distribution network in contact with the backside power rail, the backside power distribution network distributing power to the transistors.

[0013] In an embodiment of the present application, the structure further comprises a front-side source / drain contact structure in contact with the second source / drain region, the presence of the front-side source / drain contact structure allowing the transistor to be connected to other electronic components.

[0014] In an embodiment of the present application, the front side source / drain contact structures are embedded within the first front side inter-layer dielectric material layer and the second front side inter-layer dielectric material layer.

[0015] In an embodiment of the present application, the structure further comprises a front-side gate contact structure located in the second front-side inter-layer dielectric material layer and in contact with the gate electrode of the gate structure, the presence of the front-side gate contact structure allowing the transistor to be connected to other electronic components.

[0016] In an embodiment of the present application, the structure further comprises a front-side back-end structure located on the second front-side inter-layer dielectric material layer, wherein the front-side back-end structure is electrically connected to the second source / drain regions by front-side source / drain contact structures.

[0017] In an embodiment of the present application, the structure further comprises a carrier wafer positioned on the surface of the front-side back-end structure.

[0018] In the present embodiment, the transistors are located on one side of a gate-cut dielectric pillar, which is used to separate one transistor from another.

[0019] In embodiments of the present application, the transistor is a nanosheet transistor comprising a nanosheet stack of suspended semiconductor channel material nanosheets, in such embodiments, a gate structure of the transistor wraps around each of the suspended semiconductor material nanosheets.

[0020] In an embodiment of the present application, the gate structure of the transistor includes a gate electrode located above and laterally adjacent to the triple-layer bottom dielectric isolation structure.

[0021] In another aspect of the present application, a method for forming a semiconductor structure is provided. The method includes forming a three-layer bottom dielectric isolation structure under a gate structure of a transistor, the gate structure including a first source / drain region located on one side of the gate structure and a second source / drain region located on a second side of the gate structure. A backside source / drain contact structure is then formed in contact with a surface of the first source / drain region, wherein forming the backside source / drain contact structure includes etching partially through the three-layer bottom dielectric isolation structure. This method improves process margins and eliminates shorts between the gate structure and the backside source / drain contact structure. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1B is a top view of a device layout that may be used to describe a semiconductor structure according to the present application, including an XX cut along a first semiconductor fin structure, a Y1-Y1 cut located through a gate structure, and a Y2-Y2 cut within a source / drain area located between two adjacent gate structures.

[0023] [Figure 2A] 1 through XX of FIG. 1 of an exemplary structure that may be used in the present application, the exemplary structure including at least one semiconductor fin structure located on a surface of a semiconductor substrate, the semiconductor fin structure including a material stack of a first sacrificial semiconductor material layer, a second sacrificial semiconductor material layer, a third sacrificial semiconductor material layer, and an alternating fourth sacrificial semiconductor material layer and a semiconductor channel material layer, and at least one sacrificial gate structure located on the surface of the semiconductor fin structure. [Figure 2B] 1 is a cross-sectional view taken along line Y1-Y1 of FIG. 1 of an exemplary structure that may be used in the present application, the exemplary structure including at least one semiconductor fin structure located on a surface of a semiconductor substrate, the semiconductor fin structure including a material stack of a first sacrificial semiconductor material layer, a second sacrificial semiconductor material layer, a third sacrificial semiconductor material layer, and an alternating fourth sacrificial semiconductor material layer and a semiconductor channel material layer, and at least one sacrificial gate structure located on the surface of the semiconductor fin structure. [Figure 2C] 1 through Y2-Y2 of an exemplary structure that may be used in the present application, the exemplary structure including at least one semiconductor fin structure located on a surface of a semiconductor substrate, the semiconductor fin structure including a material stack of a first sacrificial semiconductor material layer, a second sacrificial semiconductor material layer, a third sacrificial semiconductor material layer, and an alternating fourth sacrificial semiconductor material layer and a semiconductor channel material layer, and at least one sacrificial gate structure located on the surface of the semiconductor fin structure.

[0024] [Figure 3A] 2B is a cross-sectional view of the exemplary structure shown in FIG. 2A after removing the first sacrificial semiconductor material layer to form a first gap and removing the third sacrificial semiconductor material layer to form a second gap, the first gap and the second gap being separated by the second sacrificial semiconductor material layer. [Figure 3B] 2B, after removing the first sacrificial semiconductor material layer to form a first gap and removing the third sacrificial semiconductor material layer to form a second gap, the first gap and the second gap are separated by the second sacrificial semiconductor material layer. [Figure 3C] 2C, after removing the first sacrificial semiconductor material layer to form a first gap and removing the third sacrificial semiconductor material layer to form a second gap, where the first gap and the second gap are separated by the second sacrificial semiconductor material layer.

[0025] [Figure 4A] 3B is a cross-sectional view of the exemplary structure shown in FIG. 3A after forming a gate dielectric spacer material along sidewalls of at least one sacrificial gate structure and in the first and second gaps. [Figure 4B] 3C is a cross-sectional view of the exemplary structure shown in FIG. 3B after forming a gate dielectric spacer material along sidewalls of at least one sacrificial gate structure and in the first and second gaps. [Figure 4C] 3D is a cross-sectional view of the exemplary structure shown in FIG. 3C after forming a gate dielectric spacer material along sidewalls of at least one sacrificial gate structure and in the first and second gaps.

[0026] [Figure 5A] FIG. 4B is a cross-sectional view of the exemplary structure shown in FIG. 4A after patterning the material stack to form a nanosheet stack of alternating fourth sacrificial semiconductor material nanosheets and semiconductor channel material nanosheets, forming a recess in each fourth sacrificial semiconductor material nanosheet of the nanosheet stack, and forming an inner spacer laterally adjacent to each recessed fourth semiconductor material nanosheet. [Figure 5B] FIG. 4C is a cross-sectional view of the exemplary structure shown in FIG. 4B after patterning the material stack to form a nanosheet stack of alternating fourth sacrificial semiconductor material nanosheets and semiconductor channel material nanosheets, forming a recess in each fourth sacrificial semiconductor material nanosheet in the nanosheet stack, and forming an inner spacer laterally adjacent to each recessed fourth semiconductor material nanosheet. [Figure 5C]FIG. 4C is a cross-sectional view of the exemplary structure shown in FIG. 4C after patterning the material stack to form a nanosheet stack of alternating fourth sacrificial semiconductor material nanosheets and semiconductor channel material nanosheets, forming a recess in each fourth sacrificial semiconductor material nanosheet in the nanosheet stack, and forming an inner spacer laterally adjacent to each recessed fourth semiconductor material nanosheet.

[0027] [Figure 6A] 5B is a cross-sectional view of the exemplary structure shown in FIG. 5A after performing an etch to physically expose the footprint of at least one sacrificial gate structure and a surface of the second semiconductor material layer of the semiconductor substrate located on each side thereof, forming a semiconductor buffer layer on the physically exposed surface of the second semiconductor material layer of the semiconductor substrate, forming source / drain regions on the semiconductor buffer layer, and forming a front-side inter-layer dielectric (ILD) material layer on the source / drain regions. [Figure 6B] 5B after performing an etch to physically expose the footprint of at least one sacrificial gate structure and a surface of the second semiconductor material layer of the semiconductor substrate on each side thereof, forming a semiconductor buffer layer on the physically exposed surface of the second semiconductor material layer of the semiconductor substrate, forming source / drain regions on the semiconductor buffer layer, and forming a front-side inter-layer dielectric (ILD) material layer on the source / drain regions. [Figure 6C] 5C after performing an etch to physically expose the footprint of at least one sacrificial gate structure and a surface of the second semiconductor material layer of the semiconductor substrate on each side thereof, forming a semiconductor buffer layer on the physically exposed surface of the second semiconductor material layer of the semiconductor substrate, forming source / drain regions on the semiconductor buffer layer, and forming a front-side inter-layer dielectric (ILD) material layer on the source / drain regions.

[0028] [Figure 7A]6B is a cross-sectional view of the exemplary structure shown in FIG. 6A after removing at least one sacrificial gate structure, the second sacrificial semiconductor material layer, and each of the recessed fourth semiconductor material nanosheets, and after removing the second semiconductor material layer to form a third gap between the first and second gaps filled with a gate dielectric spacer material. [Figure 7B] 6B after removing at least one sacrificial gate structure, the second sacrificial semiconductor material layer, and the recessed fourth semiconductor material nanosheet, and after removing the second semiconductor material layer to form a third gap between the first and second gaps filled with a gate dielectric spacer material. [Figure 7C] 6D is a cross-sectional view of the exemplary structure shown in FIG. 6C after removing at least one sacrificial gate structure, the second sacrificial semiconductor material layer, and each of the recessed fourth semiconductor material nanosheets, and after removal of the second semiconductor material layer has formed a third gap between the first and second gaps filled with a gate dielectric spacer material.

[0029] [Figure 8A] FIG. 7B is a cross-sectional view of the exemplary structure shown in FIG. 7A after forming a high-k gate dielectric material in the third gap and on the physically exposed portion of each semiconducting channel material nanosheet. [Figure 8B] FIG. 7C is a cross-sectional view of the exemplary structure shown in FIG. 7B after forming a high-k gate dielectric material in the third gap and on the physically exposed portion of each semiconducting channel material nanosheet. [Figure 8C] FIG. 7D is a cross-sectional view of the exemplary structure shown in FIG. 7C after forming a high-k gate dielectric material in the third gap and on the physically exposed portion of each semiconducting channel material nanosheet.

[0030] [Figure 9A] 8B is a cross-sectional view of the example structure shown in FIG. 8A after forming a gate electrode, forming a gate cut dielectric pillar, forming a second front-side ILD material layer, and forming a front-side contact structure. [Figure 9B] 8C is a cross-sectional view of the example structure shown in FIG. 8B after forming a gate electrode, forming a gate cut dielectric pillar, forming a second front-side ILD material layer, and forming a front-side contact structure. [Figure 9C] 8D is a cross-sectional view of the example structure shown in FIG. 8C after forming a gate electrode, forming a gate cut dielectric pillar, forming a second front-side ILD material layer, and forming a front-side contact structure.

[0031] [Figure 10A] FIG. 9B is a cross-sectional view of the example structure shown in FIG. 9A after forming front-side back-end (BEOL) structures and a carrier wafer. [Figure 10B] FIG. 9C is a cross-sectional view of the example structure shown in FIG. 9B after forming front-side back-end (BEOL) structures and a carrier wafer. [Figure 10C] FIG. 9D is a cross-sectional view of the example structure shown in FIG. 9C after forming front-side back-end (BEOL) structures and a carrier wafer.

[0032] [Figure 11A] 10B is a cross-sectional view of the exemplary structure shown in FIG. 10A after flipping the wafer to physically expose the backside of the semiconductor substrate and removing a first semiconductor material layer of the semiconductor substrate to physically expose an etch stop layer of the semiconductor substrate. [Figure 11B] 10B after flipping the wafer to physically expose the backside of the semiconductor substrate and removing the first semiconductor material layer of the semiconductor substrate to physically expose the etch stop layer of the semiconductor substrate. [Figure 11C] 10C after flipping the wafer to physically expose the backside of the semiconductor substrate and removing the first semiconductor material layer of the semiconductor substrate to physically expose the etch stop layer of the semiconductor substrate.

[0033] [Figure 12A]11B is a cross-sectional view of the example structure shown in FIG. 11A after removing the physically exposed etch stop layer of the semiconductor substrate to physically expose a second semiconductor material layer of the semiconductor substrate. [Figure 12B] 11C is a cross-sectional view of the exemplary structure shown in FIG. 11B after removing the physically exposed etch stop layer of the semiconductor substrate to physically expose a second semiconductor material layer of the semiconductor substrate. [Figure 12C] 11D is a cross-sectional view of the exemplary structure shown in FIG. 11C after removing the physically exposed etch stop layer of the semiconductor substrate to physically expose a second semiconductor material layer of the semiconductor substrate.

[0034] [Figure 13A] 12B is a cross-sectional view of the example structure shown in FIG. 12A after removing the second layer of semiconductor material and a portion of the semiconductor buffer layer. [Figure 13B] 12C is a cross-sectional view of the example structure shown in FIG. 12B after removing the second layer of semiconductor material and a portion of the semiconductor buffer layer. [Figure 13C] 12D is a cross-sectional view of the example structure shown in FIG. 12C after removing the second layer of semiconductor material and a portion of the semiconductor buffer layer.

[0035] [Figure 14A] 13B is a cross-sectional view of the exemplary structure shown in FIG. 13A after forming a backside ILD material layer. [Figure 14B] FIG. 13C is a cross-sectional view of the exemplary structure shown in FIG. 13B after forming a backside ILD material layer. [Figure 14C] FIG. 13D is a cross-sectional view of the exemplary structure shown in FIG. 13C after forming a backside ILD material layer.

[0036] [Figure 15A] FIG. 14B is a cross-sectional view of the exemplary structure shown in FIG. 14A after forming a self-aligned backside source / drain contact structure. [Figure 15B]FIG. 14C is a cross-sectional view of the exemplary structure shown in FIG. 14B after forming a self-aligned backside source / drain contact structure. [Figure 15C] FIG. 14D is a cross-sectional view of the exemplary structure shown in FIG. 14C after forming a self-aligned backside source / drain contact structure.

[0037] [Figure 16A] A cross-sectional view of the exemplary structure shown in Figure 15A after additional backside ILD material has been formed on the backside LID material layer and self-aligned backside source / drain contact structures to form backside power rails and backside distribution networks. [Figure 16B] A cross-sectional view of the exemplary structure shown in Figure 15B after additional backside ILD material is formed on the backside LID material layer and self-aligned backside source / drain contact structures to form backside power rails and backside distribution networks. [Figure 16C] A cross-sectional view of the exemplary structure shown in Figure 15C after additional backside ILD material has been formed on the backside LID material layer and self-aligned backside source / drain contact structures to form backside power rails and backside distribution networks. DETAILED DESCRIPTION OF THE INVENTION

[0038] The present application will now be described in more detail by reference to the following discussion and the drawings that accompany this application. It should be noted that the drawings herein are provided for illustrative purposes only, and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0039] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, it will be understood by those skilled in the art that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0040] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it is understood that the element can be directly on the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it is understood that the element can be directly below or directly below the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0041] Referring first to FIG. 1 , a top view of a device layout that can be used to describe a semiconductor structure according to the present application is shown. The device layout shown in FIG. 1 includes three parallel-oriented gate structures (GS), which intersect different portions of two semiconductor fin structures (Fin) oriented parallel to each other and perpendicular to each of the gate structures. As used herein, a "Fin" refers to a continuous structure that includes one or more semiconductor materials and includes a pair of substantially vertical sidewalls that are parallel to each other. As used herein, a "surface" is "substantially vertical" if there is a vertical plane from which the surface deviates by no more than three times the root-mean-square roughness of the surface. Each Fin may have a vertical height of 15 nm to 100 nm and a width of 4 nm to 100 nm. This device layout includes an XX cut along the first semiconductor fin structure, a Y1-Y1 cut located through the gate structures, and a Y2-Y2 cut in the source / drain area located between two adjacent gate structures. In the present application, each of FIGS. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A and 16A is taken through an XX cut, each of FIGS. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B and 16B is taken through a Y1-Y1 cut, and each of FIGS. 2C, 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C and 16C is taken through a Y2-Y2 cut.

[0042] It should be noted that although this application describes and illustrates nanosheet-containing transistors, i.e., transistors in which a gate structure is wrapped around multiple vertically stacked nanosheets of semiconducting channel material, the application is also advantageous for other types of transistors, such as planar transistors, fin-type transistors, stacked transistors, or semiconductor nanowire transistors.

[0043] In this application, the term "transistor" is used to describe a device that includes a gate structure in contact with a semiconductor channel material structure and that has a first source / drain region located on a first side of the gate structure and a second source / drain region located on a second side of the gate structure opposite the first side of the gate structure.

[0044] In this application, the term "front side" refers to the side of the structure containing the transistor that is located above the semiconductor substrate.

[0045] In this application, the term "backside" refers to the side of the structure that underlies the transistor after the semiconductor substrate has been removed.

[0046] 2A, 2B, and 2C, there are shown exemplary structures that may be used in the present application, respectively extending through XX, Y1-Y1, and Y2-Y2 in FIG. 1. The exemplary structures shown in FIGS. 2A, 2B, and 2C include at least one semiconductor fin structure (Fin) located on the surface of the semiconductor substrate 10 / 12 / 14, and at least one sacrificial gate structure 22 (three of which are shown by way of example) located on the surface of at least the semiconductor fin structure (Fin). In FIGS. 2B and 2C, two Fins are shown by way of example.

[0047] The semiconductor substrate 10 includes a first semiconductor material layer 10, an etch stop layer 12, and a second semiconductor material layer 14. An optional sacrificial cap 24 may be located on top of each sacrificial gate structure 22, and a shallow trench isolation structure 15 may be located in an upper portion of the semiconductor substrate 10 / 12 / 14. In the embodiment shown, the shallow trench isolation structure 15 is formed in the second semiconductor material layer 14, and the shallow trench isolation structure 15 contacts the surface of the etch stop layer 12.

[0048] In accordance with the present application, at least one semiconductor fin structure (Fin) includes a material stack of a first sacrificial semiconductor material layer 16A, a second sacrificial semiconductor material layer 16B, a third sacrificial semiconductor material layer 16C, and an alternating fourth sacrificial semiconductor material layer 18 and a semiconductor channel material layer 20. As shown, each semiconductor fin structure (Fin) is located on top of the second semiconductor material layer 14 of the semiconductor substrate 10 / 12 / 14.

[0049] As described above, the semiconductor substrate includes a first semiconductor material layer 10, an etch stop layer 12, and a second semiconductor material layer 14. The first semiconductor material layer 10 of the semiconductor substrate is composed of a first semiconductor material having semiconducting properties. Examples of first semiconductor materials that can be used to provide the first semiconductor material layer 10 include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloy, silicon germanium carbide (SiGeC) alloy, germanium (Ge), a III / V compound semiconductor, or a II / VI compound semiconductor. The second semiconductor material layer 14 of the semiconductor substrate is composed of a second semiconductor material. The second semiconductor material providing the second semiconductor material layer 14 can be compositionally the same as or different from the first semiconductor material providing the first semiconductor material layer 10. In some embodiments of the present application, the etch stop layer 12 can be composed of a dielectric material, such as, for example, silicon dioxide and / or boron nitride. In other embodiments of the present application, etch stop layer 12 is composed of a semiconductor material that is compositionally different from the semiconductor materials that provide both first semiconductor material layer 10 and second semiconductor material layer 14. In one example, first semiconductor material layer 10 is composed of silicon, etch stop layer 12 is composed of silicon dioxide, and second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate comprising silicon / silicon dioxide / silicon may be referred to as a silicon-on-insulator (SOI) substrate. In another example, first semiconductor material layer 10 is composed of silicon, etch stop layer 12 is composed of silicon germanium, and second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate comprising silicon / silicon germanium / silicon may be referred to as a bulk semiconductor substrate.

[0050] The shallow trench isolation structure 15 is composed of any trench dielectric material, such as, for example, silicon oxide. In some embodiments, the trench dielectric material, such as, for example, SiN, may be present along the sidewalls and bottom wall of the trench dielectric material. As shown in Figures 2B and 2C, the shallow trench isolation structure 15 is laterally adjacent to an unetched portion of the second semiconductor material layer 14 of the semiconductor substrate.

[0051] Both the first sacrificial semiconductor layer 16A and the third sacrificial semiconductor layer 16C are composed of a third semiconductor material that is compositionally different from the second semiconductor material that provides the second semiconductor material layer 14 of the semiconductor substrate, a fourth semiconductor material that provides each of the second sacrificial semiconductor material layer 16B and the fourth sacrificial semiconductor material layer 18, and a fifth semiconductor material that provides each semiconductor channel material layer 20. In one example, the third semiconductor material that provides the first sacrificial semiconductor layer 16A and the third sacrificial semiconductor layer 16C is composed of a silicon-germanium alloy having a germanium content of 55 atomic percent, the fourth semiconductor material that provides each of the second sacrificial semiconductor layer 16B and the fourth sacrificial semiconductor material layer 18 is composed of a silicon-germanium alloy having a germanium content of 30 atomic percent, and the fifth semiconductor material that forms each semiconductor channel material layer 20 is composed of silicon. The fifth semiconductor material providing each semiconductor channel material layer 20 may be compositionally the same as or compositionally different from the second semiconductor material providing second semiconductor material layer 14 .

[0052] In the present application, the first sacrificial semiconductor material layer 16A and the third sacrificial semiconductor layer 16C may have a thickness of 6 to 15 nm, the second sacrificial semiconductor layer 16B may have a thickness of 1 to 5 nm, each of the fourth sacrificial semiconductor material layers 18 may have a thickness of 4 to 15 nm (note that the thickness of the second sacrificial semiconductor material layer 16B is less than the thickness of each of the fourth sacrificial semiconductor material layers 18), and each semiconductor channel material layer 20 may have a thickness of 4 to 12 nm. The width and length of each of these layers are defined above (see the width and length mentioned for the Fin).

[0053] Each sacrificial gate structure 22 includes at least one sacrificial gate material. In some embodiments, each sacrificial gate structure 22 may include a sacrificial gate dielectric material. The sacrificial gate dielectric material may be composed of a dielectric material such as, for example, silicon dioxide. The sacrificial gate material may include, but is not limited to, polysilicon, amorphous silicon, amorphous silicon germanium, or amorphous germanium.

[0054] Each sacrificial cap 24 may be composed of a dielectric hard mask material, such as, for example, silicon nitride and / or silicon oxynitride. In the embodiment shown, each sacrificial cap 24 has a sidewall that is vertically aligned with the sidewall of one of the sacrificial gate structures 22. In embodiments, the sacrificial cap 24 may be omitted from the exemplary structure. Note that no sacrificial gate structure 22 or sacrificial cap 24 is present in the source / drain cross section shown in FIG. 2C.

[0055] 2A-2C can be formed using fin formation processing techniques well known to those skilled in the art. For example, after providing a semiconductor substrate 10 / 12 / 14, a blanket layer of a third semiconductor material used to provide first sacrificial semiconductor material layer 16A, a blanket layer of a fourth semiconductor material used to provide second sacrificial semiconductor material layer 16B, and a blanket layer of a third semiconductor material used to provide third sacrificial semiconductor material layer 16C are formed by one or more deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or epitaxial growth. The terms "epitaxial growth" or "epitaxially growing" refer to the growth of a second semiconductor material on the growth surface of a first semiconductor material, where the grown second semiconductor material has the same crystalline properties as the first semiconductor material. In an epitaxial deposition process, chemical reactants provided by source gases are controlled, and system parameters are set so that the depositing atoms arrive at the growth surface of the first semiconductor material with sufficient energy to move around on the growth surface and orient themselves into the crystalline arrangement of the atoms on the growth surface. Examples of various epitaxial growth process equipment that can be used in the present application include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Epitaxial deposition temperatures typically range from 550°C to 900°C. Higher temperatures typically result in faster deposition, but faster deposition can result in crystalline defects and film cracking.

[0056] Next, a blanket material stack of alternating blanket layers of a fourth semiconductor material used to provide each of the fourth sacrificial semiconductor material layers 18 and a fifth semiconductor material used to provide each of the semiconductor channel material layers 20 is formed. This blanket material stack may be formed by one or more deposition processes, including, for example, CVD, PECVD, or epitaxial growth. This blanket material stack and the underlying blanket material layers may then be patterned by lithography and etching to provide a fin structure including a first sacrificial semiconductor material layer 16A, a second sacrificial semiconductor material layer 16B, a third sacrificial semiconductor material layer 16C, and alternating fourth sacrificial semiconductor material layers 18 and semiconductor channel material layers 20, as shown in FIGS. 2A-2C. Next, shallow trench isolation structures 15 are formed using techniques well known to those skilled in the art. Next, blanket layers of sacrificial gate structure material and blanket layers of hard mask material are formed by a deposition process, such as, for example, CVD, PECVD, physical vapor deposition (PVD), or atomic layer deposition (ALD). The blanket layers of hard mask material and sacrificial gate structure material are then patterned by lithography and etching to provide the sacrificial cap 24 and sacrificial gate structure 22 described above.

[0057] 3A, 3B, and 3C, the exemplary structure shown in FIGS. 2A, 2B, and 2C, respectively, is shown after removing the first sacrificial semiconductor material layer 16A to form a first gap G1 and removing the third sacrificial semiconductor material layer 16C to form a second gap G2, with the first gap G1 and the second gap G2 separated by the second sacrificial semiconductor material layer 16B. The first sacrificial semiconductor material layer 16A and the third sacrificial semiconductor material layer 16C may be removed utilizing an etching process that is selective in removing the third semiconductor material to provide both the first sacrificial semiconductor material layer 16A and the third sacrificial semiconductor material layer 16C relative to other semiconductor materials present in the exemplary structure. In one example, if the third semiconductor material providing both the first sacrificial semiconductor material layer 16A and the third sacrificial semiconductor material layer 16C is composed of a silicon germanium alloy having a germanium content of 55 atomic percent, vapor phase dry hydrochloric acid (HCl) at an appropriate temperature and pressure may be used to remove both the first sacrificial semiconductor material layer 16A and the third sacrificial semiconductor material layer 16C.

[0058] 4A, 4B, and 4C, the exemplary structures shown in FIGS. 3A, 3B, and 3C, respectively, are illustrated after forming gate dielectric spacer material along the sidewalls of at least one sacrificial gate structure 22 (along the sidewalls of the sacrificial cap 24, if present) and in the first gap G1 and second gap G2. The gate dielectric spacer material formed along the sidewalls of at least one sacrificial gate structure 22 (along the sidewalls of the sacrificial cap 24, if present) may be referred to as gate spacers 30, the dielectric gate dielectric spacer material formed in the first gap G1 may be referred to as the first bottom dielectric insulating layer 26, and the dielectric gate dielectric spacer material formed in the second gap G2 may be referred to as the third bottom dielectric insulating layer 28. Note that, in this application, the gate spacers 30, the first bottom dielectric insulating layer 26, and the third bottom dielectric insulating layer 28 are of a single structure (i.e., a single workpiece composed of the same gate dielectric spacer material).

[0059] The gate dielectric spacer material is composed of a dielectric material having a first dielectric constant, typically less than 5.5. Examples of gate dielectric spacer materials that may be used herein include, but are not limited to, SiN, SiOCN, SiON, SiOC, or SiBCN. The gate dielectric spacer material may be formed by a conformal deposition process, such as CVD, PECVD, or ALD, followed by a spacer etch. The conformal deposition and spacer etch provide the gate spacers 30, first bottom dielectric insulating layer 26, and third bottom dielectric insulating layer 28 described above.

[0060] Referring now to Figures 5A, 5B and 5C, the exemplary structures shown in Figures 4A, 4B and 4C, respectively, are shown after patterning the material stack to form a nanosheet stack of alternating fourth sacrificial semiconductor material nanosheets 18NS and semiconductor channel material nanosheets 20NS, forming a recess in each of the fourth sacrificial semiconductor material nanosheets 18NS of the nanosheet stack, and forming inner spacers 32 laterally adjacent to each recessed fourth semiconductor material nanosheet 18NS.

[0061] The material stack is patterned using the gate spacers 30, the sacrificial gate structure 22, and, if present, the sacrificial cap 24 as a combed etch mask. This etching converts the material stack into the nanosheet stack defined above. Note that the fourth sacrificial semiconductor material nanosheets 18NS and the semiconductor channel material nanosheets 20NS are the unetched portions of the fourth sacrificial semiconductor material layer 18 and the semiconductor channel material layer 20. Each of the fourth sacrificial semiconductor material nanosheets 18NS and the semiconductor channel material nanosheets 20NS has a width of 10 nm to 100 nm and a length of 20 nm to 150 nm, prior to forming the inner spacers 32. Next, the inner spacers 32 are formed by selectively etching (i.e., recessing) the edges of each of the fourth sacrificial semiconductor material nanosheets 18NS relative to each of the semiconductor channel material nanosheets 20NS. This selective etching (including lateral etching) provides gaps between the recessed fourth sacrificial semiconductor material nanosheets 18NS and adjacent inner spacers that are then filled with an inner dielectric spacer material, such as SiN, SiBCN, SiOCN, SiON, or SiOC. The filling includes conformal deposition of the inner dielectric spacer material followed by performing an isotropic etch-back process. Inner spacers 32 underlie the edges of each semiconductor channel material nanosheet 20NS, and the inner spacers 32 have outermost walls that are vertically aligned with the outermost walls of the gate spacers 30.

[0062] Referring now to Figures 6A, 6B, and 6C, the exemplary structures shown in Figures 5A, 5B, and 5C, respectively, are shown after performing an etching process to physically expose the footprint of at least one sacrificial gate structure 22 and the surface of the second semiconductor material layer 14 of the semiconductor substrate located on each side thereof, forming a semiconductor buffer layer 34 on the physically exposed surface of the second semiconductor material layer 14 of the semiconductor substrate, forming source / drain regions on the semiconductor buffer layer, forming source / drain regions 36 on the semiconductor buffer layer 34 and extending outward from each of the semiconductor channel material nanosheets 20NS, and forming a front-side interlayer dielectric (ILD) material layer 38 on the source / drain regions 36.

[0063] The etching physically exposes the surface of the second semiconductor material layer 14 of the semiconductor substrate, removing portions of the third bottom dielectric insulating layer 28, the second sacrificial semiconductor material layer 16B, and the first bottom dielectric insulating layer 26 that are not located directly under the overlying nanosheet stack and gate spacer 30. This etching may include a dry etching process, such as, for example, reactive ion etching (RIE), ion beam etching (IBE), or plasma etching.

[0064] The semiconductor buffer layer 34 is formed using an epitaxial growth process followed by recess etching. The semiconductor buffer layer 34 comprises one of the semiconductor materials described above for the first semiconductor material layer 10, and the semiconductor material providing the semiconductor buffer layer 34 is typically compositionally different from the fourth semiconductor material providing each of the sacrificial semiconductor material nanosheets 18NS. The semiconductor buffer layer 34 has a top surface that is coplanar with, above, or below the top surface of the third bottom dielectric insulating layer 28 underlying each nanosheet stack. The presence of the semiconductor buffer layer 34 provides a semiconductor growth surface upon which high-quality source / drain regions 36 may be formed. By "high-quality," it is meant that the source / drain regions 36 are substantially free of epi-related defects (e.g., missing epi, stack defects, misalignment, etc.).

[0065] The source / drain regions 36 (formed on each side of the nanosheet stack) are composed of a semiconductor material (including one of the semiconductor materials described above for the first semiconductor material layer 10) and a dopant. As used herein, a "source / drain or S / D" region can be a source region or a drain region, depending on subsequent wiring and the voltage application during transistor operation. The semiconductor material providing the source / drain regions 36 can be compositionally the same as or different from the semiconductor material providing each semiconductor channel material nanosheet 20NS and / or the first semiconductor material layer 10. The dopant present in the source / drain regions 36 can be either a p-type dopant or an n-type dopant. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, phosphorus, and indium. "n-type" refers to the addition of an impurity to an intrinsic semiconductor that contributes free electrons. In silicon-containing semiconductor materials, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. In one example, the source / drain regions 36 have a dopant concentration of 4×10 20 atoms / cm 3 From 3 x 10 21 atoms / cm 3 The source / drain regions 36 may be formed by epitaxial growth followed by a recess etch to reduce the height of the source / drain regions 36 to be less than the height of the sacrificial gate structure 22.

[0066] The front-side ILD material layer 38 may be composed of a dielectric material including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" refers to a dielectric material having a dielectric constant less than 4.0. All dielectric constants referred to herein are measured in a vacuum unless otherwise specified. The front-side ILD material layer 38 may be formed by deposition of a dielectric material followed by a planarization process, such as chemical mechanical polishing (CMP). The deposition of the dielectric material may include, for example, CVD, PECVD, ALD, or spin-on coating. The planarization process may remove the sacrificial cap 24 and an upper portion of each gate spacer 30. The front-side ILD material layer 38 has a top surface that is coplanar with at least the top surface of the sacrificial gate structure 22.

[0067] 7A, 7B, and 7C, the exemplary structures shown in FIGS. 6A, 6B, and 6C, respectively, are shown after removing at least one sacrificial gate structure 22, the second sacrificial semiconductor material layer 16B, and each of the recessed fourth semiconductor material nanosheets 18NS, and removing the second semiconductor material layer 16B has formed a third gap G3 between the first and second gaps filled with gate dielectric spacer material, i.e., between the first bottom dielectric insulating layer 26 and the third bottom dielectric insulating layer 28.

[0068] Removal of the sacrificial gate structure 22 involves an etching process that is selective in removing the material that provides the sacrificial gate structure 22. Typically, a single etch is used, but multiple etches may be used depending on the materials present in the sacrificial gate structure 22. Removal of the sacrificial gate structure 22 involves removal of the sacrificial gate material and, if present, the sacrificial gate dielectric material. Removal of the sacrificial gate structure 22 exposes each nanosheet stack.

[0069] The second sacrificial semiconductor material layer 16B and each of the recessed fourth semiconductor material nano-sheets 18NS can be removed using the same selective etching process, which not only creates the third gap G3 but also leaves portions of each semiconductor channel material nano-sheet 20NS free.

[0070] 8A, 8B, and 8C, the exemplary structures shown in FIGS. 7A, 7B, and 7C, respectively, are illustrated after forming a high-k gate dielectric material 40L in the third gap and on the physically exposed portions of each semiconductor channel material nanosheet 20Ns (the high-k gate dielectric material 40L is also formed on the physically exposed surfaces of the shallow trench isolation structures 15, as shown in FIG. 8B, and on the top surface of the front-side ILD material layer, as shown in FIGS. 8A and 8C). The high-k gate dielectric material 40L has a second dielectric constant greater than the first dielectric constant described above for the gate dielectric spacer material. Thus, the high-k gate dielectric material 40L comprises a compositionally different dielectric material from the gate dielectric spacer material.

[0071] The high-k gate dielectric material 40L has a dielectric constant of 4.0 or greater. Illustrative examples of high-k gate dielectric materials include, for example, silicon dioxide, hafnium dioxide (HfO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium dioxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium silicon oxynitride (ZrSiO). x N y ), tantalum oxide (TaO xThe high-k gate dielectric material 40L may further include a dopant such as lanthanum (La), aluminum (Al), and / or magnesium (Mg). The high-k gate dielectric material 40L may be formed using any conformal deposition process, such as CVD, PECVD, or ALD.

[0072] 9A, 9B, and 9C, the exemplary structures shown in Figures 8A, 8B, and 8C, respectively, are shown after forming a gate electrode 42, forming a gate cut dielectric pillar 44, forming a second front-side ILD material layer 46, and forming front-side contact structures 48, 49. The gate electrode 42 includes a work function metal (WFM) layer and, optionally, a conductive metal layer.

[0073] The WFM layer can be used to set the threshold voltage of a transistor to a desired value. In some embodiments, the WFM layer can be selected to produce an n-type threshold voltage shift. "N-type threshold voltage shift," as used herein, refers to a shift in the effective work function of a work function metal-containing material toward the conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal ranges from 4.1 eV to 4.3 eV. Examples of such materials that can produce an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM layer can be selected to produce a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal ranges from 4.9 eV to 5.2 eV. As used herein, "threshold voltage" refers to the lowest achievable gate voltage that turns on a semiconductor device, e.g., a transistor, by making the device's channel conductive. The term "p-type threshold voltage shift," as used herein, refers to a shift in the effective work function of a metal-containing material toward the valence band of silicon within the silicon-containing material. Examples of such materials that can produce a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. The optional conductive metal layer of the gate electrode 42 may be composed of aluminum (Al), tungsten (W), copper (Co), etc.

[0074] The gate electrode 42 may be formed by a deposition process followed by a planarization process, such as CMP. Deposition processes include, but are not limited to, CVD, PECVD, sputtering, or plating. The planarization process removes any WFM layer and, if present, the conductive metal layer present on top of the first ILD material layer 38 and the gate spacers 30. The planarization process also removes the high-k gate dielectric material 40L present on top of the first ILD material layer 38 and the gate spacers 30. The high-k gate dielectric material 40L remains in the third gap G3 along the physically exposed surfaces of each semiconductor channel material nanosheet, along the inner sidewalls of the gate spacers, along the top surface of the shallow trench isolation structure 15, and along the physically exposed surfaces of the first bottom dielectric insulating layer 26 and the third bottom dielectric insulating layer 38. The remaining high-k gate dielectric material 40L present in the third gap G3 may be referred to herein as the second bottom dielectric insulating layer 41 of the three-layer bottom dielectric insulating structure, which also includes the first bottom dielectric insulating layer 26 and the third bottom dielectric insulating layer 28. The second bottom dielectric insulating layer 41 of the three-layer bottom dielectric insulating structure is sandwiched between the first bottom dielectric insulating layer 26 and the third bottom dielectric insulating layer 28 of the three-layer bottom dielectric insulating structure. The high-k gate dielectric material 40L present on the physically exposed portions of the semiconductor channel material nanosheet 20NS, along the inner sidewalls of the gate spacer 30, forms a gate dielectric material layer 40 of the transistor's gate structure, which further includes a gate electrode 42 including a WFM layer and an optional conductive metal layer. The high-k material layer remaining on the physically exposed surfaces of the first and second bottom dielectric insulating layers 26 and 28 also forms the gate dielectric material layer of the gate structure.

[0075] After forming the gate electrode 42, a gate-cut trench (not shown) is formed in the gate electrode 42 and then filled with a gate-cut dielectric material, such as silicon dioxide or silicon nitride, to form a gate-cut dielectric pillar 44. The gate-cut dielectric pillar 44 extends through the gate electrode 42 and a portion of the high-k gate material present above the shallow trench isolation structure 15. The gate-cut dielectric pillar 44 has a top surface that is coplanar with the top surface of the gate electrode 42. In some embodiments, the gate-cut dielectric pillar 44 may be omitted.

[0076] The second front-side ILD material layer 46 comprises one of the dielectric materials described above for the first front-side ILD material layer 38. The dielectric material providing the second front-side ILD material layer 46 may be compositionally the same as or compositionally different from the dielectric material providing the first front-side ILD material layer 38. The second front-side ILD material layer 46 may be formed utilizing one of the deposition processes described above for forming the dielectric material providing the first front-side ILD material layer 38.

[0077] Front-side contact structures 48, 49 are formed using any conventional metallization process. The front-side contact structures in contact with the source / drain regions 36 may be referred to as front-side source / drain contact structures 48, while the front-side contact structures in contact with the gate electrode 42 may be referred to as front-side gate contact structures 49. The front-side contact structures 48, 49 include at least one contact conductor material, such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof. In embodiments, the front-side contact structures 48, 49 may also include a silicide liner, such as TiSi, NiSi, NiPtSi, and an adhesion metal liner, such as TiN. Each front-side contact structure 48, 49 may be formed by forming contact openings in the various front-side ILD material layers using lithography and etching. For the front-side gate contact structure 49, the contact opening is formed only through the second front-side ILD material layer 46, while for the front-side source / drain contact structure 48, the contact opening is formed through both the first and second front-side ILD material layers 38, 46. The contact conductor material may be formed in the contact openings by any suitable deposition method, such as ALD, CVD, PVD, or plating. In some embodiments (not shown), a metal semiconductor alloy region may be formed in each of the contact openings before forming the contact conductor material. The metal semiconductor alloy region may be composed of a silicide or a biocide. In one or more embodiments herein, the metal semiconductor alloy region may be formed by first depositing a metal layer (not shown) in the trench. The metal layer may include a metal such as Ni, Co, Pt, W, Ti, Ta, a rare earth metal (e.g., Er, Yt, La), an alloy thereof, or any combination thereof. The metal layer may be deposited by ALD, CVD, PVD, or ALD. The thickness of the metal layer can be from 2 to 10 nm, although lesser and greater thicknesses can also be used. A diffusion barrier (not shown), such as TiN or TaN, can then be formed above the metal layer. An annealing process can then be performed at high temperature to induce reaction of the semiconductor material in the source / drain regions to provide a metal-semiconductor alloy region.Next, the unreacted portions of the metal layer and, if present, the diffusion barrier are removed, for example, by an etching process (or multiple etching processes). In one embodiment, the etching process can be a wet etch that removes the metal in the metal layer selectively to the metal-semiconductor alloy in the metal-semiconductor alloy region. Each front-side contact structure 48, 49 can further include one or more contact liners (not shown). In one or more embodiments, the contact liners (not shown) can include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. The contact liners can be formed using a conformal deposition process, including CVD or ALD. The formed contact liners can have a thickness ranging from 1 nm to 5 nm, although lesser and greater thicknesses can also be used. Each front-side contact structure 48, 49 has a top surface that is coplanar with the top surface of the second front-side ILD material layer 46.

[0078] 10A, 10B, and 10C, the exemplary structure shown in FIGS. 9A, 9B, and 9C, respectively, is illustrated after forming a front-side back-end (BEOL) structure 50 and a carrier wafer 52. The front-side BEOL structure 50 includes one or more interconnect dielectric material layers with one or more wiring regions embedded therein. The front-side BEOL structure 50 may be formed using BEOL processing techniques well known to those skilled in the art. As shown in FIGS. 10A through 10C, the front-side BEOL structure 50 is electrically connected to one of the source / drain regions 36 by a front-side source / drain contact structure 48 and to the gate electrode 42 by a front-side gate contact structure 39. The carrier wafer 52 may include one of the semiconductor materials described above for the first semiconductor material layer 10. In the present application, the carrier wafer 52 is bonded to the front-side BEOL structure 50.

[0079] 11A, 11B, and 11C, the exemplary structure shown in FIGS. 10A, 10B, and 10C, respectively, is illustrated after flipping the wafer to physically expose the backside of the semiconductor substrate 10 / 12 / 14 and removing the first semiconductor material 10 of the semiconductor substrate to physically expose the etch stop layer 12 of the semiconductor substrate. This flipping allows for processing of the backside of the exemplary structure. In the present application, the structure is flipped 180 degrees. Flipping the structure can be performed manually or by utilizing mechanical means such as, for example, a robotic arm. Removal of the first semiconductor material layer 10 can be performed using a material removal process that is selective in removing the semiconductor material that provides the first semiconductor material layer 10.

[0080] 12A, 12B, and 12C, the exemplary structures shown in FIGS. 11A, 11B, and 11C, respectively, are shown after removing the physically exposed etch stop layer 12 of the semiconductor substrate to physically expose the second semiconductor material layer 14 of the semiconductor substrate. Removal of the etch stop layer 12 includes a material removal process that is selective in removing the etch stop layer 12.

[0081] 13A, 13B, and 13C, the exemplary structures shown in FIGS. 12A, 12B, and 12C, respectively, are shown after removal of the second semiconductor material layer 14 and portions of the semiconductor buffer layer 34. Removal of the second semiconductor material layer 14 includes a material removal process that is selective in removing the second semiconductor material layer 14. Removal of the portions of the semiconductor buffer layer 34 includes a recess etch that is selective in removing the semiconductor buffer layer. The recess etch used to remove the portions of the semiconductor buffer layer 34 can be the same or a different etch than the selective etch used in removing the second semiconductor material layer 14. Portions of the semiconductor buffer layer 34 remain between the three-layer bottom dielectric isolation structures 26 / 41 / 28 as shown in FIG. 13A and between the gate spacers 30 as shown in FIG. 13C. The remaining semiconductor buffer layer 34 may be referred to herein as a recessed semiconductor buffer layer 34S.

[0082] 14A, 14B, and 14C, the exemplary structure shown in FIGS. 13A, 13B, and 13C, respectively, is shown after forming a backside ILD material layer 54. The backside ILD material layer 54 includes one of the dielectric materials described above for the first frontside ILD material layer 38. The dielectric material providing the backside ILD material layer 54 can be compositionally the same as or compositionally different from the dielectric material providing the first frontside ILD material layer 38. The backside ILD material layer 54 can be formed utilizing one of the deposition processes described above in forming the second frontside ILD material layer 46.

[0083] 15A, 15B, and 15C, the exemplary structures shown in FIGS. 14A, 14B, and 14C, respectively, are illustrated after forming self-aligned backside source / drain contact structures 56. The term "self-aligned," when used in conjunction with the phrase "backside source / drain contact structure," indicates that the backside contact structure connects only to the source / drain regions 36 without shorting to nearby gate structures, even when the contact structure physically overlaps the gate structure. The self-aligned backside source / drain contact structure 56 is formed into the backside ILD material layer 54 and the recessed semiconductor buffer layer 34S. In the inverted structures shown in FIGS. 15A and 15C, the self-aligned backside source / drain contact structure 56 has its bottom surface in direct physical contact with one of the source / drain regions. 15A, the self-aligned backside source / drain contact structure 56 overlaps and contacts the present three-layer bottom dielectric insulating structure 26 / 41 / 28. In particular, the self-aligned backside source / drain contact structure 56 contacts the sidewalls of the first bottom dielectric insulating layer 26, the horizontal and sidewall surfaces of the second bottom dielectric insulating layer (i.e., high-k dielectric material) 41, and the sidewall surfaces of the third bottom dielectric insulating layer 28.

[0084] The self-aligned backside source / drain contact structures 56 are formed utilizing a metallization process that includes forming backside contact openings in the backside ILD material layer 54 and in the recessed semiconductor buffer layer 34S, and then filling the backside contact openings with at least one of the contact conductor materials described above for the frontside contact structures 48, 49. The self-aligned backside source / drain contact structures 56 may also include any of the liners described above for the frontside contact structures 48, 49. The three-layer bottom dielectric isolation structure 26 / 41 / 28 forms a protective cap structure above the gate structure such that the self-aligned backside source / drain contact structures 56 are still insulated from the gate structure even when any corner loss occurs during etching of the backside ILD material layer 54.

[0085] 16A, 16B, and 16C, the exemplary structure shown in FIGS. 15A, 15B, and 15C, respectively, is illustrated after additional backside ILD material has been formed on the backside LLD material layer 54 and the self-aligned backside source / drain contact structures 56 to form a backside power rail 58 and a backside power distribution network 60. Collectively, the additional backside ILD material and the backside ILD material layer 54 form a multilayer backside ILD material structure 55. The additional backside material may include one of the dielectric materials described above for the frontside ILD material layer 46. The dielectric material providing the additional backside ILD material may be compositionally the same as or compositionally different from the dielectric material providing the backside ILD material layer 54. The additional backside ILD material may be formed utilizing one of the deposition processes described above in forming the frontside ILD material layer 46.

[0086] The backside power rail 58 may be composed of any conductive power rail material, including, but not limited to, tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), platinum (Pt), rhodium (Rh), or palladium (Pd). Typically, a thin metal adhesion layer (TiN, TaN, etc.) is formed prior to conductive metal deposition; for clarity, the metal adhesion layer is not separately shown in the drawings herein. The backside power rail 58 may be formed by forming a backside power rail opening in the multilayer backside ILD material structure 55, the backside power rail opening physically exposing the surface of the self-aligned backside source / drain contact structure 56. The backside power rail opening is then filled with at least one of the above-mentioned conductive power rail materials, and a planarization process may follow the filling of the backside power rail opening. This filling may include CVD, PECVD, ALD, sputtering, or plating. The resulting backside power rail 58 formed in the backside power rail opening is electrically connected to the source / drain regions 36 by self-aligned backside source / drain contact structures 56 .

[0087] A backside power distribution network 60 is formed on top of the multi-layer backside ILD material structure 55 and on top of the backside power rails 58 that are embedded within the multi-layer backside ILD material structure 55. Thus, the backside power distribution network 60 is in contact with the backside power rails 58. The backside power distribution network 60 includes elements / components configured to distribute power to the transistors.

[0088] 16A-16C illustrate a semiconductor structure according to an embodiment of the present application. The illustrated structure includes a transistor (i.e., the center one shown in FIG. 16A ) including gate structures 40, 42 and a first source / drain region located on a first side of the gate structures 40, 42 (i.e., the source / drain region 36 on the right-hand side of the central gate structure) and a second source / drain region located on a second side of the gate structures (i.e., the source / drain region 36 on the left-hand side of the central gate structure). The structure further includes a three-layer bottom dielectric isolation structure 26, 41, 28 located below the transistor, a backside power rail 58 located below and spaced apart from the three-layer bottom dielectric isolation structure 26, 41, 28, and a backside source / drain contact structure 56 connecting the backside power rail 58 to the first source / drain region of the transistor. According to the present application, the backside source / drain contact structure 56 overlaps at least a portion of the three-layer bottom dielectric isolation structure 26, 41, 28 (see, for example, FIG. 16A ). The presence of the three-layer bottom dielectric isolation structure 26, 41, 28 provides a thick dielectric cap that prevents the backside source / drain contact structure 56 from shorting the gate structure. In the prior art, the bottom isolation structure is a thin structure, typically less than 10 nm, and therefore a short can occur between the gate structure and the backside source / drain contact structure.

[0089] As described above, the three-layer bottom dielectric insulating structure 26, 41, 28 includes the first bottom dielectric insulating layer 26, the second bottom dielectric insulating layer 41, and the third bottom dielectric insulating layer 28. As shown in Figure 16A, the backside source / drain contact structure 56 contacts the sidewalls of the first bottom dielectric insulating layer 26, the horizontal and sidewall surfaces of the second bottom dielectric insulating layer 41, and the sidewalls of the third bottom dielectric insulating layer 28. Note that if the structures shown in Figures 16A-16C were flipped 180°, the gate electrode 42 would be located above and laterally adjacent to the three-layer bottom dielectric insulating structure 26, 41, 28.

[0090] While the present application has been particularly shown and described with reference to preferred embodiments thereof, those skilled in the art will recognize that such and other changes in form and detail may be made without departing from the scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. a transistor having a gate structure and a first source / drain region located on a first side of the gate structure and a second source / drain region located on a second side of the gate structure; a three-layer bottom dielectric isolation structure underlying said transistor; a backside power rail located below and spaced apart from the triple-layer bottom dielectric isolation structure; and a backside source / drain contact structure connecting the backside power rail to the first source / drain region of the transistor, the backside source / drain contact structure overlapping at least a portion of the triple-layer bottom dielectric isolation structure; 1. A semiconductor structure comprising:

2. 10. The semiconductor structure of claim 1, wherein said three-layer bottom dielectric insulating structure comprises a first bottom dielectric insulating layer, a second bottom dielectric insulating layer, and a third bottom dielectric insulating layer, wherein said first bottom dielectric insulating layer and said third bottom dielectric insulating layer are both composed of a first dielectric material, and said second bottom dielectric insulating layer is composed of a second dielectric material that is compositionally different from said first dielectric material.

3. 3. The semiconductor structure of claim 2 wherein said first dielectric material comprises a low-k spacer dielectric material and said second dielectric material comprises a high-k gate dielectric material.

4. 3. The semiconductor structure of claim 2 further comprising gate spacers located on sidewalls of said gate structure, said gate spacers being composed of said first dielectric material.

5. 3. The semiconductor structure of claim 2 wherein said gate structure includes a gate dielectric material layer, said gate dielectric material layer being composed of said second dielectric material.

6. 3. The semiconductor structure of claim 2, wherein said backside source / drain contact structures contact sidewalls of said first bottom dielectric insulating layer, horizontal and sidewall surfaces of said second bottom dielectric insulating layer, and sidewalls of said third bottom dielectric insulating layer.

7. 10. The semiconductor structure of claim 1 further comprising a semiconductor buffer layer overlying a surface of said first source / drain region, said semiconductor buffer layer embedding a portion of said backside source / drain contact structure.

8. 8. The semiconductor structure of claim 7, further comprising a multi-layer backside interlayer dielectric material structure embedding another portion of said backside source / drain contact structure, said multi-layer backside interlayer dielectric material structure further embedding said backside power rail.

9. 10. The semiconductor structure of claim 1 further comprising a backside power distribution network in contact with said backside power rail.

10. 10. The semiconductor structure of claim 1 further comprising a front side source / drain contact structure in contact with said second source / drain region.

11. 11. The semiconductor structure of claim 10 wherein said front side source / drain contact structures are embedded within a first front side inter-layer dielectric material layer and a second front side inter-layer dielectric material layer.

12. 12. The semiconductor structure of claim 11 further comprising a front side gate contact structure located in said second front side inter-layer dielectric material layer and in contact with a gate electrode of said gate structure.

13. 12. The semiconductor structure of claim 11, further comprising a front-side back-end structure located on said second front-side inter-layer dielectric material layer, said front-side back-end structure electrically connected to said second source / drain regions by said front-side source / drain contact structures.

14. 14. The semiconductor structure of claim 13 further comprising a carrier wafer located on a surface of said front side back end structure.

15. 10. The semiconductor structure of claim 1 wherein said transistor is located on one side of a gate cut dielectric pillar.

16. 10. The semiconductor structure of claim 1 wherein said transistor is a nanosheet transistor having a nanosheet stack of suspended semiconductor channel material nanosheets.

17. 17. The semiconductor structure of claim 16 wherein said gate structure wraps around each of said suspended semiconductor channel material nano-sheets.

18. 10. The semiconductor structure of claim 1 wherein said gate structure comprises a gate electrode located above and laterally adjacent said triple-layer bottom dielectric isolation structure.

19. 1. A method of forming a semiconductor structure, comprising: forming a triple-layer bottom dielectric isolation structure beneath a gate structure of a transistor, the triple-layer bottom dielectric isolation structure including a first source / drain region located on one side of the gate structure and a second source / drain region located on a second side of the gate structure; forming a backside source / drain contact structure in contact with a surface of the first source / drain region, the forming of the backside source / drain contact structure comprising etching partially through the triple-layer bottom dielectric isolation structure. A method comprising:

20. 20. The method of claim 19, wherein the three-layer bottom dielectric insulating structure comprises a first bottom dielectric insulating layer, a second bottom dielectric insulating layer, and a third bottom dielectric insulating layer, wherein the first bottom dielectric insulating layer and the third bottom dielectric insulating layer are both composed of a first dielectric material, and the second bottom dielectric insulating layer is composed of a second dielectric material that is compositionally different from the first dielectric material, and wherein etching removes a portion of the first bottom dielectric insulating layer while stopping on the second bottom dielectric insulating layer.

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