Printed circuit board tear security features
By integrating tear initiation sites and delamination mechanisms into PCBs, the vulnerability to unauthorized access and tampering is mitigated, ensuring the PCB's functionality is disabled upon tampering, thus maintaining security and integrity.
Patent Information
- Application Number
- JP2025518263
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-10-10
- Filing Date
- 2023-10-09
- Publication Date
- 2025-10-15
AI Technical Summary
Printed circuit boards (PCBs) are vulnerable to unauthorized access and tampering, with malicious actors seeking to obtain data, disable functions, or sabotage systems by overcoming tamper-evident enclosures.
Incorporating tear initiation sites and delamination mechanisms in PCBs, such as parallel stress notches, trenches, and alternating dielectric materials, to ensure that when tamper-evident enclosures are removed, the internal circuitry is deliberately damaged, disabling the component and preventing access to data or functionality.
The solution effectively prevents unauthorized access and tampering by ensuring that when tamper-evident enclosures are removed, the PCB's functionality is disabled, maintaining security and integrity of the protected components.
Smart Images
Figure 2025534319000001_ABST
Abstract
Description
[Background technology]
[0001] The present invention relates to hardware circuit board component security, and more particularly to creating designated tear initiation points for delamination in response to tampering with a component enclosure.
[0002] A printed circuit board (PCB) contains circuitry and components that provide functionality and memory, and in some instances, includes proprietary technology. PCBs provide electrical circuitry connections between components, including semiconductor chips connected to a substrate, which in turn is connected to the PCB, or the chips are connected directly to the surface of the PCB. PCB components also include, but are not limited to, capacitors, resistors, fuses, and connectors. PCBs may be collectively referred to as circuitized boards or printed circuit boards. Summary of the Invention
[0003] According to one embodiment of the present invention, there is provided a structure for circuitry for securing a secure area against tampering and access to the area. The structure comprises circuitry having at least one of a top tamper-evident enclosure and a bottom tamper-evident enclosure that provides a security cover for protected components in the protected area of the circuitry. The structure comprises connections bonding the top tamper-evident enclosure and / or the bottom tamper-evident enclosure to the circuitry, and the structure comprises tear initiation sites added to sides of the circuitry that border the protected area having at least one of the top tamper-evident enclosure and the bottom tamper-evident enclosure, the tear initiation sites positioned and configured to allow propagation of delamination of at least one internal layer of the circuitry and severance of the security circuit when a removal force is applied to at least one of the top tamper-evident enclosure and / or the bottom tamper-evident enclosure.
[0004] According to another embodiment of the present invention, there is provided a method for creating tear initiation sites that will disable a protected area of a printed circuit board (PCB). The method includes receiving a PCB including one or more inner layers containing security circuitry positioned in areas associated with the protected component and a tamper-evident enclosure adhesively attached to a surface of the printed circuit board, such that severing one or more of the security trace circuits initiates the disablement of data and functionality of the protected component. The method determines the areas associated with the protected component that receive the tamper-evident enclosure, and the method creates tear initiation sites along the sides of the PCB aligned with the areas associated with the protected component.
[0005] According to another embodiment of the present invention, there is provided a method for creating a defeat tear in a printed circuit board due to a tampering attempt on a protected area of the printed circuit board. The method includes receiving an interior layer of a printed circuit board (PCB), wherein at least one layer of the PCB is reduced in size along a side dimension that includes the protected area of the PCB to which one or a combination of a top tamper enclosure and a bottom tamper enclosure is attached. The method includes bonding the interior layers, wherein the at least one reduced-size interior layer is positioned to form an inserted step along the side dimension of the protected area of the PCB, wherein bonding a first normal-sized interior layer with reduced adhesion to the at least one layer of the PCB that is reduced in size along the side dimension of the PCB. [Brief explanation of the drawings]
[0006] [Figure 1] 1 is an exemplary side view illustrating a printed circuit board cross-section including tear initiation and delamination, according to one embodiment of the present invention; FIG.
[0007] [Figure 2]1 is an exemplary side view illustrating a cross-section of a printed circuit board including improved bonding of inner layers in accordance with one embodiment of the present invention.
[0008] [Figure 3A] FIG. 1 is an exemplary side view illustrating a cross-sectional view of a printed circuit board including adhesive-filled trenches adjacent to internal circuit traces, in accordance with one embodiment of the present invention.
[0009] [Figure 3B] FIG. 1 is an exemplary side view illustrating a cross-sectional view of a printed circuit board including laser-drilled trenches adjacent to internal circuit traces, in accordance with one embodiment of the present invention.
[0010] [Figure 4A] 1A-1C are exemplary side views illustrating cross-sectional views of three optional versions of a stepped insert structure on the side of a printed circuit board, according to one embodiment of the present invention.
[0011] [Figure 4B] FIG. 1 is an exemplary top view of a printed circuit board.
[0012] [Figure 5] 5 is a flowchart diagram depicting operational steps for a tamper-resistant process 500, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION
[0013] Embodiments of the present invention recognize that components mounted on printed circuit boards are often targets for unauthorized access, tampering, and attacks to obtain data, design, or functional information associated with the targeted components. Often, targeted components include tamper-evident enclosures as security protection; however, malicious actors continually seek methods and techniques to overcome the enclosures and access the targeted components. In some cases, malicious actors attempt to determine encryption keys, steal secret designs, reverse engineer functions, access data, or gain network access behind firewalls. In other cases, the goal is to disable or sabotage the system.
[0014] The disclosed structures and techniques include the use of a security wrap constructed from a tearable material and bonded to a component or a "parent device" that includes the component and a tamper-evident covering for the component. The disclosed structures and techniques utilize edge slits on the security wrap to facilitate tearing and rely on tearing the security wrap to sever localized conductors, which may result in tamper detection, but leave the component and substrate intact against malicious access. Additional disclosures include grooves or trenches as surface features for enclosure attachment to circuit boards. Embodiments of the invention provide structures, techniques, and methods for detecting tampering of a component enclosure and initiating data removal or data scrambling, and creating destructive delamination of the internal circuitry of the printed circuit board to prevent use of the component for functional access to the component's data and / or functionality, or network access to other components or features of a network. Aspects of the invention include enabling directed tearing and / or delamination of one or more printed circuit board layers containing security trace circuitry in response to a removal force applied to the tamper-evident enclosure. Tearing or delamination of PCB inner layers results in a destructive action that disables the functionality of the targeted component and at least a portion of the PCB.
[0015] A printed circuit board (PCB), as referred to herein, includes a substrate having electronic circuitry on its surface and / or within its internal layers, the internal layers being bonded together by a lamination process. A PCB, as referred to herein, may include a printed circuit board, a printed circuit card, or a flex-printed circuit. A tamper-evident enclosure covers one or more components attached to the PCB by adhesive bonding to the component and / or the substrate to which the component is attached. The tamper-evident enclosure may be constructed of a metal material, a plastic material, or a ridged coating material. Dielectric materials are used to create the internal layers of the PCB and to bond the layers together. Plated vias, which connect one layer to another adjacent layer, and plated through-holes, which may connect two or more layers of a PCB, make electrical connections between layers.
[0016] Reference is now made to the drawings. The description of various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many improvements and modifications will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
[0017] FIG. 1 shows an exemplary side view illustrating a printed circuit board cross-section including a tear initiation site and delamination, according to one embodiment of the present invention. Note that the term "tear initiation site," as used herein, in some embodiments, includes a feature that extends parallel to the PCB's internal layers along the entire perimeter of the protected area, thus forming a completely secure perimeter and providing 360-degree protection against tampering of the PCB's encapsulated components. A tear initiation site provides a weakened portion of the bond between layers of the PCB that corresponds to at least a portion of the perimeter of the protected area. The terms "tear point," "stress notch," and "tear initiation site," therefore, are not limited to a single point location but include physical changes to the PCB that allow the tear and delamination to propagate along one or more edges of the protected area. Embodiments recognize that parallel stress notches, trenches, or tear initiation sites can be created by using rotating blades, routers, lasers, and interior layers of different size and / or bonding strength that form separated edges or inserted steps on the sides of the circuitry. In other embodiments, the tear initiation sites can include stress notches formed perpendicular to the sides of the PCB.
[0018] FIG. 1 includes a PCB 102, a top tamper-evident enclosure 104, sometimes referred to as a "top can," a bottom tamper-evident enclosure 106, sometimes referred to as a "bottom can," adhesive 108, parallel tear notches 110, a delamination tear 112, a security circuit 114 (sometimes referred to as a security trace), and a tamper-removal force 116 illustrated by an upwardly directed arrow. Embodiments recognize that not all instances of a tamper-evident enclosure include both a top and a bottom tamper-evident enclosure, and that FIG. 1 illustrates both for clarity and completeness, in some embodiments. The PCB 102 includes multiple internal circuitry layers and may include components connected to a surface of the PCB 102. Components connected to a surface of the PCB 102 (e.g., by solder connections) may be protected by bonding the top tamper-evident enclosure 104 and / or the bottom tamper-evident enclosure 106 to the respective surfaces of the PCB 102 via adhesive 108. 1 illustrates PCB 102 in cross section as including multiple internal circuitry layers. A tamper attempt to remove the tamper enclosure results in a delamination tear 112 of at least one internal layer of PCB 102 that is aligned with the positioning of instances of parallel tear notches 110.
[0019] In some embodiments, creating the parallel tear notch 110 (i.e., tear initiation site) includes, without limitation, mechanically, chemically, or optically removing material from a side of the PCB 102 aligned with a protected component attached to the surface of the PCB 102. For example, the parallel tear notch 110 is created by mechanically, chemically, or optically removing material along the side of the PCB 102. An adhesive 108 bonds the top tamper-evident housing 104 and the bottom tamper-evident housing 106 to the surface of the PCB 102. In some embodiments, the adhesive 108 also bonds the top tamper-evident housing 104 and the bottom tamper-evident housing 106 to a protected component (not shown). The illustration of FIG. 1 includes a delamination tear 112 occurring at a layer bond aligned with one instance of the parallel tear notch 110, and displacement and / or severance of the security circuit 114 also results from the delamination tear 112. A tamper-removal force 116, depicted by a large arrow, represents the effort of a tamper attempting to remove the top tamper enclosure 104, which generates enough force to cause a delamination tear 112. In some embodiments, severing the security circuit 114 triggers an action that may include deleting or scrambling data contained within the protected component, deactivating the PCB 102 from delaminating layers, or other protective action.
[0020] Figure 2 is an exemplary side view illustrating a cross section of a printed circuit board including improved bonding of inner layers, according to one embodiment of the present invention. Figure 2 depicts three different structural options that, alone or in combination, may be incorporated into a PCB to provide tear initiation points within the PCB for tamper security. Figure 2 includes a PCB 202, a top tamper enclosure 204, a bottom tamper enclosure 206, adhesive 208, alternating dielectric material 211, inner circuitry 214, security circuits 215 and 216, locally tailored dielectric material 218, and edge plating 220.
[0021] The top tamper-evident housing 204 and the bottom tamper-evident housing 206 form a protective cover for one or more components of the PCB 202, similar to the description provided with respect to FIG. 1 . The adhesive 208 provides a bond between the surfaces of the top and bottom tamper-evident housings 204, 206 and the respective PCBs 202. In an embodiment of the present invention, the alternating dielectric material 211 forms a weaker interlayer bond that provides a selective separation point for failure of the PCB 202 as a result of a tamper-evident removal force of at least one of the top tamper-evident housing 204 and the bottom tamper-evident housing 206. The separation of layers due to delamination of the alternating dielectric material 211 resulting from the removal tamper-evident force results in the disconnection of the security circuit 215, which is depicted in the cross-sectional view. The security circuitry 216 includes plated vias and through-holes to other layers of the PCB 202 that are disrupted by delamination of the alternating dielectric material 211 due to a removal tamper force applied to the top tamper enclosure 204 and / or bottom tamper enclosure 206. The weaker bonds of the alternating dielectric material 211 establish designated separation points within the protected area of the PCB that, when disrupted or destroyed, include security circuitry that initiates reactive actions such as clearing memory, randomly setting circuit bits, and / or disabling the functionality of the protected component.
[0022] The partially conditioned dielectric material 218 includes surface characteristics that reduce the bonding strength of portions of the dielectric material between layers of the PCB 202. The partially conditioned dielectric material 218 may comprise the same material as other dielectric materials within the layers of the PCB 202; however, the partially conditioned dielectric material 218 has undergone a surface treatment operation on a designated outer portion of the dielectric material corresponding to the perimeter region of the protected component of the PCB 202 that intentionally reduces bonding to other layers during the lamination process. The "partially conditioned" nature of the partially conditioned dielectric material 218 results in specific areas of separation intended to correspond to security circuitry that is broken or severed in response to a removal force applied to a tamper-evident enclosure of the PCB 202, such as the top tamper-evident enclosure 204 and / or the bottom tamper-evident enclosure 206. The partially conditioned dielectric material 218 promotes tearing of the PCB 202 within the predesignated areas while avoiding tearing within other areas within the PCB 202.
[0023] In an alternative embodiment, a selective microetching operation performed on the perimeter outside the protected area of the PCB 202 reduces the thickness of the edge plating 220, creating weaker points for initiation of tearing and separation of the PCB 202 aligned with the security circuitry. The edge plating 220 provides shielding protection for electromagnetic compatibility (EMC) of the PCB signals and avoids unacceptable electromagnetic interference (EMI) effects or excessive radiation of signals generated by the circuitry within the tamper-resistant enclosure. Embodiments recognize the edge plating 220 as having a thickness that can prevent intended layer separation for tamper protection. Embodiments include actions that weaken the edge plating 220 in areas designated for tearing or separation due to tamper forces. In one embodiment, a combination of alternating dielectric material 211 and parallel tear notches 110 can be applied to weaken the effect of the edge plating 220 and enable tearing and delamination between designated layers around the perimeter of the PCB 202. In another embodiment, application of an etching operation to the perimeter region corresponding to the designated delamination layer results in a reduced plating thickness. In yet another embodiment, the etching operation completely removes the edge plating 220 from the perimeter region corresponding to the designated delamination or tear layer. Inclusion of stitching vias in the region absent edge plating 220 provides an EMC seal in place of edge plating 220.
[0024] FIG. 3A provides an exemplary side view illustrating a printed circuit board cross-section including an adhesive-filled trench adjacent to an internal circuit trace, according to one embodiment of the present invention. FIG. 3A includes a PCB 302, a top tamper-evident enclosure 304, adhesive 308, an adhesive-filled trench 313, and a security circuit 314. In some embodiments, the surface area of the PCB 302 aligned with the area of attachment of the top tamper-evident enclosure 304 receives a trench structure ("trench") extending from the surface to an interior layer of the PCB. The top tamper-evident enclosure 304 provides physical covering for the protected components (not shown) of the PCB 302. An adhesive 308 bonds the top tamper-evident enclosure 304 to the surface of the PCB 302. An embodiment includes removing dielectric material between the internal circuit traces to form a trench along at least a portion of the area to be protected, where the adhesive 308 bonds the top tamper-evident enclosure 304 and the PCB 302. Adhesive-filled trench 313 results from adhesive 308 filling a trench structure that may extend to one or more interior layers of PCB 302. The location and dimensions of adhesive-filled trench 313 allow proximity to security circuit 314 on an interior layer of PCB 302. Security circuit 314 is destroyed or severed as a result of a removal force applied to adhesive-filled trench 313 by top tamper enclosure 304 bonded to PCB 302 and adhesive 308. The removal force results in a tear between the layers of PCB 302 associated with adhesive-filled trench 313 and a severing of security circuit 314, initiating a predetermined action that protects the components covered by top tamper enclosure 304 of PCB 302.
[0025] FIG. 3B is an exemplary side view illustrating a cross-section of a printed circuit board including a laser-drilled trench positioned adjacent to an internal circuit trace, according to one embodiment of the present invention. FIG. 3B includes a PCB 302, a laser 305, a security circuit 314, and a surface trench 315. In one embodiment of the present invention, the laser 305, configured as a laser drilling device for removing organic material from dielectric materials used in fabricating multilayer printed circuit boards, creates the trench 315. The laser 305 includes parameters such as power level, beam diameter, and duration to create a surface trench of a specified width, depth, and length in a protected area of the PCB 302 corresponding to an adhesive bond location in the top tamper-evident enclosure 304 (FIG. 3A). FIG. 3B depicts the surface trench 315 prior to filling with adhesive 308 (FIG. 3A). 3B depicts removing enough dielectric material so that trench 315 is in close proximity to security circuit 314, allowing, in some embodiments, bonding of adhesive 308 to the side of security circuit 314 rather than bonding to the surface layer. The additional bonding surface area results in an additional amount of tearing and delamination of PCB 302 and severing of security circuit 314 due to the removal level of force applied to the tamper enclosure (i.e., top tamper enclosure 304, FIG. 3A).
[0026] FIG. 4A is an exemplary side view illustrating a cross-section including a stepped structure formed on the side of a printed circuit board, according to one embodiment of the present invention. The embodiment uses interior layers cut to different sizes to form a stepped structure on the side of the PCB. The resulting stepped structure creates tear initiation sites caused by areas of stress concentration, where delamination tears preferentially occur due to applied forces attempting to remove a tamper-evident enclosure covering a protected component. In one embodiment of the present invention, bonding different-sized interior layers of a PCB to regular-sized layers of the PCB forms a stepped structure along the side of the PCB. For example, a first interior layer having a shorter dimension along the side of the PCB than the surface layer and layers below it can be bonded (e.g., laminated) with the surface layer and the lower layers to form a stepped structure that provides an area of stress concentration for layer separation for the PCB.
[0027] FIG. 4A depicts three optional versions of the stepped insert structure, and each option may be used in a single instance, multiple instances, or in any combination. FIG. 4A includes an alternating step structure 404, a strategically placed step structure 406, and a multi-layer step structure 408. FIG. 4A also includes a regular-sized inner layer 409 and a smaller-sized inner layer 411. In one embodiment, the smaller-sized inner layer 411 has a shorter dimension around the periphery of the area of the PCB to be protected. The alternating step structure 404 creates areas of stress concentration due to the step-like structure created by the alternating sizes of the layers. In one embodiment, the strategically placed step structure 406 includes the formation of step structures in predetermined strategically placed layers, such as specific layers containing security circuitry that detects tears and delamination of the PCB due to removal forces applied to the tamper-evident enclosure. The multi-layer step structure 408 illustrates the formation of a step structure that includes multiple inner layers having different sizes (i.e., shorter lengths relative to the side region of the PCB) bonded between multiple layers having larger sizes in the dimensions of the side region of the PCB. Note that Figure 4A depicts three different formations of step structures on the side of the PCB as convenient examples, and embodiments may include only one of the step structures or any combination thereof when applying a tear initiation site structure to the perimeter of the protected region of the PCB.
[0028] FIG. 4B is an exemplary top view diagram of a printed circuit board with a top tamper-evident enclosure covering the area to be protected, according to one embodiment of the present invention. FIG. 4B includes a PCB 420, a top tamper-evident enclosure 422, and an edge plating enhancement area 424. The top tamper-evident enclosure 422 covers the protected component (not shown) of the PCB 420. A dark edge delineating the edge plating enhancement area 424 borders the outer edge of the top tamper-evident enclosure 422 on three sides, and the edge plating enhancement area 424 includes step structure stress points along the three side edges of the PCB 420 that are parallel to the interior layers. Embodiments include performing an operation on the edge plating enhancement area 424 to reduce or eliminate edge plating from the outer region of the step structure. In some embodiments, removal of all edge plating is performed by an etching operation or other processing method. In other embodiments, reducing the thickness of the edge plating weakens the connections between the layers contained within the stepped structure, making it more susceptible to tearing and delamination due to removal forces applied to the top tamper-evident enclosure 422. In some embodiments, a tacky adhesive may be used in bonding the stepped structure layers to prevent the adhesive from providing greater lamination strength to the inner layers and negating the benefits of the stepped structure.
[0029] FIG. 5 is a flowchart depicting operational steps for a tamper-proof process 500 according to one embodiment of the present invention. The tamper-proof process 500 begins with receiving a printed circuit board (PCB) (also referred to as a printed circuit board) (step 502) that includes at least one inner layer having security circuitry associated with a protected area of the PCB. The embodiment includes receiving a PCB that has been processed through bonding operations that bond the inner and surface layers that form the PCB. The received PCB includes at least one area designated as a protected area where components will be surface-mounted and covered with a tamper-proof enclosure that protects the components from access and attack. The security circuitry, positioned within the at least one inner layer of the PCB, includes a location that corresponds to the outer edge of the protected area and, if disconnected, initiates an action to protect the data and functionality of the protected component, such as clearing or scrambling data stored within the protected component and / or disabling the component's functionality and response as a result of access or attack.
[0030] Embodiments determine the location of the protected area of the PCB (step 504). Embodiments inspect the received PCB to precisely determine the protected area of the PCB; in some embodiments, there may be more than one protected area. Embodiments identify an outer edge associated with the location of the protected area and obtain information about the specific layer designated for enabled tearing and delamination. The specific layer information includes the distance from the surface of the PCB to the internal layer designated for tearing and delamination and bonded to the security circuit to precisely locate the tear initiation point along the PCB edge associated with the protected area. For example, embodiments determine the dimensions of the protected area and the outer edge adjacent to the protected area, and further determine the location of the internal layer designated for tearing and bonded to the security circuit at the determined distance from the top surface of the PCB.
[0031] Embodiments create tear initiation sites along one or more sides of the PCB aligned with the interior layers associated with the protected area and security circuit (step 506). Embodiments physically create tear initiation sites along the sides of the PCB parallel to the interior layers of the PCB. In some embodiments, the creation and positioning of the tear initiation sites aligns with designated interior layers bonded to the security circuit. The tear initiation sites may include physically removing material along the sides of the PCB adjacent to the protected area, for example, by mechanical, chemical, optical, or other material removal processes. Embodiments include tear initiation sites formed by using a different dielectric material in the designated interior layer that includes a lower bonding strength, enabling tearing and delamination at the designated layer. Embodiments may also include surface conditioning the perimeter of the protected area of the designated interior layer, such that the surface conditioning process reduces the bonding strength of the interior layer to other layers of the PCB, enabling tearing and delamination at the designated layer. Embodiments may include using different sized interior layers to form a step structure along the outer edge of the protected area of the PCB. The step-like structure creates an area of stress concentration that favors tearing or delamination at the step, and may be further enabled by etching of edge plating along the outer edge of the PCB corresponding to the step structure. Embodiments may include performing an operation to weaken a portion of the edge plating or selectively remove all edge plating aligned with the step structure, and may include stitching vias in the interior layers to provide electromagnetic compatibility (EMC) functionality for the PCB in the area of the step structure.
[0032] In response to detecting disconnection of at least one security circuit due to an internal layer tear from tampering, embodiments perform actions to protect access to data within the component and disable functionality of the PCB (step 508). Embodiments recognize that following the step of creating a tear initiation site within the PCB, additional PCB processing results in surface-populated components and a tamper-evident enclosure that covers the protected components with an adhesive. Components of the PCB may be protected to prevent access to cryptographic keys or other data that may be contained or stored within the components. Embodiments recognize that components may be protected against attacks that monitor the component's ability to obtain information that is supposed to be secure. Embodiments also recognize that access to functioning components may enable network access that would otherwise be unavailable.
[0033] Embodiments detect the disconnection of a security circuit as a result of a removal force applied to a tamper-evident enclosure covering a protected component that is adhesively bonded to a surface of a PCB, where the removal force creates delamination at a tear initiation point associated with the protected area, resulting in the initiation of a predetermined action that protects access to data and disables the functionality of the PCB to prevent access to other components, other PCBs, or network access that overcomes the protective firewall.
[0034] It should be noted that in some embodiments, the disruption or disconnection of the security circuitry may also trigger an alert or notification to appropriate responders. Embodiments may include combinations of tear initiation points, different dielectric materials, edge plating reduction or removal, different sized inner layers, and applying a surface conditioning process to the perimeter of the protected area on the inner layer.
Claims
1. 1. A structure of a circuitry (hardware) board for securing an area against tampering, said structure comprising: the circuitry having at least one of a top tamper-evident enclosure and a bottom tamper-evident enclosure that provide a security cover for a protected area of the circuitry; a connection bonding the at least one of the top tamper-evident enclosure and the bottom tamper-evident enclosure to the circuitry; and a tear initiation point provided as a feature extending along at least a portion of a perimeter of a protected area of the circuitry comprising said at least one of said top tamper-evident enclosure and said bottom tamper-evident enclosure, said tear initiation point being positioned and configured to allow propagation of delamination of at least one internal layer of said circuitry and severance of a security circuit when a removal force is applied to said at least one of said top tamper-evident enclosure and said bottom tamper-evident enclosure; A structure comprising:
2. 10. The structure of claim 1, wherein the tear initiation locations comprise creating notches on sides of the substrate corresponding to the top and bottom tamper-evident enclosures, the notches at the tear initiation locations being parallel to the at least one interior layer of the circuitry.
3. 10. The structure of claim 1, wherein the tear initiation locations comprise creating notches on sides of the substrate corresponding to the top and bottom tamper-evident enclosures, the notches at the tear initiation locations being perpendicular to the at least one interior layer of the circuitry.
4. The structure of claim 1 , wherein the security circuit between layers of the circuitry corresponds to the tear initiation location and includes one or a combination of vias and through-holes.
5. 10. The structure of claim 1, wherein a dielectric material that provides weaker interlayer bonding is used for one or more interior layers to allow delamination from the removal force applied to the at least one of the top tamper enclosure and the bottom tamper enclosure.
6. 10. The structure of claim 1, wherein the tear initiation site comprises creating a trench into which adhesive is applied to enhance bond strength connecting the top tamper enclosure or the bottom tamper enclosure to a layer of the electronic circuitry, the trench extending from a surface of the electronic circuitry adjacent an inner layer security circuit designated for delamination upon physical tampering.
7. 10. The structure of claim 1, wherein the tear initiation site comprises a change in dielectric material that has reduced bonding strength to other layers of the circuitry.
8. 10. The structure of claim 1, wherein the tear initiation location comprises applying a surface treatment to the periphery of the protected area of the circuitry to reduce bond strength of the at least one inner layer of the circuitry.
9. 10. The structure of claim 1, wherein edge plating is removed and stitching vias are used along the edge regions to provide electromagnetic compatibility (EMC) shielding.
10. 10. The structure of claim 1, wherein trenches are created by removal of organic material to allow adhesive bonding to sides of security traces on multiple inner layers of the circuitry.
11. 10. The structure of claim 1, wherein the tear initiation site is created by at least one physical action selected from the group consisting of a stress notch created by a blade, the stress notch created by a router, the stress notch created by a laser, a trench created by the laser, the trench created by the router, and different sized interior layers forming at least alternating recessed steps on sides of the circuitry.
12. 10. The structure of claim 1, wherein the severing of security tracing circuitry initiates at least one of an action from the group consisting of deleting data from components within at least one of the top tamper-evident enclosure and the bottom tamper-evident enclosure, and disabling the circuitry.
13. 1. A method for producing a defeat tear in a printed circuit board (PCB), the method comprising: receiving a tamper-evident enclosure attached to a surface of a printed circuit board using an adhesive, said PCB including one or more interior layers including security circuits positioned in areas associated with components to be protected, wherein severing one or more of said security trace circuits initiates disabling of data and functionality of said protected components; determining the area associated with the protected component receiving the tamper-evident enclosure; and creating tear initiation sites along the sides of the PCB aligned with the areas associated with the protected components. A method comprising:
14. 14. The method of claim 13, wherein the tear initiation point is parallel to the one or more interior layers including the security circuit positioned in the area associated with the protected component.
15. 14. The method of claim 13, wherein the tear initiation location comprises a trench formed from removing dielectric material from the surface of the PCB to an interior layer of the PCB, wherein the trench is adjacent to a security circuit and contains adhesive from bonding a tamper-evident housing of the protected component to the PCB.
16. 14. The method of claim 13, wherein the tear initiation location comprises reducing bond strength between one or more internal layers of the PCB by one or a combination selected from the group consisting of alternating dielectric materials and surface conditioning operations around the area associated with the protected component.
17. 14. The method of claim 13, wherein the security circuitry includes vias and through-holes connecting a layer with reduced bond strength to another internal layer of the PCB.
18. 1. A method for producing a defeat tear in a printed circuit board due to an attempt to tamper with a protected area of the printed circuit board, the method comprising: receiving an interior layer of a printed circuit board (PCB), wherein at least one layer of the PCB is reduced in size along a side dimension that includes a protected area of the PCB to which the top or bottom tamper enclosure is attached; and bonding the internal layers, wherein the at least one internal layer having a reduced size is positioned to form an inserted step along the side dimension of the protected area of the PCB, and wherein the bonding of a first internal layer of normal size is bonded with reduced adhesive strength to the at least one layer of the PCB having a reduced size along the side dimension of the PCB. A method comprising:
19. 20. The method of claim 18, wherein the bond strength of the at least one inner layer that is reduced in size is reduced by using alternating dielectric materials for the at least one inner layer.
20. 20. The method of claim 18, wherein the bonding strength of the at least one internal layer that has been reduced in size is reduced using a surface conditioning operation around the protected area of the at least one internal layer.