Metal source / drain Sacrificial source / drain for horizontal gate-all-around architecture

Abstract

A semiconductor device and method for fabricating the same are described. The method includes forming source and drain regions on a substrate adjacent to a superlattice structure. The source and drain regions include a metal suicide material. In some embodiments, a sacrificial material is first deposited and then removed to form the metal suicide material in the source and drain regions.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure relate generally to semiconductor devices, and more particularly to gate-all-around (GAA) devices having metal source-drain regions. [Background technology]

[0002]

[0002] Transistors are key components of most integrated circuits. A transistor's drive current, and therefore its speed, is proportional to its gate width, so faster transistors generally require larger gate widths. Therefore, there is a trade-off between transistor size and speed, and to address the conflicting goals of a transistor with maximum drive current and minimum size, the "fin" field-effect transistor (FinFET) was developed. FinFETs feature a fin-shaped channel region that significantly increases the size of a transistor without significantly increasing the transistor's footprint, and are currently being applied in many integrated circuits. However, FinFETs also have drawbacks.

[0003]

[0003] As transistor device feature sizes continue to shrink to achieve increased circuit density and higher performance, improved transistor device structures are needed to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and horizontal gate-all-around (hGAA) structures. hGAA device structures contain several lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. hGAA structures offer good electrostatic control and can be widely adopted in complementary metal-oxide-semiconductor (CMOS) wafer fabrication.

[0004] A known challenge with gate-all-around architectures is that the current flowing through the bottom sheet is lower than that through the top sheet due to higher series resistance. Indeed, electrical carriers must traverse the height of the source / drain epitaxial material before being injected into the bottom sheet. As a solution, engineers have focused on increasing the doping level of the epitaxial source / drain to minimize source / drain resistance. However, varying the doping level becomes problematic as devices become smaller. Therefore, improved devices and methods for forming gate-all-around devices are needed. Summary of the Invention

[0005]

[0005] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method of forming the semiconductor device includes forming source and drain trenches adjacent to a superlattice structure on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs; depositing a sacrificial material in the source and drain trenches; forming a replacement metal gate structure on a top surface of the superlattice structure; opening contact trenches adjacent to the replacement metal gate structure, the contact trenches extending to a top surface of the sacrificial material; selectively removing the sacrificial material through the contact trenches; forming source and drain regions adjacent to the replacement metal gate structure; and filling the contact trenches, source trenches, and drain trenches with a metal fill layer.

[0006]

[0006] Further embodiments of the present disclosure are directed to methods of forming a semiconductor device. In one or more embodiments, the method of forming the semiconductor device includes forming source and drain regions adjacent to a superlattice structure on a substrate, the superlattice structure including a plurality of horizontal channel layers and corresponding plurality of layers of semiconductor material arranged alternately in a plurality of stacked pairs, the source and drain regions including a metal suicide material.

[0007]

[0007] Further embodiments of the present disclosure are directed to a non-transitory computer-readable medium. In one or more embodiments, the non-transitory computer-readable medium includes instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform an operation of forming source and drain regions adjacent to a superlattice structure on a substrate, the superlattice structure including a plurality of horizontal channel layers and corresponding plurality of layers of semiconductor material arranged alternately in a plurality of stacked pairs, the source and drain regions including a metal suicide material.

[0008]

[0008] So that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above will be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the present disclosure may admit of other equally effective embodiments, and therefore the accompanying drawings merely illustrate typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure. [Brief explanation of the drawings]

[0009] [Figure 1]

[0009] A process flow diagram of a method for forming a semiconductor device according to some embodiments of the present disclosure is shown. [Figure 2A]

[0010] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2B]

[0011] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2C]

[0012] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2D]

[0013] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2E]

[0014] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2F]

[0015] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2G]

[0016] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2H]

[0017] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 3]

[0018] 1 illustrates a process flow diagram of a method for forming a semiconductor device according to some embodiments of the present disclosure. [Figure 4A]

[0019] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4B]

[0020] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4C]

[0021] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4D]

[0022] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4E]

[0023] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4F]

[0024] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4G]

[0025] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4H]

[0026] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 5]

[0027] 1 illustrates a cluster tool according to one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0028] To facilitate understanding, the same reference numerals have been used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further description.

[0011]

[0029] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0012]

[0030] The term "substrate," as used herein and in the appended claims, refers to a surface or portion of a surface upon which a process acts. Those skilled in the art will also understand that a reference to a substrate may refer to only a portion of a substrate, unless the context clearly dictates otherwise. Additionally, when reference is made to deposition on a substrate, it can refer to both a bare substrate and a substrate upon which one or more films or features have been deposited or formed.

[0013]

[0031] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may also be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise create or graft target chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may also be performed on underlayers formed on the substrate, which are disclosed in more detail below. The term "substrate surface" is intended to include such underlying layers, as the context indicates. So, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer is the substrate surface. What a given substrate surface includes will depend on what film is being deposited and the particular chemistry used.

[0014]

[0032] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably and refer to any gas species capable of reacting with the substrate surface.

[0015]

[0033] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on the semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Typically, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions may include doped substrate regions and may exhibit a doping profile suitable for a particular application. The gate is positioned over a channel region and includes a gate dielectric interposed between the gate electrode in the substrate and the channel region.

[0016]

[0034] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement mode field effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field within the device, which is generated by a voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), through which carriers enter the channel, the drain (D), through which carriers exit the channel, and the gate (G), which is the terminal that regulates the conductivity of the channel. Conventionally, the current entering the channel at the source (S) is known as I S , the current entering the channel at the drain (D) is I D The drain-source voltage was V DS By applying a voltage to the gate (G), the drain (i.e., I D ) can control the current entering the channel.

[0017]

[0035] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate; the voltage across the gate determines the device's conductivity. This ability to change conductivity in response to an applied voltage is used to amplify or switch electronic signals. MOSFETs are based on modulation of charge concentrations by a metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET contains two additional terminals (source and drain), each connected to a separate highly doped region separated by a body region. These regions can be p-type or n-type, but both are the same type, opposite the type of the body region. The source and drain are highly doped (unlike the body), and are denoted by a "+" symbol after the doping type.

[0018]

[0036] If the MOSFET is n-channel, or nMOSFET, the source and drain are n+ regions and the body is p region. If the MOSFET is p-channel, or pMOSFET, the source and drain are p+ regions and the body is n region. The source is so named because it is the source of charge carriers (electrons in the case of n-channel and holes in the case of p-channel) that flow through the channel. Similarly, the drain is where the charge carriers exit the channel.

[0019]

[0037] As used herein, the term "fin field effect transistor (FinFET)" refers to a MOSFET transistor constructed on a substrate where the gate is placed on two or three sides of the channel, forming a double-gate or triple-gate structure. FinFET devices are given the collective name FinFET because the channel region forms a "fin" on the substrate. FinFET devices have fast switching times and high current densities.

[0020]

[0038] As used herein, the term "gate-all-around (GAA)" refers to an electronic device, e.g., a transistor, in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor may comprise a nanowire or nanoslab, or a nanosheet, a rod-shaped channel, or other suitable channel configuration known to those skilled in the art. In one or more embodiments, the channel region of a GAA device comprises multiple vertically spaced horizontal nanowires or bars, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0021]

[0039] As used herein, the term "nanowire" refers to a wire measuring 10 nanometers (10 -9 Nanowires refer to nanostructures having diameters on the order of meters. Nanowires may also be defined as having a length-to-width ratio greater than 1000. Alternatively, nanowires may be defined as structures whose thickness or diameter is constrained to tens of nanometers or less, but whose length is not. Nanowires are used in transistor and some laser applications and, in one or more embodiments, are made of semiconducting, metallic, insulating, superconducting, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and nonvolatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to two-dimensional nanostructures having a thickness ranging from about 0.1 nm to about 1000 nm.

[0022]

[0040] Embodiments of the present disclosure are illustrated by figures that show devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The illustrated processes are merely exemplary of possible applications of the disclosed processes, and one of ordinary skill in the art will recognize that the disclosed processes are not limited to the applications illustrated.

[0023]

[0041] One or more embodiments of the present disclosure are described with reference to the drawings. In one or more embodiment methods, a horizontal gate-all-around transistor with a metal source / drain is fabricated using a standard process flow. In one or more embodiments, source and drain regions are formed adjacent to a superlattice structure on a substrate, the source and drain regions comprising a metal silicide material. After source / drain cavities are formed, a sacrificial source / drain material is deposited in the source / drain cavities, a replacement metal gate (RMG) is formed, contact trenches are opened, the sacrificial source / drain material is selectively removed, a contact epitaxial layer is selectively grown, and a conformal silicide layer is formed on the epitaxial layer.

[0024]

[0042] As used herein, the term "conformal" means that a layer conforms to the contours of a feature or layer. The conformality of a layer is typically quantified by the ratio of the average thickness of a layer deposited on the sidewall of a feature to the average thickness of the same deposited layer on the field (or top) surface of the substrate.

[0025]

[0043] 1 shows a process flow diagram of a method 10 for forming a semiconductor device according to some embodiments of the present disclosure. 2A-2H illustrate stages in the fabrication of a semiconductor structure according to some embodiments of the present disclosure. In one or more embodiments, a sacrificial material is deposited, followed by epitaxial growth of source / drain regions.

[0026]

[0044] Method 10 is described below with reference to Figures 1-2F. Figures 2A-2H are cross-sectional views of an electronic device (e.g., a hGAA) according to one or more embodiments. Method 10 may be part of a multi-step manufacturing process for semiconductor devices. Thus, method 10 may be performed in any suitable process chamber coupled to a cluster tool. The cluster tool may include processing chambers for manufacturing semiconductor devices, such as etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in manufacturing semiconductor devices.

[0027]

[0045] 2A-2H illustrate the fabrication steps of acts 12 through 28 of FIG. 1. Referring to FIG. 1, a method 10 for forming a device 100 begins in act 12 by providing a substrate 102. In some embodiments, the substrate 102 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate composed entirely of semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor substrate 102 may comprise one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 102 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 102 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials from which the substrate may be formed are described herein, any material that can serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) may be constructed is within the spirit and scope of the present disclosure.

[0028]

[0046] In some embodiments, the semiconductor material may be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor made by doping an intrinsic semiconductor with an electron-donating element during fabrication. The term n-type comes from the negative charge of the electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a higher hole concentration than the electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0029]

[0047] In some embodiments, a replacement gate structure (e.g., a dummy gate structure 112) is formed on the superlattice structure 108. The dummy gate structure 112 defines a channel region of the transistor device. The dummy gate structure 112 may be formed using any suitable conventional deposition and patterning process known in the art. In one or more embodiments, the dummy gate structure 112 comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and titanium aluminum (TiAl).

[0030]

[0048] In some embodiments, sidewall spacers 110 are formed along the outer sidewalls of dummy gate structures 112. Sidewall spacers 110 may comprise any suitable insulating material known in the art, such as, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, sidewall spacers are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0031]

[0049] At least one superlattice structure 108 is formed on the top surface of the substrate 102. In one or more embodiments, the superlattice structure 108 includes a plurality of semiconductor material layers 106 and a corresponding plurality of nanosheet channel layers 104 arranged alternately in a plurality of stacked pairs. In some embodiments, the plurality of stacked layer groups include silicon (Si) and silicon germanium (SiGe) groups. In some embodiments, the plurality of semiconductor material layers 106 include silicon germanium (SiGe) and the plurality of nanosheet channel layers 104 include silicon (Si). In other embodiments, the plurality of nanosheet channel layers 104 include silicon germanium (SiGe) and the plurality of semiconductor material layers include silicon (Si).

[0032]

[0050] In some embodiments, the plurality of semiconductor material layers 106 and the corresponding plurality of nanosheet channel layers 104 may include any number of lattice-matched material pairs suitable for forming the superlattice structure 108. In some embodiments, the plurality of semiconductor material layers 106 and the corresponding plurality of nanosheet channel layers 104 include from about 2 pairs to about 50 pairs of lattice-matched materials.

[0033]

[0051] In one or more embodiments, the thickness t1 of the plurality of semiconductor material layers 106 and the plurality of nanosheet channel layers 104 is in the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm.

[0034]

[0052] The channel region 114 separates the superlattice structure 108 from an adjacent superlattice structure 108. In operation 14, the channel region 114 is recessed to form source trenches 115a and drain trenches 115b. In one or more embodiments, the source trenches 115a and drain trenches 115b are formed adjacent to (i.e., on either side of) the superlattice structure 108.

[0035]

[0053] 2B and 1, in operation 16, a sacrificial material 116 is deposited in the channel region 114 and on the bottom surfaces of the source / drain trenches 115a / 115b. The sacrificial material 116 may include any suitable material known to those skilled in the art. In some embodiments, the sacrificial material 116 is amorphous. In one or more embodiments, the sacrificial material 116 includes one or more of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), aluminum oxide (AlOx), silicon oxide (SiOx), silicon oxycarbide (SiOC), or the like. In some embodiments, the sacrificial material 116 is a stress material that is subsequently replaced. The sacrificial stress material may be characterized by a greater amount of stress than the stress of surrounding layers.

[0036]

[0054] The sacrificial material 116 may be deposited using any suitable conventional deposition process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0037]

[0055] In one or more embodiments, the thickness of the sacrificial material 116 is in the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm.

[0038]

[0056] Referring to FIG. 2B, in some embodiments, the sacrificial material 116 may be deposited in the channel region 114 and on the bottom surfaces of the source / drain trenches 115a, 115b and on the sidewalls of the superlattice structure 108.

[0039]

[0057] Referring to FIG. 1 , in operation 18, the formation of a semiconductor device, e.g., a GAA, continues by conventional procedures involving nanosheet exfoliation and formation of a replacement metal gate. Specifically, as shown in FIG. 2C , the semiconductor material layers 106 are selectively etched between the horizontal channel layers 104 in the superlattice structure 108. For example, if the superlattice structure 108 is composed of silicon (Si) and silicon germanium (SiGe) layers, the silicon germanium (SiGe) is selectively etched to form channel nanowires. The semiconductor material layers 106, e.g., silicon germanium (SiGe), can be removed using known etchants that are selective to the horizontal channel layers 104, which etch the semiconductor material layers 106 at a significantly faster rate than the horizontal channel layers 104. In some embodiments, a selective dry or wet etching etch process may be used. In some embodiments, when the horizontal channel layers 104 are silicon (Si) and the semiconductor material layers 106 are silicon germanium (SiGe), the silicon germanium layer can be selectively removed using a wet etchant such as, but not limited to, a carboxylic acid / nitric acid / HF solution and a citric acid / nitric acid / HF solution. Removal of the semiconductor material layers 106 leaves voids between the horizontal channel layers 104. The voids between the horizontal channel layers 104 have a thickness of about 3 nm to about 20 nm. The remaining horizontal channel layers 104 form a vertical array of channel nanowires that connect to the source / drain regions. The channel nanowires run parallel to the top surface of the substrate 102 and are aligned with each other to form a single row of channel nanowires.

[0040]

[0058] In one or more embodiments, a high-k dielectric is formed. The high-k dielectric may be any suitable high-k dielectric material deposited by any suitable deposition technique known to those skilled in the art. In some embodiments, the high-k dielectric comprises hafnium oxide. In some embodiments, a conductive material, such as titanium nitride (TiN), tungsten (W), cobalt (Co), or aluminum (Al), is deposited on the high-k dielectric to form a replacement metal gate 118. The conductive material may be formed using any suitable deposition process, such as, but not limited to, atomic layer deposition (ALD), for reliable formation.

[0041]

[0059] Referring to FIG. 2D, a contact material 120 is deposited over the sacrificial material 116 .

[0042]

[0060] 1 and 2E, in operation 20, contact trenches 122 are opened. In one or more embodiments, the contact trenches extend to the sacrificial material 116. The contact trenches 122 may be formed by any suitable means known to those skilled in the art. In some embodiments, the contact trenches 122 are formed by etching.

[0043]

[0061] 1 and 2F, in operation 22, sacrificial material 116 is selectively removed to form source / drain trenches 124. Sacrificial material 116 may be selectively removed by any suitable means known to those skilled in the art. In one or more embodiments, sacrificial material 116 is selectively removed.

[0044]

[0062] 2G, source / drain material 126 is selectively grown in source / drain trenches 124 adjacent to semiconductor material layer 106. In one or more embodiments, source / drain material 126 is epitaxially grown. Source / drain material 126 may include any suitable material known to those skilled in the art. In one or more embodiments, source / drain material 126 includes silicon germanium (SiGe), boron-doped silicon germanium (SiGeB), silicon phosphorus (SiP), carbon-doped silicon phosphorus (SiPC), germanium (Ge), or boron-doped germanium (GeB).

[0045]

[0063] 1 and 2H, in operation 26, a silicide layer 128 is formed on the source / drain material 126. In one or more embodiments, the silicide layer 128 may be a substantially conformal layer of silicide. As used herein, a "substantially conformal" layer refers to a layer that is about the same thickness throughout. A substantially conformal layer varies in thickness by no more than about 10%, 5%, 2%, or 0.5%.

[0046]

[0064] Thereafter, contact metallization is completed in operation 28 by depositing metal fill 130 in contact trenches 122 and in source / drain trenches 124 .

[0047]

[0065] The metal fill 130 may include any suitable material known to those skilled in the art, and in one or more embodiments, the metal fill 130 includes one or more of cobalt (Co), molybdenum (Mo), ruthenium (Ru), and tungsten (W).

[0048]

[0066] In some embodiments, the silicide layer 128 in combination with the metal fill 130 forms a metal silicide in the source and drain trenches. Thus, in one or more embodiments, the source / drain trenches 124 are filled with a metal silicide material including one or more of cobalt silicide (CoSi), molybdenum silicide (MoSi), ruthenium (RuSi), and tungsten silicide (WSi).

[0049]

[0067] 1 is integrated without a vacuum break. In one or more embodiments, the deposition of sacrificial material (operation 16), replacement gate formation (operation 18), opening of contact trenches (operation 20), selective removal of sacrificial material (operation 22), source / drain growth (operations 24 and 26), and filling of contact trenches (operation 28) may be integrated without a vacuum break between operations.

[0050]

[0068] 3 shows a process flow diagram of a method 50 for forming a semiconductor device according to some embodiments of the present disclosure. FIGS. 4A-4H illustrate stages in the fabrication of a semiconductor structure according to some embodiments of the present disclosure. In one or more embodiments, source / drain regions are epitaxially grown, followed by a substitution to form a metal silicide. In one or more embodiments, the source and drain regions are formed on a substrate adjacent to the superlattice structure. The source and drain regions comprise a metal silicide material.

[0051]

[0069] Method 50 is described below with respect to Figures 3-4H. Figures 4A-4H are cross-sectional views of an electronic device (e.g., an hGAA) according to one or more embodiments. Method 50 may be part of a multi-step manufacturing process for semiconductor devices. Thus, method 50 may be performed in any suitable process chamber coupled to a cluster tool. The cluster tool may include processing chambers for manufacturing semiconductor devices, such as etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in manufacturing semiconductor devices.

[0052]

[0070] 4A-4H are fabrication steps for operations 52 to 64 of FIG. 3. Referring to FIG. 3, a method 50 for forming a device 200 begins with providing a substrate 202 in operation 52. In some embodiments, the substrate 202 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate composed entirely of semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor substrate 202 may comprise one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 202 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 202 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials from which the substrate may be formed are described herein, any material that can serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) may be constructed is within the spirit and scope of the present disclosure.

[0053]

[0071] In some embodiments, the semiconductor material may be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor made by doping an intrinsic semiconductor with an electron-donating element during fabrication. The term n-type comes from the negative charge of the electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a higher hole concentration than the electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0054]

[0072] In some embodiments, a replacement gate structure (e.g., dummy gate structure 212) is formed on the superlattice structure 208. The dummy gate structure 212 defines a channel region of the transistor device. The dummy gate structure 212 may be formed using any suitable conventional deposition and patterning process known in the art. In one or more embodiments, the dummy gate structure 212 comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and titanium aluminum (TiAl).

[0055]

[0073] In some embodiments, sidewall spacers 210 are formed along the outer sidewalls of dummy gate structures 212. Sidewall spacers 210 may comprise any suitable insulating material known in the art, such as, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, sidewall spacers are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0056]

[0074] At least one superlattice structure 208 is formed on the top surface of the substrate 202. In one or more embodiments, the superlattice structure 208 includes a plurality of semiconductor material layers 206 and a corresponding plurality of nanosheet channel layers 204 arranged alternately in a plurality of stacked pairs. In some embodiments, the plurality of stacked pairs includes silicon (Si) and silicon germanium (SiGe) groups. In some embodiments, the plurality of semiconductor material layers 206 includes silicon germanium (SiGe) and the plurality of nanosheet channel layers 204 includes silicon (Si). In other embodiments, the plurality of nanosheet channel layers 204 includes silicon germanium (SiGe) and the plurality of semiconductor material layers includes silicon (Si).

[0057]

[0075] In some embodiments, the plurality of semiconductor material layers 206 and the corresponding plurality of nanosheet channel layers 204 may include any number of lattice-matched material pairs suitable for forming a superlattice structure 208. In some embodiments, the plurality of semiconductor material layers 206 and the corresponding plurality of nanosheet channel layers 104 include from about 2 pairs to about 50 pairs of lattice-matched materials.

[0058]

[0076] In one or more embodiments, the thickness t1 of the semiconductor material layers 206 and the nanosheet channel layers 204 is in the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm.

[0059]

[0077] The channel region 214 separates the superlattice structure 208 from an adjacent superlattice structure 208. In operation 54, the channel region 214 is recessed to form source trenches 215 a and drain trenches 215 b. In one or more embodiments, the source trenches 215 a and drain trenches 215 b are formed adjacent to (i.e., on either side of) the superlattice structure 208.

[0060]

[0078] 4B and 3, in operation 56, source / drain material 226 is selectively grown in source / drain trenches 215a / 215b adjacent to semiconductor material layer 206. In one or more embodiments, source / drain material 226 is epitaxially grown. Source / drain material 226 may include any suitable material known to those skilled in the art. In one or more embodiments, source / drain material 226 includes silicon germanium (SiGe), boron-doped silicon germanium (SiGeB), silicon phosphorus (SiP), carbon-doped silicon phosphorus (SiPC), germanium (Ge), or boron-doped germanium (GeB).

[0061]

[0079] 3 and 4C, in operation 58, a silicide layer 228 is formed on the source / drain material 226.

[0062]

[0080] 3 and 4D , in operation 60, a sacrificial material 216 is deposited in the channel region 214 and on the bottom surfaces of the source / drain trenches 215 a / 215 b. The sacrificial material 216 may include any suitable material known to those skilled in the art. In some embodiments, the sacrificial material 216 is amorphous. In one or more embodiments, the sacrificial material 216 includes one or more of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), aluminum oxide (AlOx), silicon oxide (SiOx), silicon oxycarbide (SiOC), or the like. In some embodiments, the sacrificial material 216 is a stress material that is subsequently replaced. The sacrificial stress material may be characterized by a greater amount of stress than the stress of surrounding layers.

[0063]

[0081] The sacrificial material 216 may be deposited using any suitable conventional deposition process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0064]

[0082] In one or more embodiments, the thickness of the sacrificial material 216 is in the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm.

[0065]

[0083] Referring to FIG. 4D, in some embodiments, a sacrificial material 216 may be deposited in the channel region 214 and on the bottom surfaces of the source / drain trenches 215a, 215b and on the sidewalls of the superlattice structure 108.

[0066]

[0084] Referring to FIG. 3 , in operation 62, the formation of a semiconductor device, e.g., a GAA, continues by conventional procedures involving nanosheet exfoliation and formation of a replacement metal gate. Specifically, as shown in FIG. 4E , the semiconductor material layers 206 are selectively etched between the horizontal channel layers 204 in the superlattice structure 208. For example, if the superlattice structure 208 is composed of silicon (Si) and silicon germanium (SiGe) layers, the silicon germanium (SiGe) is selectively etched to form channel nanowires. The semiconductor material layers 206, e.g., silicon germanium (SiGe), can be removed using known etchants that are selective to the horizontal channel layers 204, which etch the semiconductor material layers 206 at a significantly faster rate than the horizontal channel layers 204. In some embodiments, a selective dry or wet etching etch process may be used. In some embodiments, when the horizontal channel layers 204 are silicon (Si) and the semiconductor material layers 206 are silicon germanium (SiGe), the silicon germanium layer can be selectively removed using a wet etchant such as, but not limited to, a carboxylic acid / nitric acid / HF solution and a citric acid / nitric acid / HF solution. Removal of the semiconductor material layers 206 leaves voids between the horizontal channel layers 204. The voids between the horizontal channel layers 204 have a thickness of about 3 nm to about 20 nm. The remaining horizontal channel layers 204 form a vertical array of channel nanowires that connect to the source / drain regions. The channel nanowires run parallel to the top surface of the substrate 202 and are aligned with each other to form a single row of channel nanowires.

[0067]

[0085] In one or more embodiments, a high-k dielectric is formed. The high-k dielectric may be any suitable high-k dielectric material deposited by any suitable deposition technique known to those skilled in the art. In some embodiments, the high-k dielectric comprises hafnium oxide. In some embodiments, a conductive material, such as titanium nitride (TiN), tungsten (W), cobalt (Co), or aluminum (Al), is deposited on the high-k dielectric to form a replacement metal gate 218. The conductive material may be formed using any suitable deposition process, such as, but not limited to, atomic layer deposition (ALD), for reliable formation.

[0068]

[0086] Referring to FIG. 4F, contact material 220 is deposited on the sacrificial material 216 in the source / drain regions and in the channel region 214 .

[0069]

[0087] 3 and 4G, in operation 64, contact trenches 222 are opened. In one or more embodiments, the contact trenches extend to the source / drain regions, source / drain material 226, and silicide layer 228. The contact trenches 222 may be formed by any suitable means known to those skilled in the art. In some embodiments, the contact trenches 222 are formed by etching. In one or more embodiments, the sacrificial material 216 is selectively removed to form the source / drain trenches 224. The sacrificial material 216 may be selectively removed by any suitable means known to those skilled in the art.

[0070]

[0088] Referring to FIG. 4H and FIG. 3, in operation 66, contact metallization is completed by depositing metal fill 230 in contact trenches 222 and source / drain trenches 224.

[0071]

[0089] The metal fill 230 may include any suitable material known to those skilled in the art, and in one or more embodiments, the metal fill 230 includes one or more of cobalt (Co), molybdenum (Mo), ruthenium (Ru), and tungsten (W).

[0072]

[0090] In some embodiments, the silicide layer 228 in combination with the metal fill 230 forms a metal silicide in the source and drain trenches. Thus, in one or more embodiments, the source / drain trenches 224 are filled with a metal silicide material including one or more of cobalt silicide (CoSi), molybdenum silicide (MoSi), ruthenium (RuSi), and tungsten silicide (WSi).

[0073]

[0091] 3 is integrated without a vacuum break. In one or more embodiments, the source / drain material growth (operations 56 and 58), replacement gate formation (operation 60), contact trench opening (operation 62), and contact trench filling (operation 64) may be integrated without a vacuum break between operations.

[0074]

[0092] In some embodiments, the apparatus or process tool is configured to maintain the substrate under vacuum conditions to prevent the formation of an oxide layer, for example, after deposition of the sacrificial material 116. In such embodiments, the process tool is configured to move the substrate without exposing it to atmospheric conditions.

[0075]

[0093] An additional embodiment of the present disclosure is directed to a processing tool 300 for forming GAA devices and the methods described, as shown in FIG. 5. Various multi-processing platforms, including Centura®, Dual ACP, Producer® GT, and Endura® platforms available from Applied Materials®, as well as other processing systems, can be used. The cluster tool 300 includes at least one central transfer station 314 having multiple sides. A robot 316 is positioned within the central transfer station 314 and configured to move the robot blade and wafer to each of the multiple sides.

[0076]

[0094] Cluster tool 300 includes multiple processing chambers 308, 310, and 312, also referred to as processing stations, connected to a central transfer station. The various processing chambers provide distinct processing regions separate from adjacent processing stations. The processing chambers may be any suitable chambers, including, but not limited to, pre-clean chambers, deposition chambers, annealing chambers (i.e., mold crystallization chambers), etch chambers, etc. The specific arrangement of processing chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0077]

[0095] 5, a factory interface 318 is connected to the front of the cluster tool 300. The factory interface 318 includes a chamber 302 for loading and unloading onto a front surface 319 of the factory interface 318.

[0078]

[0096] The size and shape of the loading and unloading chambers 302 can vary depending on, for example, the substrates to be processed in the cluster tool 300. In the illustrated embodiment, the loading and unloading chambers 302 are sized to hold a wafer cassette with multiple wafers positioned within the cassette.

[0079]

[0097] The robot 304 resides within a factory interface 318 and is capable of moving between the loading chamber and the unloading chamber 302. The robot 304 is capable of transferring wafers through the factory interface 318 from a cassette in the loading chamber 302 to a load lock chamber 320. The robot 304 is also capable of transferring wafers through the factory interface 318 from the load lock chamber 320 to a cassette in the unloading chamber 302.

[0080]

[0098] In some embodiments, the robot 316 is a multi-arm robot capable of independently moving multiple wafers at a time. The robot 316 is configured to move wafers between chambers around the transfer chamber 314. Individual wafers are carried on a wafer transfer blade located at the distal end of the first robotic mechanism.

[0081]

[0099] A system controller 357 is in communication with the robot 316 and the plurality of processing chambers 308, 310, and 312. The system controller 357 may be any suitable component capable of controlling the processing chambers and the robot. For example, the system controller 357 may be a computer including a central processing unit (CPU) 392, memory 394, input / output 396, appropriate circuitry 398, and storage.

[0082]

[0100] The processes may generally be stored in the memory of the system controller 357 as software routines that, when executed by a processor, cause the processing chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be implemented in hardware. Thus, the processes may be implemented in software and executed in hardware using a computer system, for example, as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chamber to perform the processes.

[0083]

[0101] In some embodiments, the system controller 357 is configured to control the deposition of the sacrificial material as well as the selective removal of the sacrificial material.

[0084]

[0102] In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move wafers; a plurality of processing stations, including a mold deposition chamber and a mold crystallization chamber, each process station connected to the central transfer station and providing a processing area isolated from the processing areas of adjacent processing stations; and a controller connected to the central transfer station and the plurality of processing stations, configured to activate the robot to move wafers between the processing stations and to control the processes performed at each of the processing stations.

[0085]

[0103] One or more embodiments provide a non-transitory computer-readable medium including instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the operations of forming source and drain regions adjacent to a superlattice structure on a substrate, the superlattice structure including a plurality of horizontal channel layers and corresponding plurality of layers of semiconductor material arranged alternately in a plurality of stacked pairs, the source and drain regions including a metal suicide material. In some embodiments, the non-transitory computer-readable medium may cause the processing chamber to perform the further operations of forming source and drain trenches adjacent to the superlattice structure on the substrate; depositing a sacrificial material in the source and drain trenches; forming a replacement metal gate structure on a top surface of the superlattice structure; opening contact trenches adjacent to the replacement metal gate structure, the contact trenches extending to a top surface of the sacrificial material; selectively removing the sacrificial material through the contact trenches; and filling the contact trenches, the source trenches, and the drain trenches with a metal fill layer.

[0086]

[0104] In the context of describing the materials and methods discussed herein (particularly in the context of the claims that follow), the use of "a" and "an," "the," and similar referents should be construed to encompass both the singular and the plural unless otherwise indicated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better describe the materials and methods and does not limit the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0087]

[0105] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the present disclosure. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0088]

[0106] Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will recognize that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Accordingly, the disclosure may include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a semiconductor device, comprising: forming source and drain trenches adjacent to a superlattice structure on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of layers of semiconductor material arranged alternately in a plurality of stacked pairs; depositing a sacrificial material within the source trench and within the drain trench; forming a replacement metal gate structure on a top surface of the superlattice structure; opening a contact trench adjacent the replacement metal gate structure, the contact trench extending to a top surface of the sacrificial material; selectively removing the sacrificial material through the contact trench; forming source and drain regions adjacent the replacement metal gate structure by growing an epitaxial layer on the plurality of layers of semiconductor material in the source trench and the drain trench and forming a conformal layer of silicide on the epitaxial layer; filling the contact trenches, the source trenches, and the drain trenches with a metal fill layer to form a metal silicide; A method comprising:

2. 10. The method of claim 1, wherein the sacrificial material comprises one or more of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), aluminum oxide (AlOx), silicon oxide (SiOx), and silicon oxycarbide (SiOC).

3. The method of claim 2 , wherein the sacrificial material has a thickness in the range of 2 nm to 50 nm.

4. (delete)

5. The method of claim 1 , wherein the metal fill layer comprises one or more of cobalt (Co), molybdenum (Mo), ruthenium (Ru), and tungsten (W).

6. 10. The method of claim 1, wherein the epitaxial layer comprises one or more of silicon germanium (SiGe), boron-doped silicon germanium (SiGeB), silicon phosphorus (SiP), carbon-doped silicon phosphorus (SiPC), germanium (Ge), and boron-doped germanium (GeB).

7. 10. The method of claim 1, wherein the plurality of semiconductor material layers and the plurality of horizontal channel layers independently comprise one or more of silicon germanium (SiGe) and silicon (Si).

8. 10. The method of claim 1, wherein the replacement metal gate structure comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and titanium aluminum (TiAl).

9. 1. A method of forming a semiconductor device, comprising: forming source and drain regions adjacent to a superlattice structure on a substrate, the superlattice structure including a plurality of horizontal channel layers and corresponding layers of semiconductor material arranged alternately in a plurality of stacked pairs, the source and drain regions including a metal suicide material; A method comprising:

10. forming the source region and the drain region; forming source and drain trenches adjacent to the superlattice structure on the substrate; depositing a sacrificial material within the source trench and within the drain trench; forming a replacement metal gate structure on a top surface of the superlattice structure; opening a contact trench adjacent the replacement metal gate structure, the contact trench extending to a top surface of the sacrificial material; selectively removing the sacrificial material through the contact trench; filling the contact trench, the source trench, and the drain trench with a metal fill layer; 10. The method of claim 9, comprising:

11. 11. The method of claim 10, wherein the sacrificial material comprises one or more of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), aluminum oxide (AlOx), silicon oxide (SiOx), silicon oxycarbide (SiOC).

12. The method of claim 10 , wherein the sacrificial material has a thickness in the range of 2 nm to 50 nm.

13. The method of claim 10 , wherein the metal fill layer comprises one or more of cobalt (Co), molybdenum (Mo), ruthenium (Ru), and tungsten (W).

14. forming the source region and the drain region; growing an epitaxial layer on the layers of semiconductor material in the source trench and the drain trench before depositing the sacrificial material; forming a conformal layer of silicide on the epitaxial layer; The method of claim 10 further comprising:

15. 15. The method of claim 14, wherein the epitaxial layer comprises one or more of silicon germanium (SiGe), boron-doped silicon germanium (SiGeB), silicon phosphorus (SiP), carbon-doped silicon phosphorus (SiPC), germanium (Ge), and boron-doped germanium (GeB).

16. 15. The method of claim 14, wherein the metal fill layer comprises one or more of cobalt (Co), molybdenum (Mo), ruthenium (Ru), and tungsten (W).

17. 15. The method of claim 14, wherein the epitaxial layer comprises one or more of silicon germanium (SiGe), boron-doped silicon germanium (SiGeB), silicon phosphorus (SiP), carbon-doped silicon phosphorus (SiPC), germanium (Ge), and boron-doped germanium (GeB).

18. 1. A non-transitory computer-readable medium containing instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the following operations: forming source and drain regions adjacent to a superlattice structure on a substrate, the superlattice structure including a plurality of horizontal channel layers and corresponding layers of semiconductor material arranged alternately in a plurality of stacked pairs, the source and drain regions including a metal suicide material; A non-transitory computer-readable medium for implementing the above.

19. The processing chamber is subjected to the following further operations: forming source and drain trenches on the substrate adjacent to the superlattice structure; depositing a sacrificial material within the source trench and within the drain trench; forming a replacement metal gate structure on a top surface of the superlattice structure; opening a contact trench adjacent the replacement metal gate structure, the contact trench extending to a top surface of the sacrificial material; Selectively removing the sacrificial material through the contact trench; and 20. The non-transitory computer-readable medium of claim 18, further comprising: filling the contact trenches, the source trenches, and the drain trenches with a metal fill layer.

20. The processing chamber is subjected to the following further operations: growing an epitaxial layer on the layers of semiconductor material in the source trench and the drain trench; and 20. The non-transitory computer-readable medium of claim 19, further comprising forming a conformal layer of a silicide layer on the epitaxial layer.

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