Qubit-selective tuning of two-level systems in superconducting qubits by optical control

Abstract

A method and system for mitigating the effects of defects in a quantum processor are provided. The mitigation system includes a quantum processor having a plurality of qubits. The system includes an array of luminescence sources. Each luminescence source is aligned with a qubit on the quantum processor. The system includes a controller configured to receive a selection of the qubits and enable the luminescence sources to emit light to the selected qubit from the array of luminescence sources. The light is used to scramble a strongly coupled two-level system (TLS) in the quantum processor. (FIG. 9)

Description

[Technical Field]

[0001] The present disclosure relates generally to quantum computing, and more particularly to selective tuning of qubits by optical control. [Background technology]

[0002] A quantum bit, or qubit, is a fundamental element of information encoding in a quantum computer. A two-level system, or TLS, is a spurious quantum system that can couple to a qubit and cause decoherence. TLS is one of the main causes of decoherence in superconducting quantum circuits. Typically, TLSs contain two sets: a large set (bus) with low-frequency two-level fluctuations, and several discrete two-level systems that are close to the qubit's transition and resonance. When TLSs interact strongly with a qubit, the qubit becomes inoperable due to frequency shifts and decoherence.

[0003] The nature of these TLS is not fully understood, but they are thought to originate from crystalline imperfections, surface defects, or atomic-level defects in the material that generate microscopic dipoles (atomic or electronic traps) that interact with the qubit (e.g., couple to the qubit's electric field). TLS are always present and randomly distributed.

[0004] A two-level system can be either off-resonant or on-resonant with the qubit. On-resonant TLS is much more detrimental than off-resonant TLS. These on-resonant, strongly coupled TLS have a significant negative impact on gate fidelity in processors. This is especially true for processors based on fixed-frequency qubits. Summary of the Invention

[0005] Some embodiments of the present disclosure provide methods and systems for mitigating the effects of defects in a quantum processor. The system includes a quantum processor including a plurality of qubits. The system includes an array of luminescence sources. In some embodiments, the luminescence sources are used to scramble a two-level system (TLS) in the quantum processor. Each luminescence source is aligned with a qubit on the quantum processor. The system includes a controller configured to receive a selection of the qubits and enable the luminescence sources to emit light to the selected qubits from the array of luminescence sources.

[0006] In some embodiments, the array of luminescence sources is provided by different light sources. In some embodiments, multiple luminescence sources are provided by a common light source. In some embodiments, each of the array of luminescence sources is a light emitting diode (LED). In some embodiments, each of the luminescence sources is a laser. In some embodiments, the array of luminescence sources may be provided by an array of mounted lenses connected to multiple optical fibers. In an embodiment that may be combined with the previous embodiments, the lenses of the array of mounted lenses may be mounted on an illumination chip in the same package as the quantum processor. The illumination chip may be in the same refrigeration unit as the quantum processor. In some embodiments, the array of luminescence sources is provided by an array of mounted optical fibers.

[0007] In some embodiments, the system may include an optical switching matrix that distributes light pulses from optical fibers to an array of lenses. The inputs of the optical switching matrix are connected to the optical fibers. The outputs of the optical switching matrix are connected to an array of optical fibers that feed the array of lenses. The system may also further include a controller configured to receive a selection of a qubit and enable the optical switching matrix to pass light pulses from the optical fibers to the light emission source aligned with the selected qubit.

[0008] In some embodiments, the system may include an optical emission source and a positioning device configured to physically move the optical emission source relative to the quantum processor. The system may also include a controller configured to receive a selection of a qubit and to control the positioning device to move the optical emission source to a position corresponding to the selected qubit.

[0009] Two-level systems are one of the most fundamental problems in superconducting qubits and are the dominant source of decoherence. The ability to focus light on a specific qubit without resorting to time-consuming processes such as heating the entire quantum processor could rapidly improve the qubit's coherence.

[0010] The foregoing summary is intended to serve as a brief introduction to some embodiments of the present disclosure. It is not intended to be an introduction or overview of all inventive subject matter disclosed herein. The following detailed description and the drawings referenced in the detailed description further describe the embodiments described in the summary and other embodiments. Thus, the summary, detailed description, and drawings are provided to provide an understanding of all embodiments described herein. Moreover, because the claimed subject matter may be embodied in other specific forms without departing from the spirit of the subject matter, the claimed subject matter is not limited by the illustrative details of the summary, detailed description, and drawings, but is instead defined by the appended claims. [Brief explanation of the drawings]

[0011] The drawings are of exemplary embodiments. The drawings do not depict all embodiments. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for a more effective illustration. Some embodiments may be practiced with additional components or steps, or without all of the components or steps shown, or both. When the same numeral appears in different drawings, it refers to the same or similar components or steps.

[0012] [Figure 1] FIG. 1 illustrates a two-level system mitigation system that uses illumination to mitigate the effects of two-level systems in a quantum processor, consistent with an example embodiment.

[0013] [Figure 2] FIG. 1 illustrates a method for measuring the performance of a qubit.

[0014] [Figure 3] FIG. 1 illustrates an exemplary two-level system landscape, consistent with an exemplary embodiment.

[0015] [Figure 4] FIG. 1 illustrates a quantum processor having qubits illuminated by optical fibers, consistent with an illustrative embodiment.

[0016] [Figure 5] 1A-1C show spectrograms of qubits in a quantum processor before and after illumination, consistent with an illustrative embodiment.

[0017] [Figure 6] FIG. 1 conceptually illustrates a process for repeatedly applying illumination to a quantum processor to eliminate strongly coupled two-level system interactions, consistent with an example embodiment.

[0018] [Figure 7]1 shows a plurality of optical emission sources being used to illuminate qubits of a quantum processor, where each optical emission source in the array is aligned with a qubit on the quantum processor, consistent with an example embodiment.

[0019] [Figure 8] FIG. 10 shows an array of light-emitting diodes (LEDs) in an illumination chip being used to illuminate an array of qubits in a processor, consistent with an illustrative embodiment.

[0020] [Figure 9] FIG. 10 shows an array of lenses implemented connected to multiple optical fibers being used to illuminate an array of qubits in a processor, consistent with an example embodiment.

[0021] [Figure 10] FIG. 10 illustrates an array of optical fibers implemented and being used to illuminate an array of qubits in a processor, consistent with an example embodiment.

[0022] [Figure 11] FIG. 10 illustrates multiple optical emission sources being fed by a common light source to illuminate an array of qubits in a processor, consistent with an example embodiment.

[0023] [Figure 12] FIG. 1 illustrates a positioning apparatus being used to position a light source to illuminate selected qubits in a quantum processor, consistent with an example embodiment.

[0024] [Figure 13] FIG. 1 illustrates a block diagram of components of a data processing system in accordance with an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0025] In the following detailed description, by way of example, numerous specific details are set forth in order to provide a thorough understanding of the relevant teachings. However, it will be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and / or circuits have been described relatively broadly, without detailed description, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0026] Because strongly coupled TLS are significantly detrimental to qubit performance in large-scale quantum circuits, it is important to develop methods to shift their frequency off-resonance. Because TLS tend to drift slowly over time (spectral diffusion), on timescales of hours to days, it has been shown that TLS can be frequency-tuned by electric fields and material strain. Therefore, waiting for TLS to diffuse over a wide area can relax TLS. TLS can also be removed from qubits by heating or thermal cycling the entire processor to several degrees Kelvin. Heating the entire processor is a time-consuming process, typically requiring long periods (e.g., hours) and complete recalibration of the processor. Furthermore, heating the entire processor is a stochastic global process and therefore cannot be used to target specific qubits. It is not certain whether a specific TLS will shift its frequency through global heating. Furthermore, it is possible that a qubit previously released from one TLS may interact with another TLS after heating.

[0027] Some embodiments provide methods and systems for mitigating the effects of strongly coupled two-level systems. Specifically, optical illumination is used to scramble the frequency of the two-level system. Scrambling the TLS distribution can improve the coherence time and maintain stable quantum processor performance over time. The optical illumination can use light at telecommunication frequencies of 1310 nm and 1550 nm. In some embodiments, the optical illumination is delivered to a quantum processor or any array of qubits through a dilution refrigerator, and the light is selectively focused on individual qubits or globally applied to all qubits of the quantum processor.

[0028] 1 shows a TLS mitigation system 100 that uses illumination to mitigate the effects of TLS in a quantum processor 110. As shown, a TLS mitigation controller 120 controls a qubit measurement system 130 and an illumination system 140. The qubit measurement system 130 is used to detect or identify TLS in the quantum processor 110. The illumination system 140 is used to apply light to the quantum processor 110.

[0029] Measurement system 130 provides performance parameters of the qubits of quantum processor 110, including the decoherence time (or relaxation time) of the qubits at different electric field frequencies. In some embodiments, the performance parameters of the qubits at different frequencies are captured. Relaxation controller 120 can use the captured qubit performance parameters to create a spectrogram of the qubit. The spectrogram can be used as a TLS landscape to identify frequencies at which TLS couples strongly with the qubit (e.g., by identifying frequencies at which the qubit's decoherence time is reduced by 25% or more).

[0030] Illumination system 140 is used to provide optical pulses to quantum processor 110. The optical pulses may be, for example, polarized to prevent the TLS from coupling strongly to the qubits. The frequency landscape of the TLS can be scrambled to be off-resonant so that the decoherence time of the qubit is at least 75% of the ideal or expected relaxation time.

[0031] The TLS relaxation controller 120 can use the TLS landscape generated based on measurements provided by the measurement system 130 to determine when and how to apply light pulses to the quantum processor 110 and control the illumination system 140 accordingly.

[0032] In some embodiments, one or more laser sources are used to scramble the frequency of the TLS. Laser pulses are used to change the TLS landscape of a superconducting quantum processor on a very short timescale (e.g., less than a second). In some embodiments, very short laser pulses can be applied to instantaneously shift the TLS frequency. Recovery times from laser pulses are on the timescale of seconds (or less), compared to the hours it can take to warm up an entire quantum processor. The light pulses can be visible or infrared light.

[0033] FIG. 2 conceptually illustrates a method for measuring qubit performance. A microwave pulse 200 of calibrated amplitude, frequency, and duration is applied to the qubit, placing the qubit in its excited state. The qubit's state is measured at several different delay times after application of the microwave pulse. The measurements are repeated and averaged to obtain a characteristic exponential decay curve 210. (The vertical axis of decay curve 210 refers to the proportion of qubit measurements that find the qubit to be in the excited state at a given delay time; thus, 1.0 corresponds to finding 100% of the qubits measured at a given delay time to be in the excited state.) The time constant of decay curve 210 is used to measure the qubit's performance.

[0034] Defects can resonantly couple to qubits and function as strong energy relaxation channels with Lorentzian spectroscopic signatures. This signature can be used to identify defects. Figure 3 shows an example TLS landscape. The TLS landscape is based on measurements of a flux-tunable qubit, which exhibits several regions of strongly coupled TLS. If a fixed-frequency transmon happens to have a transition frequency near strong TLS, qubit performance will become significantly degraded—i.e., the relaxation or decoherence time will be significantly shorter. In the figure, the measured qubit relaxation time (also referred to as T1) is normalized with respect to the ideal or expected relaxation time. Thus, at frequencies with weak or no TLS coupling, the normalized relaxation time will be close to 1.0, whereas at frequencies with strong TLS coupling, the normalized relaxation time can be significantly reduced (to 0.1 or less).

[0035] Figure 4 illustrates a quantum processor with qubits illuminated by an optical fiber. The quantum processor can be constructed on a silicon, sapphire, or other dielectric substrate. In some embodiments, a laser or optical fiber penetrates the quantum processor chip to provide illumination. As shown, an optical fiber 400 is coupled to an enclosure 405 above the quantum processor 110. Light pulses can be directed from outside the enclosure to illuminate part or all of the quantum processor 110. Because silicon is transparent to infrared light at wavelengths of 1100 nm or higher, the quantum processor can be illuminated from either surface (front or back). Applying an optical pulse to the quantum processor or qubit can shift or scramble the frequency landscape of the TLS. It can be shown that the frequency of the TLS can change in a random manner after an optical pulse. On the other hand, without applying an optical pulse, the TLS can remain nearly constant for several hours.

[0036] FIG. 5 illustrates spectrograms of a qubit in a quantum processor before and after irradiation. The figure shows two spectrograms 510 and 520 illustrating the relaxation times of a qubit in the quantum processor at different frequencies. The first spectrogram 510 is based on measurements of the qubit taken before the light pulse is applied, and the second spectrogram 520 is based on measurements of the qubit taken after the light pulse is applied. As shown, after the light pulse is applied, the profiles of the qubit relaxation times at different frequencies shift. This is because the TLS in the quantum processor has been scrambled by the applied light pulse. Based on the TLS landscape illustrated by spectrogram 520, TLS relaxation controller 120 can determine that (i) TLS does not significantly impair the operation of the qubit at the frequency of interest, or (ii) the qubit is still impaired by TLS at the frequency of interest such that an additional light pulse is required to further scramble the TLS. This determination can be made by determining whether the relaxation time of the qubit falls below a particular threshold fraction (eg, 0.75 or 75%) of the expected relaxation time.

[0037] Because the laser operates so quickly, the process of laser-induced TLS frequency scrambling can be repeated several times to find the ideal TLS configuration, where all violent or strongly coupled TLS interactions are eliminated. This significantly improves the functionality of the quantum processor. The ability to rapidly cycle through TLS configurations and find the optimal configuration will have a major impact on the performance of any large-scale fixed-frequency quantum processor.

[0038] FIG. 6 conceptually illustrates a process 600 for iteratively applying irradiation to a quantum processor to eliminate strongly coupled TLS interactions, consistent with an illustrative embodiment. The TLS mitigation system 100 or TLS mitigation controller 120 can perform a process to mitigate the adverse effects of TLS to prepare the quantum processor for use. The process rearranges the TLS landscape by rapidly cycling through TLS configurations. Qubit properties are measured to determine whether scrambling with irradiation improves processor performance. An iterative search is performed to find a good global TLS configuration across different qubits of the quantum processor. In some embodiments, one or more processing units (e.g., processors) of a computing device implementing the TLS mitigation controller 120 perform the process 600 by executing instructions stored on a computer-readable medium.

[0039] The system measures the coherence properties of all qubits (at block 605). Figure 2 above illustrates one example of how qubits may be measured.

[0040] The system determines (at block 610) whether one or more qubits fail to meet a performance criterion. The system may receive performance parameters (e.g., coherence properties) of one or more qubits in the quantum processor to identify qubits that fail to meet a performance threshold. If none of the qubits meet the performance criterion, the system proceeds to 650 to calibrate the quantum processor and make it ready for use. If at least one qubit fails to meet the performance criterion, processing proceeds to 620.

[0041] At block 620, the system illuminates one or more qubits in the processor. The system may apply a global light pulse to the quantum processor such that multiple qubits in the processor are illuminated. The system may also use a local light pulse limited to qubits identified as experiencing bad TLS interactions.

[0042] The system (at block 630) performs spectroscopy (e.g., Stark spectroscopy, a method of obtaining small, fast frequency tuning of a qubit via the AC Stark effect) on the qubit of the processor to obtain a spectrogram as a TLS landscape. A qubit's TLS landscape is a collection of measured relaxation times of the qubit across different probe frequencies. The system receives or captures qubit relaxation times measured at different qubit frequencies, including relaxation times measured before and after a light pulse. In some embodiments, the system may perform multiple frequency sweeps to obtain multiple sets of relaxation times. As the system identifies qubits that do not meet performance requirements, the received qubit relaxation times include the relaxation times of the identified failing qubits.

[0043] The system determines (at block 640) whether the TLS landscape is acceptable, e.g., whether there is a good global TLS configuration across different qubits in the quantum processor, or whether there is a strongly coupled TLS in the quantum processor. If the TLS landscape is acceptable, the process proceeds to 650 to calibrate the quantum processor to a usable state. If the TLS landscape is not acceptable, e.g., if there is strong coupling between the qubit and the TLS that causes severe degradation of the decoherence time (e.g., less than 75% of the expected qubit relaxation time), the process returns to 620 to again apply a laser pulse and measure qubit performance. In other words, the system determines whether to apply a first light pulse to illuminate the quantum processor, and then apply a second light pulse to illuminate the quantum processor, based on the current TLS configuration or landscape. This is an iterative process of applying a light pulse and examining the qubit relaxation time in order to eliminate or minimize TLS interactions with the qubit.

[0044] In some embodiments, one or more optical fibers are used to guide laser light from room temperature to the chip. The focus of the laser can be manipulated to either direct all of the laser power to one specific region (e.g., one specific qubit) or to apply a global diffusive field (e.g., to a set of multiple qubits). In some embodiments, one or several optical fibers are integrated into the package, allowing for either qubit-specific or global scrambling of the TLS landscape. In some embodiments, far-infrared laser light is used to illuminate the chip to scramble the TLS, where the silicon substrate is transparent.

[0045] In some embodiments, an array of luminescence sources is used to illuminate qubits of a quantum processor. Each luminescence source in the array is aligned with a qubit on the quantum processor. Figure 7 shows multiple luminescence sources (e.g., an array of luminescence sources) being used to illuminate qubits of quantum processor 110, where each luminescence source in the array is aligned with a qubit on the quantum processor. The luminescence sources are on an illumination chip 710 in the same package as quantum processor 110 and are located in the same refrigeration unit (e.g., cryostat). A controller (e.g., TLS relaxation controller 120) (not shown) can be configured to receive the qubit selection and enable an luminescence source from the array of luminescence sources to emit light to the selected qubit.

[0046] In some embodiments, the multiple luminescence sources are provided by different light sources. Figure 8 shows an array of light emitting diodes (LEDs) in illumination chip 710 being used to illuminate an array of qubits in processor 110. Each LED acts as a luminescence source for illuminating a corresponding one qubit.

[0047] In some embodiments, multiple optical emission sources may be provided by an array of mounted lenses connected to multiple optical fibers. 9 shows an array of mounted lenses connected to multiple optical fibers that are used to illuminate the array of qubits in processor 110. A lens coupled to the optical fibers is coupled to each lens mount. Incident light from each optical fiber is focused or collimated by a corresponding lens and directed to the corresponding qubit. In some embodiments, the lenses are mounted on an illumination chip 910 in the same package as the quantum processor. The illumination chip 910 can be in the same refrigeration unit (e.g., cryostat) as the quantum processor.

[0048] In some embodiments, the multiple optical emission sources are provided by an array of mounted optical fibers. Figure 10 shows an array of mounted optical fibers 1010 being used to illuminate an array of qubits in processor 110. Each location in mount 1010 has a lensed optical fiber coupled to it. The lensed optical fiber focuses or collimates the light from the fiber onto the qubits on a one-to-one basis.

[0049] In some embodiments, the multiple luminescence sources used to illuminate individual qubits are fed by a common light source. Figure 11 shows multiple luminescence sources being fed by a common light source to illuminate an array of qubits in processor 110. As shown, the array of qubits is mounted by a fiber optic array mount 1110. The fiber optic array mount 1110 has an array of lenses, each lens aligned with a qubit on quantum processor 110. In some embodiments, the array of lenses 1110 is mounted on an illumination chip in the same package as quantum processor 110, and the illumination chip is in the same refrigeration unit as quantum processor 110.

[0050] Optical switching matrix 1120 is used to direct an incident light source (optical fiber 1105) to a target qubit in the array. Optical switching matrix 1120 distributes light pulses from optical fiber 1105 to an array of lenses. The input of optical switching matrix 1120 is connected to optical fiber 1105, and the output of optical switching matrix 1120 is connected to an array of optical fibers that feed the array of lenses 1110. In some embodiments, a controller (e.g., relaxation controller 120) (not shown) can be configured to receive a qubit selection and enable optical switching matrix 1120 to pass a light pulse from optical fiber 1105 to a lens that is aligned with the selected qubit.

[0051] In some embodiments, a positioning device capable of physically moving an optical emission source relative to a quantum processor is used to target illumination to specific qubits in the processor. A controller can be configured to receive a qubit selection and control the positioning device to move the optical emission source to a position corresponding to the selected qubit. FIG. 12 shows a positioning device being used to position an optical source to illuminate selected qubits in a quantum processor. As shown, optical fiber 1205 coupled to lens 1210 is mounted on a three-dimensional translation stage 1220. Lens 1210 is aimed at qubit array 110. Manipulating stage 1220 can select the qubit to be illuminated by the optical pulse from optical fiber 1205. Furthermore, the spatial position of the fiber / lens can target a specific point within a single qubit.

[0052] This application may employ systems, methods, and / or computer program products at any possible level of technical detail. The computer program products may include one or more computer-readable storage media having computer-readable program instructions thereon for causing a processor to perform aspects of the present disclosure.

[0053] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves on which instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as being a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through a fiber optic cable), or an electrical signal transmitted through a wire.

[0054] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device. The computer-readable program instructions for performing the operations of the present disclosure may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer-readable program instructions may run entirely on the user's computer as a stand-alone software package, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry to perform aspects of the present disclosure.

[0055] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored has an article of manufacture including instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0056] The computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device and cause the computer, other programmable apparatus, or other device to perform a series of operational steps to generate a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. The flowcharts and block diagrams in the figures (e.g., FIG. 6) illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or actions or executes a combination of dedicated hardware and computer instructions.

[0057] 13 illustrates a block diagram of components of data processing systems 1300 and 1350 that may be used to implement the TLS mitigation controller 120 in accordance with an exemplary embodiment of the present disclosure. It should be understood that FIG. 13 provides only an illustration of one implementation and is not intended to suggest any limitations with regard to the environments in which different embodiments may be implemented. Many modifications to the depicted environments may be made based on design and implementation requirements.

[0058] Data processing systems 1300 and 1350 represent any electronic device capable of executing machine-readable program instructions. Data processing systems 1300 and 1350 can represent a smartphone, a computer system, a PDA, or other electronic device. Examples of computing systems, environments, and / or configurations that may be represented by data processing systems 1300 and 1350 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, network PCs, minicomputer systems, and distributed cloud computing environments that include any of the above systems or devices.

[0059] Data processing systems 1300 and 1350 may include a set of internal components 1305 and a set of external components 1355 shown in Figure 13. The set of internal components 1305 includes one or more processors 1320, one or more computer-readable RAMs 1322 and one or more computer-readable ROMs 1324 on one or more buses 1326, as well as one or more operating systems 1328 and one or more computer-readable tangible storage devices 1330. The one or more operating systems 1328 and programs, such as those for executing process 600, are stored in the one or more computer-readable tangible storage devices 1330 for execution by the one or more processors 1320 via one or more RAMs 1322 (which typically include cache memory). In the embodiment shown in Figure 13, each of the computer-readable tangible storage devices 1330 is an internal hard drive magnetic disk storage device. Alternatively, each of the computer-readable tangible storage devices 1330 is a semiconductor storage device such as a ROM 1324, an EPROM, a flash memory, or any other computer-readable tangible storage device capable of storing computer programs and digital information.

[0060] The set of internal components 1305 also includes a R / W drive or interface 1332 for reading from and writing to one or more portable computer-readable tangible storage devices 1386, such as a CD-ROM, a DVD, a memory stick, a magnetic tape, a magnetic disk, an optical disk, or a semiconductor storage device. Instructions for executing the process 600 may be stored on one or more of the respective portable computer-readable tangible storage devices 1386, read via the respective R / W drive or interface 1332, and loaded onto a respective hard drive 1330.

[0061] The set of internal components 1305 may also include a network adapter (or switch port card) or interface 1336, such as a TCP / IP adapter card, a wireless Wi-Fi interface card, or a 3G or 4G wireless interface card, or other wired or wireless communication link. Instructions for the processes or programs described above may be downloaded from an external computer (e.g., a server) via a network (e.g., the Internet, a local area network, or other wide area network) and the respective network adapter or interface 1336. From the network adapter (or switch port adapter) or interface 1336, instructions and data for the described programs or processes are loaded onto the respective hard drives 1330. The network may comprise copper wire, fiber optic, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers.

[0062] The set of external components 1355 may include a computer display monitor 1370, a keyboard 1380, and a computer mouse 1384. The set of external components 1355 may also include a touch screen, a virtual keyboard, a touchpad, a pointing device, or other human interface devices. The set of internal components 1305 may also include a device driver 1340 for interfacing with the computer display monitor 1370, the keyboard 1380, and the computer mouse 1384. The device driver 1340, the R / W drive or interface 1332, and the network adapter or interface 1336 include hardware and software (stored in the storage device 1330 or the ROM 1324, or both).

[0063] The description of various embodiments of the present teachings has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments over technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A system comprising: a quantum processor including a plurality of qubits; an array of light emission sources, each light emission source aligned with a qubit on the quantum processor; and a controller configured to receive a selection of a qubit and enable a light emission source from the array of light emission sources to emit light to the selected qubit.

2. 10. The system of claim 1, wherein each of the array of light emitting sources is a light emitting diode (LED).

3. 10. A system according to any one of the preceding claims, wherein the array of light emitting sources is provided by an array of mounted lenses connected to an array of optical fibres.

4. The system of claim 3 , wherein the lenses of the array of mounted lenses are mounted on an illumination chip in the same package as the quantum processor.

5. The system of claim 4 , wherein the illumination chip is in the same refrigeration unit as the quantum processor.

6. 10. A system according to any one of the preceding claims, wherein the array of light emitting sources is provided by an array of mounted optical fibres.

7. 10. A system according to any one of the preceding claims, wherein the array of luminescence sources is supplied by different light sources.

8. 10. A system according to any one of the preceding claims, wherein the array of luminescence sources is supplied by one common light source.

9. 10. A system according to any one of the preceding claims, wherein the luminescence sources are arranged as a two-dimensional array of luminescence sources.

10. A system comprising: a quantum processor including an array of qubits; an optical fiber; an array of lenses, each lens aligned with a qubit on said quantum processor; and an optical switching matrix that distributes light pulses from said optical fiber to said array of lenses.

11. The system of claim 10 , wherein the lenses are arranged as a two-dimensional array of lenses.

12. 12. A system according to any one of claims 10 to 11, wherein the inputs of an optical switching matrix are connected to the optical fibres; and the outputs of the optical switching matrix are connected to an array of optical fibres feeding the array of lenses.

13. 13. A system according to any one of claims 10 to 12, wherein the lenses of the array of lenses are implemented on an illumination chip that is in the same package as the quantum processor.

14. 14. The system of any one of claims 10 to 13, wherein the illumination chip is in the same refrigeration unit as the quantum processor.

15. 15. The system of any one of claims 10 to 14, further comprising a controller configured to receive a selection of a qubit and enable the optical switching matrix to pass a light pulse from the optical fiber to the light emission source aligned with the selected qubit.

16. A system comprising: a quantum processor including a plurality of qubits; an optical emission source; a positioning device configured to physically move the optical emission source relative to the quantum processor; and a controller configured to receive a selection of a qubit and control the positioning device to move the optical emission source to a position corresponding to the selected qubit.

17. 17. The system of claim 16, wherein the positioning device is configured to move the optical emission source relative to the quantum processor in three dimensions.

18. 1. A method comprising: providing a quantum processor including a plurality of qubits; aligning each luminescence source of an array of luminescence sources with a qubit on the quantum processor; and receiving, by a controller, a selection of a qubit; and enabling, by the controller, the luminescence source to emit light from the array of luminescence sources to the selected qubit.

19. 20. The method of claim 18, wherein each of the array of light emitting sources is a light emitting diode (LED).

20. 20. A method according to any one of claims 18 to 19, wherein the array of light emitting sources is provided by an array of mounted lenses connected to an array of optical fibres.

21. 21. The method of claim 20, wherein the lenses of the array of mounted lenses are mounted on an illumination chip in the same package as the quantum processor.

22. 22. The method of claim 21, wherein the illumination chip is in the same refrigeration unit as the quantum processor.

23. 23. A method according to any one of claims 18 to 22, previously described, wherein the array of light emitting sources is provided by an array of mounted optical fibres.

24. 24. A method according to any one of the preceding claims 18 to 23, wherein the array of luminescence sources is supplied by different light sources.

25. 25. A method according to any one of claims 18 to 24, wherein the array of luminescence sources is supplied by one common light source.

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